From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=lks47jOf; spf=pass (domain: linaro.org, ip: 209.85.128.67, mailfrom: leif.lindholm@linaro.org) Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) by groups.io with SMTP; Thu, 26 Sep 2019 16:30:58 -0700 Received: by mail-wm1-f67.google.com with SMTP id y135so7669706wmc.1 for ; Thu, 26 Sep 2019 16:30:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=0hYruCF+s601J6D3bAWu5rs+fXOWlI657OHCMay5NW4=; b=lks47jOf+d3mYuVIyObnGLvaMCsibh5tlZedeRzpMnhjdQtC82M95P0uw6Pc/R3ulw bCGTFRckAV338uWIDumNXse3EaT1WOqwVovzdSYLg+eKvtLZAsf8buBn3CeW7XQcle8f 6zNdBVIIrlPnS8/PFVql00y1tKW/suSLbeU5cGlPPVf8bhxq6UiBCcvMoj9Nb5aPV2nb 12C0C7GGy0uvxcwbcIzGH/eFrIgsGnhCOTdLe2odNI4rLmMEYYpnyKn1WLfBHNOtN7Ak ptjEIBPDQ+2sW8cwf3GhfMPyoOjPLAPjkcsNdjLmpITvNtsKaG9jnCNrix5Sc5MU/Ojb 3Gsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=0hYruCF+s601J6D3bAWu5rs+fXOWlI657OHCMay5NW4=; b=O0Cm4CIuOKXwUwPaix6HrmMsZrWoWeseEuO0lb1HxbLVQzXCbsZxJ9D7oywMJJuGYS FowYmbeo5QqOLSnTGd8Xwil7o9v0eaLSnnFD5UXEAE/LHL2XJrd5c0dYFOaCFh4JWR2t c+rBHuBQbLWT2AzUy+UZzSsgxyCVgclY2xIW8D7nEPMZ67cwiWL7RszNlN8zhCj73SIx zyEKxWumuMTx/dCSrf6tBvB5Y+wmsEJbMLl6J1eQrx+HC8OzgUsdA2x/QaPu4bl48ajG WDH+7x45gbM0VBKyaMvlVAmvN1WOBq7FMDayHwTlqme+6jbKRrMK/y5r1Ijl8w9h2r60 J6tg== X-Gm-Message-State: APjAAAWoFs7vipFfuuRAPssQO6FvNcjVy6dGd4+6dVNDgwgHPFQ2FiVl uxEKG3GvZmAuP7cPfZrWYnmIKRgD+bag/Q== X-Google-Smtp-Source: APXvYqzpXv6+JiIY005Qb5ChrIIT04GEK3tbeRBVtwqkYtCr/RZ5vgMM9nwseWNrSX5DFHfPSP30tw== X-Received: by 2002:a7b:c764:: with SMTP id x4mr4942339wmk.138.1569540656327; Thu, 26 Sep 2019 16:30:56 -0700 (PDT) Return-Path: Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id s5sm1138339wro.27.2019.09.26.16.30.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Sep 2019 16:30:55 -0700 (PDT) Date: Fri, 27 Sep 2019 00:30:54 +0100 From: "Leif Lindholm" To: devel@edk2.groups.io, abner.chang@hpe.com Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation. Message-ID: <20190926233054.GK25504@bivouac.eciton.net> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> <1569198715-31552-10-git-send-email-abner.chang@hpe.com> MIME-Version: 1.0 In-Reply-To: <1569198715-31552-10-git-send-email-abner.chang@hpe.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Sep 23, 2019 at 08:31:34AM +0800, Abner Chang wrote: > Implement RISC-V cache maintenance functions in > BaseCacheMaintenanceLib. > > Signed-off-by: Abner Chang I can't comment on their correctness, but the code looks fine. Acked-by: Leif Lindholm > --- > .../BaseCacheMaintenanceLib.inf | 4 + > .../Library/BaseCacheMaintenanceLib/RiscVCache.c | 250 +++++++++++++++++++++ > 2 files changed, 254 insertions(+) > create mode 100644 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c > > diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf > index ec7feec..d9bfa04 100644 > --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf > +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf > @@ -6,6 +6,7 @@ > # > # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
> # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
> +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -41,6 +42,9 @@ > [Sources.AARCH64] > ArmCache.c > > +[Sources.RISCV64] > + RiscVCache.c > + > [Packages] > MdePkg/MdePkg.dec > > diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c > new file mode 100644 > index 0000000..d8e4665 > --- /dev/null > +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c > @@ -0,0 +1,250 @@ > +/** @file > + RISC-V specific functionality for cache. > + > + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > + > +/** > + RISC-V invalidate instruction cache. > + > +**/ > +VOID > +EFIAPI > +RiscVInvalidateInstCacheAsm ( > + VOID > + ); > + > +/** > + RISC-V invalidate data cache. > + > +**/ > +VOID > +EFIAPI > +RiscVInvalidateDataCacheAsm ( > + VOID > + ); > + > +/** > + Invalidates the entire instruction cache in cache coherency domain of the > + calling CPU. > + > +**/ > +VOID > +EFIAPI > +InvalidateInstructionCache ( > + VOID > + ) > +{ > + RiscVInvalidateInstCacheAsm (); > +} > + > +/** > + Invalidates a range of instruction cache lines in the cache coherency domain > + of the calling CPU. > + > + Invalidates the instruction cache lines specified by Address and Length. If > + Address is not aligned on a cache line boundary, then entire instruction > + cache line containing Address is invalidated. If Address + Length is not > + aligned on a cache line boundary, then the entire instruction cache line > + containing Address + Length -1 is invalidated. This function may choose to > + invalidate the entire instruction cache if that is more efficient than > + invalidating the specified range. If Length is 0, then no instruction cache > + lines are invalidated. Address is returned. > + > + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). > + > + @param Address The base address of the instruction cache lines to > + invalidate. If the CPU is in a physical addressing mode, then > + Address is a physical address. If the CPU is in a virtual > + addressing mode, then Address is a virtual address. > + > + @param Length The number of bytes to invalidate from the instruction cache. > + > + @return Address. > + > +**/ > +VOID * > +EFIAPI > +InvalidateInstructionCacheRange ( > + IN VOID *Address, > + IN UINTN Length > + ) > +{ > + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__)); > + return Address; > +} > + > +/** > + Writes back and invalidates the entire data cache in cache coherency domain > + of the calling CPU. > + > + Writes back and invalidates the entire data cache in cache coherency domain > + of the calling CPU. This function guarantees that all dirty cache lines are > + written back to system memory, and also invalidates all the data cache lines > + in the cache coherency domain of the calling CPU. > + > +**/ > +VOID > +EFIAPI > +WriteBackInvalidateDataCache ( > + VOID > + ) > +{ > + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__)); > +} > + > +/** > + Writes back and invalidates a range of data cache lines in the cache > + coherency domain of the calling CPU. > + > + Writes back and invalidates the data cache lines specified by Address and > + Length. If Address is not aligned on a cache line boundary, then entire data > + cache line containing Address is written back and invalidated. If Address + > + Length is not aligned on a cache line boundary, then the entire data cache > + line containing Address + Length -1 is written back and invalidated. This > + function may choose to write back and invalidate the entire data cache if > + that is more efficient than writing back and invalidating the specified > + range. If Length is 0, then no data cache lines are written back and > + invalidated. Address is returned. > + > + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). > + > + @param Address The base address of the data cache lines to write back and > + invalidate. If the CPU is in a physical addressing mode, then > + Address is a physical address. If the CPU is in a virtual > + addressing mode, then Address is a virtual address. > + @param Length The number of bytes to write back and invalidate from the > + data cache. > + > + @return Address of cache invalidation. > + > +**/ > +VOID * > +EFIAPI > +WriteBackInvalidateDataCacheRange ( > + IN VOID *Address, > + IN UINTN Length > + ) > +{ > + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); > + return Address; > +} > + > +/** > + Writes back the entire data cache in cache coherency domain of the calling > + CPU. > + > + Writes back the entire data cache in cache coherency domain of the calling > + CPU. This function guarantees that all dirty cache lines are written back to > + system memory. This function may also invalidate all the data cache lines in > + the cache coherency domain of the calling CPU. > + > +**/ > +VOID > +EFIAPI > +WriteBackDataCache ( > + VOID > + ) > +{ > + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); > +} > + > +/** > + Writes back a range of data cache lines in the cache coherency domain of the > + calling CPU. > + > + Writes back the data cache lines specified by Address and Length. If Address > + is not aligned on a cache line boundary, then entire data cache line > + containing Address is written back. If Address + Length is not aligned on a > + cache line boundary, then the entire data cache line containing Address + > + Length -1 is written back. This function may choose to write back the entire > + data cache if that is more efficient than writing back the specified range. > + If Length is 0, then no data cache lines are written back. This function may > + also invalidate all the data cache lines in the specified range of the cache > + coherency domain of the calling CPU. Address is returned. > + > + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). > + > + @param Address The base address of the data cache lines to write back. If > + the CPU is in a physical addressing mode, then Address is a > + physical address. If the CPU is in a virtual addressing > + mode, then Address is a virtual address. > + @param Length The number of bytes to write back from the data cache. > + > + @return Address of cache written in main memory. > + > +**/ > +VOID * > +EFIAPI > +WriteBackDataCacheRange ( > + IN VOID *Address, > + IN UINTN Length > + ) > +{ > + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); > + return Address; > +} > + > +/** > + Invalidates the entire data cache in cache coherency domain of the calling > + CPU. > + > + Invalidates the entire data cache in cache coherency domain of the calling > + CPU. This function must be used with care because dirty cache lines are not > + written back to system memory. It is typically used for cache diagnostics. If > + the CPU does not support invalidation of the entire data cache, then a write > + back and invalidate operation should be performed on the entire data cache. > + > +**/ > +VOID > +EFIAPI > +InvalidateDataCache ( > + VOID > + ) > +{ > + RiscVInvalidateDataCacheAsm (); > +} > + > +/** > + Invalidates a range of data cache lines in the cache coherency domain of the > + calling CPU. > + > + Invalidates the data cache lines specified by Address and Length. If Address > + is not aligned on a cache line boundary, then entire data cache line > + containing Address is invalidated. If Address + Length is not aligned on a > + cache line boundary, then the entire data cache line containing Address + > + Length -1 is invalidated. This function must never invalidate any cache lines > + outside the specified range. If Length is 0, then no data cache lines are > + invalidated. Address is returned. This function must be used with care > + because dirty cache lines are not written back to system memory. It is > + typically used for cache diagnostics. If the CPU does not support > + invalidation of a data cache range, then a write back and invalidate > + operation should be performed on the data cache range. > + > + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). > + > + @param Address The base address of the data cache lines to invalidate. If > + the CPU is in a physical addressing mode, then Address is a > + physical address. If the CPU is in a virtual addressing mode, > + then Address is a virtual address. > + @param Length The number of bytes to invalidate from the data cache. > + > + @return Address. > + > +**/ > +VOID * > +EFIAPI > +InvalidateDataCacheRange ( > + IN VOID *Address, > + IN UINTN Length > + ) > +{ > + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__)); > + return Address; > +} > -- > 2.7.4 > > > >