From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=PIr5TWjK; spf=pass (domain: linaro.org, ip: 209.85.128.68, mailfrom: leif.lindholm@linaro.org) Received: from mail-wm1-f68.google.com (mail-wm1-f68.google.com [209.85.128.68]) by groups.io with SMTP; Thu, 26 Sep 2019 16:47:31 -0700 Received: by mail-wm1-f68.google.com with SMTP id p7so4571909wmp.4 for ; Thu, 26 Sep 2019 16:47:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=62nVwSTqrKCyXAcBGliSA9FZOO0zT1HiYfJOW6kdT9U=; b=PIr5TWjKZcc2ZFsek8NJ3pjkAyP3MGi+qB2dsd63668N8F2akC1hnvm+u/nd21zfd0 lO87qvCSPDaVXeCg2zgP11sz7CEpgTpc2Ge9aSJkKR51ztLN7Wlo8MVEegNOPKLDqGyC SBsaBQnMaXbdkYsJhFTpcrirSc6WOmJkP9wP7UD8vXFsCLFSQZLUo5V9JmO09o1IJCJa tlPVxO9KD/MrPbRAd8O/0KOSY5XDm9qTxCsEjL5RCRaWVr9mdWJzYhdx35X6inzduUVY kZH27+xXeqNEb6Cg1QhZYOqVzlORTRSyIq9H3RWgzsJKIx4Oa3/2C3Ab5d/IsEJtl60l 6wHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=62nVwSTqrKCyXAcBGliSA9FZOO0zT1HiYfJOW6kdT9U=; b=BAl1DHnCEDLg3TlVKZetMwq75Sw6wtBVVda/jb6qf8w1sA7plktMHRs67GUc/rIxnC 5GFimzqFKrrp1CYUQEu+EA/Hv7KZSK+6l7cGTpaLJ0KH+IdDOQ1XgwXrlVOE86clVgoi JOCHLyP0rDFW+qlTqXdKGXSTzqv0hIJAAAtpJO15lfLt+l3PY7ilD9fNu9DwtwFZkw5Q BVG4FVjsHoziimIYhJ4PFWW+hIqlLHYyED/Z59W5vgPqJwqAINIaA7uyz4tvRpAXydvN lHDRglKsQzLDLBTdk17ZHdQxWLRuyo1g6eFUXQRELojYFwTmIU5UlGJ4hpjBCrCScSfQ D8Jw== X-Gm-Message-State: APjAAAV3jEaWfPLEPeZ9ke5dNcaMBy9BCqquXhCfGb2tFF3NAmEsVHwA Z8bF1DAv33m9+i2+3krhLX8UIbE/fwQ34w== X-Google-Smtp-Source: APXvYqwjgH43fJxi4Xchacrrw0QB9q+tDye+HCs3qzXFh0gW+EvWVOejAkOAoMn2xDgb/46aI7cmZg== X-Received: by 2002:a1c:6841:: with SMTP id d62mr5049068wmc.48.1569541648727; Thu, 26 Sep 2019 16:47:28 -0700 (PDT) Return-Path: Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id w12sm1847269wrg.47.2019.09.26.16.47.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Sep 2019 16:47:27 -0700 (PDT) Date: Fri, 27 Sep 2019 00:47:26 +0100 From: "Leif Lindholm" To: devel@edk2.groups.io, abner.chang@hpe.com Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 11/29] MdePkg/BaseCpuLib: RISC-V Base CPU library implementation. Message-ID: <20190926234726.GN25504@bivouac.eciton.net> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> <1569198715-31552-13-git-send-email-abner.chang@hpe.com> MIME-Version: 1.0 In-Reply-To: <1569198715-31552-13-git-send-email-abner.chang@hpe.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Sep 23, 2019 at 08:31:37AM +0800, Abner Chang wrote: > Implement RISC-V CPU related functions in BaseCpuLib. > > Signed-off-by: Abner Chang Reviewed-by: Leif Lindholm > --- > MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 6 +++++- > MdePkg/Library/BaseCpuLib/BaseCpuLib.uni | 5 +++-- > MdePkg/Library/BaseCpuLib/RiscV/Cpu.S | 19 +++++++++++++++++++ > 3 files changed, 27 insertions(+), 3 deletions(-) > create mode 100644 MdePkg/Library/BaseCpuLib/RiscV/Cpu.S > > diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf > index a7cb381..a95d8a0 100644 > --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf > +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf > @@ -7,6 +7,7 @@ > # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
> # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
> # Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
> +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -24,7 +25,7 @@ > > > # > -# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 > +# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64 > # > > [Sources.IA32] > @@ -59,6 +60,9 @@ > AArch64/CpuFlushTlb.asm | MSFT > AArch64/CpuSleep.asm | MSFT > > +[Sources.RISCV64] > + RiscV/Cpu.S > + > [Packages] > MdePkg/MdePkg.dec > > diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni b/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni > index fc95cda..85d56ce 100644 > --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni > +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni > @@ -1,12 +1,13 @@ > // /** @file > // Instance of CPU Library for various architecture. > // > -// CPU Library implemented using ASM functions for IA-32 and X64, > +// CPU Library implemented using ASM functions for IA-32, X64 and RISCV64, > // PAL CALLs for IPF, and empty functions for EBC. > // > // Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.
> // Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
> // Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
> +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> // > // SPDX-License-Identifier: BSD-2-Clause-Patent > // > @@ -15,5 +16,5 @@ > > #string STR_MODULE_ABSTRACT #language en-US "Instance of CPU Library for various architectures" > > -#string STR_MODULE_DESCRIPTION #language en-US "CPU Library implemented using ASM functions for IA-32 and X64, PAL CALLs for IPF, and empty functions for EBC." > +#string STR_MODULE_DESCRIPTION #language en-US "CPU Library implemented using ASM functions for IA-32, X64 and RISCV64, PAL CALLs for IPF, and empty functions for EBC." > > diff --git a/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S b/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S > new file mode 100644 > index 0000000..703b1e8 > --- /dev/null > +++ b/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S > @@ -0,0 +1,19 @@ > +//------------------------------------------------------------------------------ > +// > +// CpuSleep for RISC-V > +// > +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> +// SPDX-License-Identifier: BSD-2-Clause-Patent > +// > +//------------------------------------------------------------------------------ > +.data > +.align 3 > +.section .text > + > +.global ASM_PFX(_CpuSleep) > + > +ASM_PFX(_CpuSleep): > + wfi > + ret > + > + > -- > 2.7.4 > > > >