From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=wPEIr6+A; spf=pass (domain: linaro.org, ip: 209.85.128.65, mailfrom: leif.lindholm@linaro.org) Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by groups.io with SMTP; Sat, 28 Sep 2019 15:54:52 -0700 Received: by mail-wm1-f65.google.com with SMTP id 3so8940749wmi.3 for ; Sat, 28 Sep 2019 15:54:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=8tgV0Ul4GH00P7qxfapQMNnD0LnaOyQn4biLTj7EjNs=; b=wPEIr6+Asc/8iwyW4Nd2Ctw+RtOb6/ily06duqbeQiETGZDfuCMrvuuW34f8FHrij7 IW9aHDY1j+AhYK2PS+dRUJ7aRPS99l8N+pMkygZoPFPsvnQYkMQLDAx5loYDnkdqCQha a0sC66kT99p9fl5s3MFqN0eKDbf7VA8QGbsVygEsaclKgGuldsx8pidaBi+vexoP/dea zyNpQ3fIKAu4OGyBgwN6690CPOJhsbLXqsSRnH+ODHxdyDksnUER7hGo5n1kTFlb7xQQ YSx0FGENvWh7p92IpcCpbWcgHB+7tuRRoT01EZyJnbmj7Of648CIWSdrFxL5dVnt1NfG Erdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=8tgV0Ul4GH00P7qxfapQMNnD0LnaOyQn4biLTj7EjNs=; b=JSOyuFAQMXWA3kymCa2QVitijZhJ9BCjt4i8c+UHd/EHkGIEEobgRzEkTu2tb1isCi rOCltzYJ+zhdagqfrxpcMdI8H4l1N1LSlm/5cl97FuhI+EK4CpMXk3yNvBWLXbq+JGnL o3KkUfRe17wbi4Eplv8uwrxklqqLHo70LQre4k6EF+baCgSwLD61ayno8k6Rr3XZTD8+ w/b1boC7FJxgSY7NrbyZfmKc450qAYEXJlLvNYxXtR+tCFs/Zrx5rRk3Bd1HQebOEGeb O1RhjQDORn7YeaAG20cqXrSWFe5O2YMc8mHKOpXML89ykF6ILs4oEqzJCHMppWaqGbfb FLXw== X-Gm-Message-State: APjAAAVbNlzulERtprAwAKKaH8NsLmts/k/60VdMS7ae+EzZ1ws4e/Kx eXvfLX/0WsjJe1GpdfAYzM10nw== X-Google-Smtp-Source: APXvYqyman6vb3v656/3GnuMS0QNNqjoH93rdKVMVJCMxSuGev4naK4vIYhH/zo9Pjo4zudBVM570w== X-Received: by 2002:a1c:1b14:: with SMTP id b20mr11102272wmb.122.1569711290627; Sat, 28 Sep 2019 15:54:50 -0700 (PDT) Return-Path: Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id s10sm21291555wmf.48.2019.09.28.15.54.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Sep 2019 15:54:49 -0700 (PDT) Date: Sat, 28 Sep 2019 23:54:48 +0100 From: "Leif Lindholm" To: Marcin Wojtas Cc: devel@edk2.groups.io, ard.biesheuvel@linaro.org, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: Re: [edk2-platforms: PATCH] Marvell/Drivers: XenonDxe: Use new enums for SD card initialization Message-ID: <20190928225448.GW25504@bivouac.eciton.net> References: <1569596894-9601-1-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: <1569596894-9601-1-git-send-email-mw@semihalf.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Sep 27, 2019 at 05:08:14PM +0200, Marcin Wojtas wrote: > MdeModulePkg/SdMmcHcDxe update to use rev 3 of SdMmcOverrideProtocol > reworked SD card initialization and added new enums describing lower > speeds. Include this in XenonDxe, which fixes Armada70x0Db SD interface. > > Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Pushed as c2f593bde282. Thanks! > --- > Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c > index 7bfe240..6059cf8 100755 > --- a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c > +++ b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c > @@ -360,6 +360,8 @@ XenonPhySlowMode ( > if (((Timing == SdMmcUhsSdr50) || > (Timing == SdMmcUhsSdr25) || > (Timing == SdMmcUhsSdr12) || > + (Timing == SdMmcSdDs) || > + (Timing == SdMmcSdHs) || > (Timing == SdMmcMmcHsDdr) || > (Timing == SdMmcMmcHsSdr) || > (Timing == SdMmcMmcLegacy)) && SlowMode) { > @@ -396,7 +398,7 @@ XenonSetPhy ( > Var &= ~(EMMC5_1_FC_CMD_PD | EMMC5_1_FC_DQ_PD); > XenonHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_PAD_CONTROL1, FALSE, SDHC_REG_SIZE_4B, &Var); > > - if (Timing == SdMmcUhsSdr12) { > + if (Timing == SdMmcUhsSdr12 || Timing == SdMmcSdDs) { > if (SlowMode) { > XenonHcRwMmio (PciIo, SD_BAR_INDEX, EMMC_PHY_TIMING_ADJUST, TRUE, SDHC_REG_SIZE_4B, &Var); > Var |= QSN_PHASE_SLOW_MODE_BIT; > @@ -749,7 +751,7 @@ XenonInit ( > > // Set lowest clock and the PHY for the initialization phase > XenonSetClk (PciIo, XENON_MMC_BASE_CLK); > - Status = XenonSetPhy (PciIo, SlowMode, TuningStepDivisor, SdMmcUhsSdr12); > + Status = XenonSetPhy (PciIo, SlowMode, TuningStepDivisor, SdMmcSdDs); > if (EFI_ERROR (Status)) { > return Status; > } > -- > 2.7.4 >