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From: "Leif Lindholm" <leif.lindholm@linaro.org>
To: devel@edk2.groups.io, abner.chang@hpe.com
Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 16/29] RiscVPkg/Library: Add RISC-V exception library
Date: Mon, 30 Sep 2019 20:15:41 +0100	[thread overview]
Message-ID: <20190930191541.GA25504@bivouac.eciton.net> (raw)
In-Reply-To: <1569198715-31552-18-git-send-email-abner.chang@hpe.com>

On Mon, Sep 23, 2019 at 08:31:42AM +0800, Abner Chang wrote:
> Initial RISC-V Supervisor Mode trap handler
> 
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
>  .../RiscVExceptionLib/CpuExceptionHandler.S        |  88 ++++++++++
>  .../CpuExceptionHandlerDxeLib.inf                  |  42 +++++
>  .../RiscVExceptionLib/CpuExceptionHandlerLib.c     | 182 +++++++++++++++++++++
>  .../RiscVExceptionLib/CpuExceptionHandlerLib.uni   |  13 ++
>  4 files changed, 325 insertions(+)
>  create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.S
>  create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
>  create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
>  create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni
> 
> diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.S b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.S
> new file mode 100644
> index 0000000..cffe485
> --- /dev/null
> +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.S

Since the actual handling is done elsewhere, would CpuExceptionEntry.S
be a more descriptive filename?

> @@ -0,0 +1,88 @@
> +/** @file
> +  RISC-V Processor supervisor mode trap handler
> +
> +  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Base.h>
> +#include <RiscV.h>
> +#include <sbi/riscv_asm.h>
> +#include <sbi/riscv_encoding.h>
> +#include <sbi/sbi_platform.h>
> +#include <sbi/sbi_scratch.h>
> +#include <sbi/sbi_trap.h>
> +
> +  .align 3
> +  .section .entry, "ax", %progbits
> +  .globl _strap_handler
> +_strap_handler:

Please rename this one:
- Drop _ from function name.
- Rename to proper CamelCase. Suggest: SupervisorTrapHandler.

> +  addi sp, sp, -34*8

Please add spaces around '*', throughout.

> + /* Save all general regisers except SP and T0 */
> +  sd    ra, 1*8(sp)
> +  sd    gp, 2*8(sp)
> +  sd    tp, 3*8(sp)
> +  sd    t1, 4*8(sp)
> +  sd    t2, 5*8(sp)
> +  sd    s0, 6*8(sp)
> +  sd    s1, 7*8(sp)
> +  sd    a0, 8*8(sp)
> +  sd    a1, 9*8(sp)
> +  sd    a2, 10*8(sp)
> +  sd    a3, 11*8(sp)
> +  sd    a4, 12*8(sp)
> +  sd    a5, 13*8(sp)
> +  sd    a6, 14*8(sp)
> +  sd    a7, 15*8(sp)
> +  sd    s2, 16*8(sp)
> +  sd    s3, 17*8(sp)
> +  sd    s4, 18*8(sp)
> +  sd    s5, 19*8(sp)
> +  sd    s6, 20*8(sp)
> +  sd    s7, 21*8(sp)
> +  sd    s8, 22*8(sp)
> +  sd    s9, 23*8(sp)
> +  sd    s10, 24*8(sp)
> +  sd    s11, 25*8(sp)
> +  sd    t3, 26*8(sp)
> +  sd    t4, 27*8(sp)
> +  sd    t5, 28*8(sp)
> +  sd    t6, 29*8(sp)
> +
> +  /* Call C routine */

Something like "Call main trap handling routine in x.c" would be more
helpful.

> +  call  RiscVSupervisorModeTrapHandler
> +
> +  /* Restore all general regisers except SP and T0 */
> +  ld    ra, 1*8(sp)
> +  ld    gp, 2*8(sp)
> +  ld    tp, 3*8(sp)
> +  ld    t1, 4*8(sp)
> +  ld    t2, 5*8(sp)
> +  ld    s0, 6*8(sp)
> +  ld    s1, 7*8(sp)
> +  ld    a0, 8*8(sp)
> +  ld    a1, 9*8(sp)
> +  ld    a2, 10*8(sp)
> +  ld    a3, 11*8(sp)
> +  ld    a4, 12*8(sp)
> +  ld    a5, 13*8(sp)
> +  ld    a6, 14*8(sp)
> +  ld    a7, 15*8(sp)
> +  ld    s2, 16*8(sp)
> +  ld    s3, 17*8(sp)
> +  ld    s4, 18*8(sp)
> +  ld    s5, 19*8(sp)
> +  ld    s6, 20*8(sp)
> +  ld    s7, 21*8(sp)
> +  ld    s8, 22*8(sp)
> +  ld    s9, 23*8(sp)
> +  ld    s10, 24*8(sp)
> +  ld    s11, 25*8(sp)
> +  ld    t3, 26*8(sp)
> +  ld    t4, 27*8(sp)
> +  ld    t5, 28*8(sp)
> +  ld    t6, 29*8(sp)
> +  addi sp, sp, 34*8
> +  sret
> diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
> new file mode 100644
> index 0000000..e5871dc
> --- /dev/null
> +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
> @@ -0,0 +1,42 @@
> +## @file
> +#  RISC-V CPU Exception Handler Library
> +#
> +#  Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +
> +[Defines]
> +  INF_VERSION                    = 0x0001001b
> +  BASE_NAME                      = CpuExceptionHandlerLib
> +  MODULE_UNI_FILE                = CpuExceptionHandlerLib.uni
> +  FILE_GUID                      = 16309FCF-E900-459C-B071-052118394D11
> +  MODULE_TYPE                    = DXE_DRIVER
> +  VERSION_STRING                 = 1.0
> +  LIBRARY_CLASS                  = CpuExceptionHandlerLib
> +  CONSTRUCTOR                    = CpuExceptionHandlerLibConstructor
> +
> +#
> +# The following information is for reference only and not required by the build tools.
> +#
> +#  VALID_ARCHITECTURES           = RISCV64
> +#
> +
> +[Sources.RISCV64]
> +  CpuExceptionHandler.S
> +
> +[Sources.common]
> +  CpuExceptionHandlerLib.c
> +
> +[LibraryClasses]
> +  UefiBootServicesTableLib
> +  BaseLib
> +  DebugLib
> +  RiscVCpuLib
> +
> +[Packages]
> +  MdePkg/MdePkg.dec
> +  MdeModulePkg/MdeModulePkg.dec
> +  RiscVPkg/RiscVPkg.dec

Please sort LibraryClasses and Packages alphabetically.

> +
> diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
> new file mode 100644
> index 0000000..8c75be0
> --- /dev/null
> +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
> @@ -0,0 +1,182 @@
> +/** @file
> +  RISC-V Exception Handler library implementition.
> +
> +  Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <PiPei.h>
> +#include <Library/CpuExceptionHandlerLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/RiscVCpuLib.h>
> +#include <sbi/sbi_types.h>
> +#include <sbi/riscv_asm.h>
> +#include <sbi/riscv_encoding.h>

Please sort sbi includes alphabetically.

> +
> +
> +extern void _strap_handler(void);

Please add this to a local include file.

> +EFI_CPU_INTERRUPT_HANDLER gInterruptHandlers[2];

This (thankfully) seems to be global to the local file only.
Could it be renamed with a 'm' prefix and given STATIC attribute?

> +/**
> +  Initializes all CPU exceptions entries and provides the default exception handlers.
> +
> +  Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
> +  persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
> +  If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL.
> +  If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
> +
> +  @param[in]  VectorInfo    Pointer to reserved vector list.
> +
> +  @retval EFI_SUCCESS           CPU Exception Entries have been successfully initialized
> +                                with default exception handlers.
> +  @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
> +  @retval EFI_UNSUPPORTED       This function is not supported.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +InitializeCpuExceptionHandlers (
> +  IN EFI_VECTOR_HANDOFF_INFO       *VectorInfo OPTIONAL
> +  )
> +{
> +  return EFI_SUCCESS;
> +}
> +
> +/**
> +  Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers.
> +
> +  Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
> +  persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
> +  If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL.
> +  If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
> +
> +  @param[in]  VectorInfo    Pointer to reserved vector list.
> +
> +  @retval EFI_SUCCESS           All CPU interrupt/exception entries have been successfully initialized
> +                                with default interrupt/exception handlers.
> +  @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
> +  @retval EFI_UNSUPPORTED       This function is not supported.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +InitializeCpuInterruptHandlers (
> +  IN EFI_VECTOR_HANDOFF_INFO       *VectorInfo OPTIONAL
> +  )
> +{
> +  return EFI_SUCCESS;
> +}
> +
> +/**
> +  Registers a function to be called from the processor interrupt handler.
> +
> +  This function registers and enables the handler specified by InterruptHandler for a processor
> +  interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
> +  handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
> +  The installed handler is called once for each processor interrupt or exception.
> +  NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or
> +  InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED returned.
> +
> +  @param[in]  InterruptType     Defines which interrupt or exception to hook.
> +  @param[in]  InterruptHandler  A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
> +                                when a processor interrupt occurs. If this parameter is NULL, then the handler
> +                                will be uninstalled.
> +
> +  @retval EFI_SUCCESS           The handler for the processor interrupt was successfully installed or uninstalled.
> +  @retval EFI_ALREADY_STARTED   InterruptHandler is not NULL, and a handler for InterruptType was
> +                                previously installed.
> +  @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not
> +                                previously installed.
> +  @retval EFI_UNSUPPORTED       The interrupt specified by InterruptType is not supported,
> +                                or this function is not supported.
> +**/
> +EFI_STATUS
> +EFIAPI
> +RegisterCpuInterruptHandler (
> +  IN EFI_EXCEPTION_TYPE            InterruptType,
> +  IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler
> +  )
> +{
> +
> +  DEBUG ((DEBUG_INFO, "RegisterCpuInterruptHandler: Type:%x Handler: %x\n", InterruptType, InterruptHandler));
> +  gInterruptHandlers[InterruptType] = InterruptHandler;
> +  return EFI_SUCCESS;
> +}
> +/**
> +  Machine mode trap handler.
> +
> +**/
> +VOID
> +RiscVSupervisorModeTrapHandler (
> +  VOID
> +  )
> +{
> +  EFI_SYSTEM_CONTEXT RiscVSystemContext;
> +
> +  //
> +  // Check scasue register.
> +  //
> +  if(gInterruptHandlers[EXCEPT_RISCV_TIMER_INT] != NULL) {
> +    gInterruptHandlers[EXCEPT_RISCV_TIMER_INT](EXCEPT_RISCV_TIMER_INT, (CONST EFI_SYSTEM_CONTEXT)RiscVSystemContext);
> +  }
> +}
> +
> +/**
> +  Initializes all CPU exceptions entries with optional extra initializations.
> +
> +  By default, this method should include all functionalities implemented by
> +  InitializeCpuExceptionHandlers(), plus extra initialization works, if any.
> +  This could be done by calling InitializeCpuExceptionHandlers() directly
> +  in this method besides the extra works.
> +
> +  InitData is optional and its use and content are processor arch dependent.
> +  The typical usage of it is to convey resources which have to be reserved
> +  elsewhere and are necessary for the extra initializations of exception.
> +
> +  @param[in]  VectorInfo    Pointer to reserved vector list.
> +  @param[in]  InitData      Pointer to data optional for extra initializations
> +                            of exception.
> +
> +  @retval EFI_SUCCESS             The exceptions have been successfully
> +                                  initialized.
> +  @retval EFI_INVALID_PARAMETER   VectorInfo or InitData contains invalid
> +                                  content.
> +  @retval EFI_UNSUPPORTED         This function is not supported.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +InitializeCpuExceptionHandlersEx (
> +  IN EFI_VECTOR_HANDOFF_INFO            *VectorInfo OPTIONAL,
> +  IN CPU_EXCEPTION_INIT_DATA            *InitData OPTIONAL
> +  )
> +{
> +  return InitializeCpuExceptionHandlers (VectorInfo);
> +}
> +
> +/**
> +  The constructor function to initial interrupt handlers in
> +  RISCV_MACHINE_MODE_CONTEXT.
> +
> +  @param  ImageHandle   The firmware allocated handle for the EFI image.
> +  @param  SystemTable   A pointer to the EFI System Table.
> +
> +  @retval EFI_SUCCESS   The destructor completed successfully.
> +  @retval Other value   The destructor did not complete successfully.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +CpuExceptionHandlerLibConstructor (
> +  IN EFI_HANDLE        ImageHandle,
> +  IN EFI_SYSTEM_TABLE  *SystemTable
> +  )
> +{
> +  //
> +  // Set Superviosr mode trap handler.
> +  //
> +  csr_write(CSR_STVEC, _strap_handler);
> +
> +  return EFI_SUCCESS;
> +}
> diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni
> new file mode 100644
> index 0000000..00cca22
> --- /dev/null
> +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni
> @@ -0,0 +1,13 @@
> +// /** @file
> +//
> +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +//
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +// **/
> +
> +
> +#string STR_MODULE_ABSTRACT             #language en-US "RISC-V CPU Exception Handler Librarys."
> +
> +#string STR_MODULE_DESCRIPTION          #language en-US "RISC-V CPU Exception Handler Librarys."

Library.

/
    Leif

> +
> -- 
> 2.7.4
> 
> 
> 
> 

  reply	other threads:[~2019-09-30 19:15 UTC|newest]

Thread overview: 108+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-23  0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 01/29] RiscVPkg: RISC-V processor package Abner Chang
2019-09-26 22:26   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 02/29] RiscVPkg/Include: Add header files of RISC-V CPU package Abner Chang
2019-09-26 22:29   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 03/29] RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support Abner Chang
2019-09-26 22:41   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 04/29] MdePkg: RISC-V RV64 binding in MdePkg Abner Chang
2019-09-26 22:44   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 05/29] MdePkg/Include: RISC-V definitions Abner Chang
2019-09-26 22:45   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 06/29] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch Abner Chang
2019-09-26 22:46   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 07/29] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor Abner Chang
2019-09-26 22:56   ` [edk2-devel] " Leif Lindholm
2019-10-14 16:47     ` Abner Chang
2019-10-14 18:23       ` Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation Abner Chang
2019-10-01  8:44   ` [edk2-devel] " Philippe Mathieu-Daudé
2019-09-23  0:31 ` Abner Chang
2019-09-26 23:30   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 09/29] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions Abner Chang
2019-09-26 23:39   ` [edk2-devel] " Leif Lindholm
2019-10-01  8:49     ` Philippe Mathieu-Daudé
2019-10-01  9:07       ` Leif Lindholm
2019-10-02  1:30         ` Abner Chang
2019-10-02  9:13           ` Leif Lindholm
2019-10-02 16:14             ` Abner Chang
2019-10-02 16:27               ` Andrew Fish
2019-10-02 16:35                 ` Leif Lindholm
2019-10-03  0:52                   ` Abner Chang
2019-10-03  8:38                     ` Leif Lindholm
2019-10-03 11:34                       ` Abner Chang
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 10/29] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code Abner Chang
2019-09-26 23:46   ` [edk2-devel] " Leif Lindholm
2019-10-15  4:02     ` Abner Chang
2019-10-15 10:31       ` Leif Lindholm
2019-10-15 10:56         ` Abner Chang
     [not found]     ` <15CDB6324F411B37.30896@groups.io>
2019-10-15  4:26       ` Abner Chang
2019-10-15 10:41         ` Leif Lindholm
2019-10-15 10:59           ` Abner Chang
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 11/29] MdePkg/BaseCpuLib: RISC-V Base CPU library implementation Abner Chang
2019-09-26 23:47   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 12/29] MdePkg/BaseSynchronizationLib: RISC-V cache related code Abner Chang
2019-09-27  0:19   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 13/29] MdeModulePkg/Logo Abner Chang
2019-09-30 22:51   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 14/29] NetworkPkg Abner Chang
2019-09-30 22:51   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 15/29] RiscVPkg/Library: RISC-V CPU library Abner Chang
2019-09-30 18:31   ` [edk2-devel] " Leif Lindholm
2019-10-15  2:32     ` Abner Chang
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 16/29] RiscVPkg/Library: Add RISC-V exception library Abner Chang
2019-09-30 19:15   ` Leif Lindholm [this message]
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 17/29] RiscVPkg/Library: Add RISC-V timer library Abner Chang
2019-09-30 19:46   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 18/29] RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library Abner Chang
2019-09-30 20:03   ` [edk2-devel] " Leif Lindholm
2019-10-15  1:21     ` Abner Chang
2019-10-15  8:35       ` Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 19/29] RiscVPkg/Library: RISC-V platform level DxeIPL libraries Abner Chang
2019-09-30 20:15   ` [edk2-devel] " Leif Lindholm
2019-09-30 20:44     ` Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 20/29] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL Abner Chang
2019-09-30 20:31   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 21/29] RiscVPkg/PeiServicesTablePointerLibOpenSbi: RISC-V PEI Service Table Pointer library Abner Chang
2019-09-30 20:54   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 22/29] RiscVPkg/RiscVPlatformTempMemoryInit: RISC-V Platform Temporary Memory library Abner Chang
2019-09-30 20:56   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 23/29] RiscVPkg/CpuDxe: Add RISC-V CPU DXE driver Abner Chang
2019-09-30 21:11   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 24/29] BaseTools: BaseTools changes for RISC-V platform Abner Chang
2019-09-26 22:09   ` [edk2-devel] " Leif Lindholm
2019-10-15  6:18     ` Abner Chang
2019-10-15 10:56       ` Leif Lindholm
2019-10-15 11:13         ` Abner Chang
2019-10-16  5:06         ` Abner Chang
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 25/29] BaseTools/Scripts Abner Chang
2019-09-26 20:50   ` [edk2-devel] " Leif Lindholm
2019-10-15  6:31     ` Abner Chang
2019-10-15 11:00       ` Leif Lindholm
2019-10-15 11:03         ` Abner Chang
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 26/29] RiscVPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms Abner Chang
2019-09-30 22:39   ` [edk2-devel] " Leif Lindholm
2019-10-14 11:27     ` Abner Chang
2019-10-14 11:56       ` Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 27/29] edk2-staging/RISC-V-V2: Add submodule Abner Chang
2019-09-26 22:24   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 28/29] edk2-staging/RISC-V-V2: Add ReadMe Abner Chang
2019-09-30 22:48   ` [edk2-devel] " Leif Lindholm
2019-09-23  0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 29/29] edk2-staging: Update Maintainers.txt Abner Chang
2019-09-30 22:50   ` [edk2-devel] " Leif Lindholm
     [not found] ` <15C6EB9824DD2A88.29693@groups.io>
2019-09-24  1:52   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 04/29] MdePkg: RISC-V RV64 binding in MdePkg Abner Chang
     [not found] ` <15C6EB994C26E5C4.2053@groups.io>
2019-09-24  1:52   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 05/29] MdePkg/Include: RISC-V definitions Abner Chang
     [not found] ` <15C6EB9950232DB5.29693@groups.io>
2019-09-24  1:53   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 07/29] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor Abner Chang
     [not found] ` <15C6EB9A049FF8A4.24160@groups.io>
2019-09-24  1:54   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 09/29] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions Abner Chang
     [not found] ` <15C6EB9B3E887BEB.29693@groups.io>
2019-09-24  1:55   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 13/29] MdeModulePkg/Logo Abner Chang
     [not found] ` <15C6EB9A40C408A0.24160@groups.io>
2019-09-24  1:56   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 10/29] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code Abner Chang
     [not found] ` <15C6EB9B872A5B83.24160@groups.io>
2019-09-24  1:57   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 14/29] NetworkPkg Abner Chang
     [not found] ` <15C6EB99CBC780B5.2053@groups.io>
2019-09-24  1:57   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation Abner Chang
     [not found] ` <15C6EB9A9BD83853.2053@groups.io>
2019-09-24  1:58   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 11/29] MdePkg/BaseCpuLib: RISC-V Base CPU library implementation Abner Chang
     [not found] ` <15C6EB9AEB7BB057.24160@groups.io>
2019-09-24  1:58   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 12/29] MdePkg/BaseSynchronizationLib: RISC-V cache related code Abner Chang
     [not found] ` <15C6EB99608359A3.24160@groups.io>
2019-09-24  1:59   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation Abner Chang
     [not found] ` <15C6EB9D6C0EC3B0.29693@groups.io>
2019-09-24  2:00   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 20/29] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL Abner Chang
     [not found] ` <15C6EB98AD6CCCEB.24160@groups.io>
2019-09-24  2:01   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 06/29] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch Abner Chang
     [not found] ` <15C6EB9F04387439.29693@groups.io>
2019-09-24  2:02   ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 25/29] BaseTools/Scripts Abner Chang
2019-09-26 22:22 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Leif Lindholm
2019-10-15  6:39   ` Abner Chang

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