From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=GMKoGGFL; spf=pass (domain: linaro.org, ip: 209.85.128.66, mailfrom: leif.lindholm@linaro.org) Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66]) by groups.io with SMTP; Mon, 30 Sep 2019 12:46:26 -0700 Received: by mail-wm1-f66.google.com with SMTP id p7so754838wmp.4 for ; Mon, 30 Sep 2019 12:46:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=/9K1RsJAl7T2sH1TW9hsgp1BrzWFiiNUkI3w4fh/ulw=; b=GMKoGGFLojbuQVt+RnYDY3cmI6OOhVN3yIdnCVCQgDkCkdpOYVj1afsGbHLY561iSc N0fPAxupNiO70N4Px/3dYIaXRceP4d1J0rcYvhbyxf6qcwsYNUbbN3KQWyKloFx1w8Wk nN0q0dyOmmkP3bAu6rtHGCx4+Z53+5qKa2XijElb7TPwSBVQ/QCkVNdtMflK9GFYg0cb 24cf2ScYikloyFKeCDJ932iaY23n9sl/HjhKkKjggBKXbGBY2bQRIpwp8UjYncovzWPK YZs1/Gp+6lVQFth3E2lAjXFJEeFlUvseS4W0mpxzaQFLVe4/CzpUScoXZWitT46Igh0P nlnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=/9K1RsJAl7T2sH1TW9hsgp1BrzWFiiNUkI3w4fh/ulw=; b=IqsVT46d6omlolm3BFsYhlMvtTJNa6xnljpkx89TV3BRd80m3xwMZ9V82Vtsyzu6kf RBYhzb0sclipdlJjluXHuuZo7Q5H4pRSFBF97vfnT2bMlxkavYvJ1dOySW5T8h1XPlZi 1W4QkvwdOPYSRxj6Dp+gsq+xwW2GC4wUKZMtUmtvGZEy4nQzz0UcJjMLjBwkvdfgLby3 DWkw+M1zTCbxLDjDyhGzj1bHUjdWq5FwKvqGK3ManYf4fylHZZJEG0ufnmCa5glKRgPq cJA9coDKl1D9cBgB3CSN8WkvbgdTH5rfEqVaN6Mdc7z7a4cnrZFuRPXMcGE2FipFpWf8 EQGw== X-Gm-Message-State: APjAAAWqwuaZMVJSP/LnWxiFhgxbM4428mNwqqleHYsV8lHcUojAs+G/ YwkFvc0orCeNuwbkib5ronUOlBVIEkU= X-Google-Smtp-Source: APXvYqyuAp3QhOQ6BoH/wPMqnnSnTFbZ8NMsSjbk7qKfyNIgzUmHUC1sg1yevwSCGKZQZGgw3u3OEw== X-Received: by 2002:a1c:9988:: with SMTP id b130mr660292wme.164.1569872784443; Mon, 30 Sep 2019 12:46:24 -0700 (PDT) Return-Path: Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id e9sm1063888wme.3.2019.09.30.12.46.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2019 12:46:23 -0700 (PDT) Date: Mon, 30 Sep 2019 20:46:22 +0100 From: "Leif Lindholm" To: devel@edk2.groups.io, abner.chang@hpe.com Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 17/29] RiscVPkg/Library: Add RISC-V timer library Message-ID: <20190930194622.GB25504@bivouac.eciton.net> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> <1569198715-31552-19-git-send-email-abner.chang@hpe.com> MIME-Version: 1.0 In-Reply-To: <1569198715-31552-19-git-send-email-abner.chang@hpe.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Sep 23, 2019 at 08:31:43AM +0800, Abner Chang wrote: > Timer library for RISC-V > > Signed-off-by: Abner Chang > --- > .../Library/RiscVTimerLib/BaseRiscVTimerLib.inf | 34 ++++ > RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c | 195 +++++++++++++++++++++ > RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h | 21 +++ > RiscVPkg/RiscVPkg.dec | 9 + > 4 files changed, 259 insertions(+) > create mode 100644 RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf > create mode 100644 RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c > create mode 100644 RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h > > diff --git a/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf b/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf > new file mode 100644 > index 0000000..af27049 > --- /dev/null > +++ b/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf > @@ -0,0 +1,34 @@ > +## @file > +# RISC-V Timer Library Instance. > +# > +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + INF_VERSION = 0x0001001b > + BASE_NAME = BaseRiscVTimerLib > + FILE_GUID = FB648CF5-91BE-4737-9023-FD807AC6D96D > + MODULE_TYPE = BASE > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = TimerLib > + > +[Sources] > + RiscVTimerLib.c > + > +[Packages] > + MdePkg/MdePkg.dec > + RiscVPkg/RiscVPkg.dec > + > +[Pcd] > + gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerTickInNanoSecond > + gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz > + > +[LibraryClasses] > + BaseLib > + PcdLib > + RiscVCpuLib > + RiscVPlatformTimerLib > + > diff --git a/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c b/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c > new file mode 100644 > index 0000000..acb8c77 > --- /dev/null > +++ b/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c > @@ -0,0 +1,195 @@ > +/** @file > + RISC-V instance of Timer Library. > + > + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > + > +/** > + Stalls the CPU for at least the given number of ticks. > + > + Stalls the CPU for at least the given number of ticks. It's invoked by > + MicroSecondDelay() and NanoSecondDelay(). > + > + @param Delay A period of time to delay in ticks. > + > +**/ > +VOID > +InternalRiscVTimerDelay ( > + IN UINT32 Delay > + ) > +{ > + UINT32 Ticks; > + UINT32 Times; > + > + Times = Delay >> (RISCV_TIMER_COMPARE_BITS - 2); > + Delay &= (( 1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1); > + do { > + // > + // The target timer count is calculated here > + // > + Ticks = RiscVReadMachineTimer () + Delay; > + Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2); > + while (((Ticks - RiscVReadMachineTimer ()) & ( 1 << (RISCV_TIMER_COMPARE_BITS - 1))) == 0) { > + CpuPause (); > + } > + } while (Times-- > 0); > +} > + > +/** > + Stalls the CPU for at least the given number of microseconds. > + > + Stalls the CPU for the number of microseconds specified by MicroSeconds. > + > + @param MicroSeconds The minimum number of microseconds to delay. > + > + @return MicroSeconds > + > +**/ > +UINTN > +EFIAPI > +MicroSecondDelay ( > + IN UINTN MicroSeconds > + ) > +{ > + InternalRiscVTimerDelay ( > + (UINT32)DivU64x32 ( > + MultU64x32 ( > + MicroSeconds, > + PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz) > + ), > + 1000000u > + ) > + ); > + return MicroSeconds; > +} > + > +/** > + Stalls the CPU for at least the given number of nanoseconds. > + > + Stalls the CPU for the number of nanoseconds specified by NanoSeconds. > + > + @param NanoSeconds The minimum number of nanoseconds to delay. > + > + @return NanoSeconds > + > +**/ > +UINTN > +EFIAPI > +NanoSecondDelay ( > + IN UINTN NanoSeconds > + ) > +{ > + InternalRiscVTimerDelay ( > + (UINT32)DivU64x32 ( > + MultU64x32 ( > + NanoSeconds, > + PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz) > + ), > + 1000000000u > + ) > + ); > + return NanoSeconds; > +} > + > +/** > + Retrieves the current value of a 64-bit free running performance counter. > + > + Retrieves the current value of a 64-bit free running performance counter. The > + counter can either count up by 1 or count down by 1. If the physical > + performance counter counts by a larger increment, then the counter values > + must be translated. The properties of the counter can be retrieved from > + GetPerformanceCounterProperties(). > + > + @return The current value of the free running performance counter. > + > +**/ > +UINT64 > +EFIAPI > +GetPerformanceCounter ( > + VOID > + ) > +{ > + return (UINT64)RiscVReadMachineTimer (); > +} > + > +/**return > + Retrieves the 64-bit frequency in Hz and the range of performance counter > + values. > + > + If StartValue is not NULL, then the value that the performance counter starts > + with immediately after is it rolls over is returned in StartValue. If > + EndValue is not NULL, then the value that the performance counter end with > + immediately before it rolls over is returned in EndValue. The 64-bit > + frequency of the performance counter in Hz is always returned. If StartValue > + is less than EndValue, then the performance counter counts up. If StartValue > + is greater than EndValue, then the performance counter counts down. For > + example, a 64-bit free running counter that counts up would have a StartValue > + of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter > + that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0. > + > + @param StartValue The value the performance counter starts with when it > + rolls over. > + @param EndValue The value that the performance counter ends with before > + it rolls over. > + > + @return The frequency in Hz. > + > +**/ > +UINT64 > +EFIAPI > +GetPerformanceCounterProperties ( > + OUT UINT64 *StartValue, OPTIONAL > + OUT UINT64 *EndValue OPTIONAL > + ) > +{ > + if (StartValue != NULL) { > + *StartValue = 0; > + } > + > + if (EndValue != NULL) { > + *EndValue = 32 - 1; > + } > + > + return PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz); > +} > + > +/** > + Converts elapsed ticks of performance counter to time in nanoseconds. > + > + This function converts the elapsed ticks of running performance counter to > + time value in unit of nanoseconds. > + > + @param Ticks The number of elapsed ticks of running performance counter. > + > + @return The elapsed time in nanoseconds. > + > +**/ > +UINT64 > +EFIAPI > +GetTimeInNanoSecond ( > + IN UINT64 Ticks > + ) > +{ > + UINT64 NanoSeconds; > + UINT32 Remainder; > + > + // > + // Ticks > + // Time = --------- x 1,000,000,000 > + // Frequency > + // > + NanoSeconds = MultU64x32 (DivU64x32Remainder (Ticks, PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz), &Remainder), 1000000000u); > + > + // > + // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder * 1,000,000,000) > + // will not overflow 64-bit. > + // > + NanoSeconds += DivU64x32 (MultU64x32 ((UINT64) Remainder, 1000000000u), PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)); > + > + return NanoSeconds; > +} > diff --git a/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h b/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h > new file mode 100644 > index 0000000..bac3a70 > --- /dev/null > +++ b/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h > @@ -0,0 +1,21 @@ > +/** @file > + RISC-V timer library definitions. > + > + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > + > +#ifndef _RISCV_TIMER_LIB_INTERNAL_H_ > +#define _RISCV_TIMER_LIB_INTERNAL_H_ > + > +#include > +#include > +#include > +#include > + > +#include This header file includes only include statements. Please delete the file and move the includes to the .c file, sorted alphabtically. / Leif > + > +#endif // _RISCV_TIMER_LIB_INTERNAL_H_ > diff --git a/RiscVPkg/RiscVPkg.dec b/RiscVPkg/RiscVPkg.dec > index 74314e8..a91392f 100644 > --- a/RiscVPkg/RiscVPkg.dec > +++ b/RiscVPkg/RiscVPkg.dec > @@ -23,5 +23,14 @@ > [Guids] > gUefiRiscVPkgTokenSpaceGuid = { 0x4261e9c8, 0x52c0, 0x4b34, { 0x85, 0x3d, 0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}} > > +[PcdsFixedAtBuild] > + # > + # 1000000000 > + # PcdRiscVMachineTimerTickInNanoSecond = --------------------------------------- > + # PcdRiscVMachineTimerFrequencyInHerz > + # > + gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerTickInNanoSecond|100|UINT64|0x00001010 > + gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz|10000000|UINT64|0x00001011 > + > [UserExtensions.TianoCore."ExtraFiles"] > RiscVPkgExtra.uni > -- > 2.7.4 > > > >