From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=ZGTypulr; spf=pass (domain: linaro.org, ip: 209.85.221.65, mailfrom: leif.lindholm@linaro.org) Received: from mail-wr1-f65.google.com (mail-wr1-f65.google.com [209.85.221.65]) by groups.io with SMTP; Mon, 30 Sep 2019 13:31:44 -0700 Received: by mail-wr1-f65.google.com with SMTP id a11so12851753wrx.1 for ; Mon, 30 Sep 2019 13:31:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=gFp/r6ql1EUGJSv/MxnF7tWZXh/SljgIDvZTVKn0+YE=; b=ZGTypulrshgbZsp+uJ8zNWCLp+4XLQxF3tHbcWbf2fpZexFxhspiEu+YLzsE4/PR5n aOjgZEMOuXB43tWisr4kSXP0z04hPdhK69FOLAWa1rXKn13X6TKkfmPUsirysMXxb2Gn oBPqJifyNnoMdeBGppMa4ocn3j1tkey6NtYz8eLRVj+jfK0arWz/tvhgB4ZyutoNcfz+ E/E6EPEJmujOA652FSIHNTowSR/BSjElpvy+Ii5i02P0UW1zDMA8UcEncJxB49dkeXGf FRDLlNsiIQevsWwiJLDa9ADlAUZqpkJa16ECcz/RbDn6NGFI6ZJORUXGAnixAPdq/9+F kQgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=gFp/r6ql1EUGJSv/MxnF7tWZXh/SljgIDvZTVKn0+YE=; b=BPyz3HHK8xfErdLydGUUt6isIsOl6ftQhfTaPFnwcwuriJ1kbllBnHlLnSN3bb2mci IHWQ8fN33+0Un3Lruuc4rAx28N9snbzCkwjmzoUqQPzb8Y0wbvzf/S8Nb74DBYHjgFWe oKH0djy8E/CF6dvRyJSntpe1guFbi2zS68kers3LAUapU9GFzAPpV1uQ6aMcEVB/wlWn yEYyMQdAHEkvE1SwWmcsBhEd16CKrwe7XMYQQ/eg7Z00F+tQpv9z0sv3MrXUoHjxm2i+ Gmu4/GO7ZUkW7d6JB8UNbYDQ/OVFIjnG5LUCPPotK5CSvB99T0ROCPW/txEmeKM8FTLV PKPw== X-Gm-Message-State: APjAAAWVQUFst/jjmg9r0hHj003PvqIfbBvoi2p+p/9pQkHKPcjcWlY7 dD/hWssldqf6wZ9F3KkS4yHmHVuc5NI= X-Google-Smtp-Source: APXvYqza9GUQ2PDGye/PlNfOjfXATnRhlh0uUQXdX7HbidrWxLM4eogqc3IWH5XP7YTybbMm8CoDaA== X-Received: by 2002:a5d:5384:: with SMTP id d4mr14132617wrv.255.1569875501882; Mon, 30 Sep 2019 13:31:41 -0700 (PDT) Return-Path: Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id t4sm14307572wrm.13.2019.09.30.13.31.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2019 13:31:41 -0700 (PDT) Date: Mon, 30 Sep 2019 21:31:39 +0100 From: "Leif Lindholm" To: devel@edk2.groups.io, abner.chang@hpe.com Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 20/29] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL Message-ID: <20190930203139.GE25504@bivouac.eciton.net> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> <1569198715-31552-22-git-send-email-abner.chang@hpe.com> MIME-Version: 1.0 In-Reply-To: <1569198715-31552-22-git-send-email-abner.chang@hpe.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Sep 23, 2019 at 08:31:46AM +0800, Abner Chang wrote: > Implementation of RISC-V platform level DxeIPL > > Signed-off-by: Abner Chang > --- > MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 13 +++- > MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c | 71 ++++++++++++++++++++++ > RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h | 41 +++++++++++++ > 3 files changed, 124 insertions(+), 1 deletion(-) > create mode 100644 MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c > create mode 100644 RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h > > diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf > index 98bc17f..5532323 100644 > --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf > +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf > @@ -7,6 +7,7 @@ > # > # Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
> # Copyright (c) 2017, AMD Incorporated. All rights reserved.
> +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -25,7 +26,7 @@ > # > # The following information is for reference only and not required by the build tools. > # > -# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only) AARCH64 > +# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only) AARCH64 RISCV64 > # > > [Sources] > @@ -49,6 +50,9 @@ > [Sources.ARM, Sources.AARCH64] > Arm/DxeLoadFunc.c > > +[Sources.RISCV64] > + RiscV64/DxeLoadFunc.c > + > [Packages] > MdePkg/MdePkg.dec > MdeModulePkg/MdeModulePkg.dec > @@ -56,6 +60,9 @@ > [Packages.ARM, Packages.AARCH64] > ArmPkg/ArmPkg.dec > > +[Packages.RISCV64] > + RiscVPkg/RiscVPkg.dec > + > [LibraryClasses] > PcdLib > MemoryAllocationLib > @@ -75,6 +82,10 @@ > [LibraryClasses.ARM, LibraryClasses.AARCH64] > ArmMmuLib > > +[LibraryClasses.RISCV64] > + RiscVPlatformDxeIplLib > + RiscVOpensbiLib > + > [Ppis] > gEfiDxeIplPpiGuid ## PRODUCES > gEfiPeiDecompressPpiGuid ## PRODUCES > diff --git a/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c b/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c > new file mode 100644 > index 0000000..d3c7f9d > --- /dev/null > +++ b/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c > @@ -0,0 +1,71 @@ > +/** @file > + RISC-V specific functionality for DxeLoad. > + > + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include "DxeIpl.h" > +#include "Library/RiscVPlatformDxeIpl.h" Please use <>. (Yes, I know all other architectures do this wrong in this module.) > + > +typedef > +VOID* > +(EFIAPI *DXEENTRYPOINT) ( > + IN VOID *HobStart > + ); > + > +/** > + Transfers control to DxeCore. > + > + This function performs a CPU architecture specific operations to execute > + the entry point of DxeCore with the parameters of HobList. > + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase. > + > + @param DxeCoreEntryPoint The entry point of DxeCore. > + @param HobList The start of HobList passed to DxeCore. > + > +**/ > +VOID > +HandOffToDxeCore ( > + IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint, > + IN EFI_PEI_HOB_POINTERS HobList > + ) > +{ > + VOID *BaseOfStack; > + VOID *TopOfStack; > + EFI_STATUS Status; > + // > + // > + // Allocate 128KB for the Stack > + // > + BaseOfStack = AllocatePages (EFI_SIZE_TO_PAGES (STACK_SIZE)); > + ASSERT (BaseOfStack != NULL); I think this deserves a DEBUG_ERROR message as well, given that we're now also about to start overwriting things at some small offset from address 0. > + > + // > + // Compute the top of the stack we were allocated. Pre-allocate a UINTN > + // for safety. > + // > + TopOfStack = (VOID *) ((UINTN) BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT); > + TopOfStack = ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT); > + > + // > + // End of PEI phase signal > + // > + Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi); > + ASSERT_EFI_ERROR (Status); > + Probably also deserves an ERROR. > + // > + // Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore. > + // > + UpdateStackHob ((EFI_PHYSICAL_ADDRESS)(UINTN) BaseOfStack, STACK_SIZE); > + > + DEBUG ((DEBUG_INFO, "DXE Core new stack at %x, stack pointer at %x\n", BaseOfStack, TopOfStack)); > + > + // > + // Transfer the control to the entry point of DxeCore. > + // > + RiscVPlatformHandOffToDxeCore (BaseOfStack, TopOfStack, DxeCoreEntryPoint, HobList); > +} > + > diff --git a/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h b/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h > new file mode 100644 > index 0000000..4763397 > --- /dev/null > +++ b/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h > @@ -0,0 +1,41 @@ > +/** @file > + Header file of RISC-V platform DXE IPL > + > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP.All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _RISC_V_PLATFORM_DXEIPL_H_ > +#define _RISC_V_PLATFORM_DXEIPL_H_ Please drop leading _. / Leif > + > +typedef struct { > + VOID *TopOfStack; > + VOID *BaseOfStack; > + EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint; > + EFI_PEI_HOB_POINTERS HobList; > +} OPENSBI_SWITCH_MODE_CONTEXT; > + > +/** > + RISC-V platform DXE IPL to DXE core handoff process. > + > + This function performs a CPU architecture specific operations to execute > + the entry point of DxeCore with the parameters of HobList. > + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase. > + > + @param BaseOfStack Base address of stack > + @param TopOfStack Top address of stack > + @param DxeCoreEntryPoint The entry point of DxeCore. > + @param HobList The start of HobList passed to DxeCore. > + > +**/ > + > +VOID > +RiscVPlatformHandOffToDxeCore ( > + IN VOID *BaseOfStack, > + IN VOID *TopOfStack, > + IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint, > + IN EFI_PEI_HOB_POINTERS HobList > + ); > +#endif > + > -- > 2.7.4 > > > >