From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=s5CaEA5+; spf=pass (domain: linaro.org, ip: 209.85.128.65, mailfrom: leif.lindholm@linaro.org) Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by groups.io with SMTP; Mon, 30 Sep 2019 15:48:25 -0700 Received: by mail-wm1-f65.google.com with SMTP id y21so1122980wmi.0 for ; Mon, 30 Sep 2019 15:48:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=Gah3hwbCaTirBk570n9yXL2AjKryOd6yBLAVb80qBjU=; b=s5CaEA5+wU9gLjcexZZ/JwkXHm6f/Nq8RQM14LfO/VHuaSsVmraW6+l9XhMGPZeRfH tdw849Hdez4JLM2PHqZz0Q+Nbs7XPwAK0j76+mo/1yuTiL+eEBhhe8RXyHqkbYMW3nsB WYiN/u5V6mujXiVkEDgMgUH44DNmnJaYwyF+pMGOGd0F7i+P3CiEvwvR2EXXEQ/kgbSh s9xe54FePbss0Io+KU/FF/btgK9Wif2iaNLOxGtbO5bco1IIapJpCPUFx8mnZeBC7OZP C6uA2/XNywGclm2kh8BClFPb7P8qbFa9goL4GwrAINGCphq9DWRqw/5ijc62YgZ1HezH Ym3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=Gah3hwbCaTirBk570n9yXL2AjKryOd6yBLAVb80qBjU=; b=PcU3M8c18Phjq3WK67KSbRra30R/sR6CL/Gwytr+0rvTI0ktqnpCm0ZgbYmNF+TO/5 LhqRZD6THwcrufMtwnk+e6K3LzsKrUp9ctIrTE9V0+mrGg12QH8mly5dq+daAruJQ7z3 IsE1JVWve9oPz0vEAtKV86mcnE0NnyDF0BPUWhEJJZNYcQflN/XqqfWa/3uHwkosc63k 53AvUogQipAjXMEiateWw7bmZM7/72mnydaSZku/l/KwZklSq4aA4rZN/oOVXRJr/J8v 1K3WldyxHtcXG5FG1+WAG4dKMLdquRs6n2qcspmfM7nQOtG21b6DAC5fpLSIZkpQy8wM P7MQ== X-Gm-Message-State: APjAAAVXSvkEkl3zVyAQGhXBNhkWC4Im9sbDIhU/K1A8CIskOe7DstoJ l/OvOUyjST97qJsrsOnupbk9b7lBuq0= X-Google-Smtp-Source: APXvYqwleTwmibSxW8tXUpfqZgu/J2LOJXjzbOucuJk5PzJOogrtJdpXAts0aPYm/RKZPGA08Xt8Fg== X-Received: by 2002:a1c:9ec9:: with SMTP id h192mr1050435wme.105.1569883703387; Mon, 30 Sep 2019 15:48:23 -0700 (PDT) Return-Path: Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id j1sm30356428wrg.24.2019.09.30.15.48.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Sep 2019 15:48:22 -0700 (PDT) Date: Mon, 30 Sep 2019 23:48:21 +0100 From: "Leif Lindholm" To: devel@edk2.groups.io, abner.chang@hpe.com Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 28/29] edk2-staging/RISC-V-V2: Add ReadMe Message-ID: <20190930224821.GK25504@bivouac.eciton.net> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> <1569198715-31552-30-git-send-email-abner.chang@hpe.com> MIME-Version: 1.0 In-Reply-To: <1569198715-31552-30-git-send-email-abner.chang@hpe.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Sep 23, 2019 at 08:31:54AM +0800, Abner Chang wrote: > Add RiscVEdk2Readme.md > > Signed-off-by: Abner Chang > --- > RiscVEdk2Readme.md | 34 ++++++++++++++++++++++++++++++++++ > 1 file changed, 34 insertions(+) > create mode 100644 RiscVEdk2Readme.md > > diff --git a/RiscVEdk2Readme.md b/RiscVEdk2Readme.md > new file mode 100644 > index 0000000..ec691fe > --- /dev/null > +++ b/RiscVEdk2Readme.md > @@ -0,0 +1,34 @@ > +This branch is used to contribute RISC-V architecture to EDK2 > + > +The branch owner:
No HTML tags please > +Abner Chang < abner.chang@hpe.com >
> +Gilbert Chen < gilbert.chen@hpe.com > > + > +## RISC-V EDK2 Port Introduction > +RISC-V is an open ISA which was designed to support research and education of computer architecture, but now it becomes > +a standard open Instruction Set Architecture for industry implementations. The RISC-V edk2 project is to create a new processor binding in UEFI spec and have the RISC-V edk2 implementation. The goal is to have RISC-V edk2 port as the firmware reference > +for RISC-V platforms. Please reflow the document to 80 character line length. Please also add a link to this document from the top of Readme.md. > + > +This branch (RISC-V-V2) on edk2-staging is RISC-V edk2 port with RISC-V OpenSbi (https://github.com/riscv/opensbi) library integrated. RiscVPkg provides the generic and common modules of RISC-V prcessor. The first edk2 RISC-V platform is SiFive U500 FPGA whcih is maintained in U500Pkg under Platform/RiscV/SiFive in edk2-platform repository. > + > +## RISC-V EDK2 Package > +``` > +RiscVPkg - RISC-V processor package. This package provides RISC-V processor related protocols/libraries accroding > + to UEFI specification and edk2 implementations. > +``` > +## Toolchain of RISC-V EDK2 port > +To build edk2 RISC-V platform requires GCC RISC-V toolchain, So far so good. > refer > to https://github.com/riscv/riscv-gnu-toolchain for the details. Postponing the full resolution of the issue in order to enable others to start working this is fine, but this should not be presented as a normal part of development. Suggest staing something like: "Due to not yet tracked down bugs, only the following toolchain is known to produce bootable binaries." > The > commit ID 64879b24 of riscv-gnu-toolchain repository is verified to > build RISC-V edk2 platform and boot to EFI SHELL successfully. With which toolchain has it been successfully built? On which Linux distribution? Or on cygwin? Or both? / Leif > You have to clone the toolchain from above link and check out commit:64879b24 for building RISC-V edk2 port. The commit later than 64879b24 causes system hangs at the PEI phase to DXE phase transition. We are still figuring out the root cause. > + > +## EDK2 Build Target > +"RISCV64" ARCH is the RISC-V architecture which currently supported and verified. The verified RISC-V toolchain is https://github.com/riscv/riscv-gnu-toolchain @64879b24 as mentioned above, toolchain tag is "GCC5" which is declared in tools_def.txt.
> +Below is the edk2 build options for building RISC-V RV64 platform,
> +``` > +build -a RISCV64 -p Platform/{Vendor}/{Platform}/{Platform}.dsc -t GCC5 > +``` > +For example,
> +``` > +build -a RISCV64 -p Platform/SiFive/U500/U500.dsc -t GCC5 > +``` > + > +Make sure RISC-V toolchain is built succesfully and the toolchain binaries are generated in somewhere you specified when building toolchain. 'GCC5_RISCV64_PREFIX' is the cross compilation prefix to toolchain binraries.
> +For example, set 'GCC5_RISCV64_PREFIX' to '~/RiscVToolchain/riscv64-unknown-elf-' before you build RISC-V edk2 port. > -- > 2.7.4 > > > >