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Date: Tue, 1 Oct 2019 22:14:38 +0100
From: "Leif Lindholm" <leif.lindholm@linaro.org>
To: devel@edk2.groups.io, gilbert.chen@hpe.com
Subject: Re: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 02/14] Silicon/SiFive: Add library module of SiFive RISC-V cores
Message-ID: <20191001211438.GX25504@bivouac.eciton.net>
References: <20190919035131.4700-1-gilbert.chen@hpe.com>
 <20190919035131.4700-3-gilbert.chen@hpe.com>
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On Thu, Sep 19, 2019 at 11:51:19AM +0800, Gilbert Chen wrote:
> Initial version of SiFive RISC-V core libraries. Library of each core
>  creates processor core SMBIOS data hob for building SMBIOS
>  records in DXE phase.

So yes, this implementation needs to change.
These should all implement the same LibraryClass.
Also, U54 appears to be a simple superset of U51.

What I would suggest is creating a
Silicon/SiFive/Library/SiFiveCoreInfoLib, which calls into a
SiFiveSoCCoreInfoLib in Silicon/SiFive/<SoC>/Library, providing the
acual SoC-specific bits.

/
    Leif

> Signed-off-by: Gilbert Chen <gilbert.chen@hpe.com>
> ---
>  .../E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c    | 242 +++++++++++++++++
>  .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf        |  51 ++++
>  .../U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c    | 294 +++++++++++++++++++++
>  .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf        |  51 ++++
>  .../Library/PeiCoreInfoHobLib/CoreInfoHob.c        | 185 +++++++++++++
>  .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf        |  50 ++++
>  6 files changed, 873 insertions(+)
>  create mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
>  create mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
>  create mode 100644 Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
>  create mode 100644 Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
>  create mode 100644 Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c
>  create mode 100644 Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf