From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=mBMr7FFG; spf=pass (domain: linaro.org, ip: 209.85.128.48, mailfrom: leif.lindholm@linaro.org) Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) by groups.io with SMTP; Wed, 02 Oct 2019 02:07:46 -0700 Received: by mail-wm1-f48.google.com with SMTP id v17so6085678wml.4 for ; Wed, 02 Oct 2019 02:07:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=cDeK9n8kZtLc7L24qmIEKMOXx555XK8OjS7zfrXbW/4=; b=mBMr7FFG93MEXMMhUrsDFIo/MHY2NDVtOluddJjt30b+cV2gcfKUzNc4Kk1ouGwEH4 2P9BsuUKEYjlVwvyN6OwMkFLCQkklDqmrFnc71VVlKebJ2KcFGQGm4OQu4dwVNAbIZ3h IA1ZMiJpgTQPA218K+Qi1eJrDA4l10oMre2f7gPz2AqB9MUHRTV5uBaDfxLb84TsbQGL d3Z9NkkTrVUCJLUP7MHRMF/LihIUgMF7PZ5HC1zxZehuFC+YzjZ2k9QIrPBTiAPt28Pa XC5XG4IXtuE0Fz9m1LahIrmar82dlQiY116VqvO/L58p08ZqGrZPmIaxkpUSvG3fA+Iz eckg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=cDeK9n8kZtLc7L24qmIEKMOXx555XK8OjS7zfrXbW/4=; b=Wbzp4WEEx6sNC7siLaGyeOFK388Cc2xkniFiyMGnSpBCh9JFSrEjM2e9+UbVthvqf7 TlFQ+z9mgKsH7NKs7jUjFNbI+5SPTAR6178SDn1Gzqy/yYOqofdU+NoUiqpNv5A1tj1M qjtUdx84qLR+JPXeNPpxOPgrzuNOzNWO5t/kDWTNo3CjRvOTNUupVv/wsoRtDEiTsDcJ Q0ojc+KgtZ0GbkQIxYTLNZpCb6zvzLtwqcHNPS9iPFwQ/lWwxrDJ5GbYuyqepaGRVGjG OBwMrIAOD/ZuF9av6IQs6UnLXH3oXzp0bh8jhzcp6h2XDQxikg8fhl1wS5c0u4bdiy7J n/sw== X-Gm-Message-State: APjAAAXAOV50Fb1MvNqh8061Fj0oWozovzpYuNHvwhp9yZCVG8fZhQKe xoVVKsXUCGuTmKK0SwFnkxTCsO3pw3g= X-Google-Smtp-Source: APXvYqylV8Y5qnYnG4j5s/8mS1n6Ut7yVwVctabP4EhiERYuoEsNrxm9R1yEeWftsZ1w/PlKlclXbw== X-Received: by 2002:a1c:1a4b:: with SMTP id a72mr1985181wma.44.1570007264456; Wed, 02 Oct 2019 02:07:44 -0700 (PDT) Return-Path: Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id d4sm19699837wrq.22.2019.10.02.02.07.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Oct 2019 02:07:43 -0700 (PDT) Date: Wed, 2 Oct 2019 10:07:41 +0100 From: "Leif Lindholm" To: devel@edk2.groups.io, gilbert.chen@hpe.com Subject: Re: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 03/14] platforms/RiscV: Initial version of RISC-V platform package Message-ID: <20191002090741.GY25504@bivouac.eciton.net> References: <20190919035131.4700-1-gilbert.chen@hpe.com> <20190919035131.4700-4-gilbert.chen@hpe.com> MIME-Version: 1.0 In-Reply-To: <20190919035131.4700-4-gilbert.chen@hpe.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Sep 19, 2019 at 11:51:20AM +0800, Gilbert Chen wrote: > Initial version of RISC-V platform package which provides the common > libraries, drivers, PCD and etc. for RISC-V platform development. > > Signed-off-by: Gilbert Chen > --- > Platform/RiscV/Readme.md | 89 ++++++++++++++++++++++++++++++++ > Platform/RiscV/RiscVPlatformPkg.dec | 72 ++++++++++++++++++++++++++ > Platform/RiscV/RiscVPlatformPkg.uni | 15 ++++++ > Platform/RiscV/RiscVPlatformPkgExtra.uni | 12 +++++ > 4 files changed, 188 insertions(+) > create mode 100644 Platform/RiscV/Readme.md > create mode 100644 Platform/RiscV/RiscVPlatformPkg.dec > create mode 100644 Platform/RiscV/RiscVPlatformPkg.uni > create mode 100644 Platform/RiscV/RiscVPlatformPkgExtra.uni > > diff --git a/Platform/RiscV/Readme.md b/Platform/RiscV/Readme.md > new file mode 100644 > index 00000000..277782e3 > --- /dev/null > +++ b/Platform/RiscV/Readme.md Please also add a link to this file from the top-level Readme.md. High up since this is intended for a branch specifically for this. > @@ -0,0 +1,89 @@ > +# Introduction > + > +## EDK2 RISC-V Platform Package > +RISC-V platform package provides the generic and common modules for RISC-V platforms. RISC-V platform package could include RiscPlatformPkg.dec to use the common drivers, libraries, definitions, PCDs and etc. for the platform development. Please wrap lines at max 80 characters. > + > +## EDK2 RISC-V Platforms > +RISC-V platform is created and maintained by RISC-V platform vendors. The directory of RISC-V platform should be created under Platform/RiscV. Vendor should create the folder under Platform/RiscV and name it using vendor name, under the vendor folder is the platform folder named by platform model name, code name or etc. (e.g. Platform/RiscV/SiFive/U500Pkg) > + > +## Build EDK2 RISC-V Platforms > +RISC-V platform package should provide EDK2 metafiles under RISC-V platform package folder (Platform/RiscV/{Vendor}/{Platform}). Build RISC-V platform package against edk2 and follow the build guidence mentioned in Readme.md under below link.
OK, so we reach this topic here for the first time. We don't have a Platforms/ARM and we don't have a Platforms/X86, so I don't want to see a Platforms/RiscV. The paths should be Platforms/Vendor. I will comment on the patch adding the code where the content currently there should go. > +https://github.com/tianocore/edk2-platforms
> + > +### Download the sources ### > +``` > +git clone https://github.com/tianocore/edk2-staging.git > +# Checkout RISC-V-V2 branch > +git clone https://github.com/tianocore/edk2-platforms.git > +# Checkout devel-riscv-v2 branch > +git clone https://github.com/tianocore/edk2-non-osi.git > +``` > + > +### Requirements > +Build EDK2 RISC-V platform requires GCC RISC-V toolchain. Refer to https://github.com/riscv/riscv-gnu-toolchain for the details. Please add all of the missing details I pointed out for the Readme.md on the edks-staging branch. > +The commit ID 64879b24 is verified to build RISC-V EDK2 platform and boot to EFI SHELL successfully. > + > +### EDK2 project > +Currently, the EDK2 RISC-V platform can only build with edk2 project in **edk2-staging/RISC-V-V2** branch. The build architecture whcih is supported and verified so far is "RISCV64". The verified RISC-V toolchain is https://github.com/riscv/riscv-gnu-toolchain @64879b24, toolchain tag is "GCCRISCV" declared in tools_def.txt
It's GCC5 now, not GCCRISCV. > + > +### Linux Build Instructions > +You can build the RISC-V platform using below script,
> +`build -a RISCV64 -p Platform/{Vendor}/{Platform}/{Platform}.dsc -t GCCRISCV` > + > +Or modify target.txt to set up your build parameters. Which target.txt? > + > +## RISC-V Platform PCD settings > +### EDK2 Firmware Volume Settings > +EDK2 Firmware volume related PCDs which declared in platform FDF file. > + > +| **PCD name** |**Usage**| > +|----------------|----------| > +|PcdRiscVSecFvBase| The base address of SEC Firmware Volume| > +|PcdRiscVSecFvSize| The size of SEC Firmware Volume| > +|PcdRiscVPeiFvBase| The base address of SEC Firmware Volume| > +|PcdRiscVPeiFvSize| The size of SEC Firmware Volume| PEI Firmware Volume > +|PcdRiscVDxeFvBase| The base address of SEC Firmware Volume| > +|PcdRiscVDxeFvSize| The size of SEC Firmware Volume| DXE Firmware Volume > + > +### EDK2 EFI Variable Region Settings > +The PCD settings regard to EFI Variable > + > +| **PCD name** |**Usage**| > +|----------------|----------| > +|PcdVariableFdBaseAddress| The EFI variable firmware device base address| > +|PcdVariableFdSize| The EFI variable firmware device size| > +|PcdVariableFdBlockSize| The block size of EFI variable firmware device| > +|PcdPlatformFlashNvStorageVariableBase| EFI variable base address within firmware device| > +|PcdPlatformFlashNvStorageFtwWorkingBase| The base address of EFI variable fault tolerance worksapce (FTW) within firmware device| > +|PcdPlatformFlashNvStorageFtwSpareBase| The base address of EFI variable spare FTW within firmware device| > + > +### RISC-V Physical Memory Protection (PMP) Region Settings > +Below PCDs could be set in platform FDF file. > + > +| **PCD name** |**Usage**| > +|----------------|----------| > +|PcdFwStartAddress| The starting address of firmware region to protected by PMP| > +|PcdFwEndAddress| The ending address of firmware region to protected by PMP| > + > +### RISC-V Processor HART Settings > + > +| **PCD name** |**Usage**| > +|----------------|----------| > +|PcdHartCount| Number of RISC-V HARTs, the value is processor-implementation specific| > +|PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and boot system to OS| > + > +### RISC-V OpenSBI Settings > + > +| **PCD name** |**Usage**| > +|----------------|----------| > +|PcdScratchRamBase| The base address of OpenSBI scratch buffer for all RISC-V HARTs| > +|PcdScratchRamSize| The total size of OpenSBI scratch buffer for all RISC-V HARTs| > +|PcdOpenSbiStackSize| The size of initial stack of each RISC-V HART for booting system use OpenSBI| > +|PcdTemporaryRamBase| The base address of temporary memory for PEI phase| > +|PcdTemporaryRamSize| The temporary memory size for PEI phase| > + > +## Supported Operating Systems > +Only support to boot to EFI Shell so far > + > +## Known Issues and Limitations > +Only RISC-V RV64 is verified > diff --git a/Platform/RiscV/RiscVPlatformPkg.dec b/Platform/RiscV/RiscVPlatformPkg.dec > new file mode 100644 > index 00000000..3ce16bfc > --- /dev/null > +++ b/Platform/RiscV/RiscVPlatformPkg.dec I think all of this content should either go into: Silicon/SiFive/SiFive.dec or /RiscVPkg/RiscVPkg.dec / Leif > @@ -0,0 +1,72 @@ > +## @file RiscVPlatformPkg.dec > +# This Package provides UEFI RISC-V platform modules and libraries. > +# > +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + DEC_SPECIFICATION = 0x00010005 > + PACKAGE_NAME = RiscPlatformPkg > + PACKAGE_UNI_FILE = RiscPlatformPkg.uni > + PACKAGE_GUID = 6A67AF99-4592-40F8-B6BE-62BCA10DA1EC > + PACKAGE_VERSION = 1.0 > + > +[Includes] > + Include > + > +[LibraryClasses] > + > +[LibraryClasses.RISCV32, LibraryClasses.RISCV64] > + > +[Guids] > + gUefiRiscVPlatformPkgTokenSpaceGuid = {0x6A67AF99, 0x4592, 0x40F8, { 0xB6, 0xBE, 0x62, 0xBC, 0xA1, 0x0D, 0xA1, 0xEC}} > + > +[PcdsFixedAtBuild] > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvBase|0x0|UINT32|0x00001000 > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvSize|0x0|UINT32|0x00001001 > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase|0x0|UINT32|0x00001002 > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize|0x0|UINT32|0x00001003 > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|0x0|UINT32|0x00001004 > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize|0x0|UINT32|0x00001005 > + > +# > +# Definition of EFI Variable region > +# > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress|0|UINT32|0x00001010 > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize|0|UINT32|0x00001011 > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize|0|UINT32|0x00001012 > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBase|0|UINT32|0x00001013 > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingBase|0|UINT32|0x00001014 > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBase|0|UINT32|0x00001015 > +# > +# Firmware region which is protected by PMP. > +# > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwBlockSize|0|UINT32|0x00001020 > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress|0|UINT32|0x00001021 > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress|0|UINT32|0x00001022 > +# > +# Definition of RISC-V Hart > +# > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount|0|UINT32|0x00001023 > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId|0|UINT32|0x00001024 > +# > +# Definitions for OpenSbi > +# > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase|0|UINT32|0x00001025 > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize|0|UINT32|0x00001026 > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize|0|UINT32|0x00001027 > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase|0|UINT32|0x00001028 > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize|0|UINT32|0x00001029 > + > +[PcdsPatchableInModule] > + > +[PcdsFeatureFlag] > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable|FALSE|BOOLEAN|0x00001006 > + > +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] > + > +[UserExtensions.TianoCore."ExtraFiles"] > + RiscVPlatformPkgExtra.uni > diff --git a/Platform/RiscV/RiscVPlatformPkg.uni b/Platform/RiscV/RiscVPlatformPkg.uni > new file mode 100644 > index 00000000..deb91fa1 > --- /dev/null > +++ b/Platform/RiscV/RiscVPlatformPkg.uni > @@ -0,0 +1,15 @@ > +// /** @file > +// RISC-V Package Localized Strings and Content. > +// > +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> +// > +// SPDX-License-Identifier: BSD-2-Clause-Patent > +// > +// **/ > + > + > +#string STR_PACKAGE_ABSTRACT #language en-US "Provides UEFI compatible RISC-V platform modules and libraries" > + > +#string STR_PACKAGE_DESCRIPTION #language en-US "This Package provides UEFI compatible RISC-V platform modules and libraries." > + > + > diff --git a/Platform/RiscV/RiscVPlatformPkgExtra.uni b/Platform/RiscV/RiscVPlatformPkgExtra.uni > new file mode 100644 > index 00000000..98d81aed > --- /dev/null > +++ b/Platform/RiscV/RiscVPlatformPkgExtra.uni > @@ -0,0 +1,12 @@ > +// /** @file > +// RISC-V Package Localized Strings and Content. > +// > +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> +// > +// SPDX-License-Identifier: BSD-2-Clause-Patent > +// > +// **/ > + > +#string STR_PROPERTIES_PACKAGE_NAME > +#language en-US > +"RiscV platform package" > -- > 2.12.0.windows.1 > > > >