From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=smUAaANz; spf=pass (domain: linaro.org, ip: 209.85.221.44, mailfrom: leif.lindholm@linaro.org) Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) by groups.io with SMTP; Thu, 03 Oct 2019 10:38:30 -0700 Received: by mail-wr1-f44.google.com with SMTP id y19so3681794wrd.3 for ; Thu, 03 Oct 2019 10:38:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=s1d7CRsh650Gy2y+CV8uIpXrML/IdbIUDNi6sCL6fvc=; b=smUAaANzXr6xHQvnWQkEEsJd8VVfps2xnzfqUfyyHbgL37YZxHbkeoINTRYsGKsSg5 S2Jd+gFibsrHDkwrYXYWYwkxlmUnga7LosBat163gbBHduV8dqcx5cYQG8Nx3YK8fCR4 ubLklrVs6tWfkCjq7Ncf1b7/FQpeGjEolTrsBk8NVefEUYHlgA589xSbZh6VVYHxlirU kHlk/Idi/yH+Nb3fcCjiUNurWiJnynYZrBuwf7n7bqH6pwWnbHr7JwOys57OxqclNLF0 q1/BCvYKS8NPkI89Le6Gt81x4iQS6GDOkgB8gWnvDYnuw0j0IoSMt9DkUVlq4Q/YptVV DIVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=s1d7CRsh650Gy2y+CV8uIpXrML/IdbIUDNi6sCL6fvc=; b=I6nioXwF2QhSEjQlL6xoOv4socrkUPxEOWWWFydPlF8cxYcfFPjvW/ciDBsa0rwMWm UoMZUZ9scYevXuUFrcn1ARzKBLPKXaC8Hjg8mEQ9prUfFvfzWFwXDpkWlPV15iFYNWFg k/YwD5BpdQKp7Tbj5XAALzu/uPfFd9SO45E5HyWjALpeOXYlZreBdOI5LgIjmFMVTX3l vnDtAT7hKn7b4a6urTauzwKM0M8bi5lA4QlzA7PPe7p6CICNDZWFoZoitINirkFc6LWl +HuDGi/bWvidX8eSJCv/NGX8KZqcSB0VdH6GcRLEo7By8GLw/pCXOMLbEEAbtq1q0NKq w4Nw== X-Gm-Message-State: APjAAAXdWCMe8fxa2IlVB0S8eeu+v45ucXOTq15OLzaZNSExqOsLvpbQ P4kW916DN2jbbyvdAtvLvk4FafMyYio= X-Google-Smtp-Source: APXvYqxSYsnqdxWvKg1f25tF1aPuDOdCh2V5UHz7zLmdUVyFkUFWz6tPcnEXfSFPSlkNJ/LCfYC6mA== X-Received: by 2002:adf:8b13:: with SMTP id n19mr8558736wra.203.1570124307674; Thu, 03 Oct 2019 10:38:27 -0700 (PDT) Return-Path: Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id b144sm2178722wmb.3.2019.10.03.10.38.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2019 10:38:26 -0700 (PDT) Date: Thu, 3 Oct 2019 18:38:25 +0100 From: "Leif Lindholm" To: devel@edk2.groups.io, gilbert.chen@hpe.com Cc: Palmer Dabbelt Subject: Re: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 13/14] U500Pkg/PlatformPei: Platform initialization PEIM Message-ID: <20191003173825.GR25504@bivouac.eciton.net> References: <20190919035131.4700-1-gilbert.chen@hpe.com> <20190919035131.4700-14-gilbert.chen@hpe.com> MIME-Version: 1.0 In-Reply-To: <20190919035131.4700-14-gilbert.chen@hpe.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Sep 19, 2019 at 11:51:30AM +0800, Gilbert Chen wrote: > This is the platform-implementation specific library which is executed > in early PEI phase for platform initialization. > > Signed-off-by: Gilbert Chen > --- > .../SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c | 49 ++++ > .../U500Pkg/Universal/Pei/PlatformPei/MemDetect.c | 74 +++++ > .../U500Pkg/Universal/Pei/PlatformPei/Platform.c | 313 +++++++++++++++++++++ > .../U500Pkg/Universal/Pei/PlatformPei/Platform.h | 92 ++++++ > .../Universal/Pei/PlatformPei/PlatformPei.inf | 75 +++++ > 5 files changed, 603 insertions(+) > create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c > create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDetect.c > create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.c > create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.h > create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/PlatformPei.inf > > diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c > new file mode 100644 > index 00000000..74e4d433 > --- /dev/null > +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c > @@ -0,0 +1,49 @@ > +/** @file > + Build FV related hobs for platform. > + > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> + Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include "PiPei.h" > +#include "Platform.h" > +#include > +#include > +#include > +#include Please flip above two lines around. > + > +/** > + Publish PEI & DXE (Decompressed) Memory based FVs to let PEI > + and DXE know about them. > + > + @retval EFI_SUCCESS Platform PEI FVs were initialized successfully. > + > +**/ > +EFI_STATUS > +PeiFvInitialization ( > + VOID > + ) > +{ > + DEBUG ((DEBUG_INFO, "Platform PEI Firmware Volume Initialization\n")); > + // > + // Let DXE know about the DXE FV > + // > + BuildFvHob (PcdGet32 (PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize)); > + DEBUG ((DEBUG_INFO, "Platform builds DXE FV at %x, size %x.\n", PcdGet32 (PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize))); Please wrap long line. > + > + // > + // Let PEI know about the DXE FV so it can find the DXE Core > + // > + PeiServicesInstallFvInfoPpi ( > + NULL, > + (VOID *)(UINTN) PcdGet32 (PcdRiscVDxeFvBase), > + PcdGet32 (PcdRiscVDxeFvSize), > + NULL, > + NULL > + ); > + > + return EFI_SUCCESS; > +} > diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDetect.c b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDetect.c > new file mode 100644 > index 00000000..dc99f2e0 > --- /dev/null > +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDetect.c > @@ -0,0 +1,74 @@ > +/**@file > + Memory Detection for Virtual Machines. > + > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> + Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +Module Name: > + > + MemDetect.c > + > +**/ > + > +// > +// The package level header files this module uses > +// > +#include > + > +// > +// The Library classes this module consumes > +// > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "Platform.h" > + > + > +/** > + Publish PEI core memory > + > + @return EFI_SUCCESS The PEIM initialized successfully. > + > +**/ > +EFI_STATUS > +PublishPeiMemory ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + EFI_PHYSICAL_ADDRESS MemoryBase; > + UINT64 MemorySize; > + > + MemoryBase = 0x80000000UL + 0x1000000UL; > + MemorySize = 0x40000000UL - 0x1000000UL; //1GB - 16MB > + > + DEBUG((DEBUG_INFO, "%a: MemoryBase:0x%x MemorySize:%d\n", __FUNCTION__, MemoryBase, MemorySize)); > + > + // > + // Publish this memory to the PEI Core > + // > + Status = PublishSystemMemory(MemoryBase, MemorySize); > + ASSERT_EFI_ERROR (Status); > + > + return Status; > +} > + > +/** > + Publish system RAM and reserve memory regions > + > +**/ > +VOID > +InitializeRamRegions ( > + VOID > + ) > +{ > + AddMemoryRangeHob(0x81000000UL, 0x81000000UL + 0x3F000000UL); > + > +} > diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.c b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.c > new file mode 100644 > index 00000000..45356399 > --- /dev/null > +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.c > @@ -0,0 +1,313 @@ > +/**@file > + Platform PEI driver > + > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> + Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
> + Copyright (c) 2011, Andrei Warkentin > + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +// > +// The package level header files this module uses > +// > +#include > + > +// > +// The Library classes this module consumes > +// > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +#include "Platform.h" > + > +EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = { > + { EfiACPIMemoryNVS, 0x004 }, > + { EfiACPIReclaimMemory, 0x008 }, > + { EfiReservedMemoryType, 0x004 }, > + { EfiRuntimeServicesData, 0x024 }, > + { EfiRuntimeServicesCode, 0x030 }, > + { EfiBootServicesCode, 0x180 }, > + { EfiBootServicesData, 0xF00 }, > + { EfiMaxMemoryType, 0x000 } > +}; > + > + > +EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = { > + { > + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, > + &gEfiPeiMasterBootModePpiGuid, > + NULL > + } > +}; > + > +EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION; > + > +BOOLEAN mS3Supported = FALSE; Can any/all of the above global variables be made STATIC? > + > + > +VOID > +AddIoMemoryBaseSizeHob ( > + EFI_PHYSICAL_ADDRESS MemoryBase, > + UINT64 MemorySize > + ) > +{ > + BuildResourceDescriptorHob ( > + EFI_RESOURCE_MEMORY_MAPPED_IO, > + EFI_RESOURCE_ATTRIBUTE_PRESENT | > + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | > + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_TESTED, > + MemoryBase, > + MemorySize > + ); > +} > + > +VOID > +AddReservedMemoryBaseSizeHob ( > + EFI_PHYSICAL_ADDRESS MemoryBase, > + UINT64 MemorySize > + ) > +{ > + BuildResourceDescriptorHob ( > + EFI_RESOURCE_MEMORY_RESERVED, > + EFI_RESOURCE_ATTRIBUTE_PRESENT | > + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | > + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_TESTED, > + MemoryBase, > + MemorySize > + ); > +} > + > +VOID > +AddIoMemoryRangeHob ( > + EFI_PHYSICAL_ADDRESS MemoryBase, > + EFI_PHYSICAL_ADDRESS MemoryLimit > + ) > +{ > + AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); > +} > + > + > +VOID > +AddMemoryBaseSizeHob ( > + EFI_PHYSICAL_ADDRESS MemoryBase, > + UINT64 MemorySize > + ) > +{ > + BuildResourceDescriptorHob ( > + EFI_RESOURCE_SYSTEM_MEMORY, > + EFI_RESOURCE_ATTRIBUTE_PRESENT | > + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | > + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_TESTED, > + MemoryBase, > + MemorySize > + ); > +} > + > + > +VOID > +AddMemoryRangeHob ( > + EFI_PHYSICAL_ADDRESS MemoryBase, > + EFI_PHYSICAL_ADDRESS MemoryLimit > + ) > +{ > + AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); > +} > + > + > +VOID > +AddUntestedMemoryBaseSizeHob ( > + EFI_PHYSICAL_ADDRESS MemoryBase, > + UINT64 MemorySize > + ) > +{ > + BuildResourceDescriptorHob ( > + EFI_RESOURCE_SYSTEM_MEMORY, > + EFI_RESOURCE_ATTRIBUTE_PRESENT | > + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | > + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE, > + MemoryBase, > + MemorySize > + ); > +} > + > +VOID > +AddUntestedMemoryRangeHob ( > + EFI_PHYSICAL_ADDRESS MemoryBase, > + EFI_PHYSICAL_ADDRESS MemoryLimit > + ) > +{ > + AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); > +} > + > +VOID > +AddPciResource ( > + VOID > + ) > +{ > + // > + // Platform-specific > + // > +} > + > +VOID > +MemMapInitialization ( > + VOID > + ) > +{ > + // > + // Create Memory Type Information HOB > + // > + BuildGuidDataHob ( > + &gEfiMemoryTypeInformationGuid, > + mDefaultMemoryTypeInformation, > + sizeof(mDefaultMemoryTypeInformation) > + ); > + > + // > + // Add PCI IO Port space available for PCI resource allocations. > + // > + AddPciResource (); > +} > + > +VOID > +MiscInitialization ( > + VOID > + ) > +{ > + // > + // Build the CPU HOB with guest RAM size dependent address width and 16-bits > + // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during > + // S3 resume as well, so we build it unconditionally.) > + // > + BuildCpuHob (32, 32); > +} > + > +/** > + Check if system retunrs from S3. > + > + @return BOOLEAN TRUE, system returned from S3 > + FALSE, system is not returned from S3 > + > +**/ > +BOOLEAN > +CheckResumeFromS3 ( > + VOID > + ) > +{ > + // > + //Platform implementation-specific > + // > + return FALSE; > +} > + > + > +VOID > +BootModeInitialization ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + > + if (CheckResumeFromS3 () == TRUE) { > + DEBUG ((DEBUG_INFO, "This is wake from S3\n")); > + } else { > + DEBUG ((DEBUG_INFO, "This is normal boot\n")); > + } > + Status = PeiServicesSetBootMode (mBootMode); > + ASSERT_EFI_ERROR (Status); > + > + Status = PeiServicesInstallPpi (mPpiBootMode); > + ASSERT_EFI_ERROR (Status); > +} > + > +/** > + Build processor information for U54 Coreplex processor. > + > + @return EFI_SUCCESS Status. > + > +**/ > +EFI_STATUS > +BuildCoreInformationHob ( > + VOID > +) > +{ > + EFI_STATUS Status; > + RISC_V_PROCESSOR_SMBIOS_DATA_HOB *SmbiosHobPtr; > + > + Status = CreateU5MCCoreplexProcessorSpecificDataHob (0); > + if (EFI_ERROR (Status)) { > + ASSERT(FALSE); > + } > + Status = CreateU5MCProcessorSmbiosDataHob(0, &SmbiosHobPtr); > + if (EFI_ERROR (Status)) { > + ASSERT(FALSE); > + } > + > + DEBUG ((DEBUG_INFO, "U5 MC Coreplex SMBIOS DATA HOB at address 0x%x\n", SmbiosHobPtr)); > + > + return EFI_SUCCESS; > +} > + > +/** > + Perform Platform PEI initialization. > + > + @param FileHandle Handle of the file being invoked. > + @param PeiServices Describes the list of possible PEI Services. > + > + @return EFI_SUCCESS The PEIM initialized successfully. > + > +**/ > +EFI_STATUS > +EFIAPI > +InitializePlatform ( > + IN EFI_PEI_FILE_HANDLE FileHandle, > + IN CONST EFI_PEI_SERVICES **PeiServices > + ) > +{ > + EFI_STATUS Status; > + > + DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n")); > + > + BootModeInitialization (); > + DEBUG ((DEBUG_INFO, "Platform BOOT mode initiated.\n")); > + PublishPeiMemory (); > + DEBUG ((DEBUG_INFO, "PEI memory published.\n")); > + InitializeRamRegions (); > + DEBUG ((DEBUG_INFO, "Platform RAM regions initiated.\n")); > + > + if (mBootMode != BOOT_ON_S3_RESUME) { > + PeiFvInitialization (); > + MemMapInitialization (); > + } > + > + MiscInitialization (); > + Status = BuildCoreInformationHob (); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "Fail to build processor informstion HOB.\n")); > + ASSERT(FALSE); > + } > + return EFI_SUCCESS; > +} > diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.h b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.h > new file mode 100644 > index 00000000..23600203 > --- /dev/null > +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.h > @@ -0,0 +1,92 @@ > +/** @file > + Platform PEI module include file. > + > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> + Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef _PLATFORM_PEI_H_INCLUDED_ > +#define _PLATFORM_PEI_H_INCLUDED_ Please drop leading _. > + > +VOID > +AddIoMemoryBaseSizeHob ( > + EFI_PHYSICAL_ADDRESS MemoryBase, > + UINT64 MemorySize > + ); > + > +VOID > +AddIoMemoryRangeHob ( > + EFI_PHYSICAL_ADDRESS MemoryBase, > + EFI_PHYSICAL_ADDRESS MemoryLimit > + ); > + > +VOID > +AddMemoryBaseSizeHob ( > + EFI_PHYSICAL_ADDRESS MemoryBase, > + UINT64 MemorySize > + ); > + > +VOID > +AddMemoryRangeHob ( > + EFI_PHYSICAL_ADDRESS MemoryBase, > + EFI_PHYSICAL_ADDRESS MemoryLimit > + ); > + > +VOID > +AddUntestedMemoryBaseSizeHob ( > + EFI_PHYSICAL_ADDRESS MemoryBase, > + UINT64 MemorySize > + ); > + > +VOID > +AddReservedMemoryBaseSizeHob ( > + EFI_PHYSICAL_ADDRESS MemoryBase, > + UINT64 MemorySize > + ); > + > +VOID > +AddUntestedMemoryRangeHob ( > + EFI_PHYSICAL_ADDRESS MemoryBase, > + EFI_PHYSICAL_ADDRESS MemoryLimit > + ); > + > +VOID > +AddressWidthInitialization ( > + VOID > + ); > + > +EFI_STATUS > +PublishPeiMemory ( > + VOID > + ); > + > +UINT32 > +GetSystemMemorySizeBelow4gb ( > + VOID > + ); > + > +VOID > +InitializeRamRegions ( > + VOID > + ); > + > +EFI_STATUS > +PeiFvInitialization ( > + VOID > + ); > + > +EFI_STATUS > +InitializeXen ( > + VOID > + ); > + > +extern EFI_BOOT_MODE mBootMode; > + > +extern BOOLEAN mS3Supported; > + > +extern UINT8 mPhysMemAddressWidth; > + > +#endif // _PLATFORM_PEI_H_INCLUDED_ > diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/PlatformPei.inf b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/PlatformPei.inf > new file mode 100644 > index 00000000..420b0702 > --- /dev/null > +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/PlatformPei.inf > @@ -0,0 +1,75 @@ > +## @file > +# Platform PEI driver > +# > +# This module provides platform specific function to detect boot mode. > +# > +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> +# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + INF_VERSION = 0x00010005 Please bump spec version? > + BASE_NAME = PlatformPei > + FILE_GUID = 222c386d-5abc-4fb4-b124-fbb82488acf4 > + MODULE_TYPE = PEIM > + VERSION_STRING = 1.0 > + ENTRY_POINT = InitializePlatform > + > +# > +# The following information is for reference only and not required by the build tools. > +# > +# VALID_ARCHITECTURES = IA32 X64 IPF EBC RISCV64 > +# > + > +[Sources] > + Fv.c > + MemDetect.c > + Platform.c > + > +[Packages] > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + UefiCpuPkg/UefiCpuPkg.dec > + RiscVPkg/RiscVPkg.dec > + Platform/RiscV/RiscVPlatformPkg.dec > + Silicon/SiFive/SiFive.dec > + Platform/RiscV/SiFive/U500Pkg/U500.dec Please sort alphabetically. > + > +[Guids] > + gEfiMemoryTypeInformationGuid > + gUefiRiscVPlatformU500PkgTokenSpaceGuid > + > +[LibraryClasses] > + DebugLib > + HobLib > + IoLib > + PciLib > + PeiResourcePublicationLib > + PeiServicesLib > + PeiServicesTablePointerLib > + PeimEntryPoint > + PcdLib > + SiliconSiFiveU5MCCoreplexInfoLib > + > +[Pcd] > + gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress > + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize > + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved > + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration Please sort alphabetically. / Leif > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase > + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize > + > + gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdNumberofU5Cores > + gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdE5MCSupported > + > + > +[Ppis] > + gEfiPeiMasterBootModePpiGuid > + > +[Depex] > + TRUE > -- > 2.12.0.windows.1 > > > >