From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66]) by mx.groups.io with SMTP id smtpd.web10.3689.1570748249750839365 for ; Thu, 10 Oct 2019 15:57:30 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=jj2bK4mf; spf=pass (domain: linaro.org, ip: 209.85.128.66, mailfrom: leif.lindholm@linaro.org) Received: by mail-wm1-f66.google.com with SMTP id b24so8322180wmj.5 for ; Thu, 10 Oct 2019 15:57:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=zQBgOO7qtumXabgWB/cPErZagBhgf4w6Zgl2dMZeXAE=; b=jj2bK4mflk2RZWa06Xi4Jb4PBrEJHQ+KCpcD6kyW1rH/G51W4qa1vTkt+cAq34sHs4 +ULv7eSLqQN1GlTZbQztRyjRiE2ocKWulCzbeXiqzAbw+Lh9v1mELtk8B/FzAMkT0mMA iH2YakKT2dvWlG9KZ/oGk+baEq4+EfsNsa64btsGuN6JOa2dkSwYfOO1C0u/pDl75nkP p6Xq1YwwFUhy3zxPeaUn/GdqpD25BI+QTDaTiieDsCqkJ/7aqiNnceaA0VRSlO5Ats0v +dTFRRL/MXNmHphTGgWdcdIILUDtS2qCjLgB+0lQljKWZdVkYSGD/zM60gWeo7lf1GQT cr6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=zQBgOO7qtumXabgWB/cPErZagBhgf4w6Zgl2dMZeXAE=; b=ho/R9kElXrDJBiclMBMBrbyWmI3KUZbaypafxcGJsujfCk8pRvNFga7trpPphvftBQ u0Ooxm033m+9aOiPJPg6hEEyhytKZ0lw37711qx3r1mST27kbcsI/Y+IR5aeTij46BXk p+jNM5jjEBHYrGgGwofs8NRYfmFBU2YPL7p4grTJIDkval32jpMlPV5lQiCApGG3Rr41 f+2lkshJjmQS5hW308XnBYRKe1P2FletKPEyRPCw0XfyLtCaciyOeoxiSFTYD0V4V299 4mnF2rEIYW7X2h2g3nGmgW7UTJzO439yXAYA1oK+8IUYYpXCeHASGvO54w+a/DFdOo2T EpXA== X-Gm-Message-State: APjAAAUay986babwzexN4orYxpU53TILMfqGag3uBmLe6THIkamtpuRr gbeId1OnPJDzDYeRncGscervXg== X-Google-Smtp-Source: APXvYqy2kZCRT18pvZEKIgZ1ONuXI6t6yccgGKL2Uhbi5d1dkrtJGaQKtK7l6AIGXUfjCN+gWKBX8Q== X-Received: by 2002:a1c:1bd8:: with SMTP id b207mr615848wmb.62.1570748248129; Thu, 10 Oct 2019 15:57:28 -0700 (PDT) Return-Path: Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id v6sm12647874wma.24.2019.10.10.15.57.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Oct 2019 15:57:27 -0700 (PDT) Date: Thu, 10 Oct 2019 23:57:26 +0100 From: "Leif Lindholm" To: Marcin Wojtas Cc: devel@edk2.groups.io, ard.biesheuvel@linaro.org, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: Re: [edk2-platforms: PATCH v3 7/9] Marvell/Cn9132Db: Introduce board support Message-ID: <20191010225726.GW25504@bivouac.eciton.net> References: <1570686139-25182-1-git-send-email-mw@semihalf.com> <1570686139-25182-8-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: <1570686139-25182-8-git-send-email-mw@semihalf.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Oct 10, 2019 at 07:42:17AM +0200, Marcin Wojtas wrote: > This patch introduces all necessary components required > for building EDK2 firmware for CN9132-DB setup A. Note > the ACPI is not yet available for this variant, due to > the current ICU (CP1xx interrupt controller) support > implementation. > > In order to build this variant, '-D CN9132' flag should be added. > > Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm > --- > Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc | 72 +++++++++++ > Platform/Marvell/Cn913xDb/Cn913xDbA.dsc | 13 +- > Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf | 29 +++++ > Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h | 4 + > Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c | 135 ++++++++++++++++++++ > Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 42 ++++++ > Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc | 2 + > 7 files changed, 296 insertions(+), 1 deletion(-) > create mode 100644 Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc > create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf > create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c > > diff --git a/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc b/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc > new file mode 100644 > index 0000000..a0b90fa > --- /dev/null > +++ b/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc > @@ -0,0 +1,72 @@ > +## @file > +# Component description file for the CN9132 Development Board (variant A) > +# > +# Copyright (c) 2019 Marvell International Ltd.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +################################################################################ > +# > +# Pcd Section - list of all EDK II PCD Entries defined by this Platform > +# > +################################################################################ > +[PcdsFixedAtBuild.common] > + # CP115 count > + gMarvellTokenSpaceGuid.PcdMaxCpCount|3 > + > + # MPP > + gMarvellTokenSpaceGuid.PcdMppChipCount|4 > + > + # CP115 #2 MPP > + gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE > + gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress|0xF6440000 > + gMarvellTokenSpaceGuid.PcdChip3MppPinCount|64 > + gMarvellTokenSpaceGuid.PcdChip3MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } > + gMarvellTokenSpaceGuid.PcdChip3MppSel1|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } > + gMarvellTokenSpaceGuid.PcdChip3MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0x9, 0x0 } > + gMarvellTokenSpaceGuid.PcdChip3MppSel3|{ 0x0, 0x0, 0x8, 0x0, 0x8, 0x0, 0x0, 0x2, 0x2, 0x0 } > + gMarvellTokenSpaceGuid.PcdChip3MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } > + gMarvellTokenSpaceGuid.PcdChip3MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0xA, 0xB, 0xE, 0xE, 0xE, 0xE } > + gMarvellTokenSpaceGuid.PcdChip3MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } > + > + # ComPhy > + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1, 0x1 } > + # ComPhy1 > + # 0: PCIE0 5 Gbps > + # 1: PCIE0 5 Gbps > + # 2: SATA0 5 Gbps > + # 3: USB3_HOST1 5 Gbps > + # 4: SFI 10.31 Gbps > + # 5: PCIE2 5 Gbps > + gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_SATA0), $(CP_USB3_HOST1), $(CP_SFI), $(CP_PCIE2)} > + gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) } > + > + # UtmiPhy > + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 } > + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } > + > + # MDIO > + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } > + > + # PHY > + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } > + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } > + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } > + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE > + > + # NET > + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0, 0x0 } > + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0, 0x0 } > + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_10000), $(PHY_SPEED_10000) } > + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_RGMII), $(PHY_SFI), $(PHY_SFI) } > + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF, 0xFF } > + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1, 0x2 } > + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0, 0x0 } > + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1, 0x1 } > + > + # NonDiscoverableDevices > + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 } > + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1, 0x1 } > + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1, 0x0, 0x1 } > diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc > index 70f99cf..268c39c 100644 > --- a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc > +++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc > @@ -17,6 +17,8 @@ > PLATFORM_NAME = Cn9130DbA > !elseif $(CN9131) > PLATFORM_NAME = Cn9131DbA > +!elseif $(CN9132) > + PLATFORM_NAME = Cn9132DbA > !endif > PLATFORM_GUID = 087305a1-8ddd-4027-89ca-68a3ef78fcc7 > PLATFORM_VERSION = 0.1 > @@ -38,16 +40,25 @@ > > !include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc > !include Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc > -!if $(CN9131) > +!if $(CN9131) || $(CN9132) > !include Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc > !endif > +!if $(CN9132) > +!include Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc > +!endif > > [Components.common] > Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATFORM_NAME).inf > > +!ifndef $(CN9132) > [Components.AARCH64] > Silicon/Marvell/OcteonTx/AcpiTables/T91/$(PLATFORM_NAME).inf > +!endif > > [LibraryClasses.common] > +!if $(CN9132) > + ArmadaBoardDescLib|Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf > +!else > ArmadaBoardDescLib|Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf > +!endif > NonDiscoverableInitLib|Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf > diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf > new file mode 100644 > index 0000000..27a0214 > --- /dev/null > +++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf > @@ -0,0 +1,29 @@ > +## @file > +# > +# Copyright (C) 2019, Marvell International Ltd. and its affiliates
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +# > +## > + > +[Defines] > + INF_VERSION = 0x0001001B > + BASE_NAME = Cn9132DbABoardDescLib > + FILE_GUID = cf7a0f12-45fe-417b-9c34-053605973b68 > + MODULE_TYPE = BASE > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = ArmadaBoardDescLib > + > +[Sources] > + Cn9132DbABoardDescLib.c > + > +[Packages] > + EmbeddedPkg/EmbeddedPkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MdePkg/MdePkg.dec > + Silicon/Marvell/Marvell.dec > + > +[LibraryClasses] > + DebugLib > + IoLib > diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h > index 3ca6374..a641420 100644 > --- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h > +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h > @@ -17,5 +17,9 @@ > #define CN9130_DB_SDMMC_VCCQ_PIN 15 > #define CN9131_DB_VBUS0_PIN 3 > #define CN9131_DB_VBUS0_LIMIT_PIN 2 > +#define CN9132_DB_VBUS0_PIN 2 > +#define CN9132_DB_VBUS0_LIMIT_PIN 0 > +#define CN9132_DB_VBUS1_PIN 3 > +#define CN9132_DB_VBUS1_LIMIT_PIN 1 > > #endif > diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c > new file mode 100644 > index 0000000..d2846dd > --- /dev/null > +++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c > @@ -0,0 +1,135 @@ > +/** > +* > +* Copyright (C) 2019, Marvell International Ltd. and its affiliates. > +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +* > +**/ > + > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +// > +// GPIO Expander > +// > +STATIC MV_GPIO_EXPANDER mGpioExpander = { > + PCA9555_ID, > + 0x21, > + 0x0, > +}; > + > + > +EFI_STATUS > +EFIAPI > +ArmadaBoardGpioExpanderGet ( > + IN OUT MV_GPIO_EXPANDER **GpioExpanders, > + IN OUT UINTN *GpioExpanderCount > + ) > +{ > + *GpioExpanderCount = 1; > + *GpioExpanders = &mGpioExpander; > + > + return EFI_SUCCESS; > +} > + > +// > +// PCIE > +// > +STATIC > +MV_PCIE_CONTROLLER mPcieController[] = { > + { /* PCIE0 @0xF2640000 */ > + .PcieDbiAddress = 0xF2600000, > + .ConfigSpaceAddress = 0xD0000000, > + .HaveResetGpio = FALSE, > + .PcieResetGpio = { 0 }, > + .PcieBusMin = 0, > + .PcieBusMax = 0xFE, > + .PcieIoTranslation = 0xDFF00000, > + .PcieIoWinBase = 0x0, > + .PcieIoWinSize = 0x10000, > + .PcieMmio32Translation = 0, > + .PcieMmio32WinBase = 0xC0000000, > + .PcieMmio32WinSize = 0x10000000, > + .PcieMmio64Translation = 0, > + .PcieMmio64WinBase = MAX_UINT64, > + .PcieMmio64WinSize = 0, > + } > +}; > + > +/** > + Return the number and description of PCIE controllers used on the platform. > + > + @param[in out] **PcieControllers Array containing PCIE controllers' > + description. > + @param[in out] *PcieControllerCount Amount of used PCIE controllers. > + > + @retval EFI_SUCCESS The data were obtained successfully. > + @retval other Return error status. > + > +**/ > +EFI_STATUS > +EFIAPI > +ArmadaBoardPcieControllerGet ( > + IN OUT MV_PCIE_CONTROLLER CONST **PcieControllers, > + IN OUT UINTN *PcieControllerCount > + ) > +{ > + *PcieControllers = mPcieController; > + *PcieControllerCount = ARRAY_SIZE (mPcieController); > + > + return EFI_SUCCESS; > +} > + > +// > +// Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoCDescLib > +// > +STATIC > +MV_BOARD_SDMMC_DESC mSdMmcDescTemplate[] = { > + { /* eMMC 0xF06E0000 */ > + 0, /* SOC will be filled by MvBoardDescDxe */ > + 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */ > + FALSE, /* Xenon1v8Enabled */ > + TRUE, /* Xenon8BitBusEnabled */ > + FALSE, /* XenonSlowModeEnabled */ > + 0x40, /* XenonTuningStepDivisor */ > + EmbeddedSlot /* SlotType */ > + }, > + { /* SD/MMC 0xF2780000 */ > + 0, /* SOC will be filled by MvBoardDescDxe */ > + 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */ > + FALSE, /* Xenon1v8Enabled */ > + FALSE, /* Xenon8BitBusEnabled */ > + FALSE, /* XenonSlowModeEnabled */ > + 0x19, /* XenonTuningStepDivisor */ > + EmbeddedSlot /* SlotType */ > + }, > + { /* SD/MMC 0xF6780000 */ > + 0, /* SOC will be filled by MvBoardDescDxe */ > + 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */ > + FALSE, /* Xenon1v8Enabled */ > + FALSE, /* Xenon8BitBusEnabled */ > + FALSE, /* XenonSlowModeEnabled */ > + 0x19, /* XenonTuningStepDivisor */ > + EmbeddedSlot /* SlotType */ > + } > +}; > + > +EFI_STATUS > +EFIAPI > +ArmadaBoardDescSdMmcGet ( > + OUT UINTN *SdMmcDevCount, > + OUT MV_BOARD_SDMMC_DESC **SdMmcDesc > + ) > +{ > + *SdMmcDesc = mSdMmcDescTemplate; > + *SdMmcDevCount = ARRAY_SIZE (mSdMmcDescTemplate); > + > + return EFI_SUCCESS; > +} > diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c > index dded150..42dc54a 100644 > --- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c > +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c > @@ -118,6 +118,45 @@ Cp1XhciInit ( > MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER); > } > > +STATIC CONST MV_GPIO_PIN mCp2XhciVbusPins[] = { > + { > + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, > + MV_GPIO_CP2_CONTROLLER0, > + CN9132_DB_VBUS0_PIN, > + TRUE, > + }, > + { > + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, > + MV_GPIO_CP2_CONTROLLER0, > + CN9132_DB_VBUS0_LIMIT_PIN, > + TRUE, > + }, > + { > + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, > + MV_GPIO_CP2_CONTROLLER0, > + CN9132_DB_VBUS1_PIN, > + TRUE, > + }, > + { > + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, > + MV_GPIO_CP2_CONTROLLER0, > + CN9132_DB_VBUS1_LIMIT_PIN, > + TRUE, > + }, > +}; > + > +STATIC > +EFI_STATUS > +EFIAPI > +Cp2XhciInit ( > + IN NON_DISCOVERABLE_DEVICE *This > + ) > +{ > + return ConfigurePins (mCp2XhciVbusPins, > + ARRAY_SIZE (mCp2XhciVbusPins), > + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER); > +} > + > STATIC CONST MV_GPIO_PIN mCp0SdMmcPins[] = { > { > MV_GPIO_DRIVER_TYPE_PCA95XX, > @@ -159,6 +198,9 @@ NonDiscoverableDeviceInitializerGet ( > return Cp0XhciInit; > case 2: > return Cp1XhciInit; > + case 3: > + case 4: > + return Cp2XhciInit; > } > } > > diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc b/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc > index 0c321d1..78bdb79 100644 > --- a/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc > +++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc > @@ -12,7 +12,9 @@ > # DTB > INF RuleOverride = DTB Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATFORM_NAME).inf > > +!ifndef $(CN9132) > !if $(ARCH) == AARCH64 > # ACPI support > INF RuleOverride = ACPITABLE Silicon/Marvell/OcteonTx/AcpiTables/T91/$(PLATFORM_NAME).inf > !endif > +!endif > -- > 2.7.4 >