[PATCH] IntelSiliconPkg-Vtd: Code Optimization

[Evelyn Wang <iwen.evelyn.wang@intel.com>]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1770

1) DisableDMAr Function Code Optimization
Optimize the flow to follow the VT-d spec requirements.

2) Renamed InitDmar() to InitGlobalVtd()
The oringal function name is misleading

Signed-off-by: Evelyn Wang <iwen.evelyn.wang@intel.com>
Cc: Jenny Huang <jenny.huang@intel.com>
Cc: More Shih <more.shih@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
---
 Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c                                | 30 +++++++++++++++++++++++++++---
 Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c                             | 29 ++++++++++++++++++++++++++---
 Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c |  9 +++++----
 3 files changed, 58 insertions(+), 10 deletions(-)

diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
index 22bf821d2b..699639ba88 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c
@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -309,6 +309,8 @@ DisableDmar (
   UINTN     Index;
   UINTN     SubIndex;
   UINT32    Reg32;
+  UINT32    Status;
+  UINT32    Command;
 
   for (Index = 0; Index < mVtdUnitNumber; Index++) {
     DEBUG((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%d] \n", Index));
@@ -319,9 +321,31 @@ DisableDmar (
     FlushWriteBuffer (Index);
 
     //
-    // Disable VTd
+    // Disable Dmar
     //
-    MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_SRTP);
+    //
+    // Set TE (Translation Enable: BIT31) of Global command register to zero
+    //
+    Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
+    Status = (Reg32 & 0x96FFFFFF);       // Reset the one-shot bits
+    Command = (Status & ~B_GMCD_REG_TE);
+    MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_REG, Command);
+
+    //
+    // Poll on TE Status bit of Global status register to become zero
+    //
+    do {
+      Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
+    } while ((Reg32 & B_GSTS_REG_TE) == B_GSTS_REG_TE);
+
+    //
+    // Set SRTP (Set Root Table Pointer: BIT30) of Global command register in order to update the root table pointerDisable VTd
+    //
+    Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
+    Status = (Reg32 & 0x96FFFFFF);       // Reset the one-shot bits
+    Command = (Status | B_GMCD_REG_SRTP);
+    MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_REG, Command);
+
     do {
       Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);
     } while((Reg32 & B_GSTS_REG_RTPS) == 0);
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c
index 4774a2ae5b..c9669426aa 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c
@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -197,6 +197,8 @@ DisableDmar (
   )
 {
   UINT32    Reg32;
+  UINT32    Status;
+  UINT32    Command;
 
   DEBUG((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%x] \n", VtdUnitBaseAddress));
 
@@ -206,9 +208,30 @@ DisableDmar (
   FlushWriteBuffer (VtdUnitBaseAddress);
 
   //
-  // Disable VTd
+  // Disable Dmar
   //
-  MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_SRTP);
+  //
+  // Set TE (Translation Enable: BIT31) of Global command register to zero
+  //
+  Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);
+  Status = (Reg32 & 0x96FFFFFF);       // Reset the one-shot bits
+  Command = (Status & ~B_GMCD_REG_TE);
+  MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command);
+
+   //
+   // Poll on TE Status bit of Global status register to become zero
+   //
+   do {
+     Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);
+   } while ((Reg32 & B_GSTS_REG_TE) == B_GSTS_REG_TE);
+
+  //
+  // Set SRTP (Set Root Table Pointer: BIT30) of Global command register in order to update the root table pointerDisable VTd
+  //
+  Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);
+  Status = (Reg32 & 0x96FFFFFF);       // Reset the one-shot bits
+  Command = (Status | B_GMCD_REG_SRTP);
+  MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command);
   do {
     Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);
   } while((Reg32 & B_GSTS_REG_RTPS) == 0);
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
index 3698c3d3f1..6f6c14f7a9 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
@@ -1,7 +1,7 @@
 /** @file
   Platform VTd Info Sample PEI driver.
 
-  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -166,15 +166,16 @@ EFI_PEI_PPI_DESCRIPTOR mPlatformVTdNoIgdInfoSampleDesc = {
 
 /**
   Initialize VTd register.
+  Initialize the VTd hardware unit which has INCLUDE_PCI_ALL set
 **/
 VOID
-InitDmar (
+InitGlobalVtd (
   VOID
   )
 {
   UINT32              MchBar;
 
-  DEBUG ((DEBUG_INFO, "InitDmar\n"));
+  DEBUG ((DEBUG_INFO, "InitGlobalVtd\n"));
 
   MchBar = PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0;
   PciWrite32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR), 0xFED10000 | BIT0);
@@ -346,7 +347,7 @@ PlatformVTdInfoSampleInitialize (
   DEBUG ((DEBUG_INFO, "SiliconInitialized - %x\n", SiliconInitialized));
   if (!SiliconInitialized) {
     Status = PeiServicesNotifyPpi (&mSiliconInitializedNotifyList);
-    InitDmar ();
+    InitGlobalVtd ();
 
     Status = PeiServicesInstallPpi (&mPlatformVTdNoIgdInfoSampleDesc);
     ASSERT_EFI_ERROR (Status);
-- 
2.16.2.windows.1