From: Evelyn Wang <iwen.evelyn.wang@intel.com>
To: devel@edk2.groups.io
Cc: Jenny Huang <jenny.huang@intel.com>,
More Shih <more.shih@intel.com>, Ray Ni <ray.ni@intel.com>,
Rangasai V Chaganty <rangasai.v.chaganty@intel.com>,
Jiewen Yao <jiewen.yao@intel.com>
Subject: [v7 v7] IntelSiliconPkg-Vtd: A new PMR interface
Date: Wed, 16 Oct 2019 20:21:01 -0700 [thread overview]
Message-ID: <20191017032101.14764-1-iwen.evelyn.wang@intel.com> (raw)
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1770
1) IOMMU PMR feature should be generic to support different hardware
architecture. Platforms may request no overlap between PMR regions
and system reserve memory. Create an interface to control PLMR/PHMR
regions. It allows silicon code to adjust PLMR/PHMR region base on
the project needs.
2) A new GetVtdPmrAlignmentLib for silicon code to get
PMR alignment values.
Signed-off-by: Evelyn Wang <iwen.evelyn.wang@intel.com>
Cc: Jenny Huang <jenny.huang@intel.com>
Cc: More Shih <more.shih@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
---
In V2:
1) Fixed the EFIAPI is missing in library API issue
2) Logs will be provided to make sure the backwards compatibility
3) Replaced BIT0 with EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL
4) Renamed GetVtdPmrAlignmentLib to PeiGetVtdPmrAlignmentLib
5) Fixed the indent in IntelVTdPmrPei.c
6) Follow VTd spec to define the data type of the SYSTEM_MEM_INFO_HOB
Applied few changes coordinately
---
In V3:
1) Fixed the EFIAPI is missing in library API issue
2) Fixed the S3 resume assert
---
In V4:
Fixed the missing EFIAPI in .h file and added few more comments
---
In V5:
In order to align with the future planning,
changed the hob name from SYSTEM_MEM_INFO_HOB to VTD_PMR_INFO_HOB
---
In V6:
1) Revised comments
2) Moved VtdPmrInfoHob.h under Guid folder
3) Separated to few commits
---
In V7:
1) Only the functions declared in library header file should have EFIAPI
2) Added a few comments to avoid confusion
3) Fixed a case error
---
Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c | 4 ++--
Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c | 84 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-----------------------
Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/PeiGetVtdPmrAlignmentLib.c | 164 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf | 5 ++++-
Silicon/Intel/IntelSiliconPkg/Include/Guid/VtdPmrInfoHob.h | 29 +++++++++++++++++++++++++++++
Silicon/Intel/IntelSiliconPkg/Include/Library/PeiGetVtdPmrAlignmentLib.h | 22 ++++++++++++++++++++++
Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 11 +++++++++--
Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc | 3 ++-
Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/PeiGetVtdPmrAlignmentLib.inf | 32 ++++++++++++++++++++++++++++++++
9 files changed, 325 insertions(+), 29 deletions(-)
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c
index 37283f0fab..9103e53922 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c
@@ -1,6 +1,6 @@
/** @file
- Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -294,7 +294,7 @@ SetDmaProtectedRange (
UINTN Index;
EFI_STATUS Status;
- DEBUG ((DEBUG_INFO, "SetDmaProtectedRange(0x%lx) - [0x%x, 0x%x] [0x%lx, 0x%lx]\n", EngineMask, LowMemoryBase, LowMemoryLength, HighMemoryBase, HighMemoryLength));
+ DEBUG ((DEBUG_INFO, "SetDmaProtectedRange(0x%lx) - [0x%x, 0x%x] [0x%016lx, 0x%016lx]\n", EngineMask, LowMemoryBase, LowMemoryLength, HighMemoryBase, HighMemoryLength));
for (Index = 0; Index < VTdInfo->VTdEngineCount; Index++) {
if ((EngineMask & LShiftU64(1, Index)) == 0) {
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
index ca099ed71d..ea944aa40c 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
@@ -1,6 +1,6 @@
/** @file
- Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -20,7 +20,7 @@
#include <Ppi/VtdInfo.h>
#include <Ppi/MemoryDiscovered.h>
#include <Ppi/EndOfPeiPhase.h>
-
+#include <Guid/VtdPmrInfoHob.h>
#include "IntelVTdPmrPei.h"
EFI_GUID mVTdInfoGuid = {
@@ -424,37 +424,79 @@ InitDmaProtection (
UINTN MemoryAlignment;
UINTN LowBottom;
UINTN LowTop;
- UINTN HighBottom;
+ UINT64 HighBottom;
UINT64 HighTop;
DMA_BUFFER_INFO *DmaBufferInfo;
VOID *Hob;
EFI_PEI_PPI_DESCRIPTOR *OldDescriptor;
EDKII_IOMMU_PPI *OldIoMmuPpi;
+ VTD_PMR_INFO_HOB *VtdPmrHob;
+ VOID *VtdPmrHobPtr;
+ //
+ // Initialization
+ //
+ VtdPmrHob = NULL;
Hob = GetFirstGuidHob (&mDmaBufferInfoGuid);
DmaBufferInfo = GET_GUID_HOB_DATA(Hob);
+ VtdPmrHobPtr = GetFirstGuidHob (&gVtdPmrInfoDataHobGuid);
+
+ /**
+ When gVtdPmrInfoDataHobGuid exists, it means:
+ 1. Dma buffer is reserved by memory initialize code
+ 2. PeiGetVtdPmrAlignmentLib is used to get alignment
+ 3. PMR regions are determined by the system memory map
+ 4. PMR regions will be conveyed through VTD_PMR_INFO_HOB
+
+ When gVtdPmrInfoDataHobGuid dosen't exist, it means:
+ 1. IntelVTdPmr driver will calcuate the PMR memory alignment
+ 2. Dma buffer is reserved by AllocateAlignedPages()
+ **/
+ if (VtdPmrHobPtr == NULL) {
+ //
+ // Calcuate the PMR memory alignment
+ //
+ DEBUG ((DEBUG_INFO, "No special requirements for PMR memory\n"));
+ LowMemoryAlignment = GetLowMemoryAlignment (VTdInfo, VTdInfo->EngineMask);
+ HighMemoryAlignment = GetHighMemoryAlignment (VTdInfo, VTdInfo->EngineMask);
+ if (LowMemoryAlignment < HighMemoryAlignment) {
+ MemoryAlignment = (UINTN)HighMemoryAlignment;
+ } else {
+ MemoryAlignment = LowMemoryAlignment;
+ }
+ ASSERT (DmaBufferInfo->DmaBufferSize == ALIGN_VALUE(DmaBufferInfo->DmaBufferSize, MemoryAlignment));
- DEBUG ((DEBUG_INFO, " DmaBufferSize : 0x%x\n", DmaBufferInfo->DmaBufferSize));
+ //
+ // Allocate memory for DMA buffer
+ //
+ DmaBufferInfo->DmaBufferBase = (UINTN)AllocateAlignedPages (EFI_SIZE_TO_PAGES(DmaBufferInfo->DmaBufferSize), MemoryAlignment);
+ ASSERT (DmaBufferInfo->DmaBufferBase != 0);
+ if (DmaBufferInfo->DmaBufferBase == 0) {
+ DEBUG ((DEBUG_INFO, " InitDmaProtection : OutOfResource\n"));
+ return EFI_OUT_OF_RESOURCES;
+ }
- LowMemoryAlignment = GetLowMemoryAlignment (VTdInfo, VTdInfo->EngineMask);
- HighMemoryAlignment = GetHighMemoryAlignment (VTdInfo, VTdInfo->EngineMask);
- if (LowMemoryAlignment < HighMemoryAlignment) {
- MemoryAlignment = (UINTN)HighMemoryAlignment;
+ LowBottom = 0;
+ LowTop = DmaBufferInfo->DmaBufferBase;
+ HighBottom = DmaBufferInfo->DmaBufferBase + DmaBufferInfo->DmaBufferSize;
+ HighTop = LShiftU64 (1, VTdInfo->HostAddressWidth + 1);
} else {
- MemoryAlignment = LowMemoryAlignment;
- }
- ASSERT (DmaBufferInfo->DmaBufferSize == ALIGN_VALUE(DmaBufferInfo->DmaBufferSize, MemoryAlignment));
- DmaBufferInfo->DmaBufferBase = (UINTN)AllocateAlignedPages (EFI_SIZE_TO_PAGES(DmaBufferInfo->DmaBufferSize), MemoryAlignment);
- ASSERT (DmaBufferInfo->DmaBufferBase != 0);
- if (DmaBufferInfo->DmaBufferBase == 0) {
- DEBUG ((DEBUG_INFO, " InitDmaProtection : OutOfResource\n"));
- return EFI_OUT_OF_RESOURCES;
- }
- DEBUG ((DEBUG_INFO, " DmaBufferBase : 0x%x\n", DmaBufferInfo->DmaBufferBase));
+ //
+ // Get the PMR ranges information for the VTd PMR hob
+ //
+ VtdPmrHob = GET_GUID_HOB_DATA (VtdPmrHobPtr);
+ DmaBufferInfo->DmaBufferBase = VtdPmrHob->ProtectedLowLimit;
+ LowBottom = VtdPmrHob->ProtectedLowBase;
+ LowTop = VtdPmrHob->ProtectedLowLimit;
+ HighBottom = VtdPmrHob->ProtectedHighBase;
+ HighTop = VtdPmrHob->ProtectedHighLimit;
+ }
DmaBufferInfo->DmaBufferCurrentTop = DmaBufferInfo->DmaBufferBase + DmaBufferInfo->DmaBufferSize;
DmaBufferInfo->DmaBufferCurrentBottom = DmaBufferInfo->DmaBufferBase;
+ DEBUG ((DEBUG_INFO, " DmaBufferSize : 0x%x\n", DmaBufferInfo->DmaBufferSize));
+ DEBUG ((DEBUG_INFO, " DmaBufferBase : 0x%x\n", DmaBufferInfo->DmaBufferBase));
//
// (Re)Install PPI.
@@ -472,10 +514,6 @@ InitDmaProtection (
}
ASSERT_EFI_ERROR (Status);
- LowBottom = 0;
- LowTop = DmaBufferInfo->DmaBufferBase;
- HighBottom = DmaBufferInfo->DmaBufferBase + DmaBufferInfo->DmaBufferSize;
- HighTop = LShiftU64 (1, VTdInfo->HostAddressWidth + 1);
Status = SetDmaProtectedRange (
VTdInfo,
@@ -559,7 +597,7 @@ InitVTdPmrForAll (
VTD_INFO *VTdInfo;
UINTN LowBottom;
UINTN LowTop;
- UINTN HighBottom;
+ UINT64 HighBottom;
UINT64 HighTop;
Hob = GetFirstGuidHob (&mVTdInfoGuid);
diff --git a/Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/PeiGetVtdPmrAlignmentLib.c b/Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/PeiGetVtdPmrAlignmentLib.c
new file mode 100644
index 0000000000..8471cf85ac
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/PeiGetVtdPmrAlignmentLib.c
@@ -0,0 +1,164 @@
+/** @file
+ Library to get Global VTd PMR alignment information.
+ Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiGetVtdPmrAlignmentLib.h>
+#include <Library/PeiServicesLib.h>
+#include <IndustryStandard/DmaRemappingReportingTable.h>
+#include <IndustryStandard/Vtd.h>
+
+typedef union {
+ struct {
+ UINT32 Low;
+ UINT32 High;
+ } Data32;
+ UINT64 Data;
+} UINT64_STRUCT;
+
+/**
+ Get protected low memory alignment.
+
+ @param HostAddressWidth The host address width.
+ @param VtdUnitBaseAddress The base address of the VTd engine.
+
+ @return protected low memory alignment. Ex: 0x100000
+**/
+UINT32
+GetGlobalVTdPlmrAlignment (
+ IN UINT8 HostAddressWidth,
+ IN UINTN VtdUnitBaseAddress
+ )
+{
+ UINT32 Data32;
+
+ MmioWrite32 (VtdUnitBaseAddress + R_PMEN_LOW_BASE_REG, 0xFFFFFFFF);
+ Data32 = MmioRead32 (VtdUnitBaseAddress + R_PMEN_LOW_BASE_REG);
+ Data32 = ~Data32 + 1;
+
+ return Data32;
+}
+
+/**
+ Get protected high memory alignment.
+
+ @param HostAddressWidth The host address width.
+ @param VtdUnitBaseAddress The base address of the VTd engine.
+
+ @return protected high memory alignment. Ex: 0x100000
+**/
+UINT64_STRUCT
+GetGlobalVTdPhmrAlignment (
+ IN UINT8 HostAddressWidth,
+ IN UINTN VtdUnitBaseAddress
+ )
+{
+ UINT64_STRUCT Data64;
+
+ MmioWrite64 (VtdUnitBaseAddress + R_PMEN_HIGH_BASE_REG, 0xFFFFFFFFFFFFFFFF);
+ Data64.Data = MmioRead64 (VtdUnitBaseAddress + R_PMEN_HIGH_BASE_REG);
+ Data64.Data = ~Data64.Data + 1;
+ Data64.Data = Data64.Data & (LShiftU64 (1, HostAddressWidth) - 1);
+
+ return Data64;
+}
+
+/**
+ Get Global VT-d Protected Memory alignment.
+ @return The maximum protected memory alignment. Ex: 0x100000
+**/
+UINTN
+EFIAPI
+GetGlobalVtdPmrAlignment (
+)
+{
+ UINT32 LowMemoryAlignment;
+ UINT64_STRUCT HighMemoryAlignment;
+ UINTN MemoryAlignment;
+ UINT32 GlobalVTdBaseAddress;
+ EFI_STATUS Status;
+ UINTN VtdIndex;
+ EFI_ACPI_DMAR_STRUCTURE_HEADER *DmarHeader;
+ EFI_ACPI_DMAR_DRHD_HEADER *DrhdHeader;
+ EFI_ACPI_DMAR_HEADER *AcpiDmarTable;
+
+ //
+ // Initialization
+ //
+ GlobalVTdBaseAddress = 0xFFFFFFFF;
+ LowMemoryAlignment = 0;
+ HighMemoryAlignment.Data = 0;
+ MemoryAlignment = 0;
+ Status = EFI_UNSUPPORTED;
+ VtdIndex = 0;
+ DmarHeader = NULL;
+ DrhdHeader = NULL;
+ AcpiDmarTable = NULL;
+
+ //
+ // Fatch the PEI DMAR ACPU Table that created and installed in PlatformVTdInfoSamplePei.c
+ //
+ Status = PeiServicesLocatePpi (
+ &gEdkiiVTdInfoPpiGuid,
+ 0,
+ NULL,
+ (VOID **)&AcpiDmarTable
+ );
+ if (EFI_ERROR (Status)) {
+
+ DEBUG ((DEBUG_ERROR, "PeiServicesLocatePpi gEdkiiVTdInfoPpiGuid failed\n"));
+ Status = EFI_NOT_FOUND;
+ MemoryAlignment = SIZE_1MB;
+
+ } else {
+
+ //
+ // Seatch the DRHD structure with INCLUDE_PCI_ALL flag Set -> Global VT-d
+ //
+ DmarHeader = (EFI_ACPI_DMAR_STRUCTURE_HEADER *)((UINTN)(AcpiDmarTable + 1));
+ while ((UINTN)DmarHeader < (UINTN)AcpiDmarTable + AcpiDmarTable->Header.Length) {
+ switch (DmarHeader->Type) {
+ case EFI_ACPI_DMAR_TYPE_DRHD:
+ DrhdHeader = (EFI_ACPI_DMAR_DRHD_HEADER *) DmarHeader;
+ if ((DrhdHeader->Flags & EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL) == EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL) {
+ GlobalVTdBaseAddress = (UINT32)DrhdHeader->RegisterBaseAddress;
+ DEBUG ((DEBUG_INFO," GlobalVTdBaseAddress: %x\n", GlobalVTdBaseAddress));
+ }
+ VtdIndex++;
+
+ break;
+
+ default:
+ break;
+ }
+ DmarHeader = (EFI_ACPI_DMAR_STRUCTURE_HEADER *)((UINTN)DmarHeader + DmarHeader->Length);
+ }
+
+ if (GlobalVTdBaseAddress == 0xFFFFFFFF) {
+
+ DEBUG ((DEBUG_ERROR, "Error! Please set INCLUDE_PCI_ALL flag to your Global VT-d\n"));
+ MemoryAlignment = SIZE_1MB;
+
+ } else {
+ //
+ // Get the alignment information from VT-d register
+ //
+ LowMemoryAlignment = GetGlobalVTdPlmrAlignment (AcpiDmarTable->HostAddressWidth, GlobalVTdBaseAddress);
+ HighMemoryAlignment = GetGlobalVTdPhmrAlignment (AcpiDmarTable->HostAddressWidth, GlobalVTdBaseAddress);
+ if (LowMemoryAlignment < HighMemoryAlignment.Data) {
+ MemoryAlignment = (UINTN)HighMemoryAlignment.Data;
+ } else {
+ MemoryAlignment = LowMemoryAlignment;
+ }
+ }
+ }
+
+ return MemoryAlignment;
+}
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
index 39b914cd00..3eb2b510ca 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
@@ -4,7 +4,7 @@
# This driver initializes VTd engine based upon EDKII_VTD_INFO_PPI
# and provide DMA protection in PEI.
#
-# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -40,6 +40,9 @@
IoLib
CacheMaintenanceLib
+[Guids]
+ gVtdPmrInfoDataHobGuid ## CONSUMES
+
[Ppis]
gEdkiiIoMmuPpiGuid ## PRODUCES
gEdkiiVTdInfoPpiGuid ## CONSUMES
diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Guid/VtdPmrInfoHob.h b/Silicon/Intel/IntelSiliconPkg/Include/Guid/VtdPmrInfoHob.h
new file mode 100644
index 0000000000..d08b9818e3
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Include/Guid/VtdPmrInfoHob.h
@@ -0,0 +1,29 @@
+/** @file
+ The definition for VTD PMR Regions Information Hob.
+
+ Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+
+#ifndef _VTD_PMR_INFO_HOB_H_
+#define _VTD_PMR_INFO_HOB_H_
+
+///
+/// This interface is to report the PMR regions information
+/// PMR regions means PLMR/PHMR base and limit
+/// When gVtdPmrInfoDataHobGuid exists, it means:
+/// 1. Dma buffer is reserved by memory initialize code
+/// 2. PeiGetVtdPmrAlignmentLib is used to get alignment
+/// 3. PMR regions are determined by the system memory map
+/// 4. PMR regions will be conveyed through VTD_PMR_INFO_HOB
+///
+typedef struct {
+ UINT32 ProtectedLowBase; //PLMR Base
+ UINT32 ProtectedLowLimit; //PLMR Limit
+ UINT64 ProtectedHighBase; //PHMR Base
+ UINT64 ProtectedHighLimit; //PHMR Limit
+} VTD_PMR_INFO_HOB;
+
+#endif // _VTD_PMR_INFO_HOB_H_
+
diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Library/PeiGetVtdPmrAlignmentLib.h b/Silicon/Intel/IntelSiliconPkg/Include/Library/PeiGetVtdPmrAlignmentLib.h
new file mode 100644
index 0000000000..c6918d34d5
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Include/Library/PeiGetVtdPmrAlignmentLib.h
@@ -0,0 +1,22 @@
+/** @file
+ Get Global VTd PMR alignment information library.
+
+ Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef __GET_VTD_PMR_ALIGN_LIB_H__
+#define __GET_VTD_PMR_ALIGN_LIB_H__
+#include <Library/BaseLib.h>
+
+/**
+ Get Global VT-d Protected Memory alignment.
+ @return The maximum protected memory alignment.
+**/
+
+UINTN
+EFIAPI
+GetGlobalVtdPmrAlignment (
+);
+
+#endif // __GET_VTD_PMR_ALIGN_LIB_H__
diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
index fe5bfa0dc6..5e8082e113 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -3,7 +3,7 @@
#
# This package provides common open source Intel silicon modules.
#
-# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -18,10 +18,14 @@
Include
[LibraryClasses.IA32, LibraryClasses.X64]
- ## @libraryclass Provides services to access Microcode region on flash device.
+ ## @libraryclass Provides services to access Microcode region on flash device.
#
MicrocodeFlashAccessLib|Include/Library/MicrocodeFlashAccessLib.h
+ ## @libraryclass Provides services to access VTd PMR information
+ #
+ PeiGetVtdPmrAlignmentLib|Include/Library/PeiGetVtdPmrAlignmentLib.h
+
[Guids]
## GUID for Package token space
# {A9F8D54E-1107-4F0A-ADD0-4587E7A4A735}
@@ -35,6 +39,9 @@
## Include/Guid/MicrocodeFmp.h
gMicrocodeFmpImageTypeIdGuid = { 0x96d4fdcd, 0x1502, 0x424d, { 0x9d, 0x4c, 0x9b, 0x12, 0xd2, 0xdc, 0xae, 0x5c } }
+ ## HOB GUID to get memory information after MRC is done. The hob data will be used to set the PMR ranges
+ gVtdPmrInfoDataHobGuid = {0x6fb61645, 0xf168, 0x46be, { 0x80, 0xec, 0xb5, 0x02, 0x38, 0x5e, 0xe7, 0xe7 } }
+
[Ppis]
gEdkiiVTdInfoPpiGuid = { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x67, 0xaf, 0x2b, 0x25, 0x68, 0x4a } }
diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc
index 58b5b656ef..352d1e2b6d 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc
@@ -1,7 +1,7 @@
## @file
# This package provides common open source Intel silicon modules.
#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -34,6 +34,7 @@
SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
MicrocodeFlashAccessLib|IntelSiliconPkg/Feature/Capsule/Library/MicrocodeFlashAccessLibNull/MicrocodeFlashAccessLibNull.inf
+ PeiGetVtdPmrAlignmentLib|IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/PeiGetVtdPmrAlignmentLib.inf
[LibraryClasses.common.PEIM]
PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
diff --git a/Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/PeiGetVtdPmrAlignmentLib.inf b/Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/PeiGetVtdPmrAlignmentLib.inf
new file mode 100644
index 0000000000..ebb2cc2a7f
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/PeiGetVtdPmrAlignmentLib.inf
@@ -0,0 +1,32 @@
+## @file
+# Component INF file for the GetVtdPmrAlignment library.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiGetVtdPmrAlignmentLib
+FILE_GUID = 0332BE93-0547-4D87-A7FA-0D9D76C53187
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PeiGetVtdPmrAlignmentLib
+
+[Packages]
+MdePkg/MdePkg.dec
+IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Sources]
+PeiGetVtdPmrAlignmentLib.c
+
+[LibraryClasses]
+DebugLib
+BaseMemoryLib
+MemoryAllocationLib
+BaseLib
+PeiServicesLib
+
+[Ppis]
+gEdkiiVTdInfoPpiGuid ## CONSUMES
--
2.16.2.windows.1
next reply other threads:[~2019-10-17 3:21 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-17 3:21 Evelyn Wang [this message]
2019-10-17 5:10 ` [v7 v7] IntelSiliconPkg-Vtd: A new PMR interface Ni, Ray
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