From: "Leif Lindholm" <leif.lindholm@linaro.org>
To: "Chang, Abner (HPS SW/FW Technologist)" <abner.chang@hpe.com>
Cc: "devel@edk2.groups.io" <devel@edk2.groups.io>,
"Chen, Gilbert" <gilbert.chen@hpe.com>
Subject: Re: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 02/14] Silicon/SiFive: Add library module of SiFive RISC-V cores
Date: Thu, 17 Oct 2019 11:33:42 +0100 [thread overview]
Message-ID: <20191017103342.GV25504@bivouac.eciton.net> (raw)
In-Reply-To: <CS1PR8401MB1192537C62F005818F9492BEFF920@CS1PR8401MB1192.NAMPRD84.PROD.OUTLOOK.COM>
On Wed, Oct 16, 2019 at 01:36:07AM +0000, Chang, Abner (HPS SW/FW Technologist) wrote:
> > -----Original Message-----
> > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> > Leif Lindholm
> > Sent: Wednesday, October 2, 2019 5:15 AM
> > To: devel@edk2.groups.io; Chen, Gilbert <gilbert.chen@hpe.com>
> > Subject: Re: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 02/14]
> > Silicon/SiFive: Add library module of SiFive RISC-V cores
> >
> > On Thu, Sep 19, 2019 at 11:51:19AM +0800, Gilbert Chen wrote:
> > > Initial version of SiFive RISC-V core libraries. Library of each core
> > > creates processor core SMBIOS data hob for building SMBIOS records in
> > > DXE phase.
> >
> > So yes, this implementation needs to change.
> > These should all implement the same LibraryClass.
>
> No. It shouldn't be the same library class (If you were saying the
> same LibraryClass). RISC-V SoC could be the combination of different
> RISC-V cores, or even the cores from different vendors. This depends
> on how SoC vendor combine those IPs.
Ah, OK. Sorry, did not realise this aspect.
> Either U54 or E51 could be a standalone SoC, while U54MC is the
> combination of 4 x U54 core and one E51 core.
>
> U5MC under Platform/SiFive could be 1-8 U5 core and optionally
> support E5 core. This is the special case for U500 VC707 platform
> because the core number could be customized.
>
> > Also, U54 appears to be a simple superset of U51.
> U54 is a single core.
>
> >
> > What I would suggest is creating a
> > Silicon/SiFive/Library/SiFiveCoreInfoLib, which calls into a
> > SiFiveSoCCoreInfoLib in Silicon/SiFive/<SoC>/Library, providing the acual SoC-
> > specific bits.
>
> Platform system firmware integrator just pull in the necessary core
> libraries from Silicon/{vendor} and invoke the function to create
> specific core bits.
>
> I think this implementation is well and flexible which has no need to change.
Oh, my criticism was that it was *too* flexible (with resulting code
overhead). I still feel the very small source differences, especially
between E51/U54, indicate that these could be implemented by the same
source file but different .inf files.
But this is not something that needs to be addressed before this patch
goes into -staging.
Regards,
Leif
next prev parent reply other threads:[~2019-10-17 10:33 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-19 3:51 [plaforms/devel-riscv-v2 PATCHv2 00/14] Add SiFive U500 VC707 FPGA Platform Gilbert Chen
2019-09-19 3:51 ` [plaforms/devel-riscv-v2 PATCHv2 01/14] Silicon/SiFive: Initial version of SiFive silicon package Gilbert Chen
2019-10-01 0:41 ` [edk2-devel] " Leif Lindholm
2019-09-19 3:51 ` [plaforms/devel-riscv-v2 PATCHv2 02/14] Silicon/SiFive: Add library module of SiFive RISC-V cores Gilbert Chen
2019-10-01 21:14 ` [edk2-devel] " Leif Lindholm
2019-10-16 1:36 ` Abner Chang
2019-10-17 10:33 ` Leif Lindholm [this message]
2019-09-19 3:51 ` [plaforms/devel-riscv-v2 PATCHv2 03/14] platforms/RiscV: Initial version of RISC-V platform package Gilbert Chen
2019-10-02 9:07 ` [edk2-devel] " Leif Lindholm
2019-10-15 15:24 ` Abner Chang
2019-09-19 3:51 ` [plaforms/devel-riscv-v2 PATCHv2 04/14] RiscV/Include: Initial version of header files in " Gilbert Chen
2019-10-02 16:46 ` [edk2-devel] " Leif Lindholm
2019-09-19 3:51 ` [plaforms/devel-riscv-v2 PATCHv2 05/14] RiscV/Library: Initial version of libraries introduced " Gilbert Chen
2019-10-02 17:04 ` [edk2-devel] " Leif Lindholm
2019-10-15 15:26 ` Abner Chang
2019-10-18 5:23 ` Abner Chang
2019-09-19 3:51 ` [plaforms/devel-riscv-v2 PATCHv2 06/14] RiscV/Universal: Initial version of common RISC-V SEC module Gilbert Chen
2019-10-02 19:43 ` [edk2-devel] " Leif Lindholm
2019-10-15 15:27 ` Abner Chang
2019-09-19 3:51 ` [plaforms/devel-riscv-v2 PATCHv2 07/14] RiscV/SiFive: Initial version of SiFive U500 platform package Gilbert Chen
2019-10-02 20:16 ` [edk2-devel] " Leif Lindholm
2019-09-19 3:51 ` [plaforms/devel-riscv-v2 PATCHv2 08/14] U500Pkg/Include: Header files of SiFive U500 platform Gilbert Chen
2019-10-02 21:00 ` [edk2-devel] " Leif Lindholm
2019-09-19 3:51 ` [plaforms/devel-riscv-v2 PATCHv2 09/14] U500Pkg/Library: Initial version of PlatformBootManagerLib Gilbert Chen
2019-10-02 22:02 ` [edk2-devel] " Leif Lindholm
2019-10-18 6:23 ` Abner Chang
2019-10-21 14:51 ` Leif Lindholm
2019-09-19 3:51 ` [plaforms/devel-riscv-v2 PATCHv2 10/14] U500Pkg/Library: Library instances of U500 platform library Gilbert Chen
2019-10-03 16:32 ` [edk2-devel] " Leif Lindholm
2019-10-17 2:21 ` Abner Chang
2019-10-17 7:44 ` Abner Chang
2019-10-17 11:19 ` Leif Lindholm
2019-10-17 16:09 ` Abner Chang
2019-10-17 16:38 ` Leif Lindholm
2019-10-18 5:24 ` Abner Chang
2019-09-19 3:51 ` [plaforms/devel-riscv-v2 PATCHv2 11/14] U500Pkg/RamFvbServiceruntimeDxe: FVB driver for EFI variable Gilbert Chen
2019-10-03 16:58 ` [edk2-devel] " Leif Lindholm
2019-09-19 3:51 ` [plaforms/devel-riscv-v2 PATCHv2 12/14] U500Pkg/TimerDxe: Platform Timer DXE driver Gilbert Chen
2019-10-03 17:30 ` [edk2-devel] " Leif Lindholm
2019-09-19 3:51 ` [plaforms/devel-riscv-v2 PATCHv2 13/14] U500Pkg/PlatformPei: Platform initialization PEIM Gilbert Chen
2019-10-03 17:38 ` [edk2-devel] " Leif Lindholm
2019-09-19 3:51 ` [plaforms/devel-riscv-v2 PATCHv2 14/14] Platforms: Readme file updates Gilbert Chen
2019-10-03 17:45 ` [edk2-devel] " Leif Lindholm
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