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[2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id r2sm1759310wrm.3.2019.10.17.03.33.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Oct 2019 03:33:43 -0700 (PDT) Date: Thu, 17 Oct 2019 11:33:42 +0100 From: "Leif Lindholm" To: "Chang, Abner (HPS SW/FW Technologist)" Cc: "devel@edk2.groups.io" , "Chen, Gilbert" Subject: Re: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 02/14] Silicon/SiFive: Add library module of SiFive RISC-V cores Message-ID: <20191017103342.GV25504@bivouac.eciton.net> References: <20190919035131.4700-1-gilbert.chen@hpe.com> <20190919035131.4700-3-gilbert.chen@hpe.com> <20191001211438.GX25504@bivouac.eciton.net> MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Oct 16, 2019 at 01:36:07AM +0000, Chang, Abner (HPS SW/FW Technologist) wrote: > > -----Original Message----- > > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of > > Leif Lindholm > > Sent: Wednesday, October 2, 2019 5:15 AM > > To: devel@edk2.groups.io; Chen, Gilbert > > Subject: Re: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 02/14] > > Silicon/SiFive: Add library module of SiFive RISC-V cores > > > > On Thu, Sep 19, 2019 at 11:51:19AM +0800, Gilbert Chen wrote: > > > Initial version of SiFive RISC-V core libraries. Library of each core > > > creates processor core SMBIOS data hob for building SMBIOS records in > > > DXE phase. > > > > So yes, this implementation needs to change. > > These should all implement the same LibraryClass. > > No. It shouldn't be the same library class (If you were saying the > same LibraryClass). RISC-V SoC could be the combination of different > RISC-V cores, or even the cores from different vendors. This depends > on how SoC vendor combine those IPs. Ah, OK. Sorry, did not realise this aspect. > Either U54 or E51 could be a standalone SoC, while U54MC is the > combination of 4 x U54 core and one E51 core. > > U5MC under Platform/SiFive could be 1-8 U5 core and optionally > support E5 core. This is the special case for U500 VC707 platform > because the core number could be customized. > > > Also, U54 appears to be a simple superset of U51. > U54 is a single core. > > > > > What I would suggest is creating a > > Silicon/SiFive/Library/SiFiveCoreInfoLib, which calls into a > > SiFiveSoCCoreInfoLib in Silicon/SiFive//Library, providing the acual SoC- > > specific bits. > > Platform system firmware integrator just pull in the necessary core > libraries from Silicon/{vendor} and invoke the function to create > specific core bits. > > I think this implementation is well and flexible which has no need to change. Oh, my criticism was that it was *too* flexible (with resulting code overhead). I still feel the very small source differences, especially between E51/U54, indicate that these could be implemented by the same source file but different .inf files. But this is not something that needs to be addressed before this patch goes into -staging. Regards, Leif