From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mx.groups.io with SMTP id smtpd.web11.4295.1571331237290069900 for ; Thu, 17 Oct 2019 09:53:57 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: ashraf.javeed@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Oct 2019 09:53:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,308,1566889200"; d="scan'208";a="226231708" Received: from unknown (HELO PIDSBABIOS005.gar.corp.intel.com) ([10.223.9.183]) by fmsmga002.fm.intel.com with ESMTP; 17 Oct 2019 09:53:47 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Ray Ni Subject: [edk2-staging/UEFI_PCI_ENHANCE-1 PATCH V4] MdePkg/Protocols: New interface, EFI encodings to PCI Plat protocol Date: Thu, 17 Oct 2019 22:23:41 +0530 Message-Id: <20191017165341.6956-1-ashraf.javeed@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1954 New interface added to PCI Platform Protocol / PCI Override Protocol to retrieve device-specific platform policy for the following PCI standard features, like Maximum Payload Size (MPS), Maximum Read Request Size (MRRS),Extended Tags, Relax Order, No-Snoop, Active State Power Management (ASPM),Latency Time Reporting (LTR), AtomicOp, Reference Clock Configuration, Extended SYNCH, PTM support, and Completion Timeout (CTO). New source files added with enhanced definitions are in: MdePkg/Include/Protocol/PciPlatform2.h, MdePkg/Include/Protocol/PciOverride2.h Signed-off-by: Ashraf Javeed Cc: Michael D Kinney Cc: Liming Gao Cc: Ray Ni --- In V4: Redefinition of the existing interfaces in the EFI_PCI_PLATFORM_- PROTOCOL2, to avoid type casting and to avoid further future change In V3: License update in the header sections of source files In V2: Correction made to header sections of source files --- MdePkg/Include/Protocol/PciOverride2.h | 37 +++++++++++++++++++++++++++++++++++++ MdePkg/Include/Protocol/PciPlatform2.h | 524 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ MdePkg/MdePkg.dec | 6 ++++++ 3 files changed, 567 insertions(+) diff --git a/MdePkg/Include/Protocol/PciOverride2.h b/MdePkg/Include/Protocol/PciOverride2.h new file mode 100644 index 0000000000..7e878a4f1e --- /dev/null +++ b/MdePkg/Include/Protocol/PciOverride2.h @@ -0,0 +1,37 @@ +/** @file + This file declares EFI PCI Override protocol which provides the interface between + the PCI bus driver/PCI Host Bridge Resource Allocation driver and an implementation's + driver to describe the unique features of a platform. + This protocol is optional. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#ifndef _PCI_OVERRIDE2_H_ +#define _PCI_OVERRIDE2_H_ + +/// +/// EFI_PCI_OVERRIDE_PROTOCOL has the same structure with EFI_PCI_PLATFORM_PROTOCOL +/// +#include + +/// +/// Global ID for the EFI_PCI_OVERRIDE_PROTOCOL +/// +#define EFI_PCI_OVERRIDE2_GUID \ + { \ + 0xb9d5ea1, 0x66cb, 0x4546, {0xb0, 0xbb, 0x5c, 0x6d, 0xae, 0xd9, 0x42, 0x47} \ + } + +/// +/// Declaration for EFI_PCI_OVERRIDE_PROTOCOL +/// +typedef EFI_PCI_PLATFORM_PROTOCOL2 EFI_PCI_OVERRIDE_PROTOCOL2; + + +extern EFI_GUID gEfiPciOverrideProtocol2Guid; + +#endif diff --git a/MdePkg/Include/Protocol/PciPlatform2.h b/MdePkg/Include/Protocol/PciPlatform2.h new file mode 100644 index 0000000000..6dcae70d6d --- /dev/null +++ b/MdePkg/Include/Protocol/PciPlatform2.h @@ -0,0 +1,524 @@ +/** @file + This file declares PCI Platform Protocol that provide the interface between + the PCI bus driver/PCI Host Bridge Resource Allocation driver and a platform-specific + driver to describe the unique features of a platform. + This protocol is optional. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#ifndef _PCI_PLATFORM2_H_ +#define _PCI_PLATFORM2_H_ + +/// +/// This file must be included because the EFI_PCI_PLATFORM_PROTOCOL2 uses +/// EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE. +/// +#include + +/// +/// This file is included to reuse the existing PCI Platform data structure +/// definitions of EFI_PCI_EXECUTION_PHASE,EFI_PCI_PLATFORM_POLICY +/// +#include + +/// +/// Global ID for the EFI_PCI_PLATFORM_PROTOCOL2. +/// +#define EFI_PCI_PLATFORM_PROTOCOL2_GUID \ + { \ + 0x787b0367, 0xa945, 0x4d60, {0x8d, 0x34, 0xb9, 0xd1, 0x88, 0xd2, 0xd0, 0xb6} \ + } + +/// +/// As per the present definition and specification of this protocol, the major +/// version is 1, and minor version is 1. Any driver utilizing this protocol +/// shall use these versions number to maintain the backward compatibility as +/// per its specification changes in future. +/// +enum EfiPciPlatformProtocolVersion { + EFI_PCI_PLATFORM_PROTOCOL_MAJOR_VERSION = 1, + EFI_PCI_PLATFORM_PROTOCOL_MINOR_VERSION = 1 +}; + +/// +/// Forward declaration for EFI_PCI_PLATFORM_PROTOCOL2. +/// +typedef struct _EFI_PCI_PLATFORM_PROTOCOL2 EFI_PCI_PLATFORM_PROTOCOL2; + +/// +/// Related Definitions +/// + +/// +/// Following are the data types for EFI_PCI_PLATYFORM_EXTENDED_POLICY +/// each for the PCI standard feature and its corresponding bitmask +/// representing the valid combinations of PCI attributes +/// + +/// +/// This data type is to retrieve the PCI device platform policy for the PCI- +/// compliant feature Maximum Payload Size (MPS). Refer to PCI Base Specification +/// 4, (chapter 7.5.3.4) on how to translate the below EFI encodings as per the +/// PCI hardware terminology. If this data member value is returned as 0 than +/// there is no platform policy to override, this feature would be enabled as +/// per its PCI specification based on the device capabilities. Below is it +/// data type and the macro definitions which the driver uses for interpreting +/// the platform policy. +/// +typedef UINT8 EFI_PCI_CONF_MAX_PAYLOAD_SIZE; + +#define EFI_PCI_CONF_MAX_PAYLOAD_SIZE_AUTO 0x00 //No request for override +#define EFI_PCI_CONF_MAX_PAYLOAD_SIZE_128B 0x01 //set to default 128B +#define EFI_PCI_CONF_MAX_PAYLOAD_SIZE_256B 0x02 //set to 256B if applicable +#define EFI_PCI_CONF_MAX_PAYLOAD_SIZE_512B 0x03 //set to 512B if applicable +#define EFI_PCI_CONF_MAX_PAYLOAD_SIZE_1024B 0x04 //set to 1024B if applicable +#define EFI_PCI_CONF_MAX_PAYLOAD_SIZE_2048B 0x05 //set to 2048B if applicable +#define EFI_PCI_CONF_MAX_PAYLOAD_SIZE_4096B 0x06 //set to 4096B if applicable + +/// +/// This data type is to retrieve the PCI device platform policy for the PCI- +/// compliant feature Maximum Read Request Size (MRRS). Refer to PCI Base +/// Specification 4, (chapter 7.5.3.4) on how to translate the below EFI +/// encodings as per the PCI hardware terminology. If this data member value +/// is returned as 0 than there is no platform policy to override, this feature +/// would be enabled as per its PCI specification based on the device capabilities. +/// Below is it data type and the macro definitions which the driver uses for +/// interpreting the platform policy. +/// +typedef UINT8 EFI_PCI_CONF_MAX_READ_REQ_SIZE; + +#define EFI_PCI_CONF_MAX_READ_REQ_SIZE_AUTO 0x00 //No request for override +#define EFI_PCI_CONF_MAX_READ_REQ_SIZE_128B 0x01 //set to default 128B +#define EFI_PCI_CONF_MAX_READ_REQ_SIZE_256B 0x02 //set to 256B if applicable +#define EFI_PCI_CONF_MAX_READ_REQ_SIZE_512B 0x03 //set to 512B if applicable +#define EFI_PCI_CONF_MAX_READ_REQ_SIZE_1024B 0x04 //set to 1024B if applicable +#define EFI_PCI_CONF_MAX_READ_REQ_SIZE_2048B 0x05 //set to 2048B if applicable +#define EFI_PCI_CONF_MAX_READ_REQ_SIZE_4096B 0x06 //set to 4096B if applicable + +/// +/// This data type is to retrieve the PCI device platform policy for the PCI- +/// compliant feature Extended Tags. Refer to PCI Base Specification +/// 4, (chapter 7.5.3.4) on how to translate the below EFI encodings as per the +/// PCI hardware terminology. If this data member value is returned as 0 than +/// there is no platform policy to override, this feature would be enabled as +/// per its PCI specification based on the device capabilities. Below is it +/// data type and the macro definitions which the driver uses for interpreting +/// the platform policy. +/// +typedef UINT8 EFI_PCI_CONF_EXTENDED_TAG; + +#define EFI_PCI_CONF_EXTENDED_TAG_AUTO 0x00 //No request for override +#define EFI_PCI_CONF_EXTENDED_TAG_5BIT 0x01 //set to default 5-bit +#define EFI_PCI_CONF_EXTENDED_TAG_8BIT 0x02 //set to 8-bit if applicable +#define EFI_PCI_CONF_EXTENDED_TAG_10BIT 0x03 //set to 10-bit if applicable + +/// +/// This data type is to retrieve the PCI device platform policy for the PCI- +/// compliant feature PCIe link's Active State Power Mgmt (ASPM). Refer to PCI Base +/// Specification 4, (chapter 7.5.3.7) on how to translate the below EFI +/// encodings as per the PCI hardware terminology. If this data member value +/// is returned as 0 than there is no platform policy to override, this feature +/// would be enabled as per its PCI specification based on the device capabilities. +/// Below is it data type and the macro definitions which the driver uses for +/// interpreting the platform policy. +/// +typedef UINT8 EFI_PCI_CONF_ASPM_SUPPORT; + +#define EFI_PCI_CONF_ASPM_AUTO 0x00 //No request for override +#define EFI_PCI_CONF_ASPM_DISABLE 0x01 //set to default disable state +#define EFI_PCI_CONF_ASPM_L0s_SUPPORT 0x02 //set to L0s state +#define EFI_PCI_CONF_ASPM_L1_SUPPORT 0x03 //set to L1 state +#define EFI_PCI_CONF_ASPM_L0S_L1_SUPPORT 0x04 //set to L0s and L1 state + +/// +/// This data type is to retrieve the PCI device platform policy for the PCI- +/// compliant feature PCIe Device's Relax Ordering enable/disable. Refer to PCI Base +/// Specification 4, (chapter 7.5.3.4) on how to translate the below EFI +/// encodings as per the PCI hardware terminology. If this data member value +/// is returned as 0 than there is no platform policy to override, this feature +/// would be enabled as per its PCI specification based on the device capabilities. +/// Below is it data type and the macro definitions which the driver uses for +/// interpreting the platform policy. +/// +typedef UINT8 EFI_PCI_CONF_RELAX_ORDER; + +#define EFI_PCI_CONF_RO_AUTO 0x00 //No request for override +#define EFI_PCI_CONF_RO_DISABLE 0x01 //set to default disable state +#define EFI_PCI_CONF_RO_ENABLE 0x02 //set to enable state + +/// +/// This data type is to retrieve the PCI device platform policy for the PCI- +/// compliant feature PCIe Device's No-Snoop enable/disable. Refer to PCI Base +/// Specification 4, (chapter 7.5.3.4) on how to translate the below EFI +/// encodings as per the PCI hardware terminology. If this data member value +/// is returned as 0 than there is no platform policy to override, this feature +/// would be enabled as per its PCI specification based on the device capabilities. +/// Below is it data type and the macro definitions which the driver uses for +/// interpreting the platform policy. +/// +typedef UINT8 EFI_PCI_CONF_NO_SNOOP; + +#define EFI_PCI_CONF_NS_AUTO 0x00 //No request for override +#define EFI_PCI_CONF_NS_DISABLE 0x01 //set to default disable state +#define EFI_PCI_CONF_NS_ENABLE 0x02 //set to enable state + +/// +/// This data type is to retrieve the PCI device platform policy for the PCI- +/// compliant feature PCIe link's Clock configuration is common or discrete. +/// Refer to PCI Base Specification 4, (chapter 7.5.3.7) on how to translate the +/// below EFI encodings as per the PCI hardware terminology. If this data member +/// value is returned as 0 than there is no platform policy to override, this +/// feature would be enabled as per its PCI specification based on the device +/// capabilities. Below is its data type and the macro definitions which the +/// driver uses for interpreting the platform policy. +/// +typedef UINT8 EFI_PCI_CONF_COMMON_CLOCK_CFG; + +#define EFI_PCI_CONF_CLK_CFG_AUTO 0x00 //No request for override +#define EFI_PCI_CONF_CLK_CFG_ASYNCH 0x01 //set to default asynchronous clock +#define EFI_PCI_CONF_CLK_CFG_COMMON 0x02 //set to common clock + +/// +/// This data type is to retrieve the PCI device platform policy for the PCI- +/// compliant feature PCIe link's Extended Synch enable or disable. +/// Refer to PCI Base Specification 4, (chapter 7.5.3.7) on how to translate the +/// below EFI encodings as per the PCI hardware terminology. If this data member +/// value is returned as 0 than there is no platform policy to override, this +/// feature would be enabled as per its PCI specification based on the device +/// capabilities. Below is its data type and the macro definitions which the +/// driver uses for interpreting the platform policy. +/// +typedef UINT8 EFI_PCI_CONF_EXTENDED_SYNCH; + +#define EFI_PCI_CONF_EXT_SYNCH_AUTO 0x00 //No request for override +#define EFI_PCI_CONF_EXT_SYNCH_DISABLE 0x01 //set to default disable state +#define EFI_PCI_CONF_EXT_SYNCH_ENABLE 0x02 //set to enable state + +/// +/// This data type is to retrieve the PCI device platform policy for the PCI- +/// compliant feature PCIe Device's AtomicOp Requester enable or disable. +/// Refer to PCI Base Specification 4, (chapter 7.5.3.16) on how to translate the +/// below EFI encodings as per the PCI hardware terminology. If this data member +/// value is returned as 0 than there is no platform policy to override, this +/// feature would be enabled as per its PCI specification based on the device +/// capabilities. Below is its data type and the macro definitions which the +/// driver uses for interpreting the platform policy. +/// +typedef UINT8 EFI_PCI_CONF_ATOMIC_OP; + +#define EFI_PCI_CONF_ATOMIC_OP_AUTO 0x00 //No request for override +#define EFI_PCI_CONF_ATOMIC_OP_DISABLE 0x01 //set to default disable state +#define EFI_PCI_CONF_ATOMIC_OP_ENABLE 0x02 //set to enable state + +/// +/// This data type is to retrieve the PCI device platform policy for the PCI- +/// compliant feature PCIe Device's LTR Mechanism enable/disable. +/// Refer to PCI Base Specification 4, (chapter 7.5.3.16) on how to translate the +/// below EFI encodings as per the PCI hardware terminology. If this data member +/// value is returned as 0 than there is no platform policy to override, this +/// feature would be enabled as per its PCI specification based on the device +/// capabilities. Below is its data type and the macro definitions which the +/// driver uses for interpreting the platform policy. +/// +typedef UINT8 EFI_PCI_CONF_LTR; + +#define EFI_PCI_CONF_LTR_AUTO 0x00 //No request for override +#define EFI_PCI_CONF_LTR_DISABLE 0x01 //set to default disable state +#define EFI_PCI_CONF_LTR_ENABLE 0x02 //set to enable state + +/// +/// This data type is to retrieve the PCI device platform policy for the PCI- +/// compliant feature PCIe Device's Precision Time Measurement (PTM) enable/disable. +/// Refer to PCI Base Specification 4, (chapter 7.5.3.16) on how to translate the +/// below EFI encodings as per the PCI hardware terminology. If this data member +/// value is returned as 0 than there is no platform policy to override, this +/// feature would be enabled as per its PCI specification based on the device +/// capabilities. Below is its data type and the macro definitions which the +/// driver uses for interpreting the platform policy. +/// +typedef UINT8 EFI_PCI_CONF_PTM; + +#define EFI_PCI_CONF_PTM_AUTO 0x00 //No request for override +#define EFI_PCI_CONF_PTM_DISABLE 0x01 //set to default disable state +#define EFI_PCI_CONF_PTM_ENABLE 0x02 //set to enable state only +#define EFI_PCI_CONF_PTM_ROOT_SEL 0x02 //set to root select & enable + +/// +/// This data type is to retrieve the PCI device platform policy for the PCI- +/// compliant feature PCIe Device's Completion Timeout (CTO) set to supported ranges +/// or disable. Refer to PCI Base Specification 4, (chapter 7.5.3.16) on how to +/// translate the below EFI encodings as per the PCI hardware terminology. If this +/// data member value is returned as 0 than there is no platform policy to override, +/// this feature would be enabled as per its PCI specification based on the device +/// capabilities. Below is its data type and the macro definitions which the +/// driver uses for interpreting the platform policy. +/// +typedef UINT8 EFI_PCI_CONF_CTO_SUPPORT; + +#define EFI_PCI_CONF_CTO_AUTO 0x00 //No request for override +#define EFI_PCI_CONF_CTO_DEFAULT 0x01 //set to default range of 5us to 50ms if applicable +#define EFI_PCI_CONF_CTO_RANGE_A1 0x02 //set to range of 50us to 100us if applicable +#define EFI_PCI_CONF_CTO_RANGE_A2 0x03 //set to range of 1ms to 10ms if applicable +#define EFI_PCI_CONF_CTO_RANGE_B1 0x04 //set to range of 16ms to 55ms if applicable +#define EFI_PCI_CONF_CTO_RANGE_B2 0x05 //set to range of 65ms to 210ms if applicable +#define EFI_PCI_CONF_CTO_RANGE_C1 0x06 //set to range of 260ms to 900ms if applicable +#define EFI_PCI_CONF_CTO_RANGE_C2 0x07 //set to range of 1s to 3.5s if applicable +#define EFI_PCI_CONF_CTO_RANGE_D1 0x08 //set to range of 4s to 13s if applicable +#define EFI_PCI_CONF_CTO_RANGE_D2 0x09 //set to range of 17s to 64s if applicable +#define EFI_PCI_CONF_CTO_DET_DISABLE 0x10 //set to CTO detection disable if applicable + +/// +/// Reserves for future use +/// +typedef UINT8 EFI_PCI_CONF_RESERVES; + +/// +/// The EFI_PCI_PLATYFORM_EXTENDED_POLICY is altogether 128-byte size, with each +/// byte field representing one PCI standerd feature defined in the PCI Express Base +/// Specification 4.0, version 1.0. +/// +typedef struct { + EFI_PCI_CONF_MAX_PAYLOAD_SIZE DeviceCtlMPS; + EFI_PCI_CONF_MAX_READ_REQ_SIZE DeviceCtlMRRS; + EFI_PCI_CONF_EXTENDED_TAG DeviceCtlExtTag; + EFI_PCI_CONF_RELAX_ORDER DeviceCtlRelaxOrder; + EFI_PCI_CONF_NO_SNOOP DeviceCtlNoSnoop; + EFI_PCI_CONF_ASPM_SUPPORT LinkCtlASPMState; + EFI_PCI_CONF_COMMON_CLOCK_CFG LinkCtlCommonClkCfg; + EFI_PCI_CONF_EXTENDED_SYNCH LinkCtlExtSynch; + EFI_PCI_CONF_ATOMIC_OP DeviceCtl2AtomicOp; + EFI_PCI_CONF_LTR DeviceCtl2LTR; + EFI_PCI_CONF_PTM PTMControl; + EFI_PCI_CONF_CTO_SUPPORT CTOsupport; + EFI_PCI_CONF_RESERVES Reserves[116]; +} EFI_PCI_PLATFORM_EXTENDED_POLICY; + +/** + The notification from the PCI bus enumerator to the platform that it is + about to enter a certain phase during the enumeration process. + + The PlatformNotify() function can be used to notify the platform driver so that + it can perform platform-specific actions. No specific actions are required. + Eight notification points are defined at this time. More synchronization points + may be added as required in the future. The PCI bus driver calls the platform driver + twice for every Phase-once before the PCI Host Bridge Resource Allocation Protocol + driver is notified, and once after the PCI Host Bridge Resource Allocation Protocol + driver has been notified. + This member function may not perform any error checking on the input parameters. It + also does not return any error codes. If this member function detects any error condition, + it needs to handle those errors on its own because there is no way to surface any + errors to the caller. + + @param[in] This The pointer to the EFI_PCI_PLATFORM_PROTOCOL2 instance. + @param[in] HostBridge The handle of the host bridge controller. + @param[in] Phase The phase of the PCI bus enumeration. + @param[in] ExecPhase Defines the execution phase of the PCI chipset driver. + + @retval EFI_SUCCESS The function completed successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_PLATFORM_PHASE_NOTIFY2)( + IN EFI_PCI_PLATFORM_PROTOCOL2 *This, + IN EFI_HANDLE HostBridge, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_EXECUTION_PHASE ExecPhase + ); + +/** + The notification from the PCI bus enumerator to the platform for each PCI + controller at several predefined points during PCI controller initialization. + + The PlatformPrepController() function can be used to notify the platform driver so that + it can perform platform-specific actions. No specific actions are required. + Several notification points are defined at this time. More synchronization points may be + added as required in the future. The PCI bus driver calls the platform driver twice for + every PCI controller-once before the PCI Host Bridge Resource Allocation Protocol driver + is notified, and once after the PCI Host Bridge Resource Allocation Protocol driver has + been notified. + This member function may not perform any error checking on the input parameters. It also + does not return any error codes. If this member function detects any error condition, it + needs to handle those errors on its own because there is no way to surface any errors to + the caller. + + @param[in] This The pointer to the EFI_PCI_PLATFORM_PROTOCOL2 instance. + @param[in] HostBridge The associated PCI host bridge handle. + @param[in] RootBridge The associated PCI root bridge handle. + @param[in] PciAddress The address of the PCI device on the PCI bus. + @param[in] Phase The phase of the PCI controller enumeration. + @param[in] ExecPhase Defines the execution phase of the PCI chipset driver. + + @retval EFI_SUCCESS The function completed successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_PLATFORM_PREPROCESS_CONTROLLER2)( + IN EFI_PCI_PLATFORM_PROTOCOL2 *This, + IN EFI_HANDLE HostBridge, + IN EFI_HANDLE RootBridge, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_EXECUTION_PHASE ExecPhase + ); + +/** + Retrieves the platform policy regarding enumeration. + + The GetPlatformPolicy() function retrieves the platform policy regarding PCI + enumeration. The PCI bus driver and the PCI Host Bridge Resource Allocation Protocol + driver can call this member function to retrieve the policy. + + @param[in] This The pointer to the EFI_PCI_PLATFORM_PROTOCOL2 instance. + @param[out] PciPolicy The platform policy with respect to VGA and ISA aliasing. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER PciPolicy is NULL. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_PLATFORM_GET_PLATFORM_POLICY2)( + IN CONST EFI_PCI_PLATFORM_PROTOCOL2 *This, + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy + ); + +/** + Gets the PCI device's option ROM from a platform-specific location. + + The GetPciRom() function gets the PCI device's option ROM from a platform-specific location. + The option ROM will be loaded into memory. This member function is used to return an image + that is packaged as a PCI 2.2 option ROM. The image may contain both legacy and EFI option + ROMs. See the UEFI 2.0 Specification for details. This member function can be used to return + option ROM images for embedded controllers. Option ROMs for embedded controllers are typically + stored in platform-specific storage, and this member function can retrieve it from that storage + and return it to the PCI bus driver. The PCI bus driver will call this member function before + scanning the ROM that is attached to any controller, which allows a platform to specify a ROM + image that is different from the ROM image on a PCI card. + + @param[in] This The pointer to the EFI_PCI_PLATFORM_PROTOCOL2 instance. + @param[in] PciHandle The handle of the PCI device. + @param[out] RomImage If the call succeeds, the pointer to the pointer to the option ROM image. + Otherwise, this field is undefined. The memory for RomImage is allocated + by EFI_PCI_PLATFORM_PROTOCOL2.GetPciRom() using the EFI Boot Service AllocatePool(). + It is the caller's responsibility to free the memory using the EFI Boot Service + FreePool(), when the caller is done with the option ROM. + @param[out] RomSize If the call succeeds, a pointer to the size of the option ROM size. Otherwise, + this field is undefined. + + @retval EFI_SUCCESS The option ROM was available for this device and loaded into memory. + @retval EFI_NOT_FOUND No option ROM was available for this device. + @retval EFI_OUT_OF_RESOURCES No memory was available to load the option ROM. + @retval EFI_DEVICE_ERROR An error occurred in obtaining the option ROM. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_PLATFORM_GET_PCI_ROM2)( + IN CONST EFI_PCI_PLATFORM_PROTOCOL2 *This, + IN EFI_HANDLE PciHandle, + OUT VOID **RomImage, + OUT UINTN *RomSize + ); + +/** + Retrieves the PCI device-specific platform policy regarding enumeration. + + The PCI Bus driver and PCI Host Bridge Resource Allocation Protocol drivers + can call this member function to retrieve the platform policies specific to + PCI device, regarding the PCI enumeration. + + The GetDevicePolicy() function retrieves the platform policy for a particular + component regarding PCI enumeration. The PCI bus driver and the PCI Host Bridge + Resource Allocation Protocol driver can call this member function to retrieve + the policy. + The existing GetPlatformPolicy() member function is used by the PCI Bus driver + to program the legacy ranges, the data that is returned by that member function + determines the supported attributes that are returned by the + EFI_PCI_IO_PROTOCOL.Attributes() function. + The GetDevicePolicy() member function is meant to return data about other PCI + compliant features which would be supported by the PCI Bus driver in future; + like for example the MPS, MRRS, Extended Tag, ASPM, etc. The details about + this PCI features can be obtained from the PCI Base Specification 4.x. The + EFI encodings for these feature are defined in the + EFI_PCI_PLATFORM_EXTENDED_POLICY, see the Related Definition section for this. + This member function will use the associated EFI handle of the PCI IO Protocol + to determine the physical PCI device within the chipset, to return its + device-specific platform policies. It is caller's responsibility to allocate + the buffer and pass its pointer to this member function, to get its device- + specific policy data. + + @param[in] This Pointer to the EFI_PCI_PLATFORM_PROTOCOL2 instance. + @param[in] PciDevice The associated PCI IO Protocol handle of the PCI + device. Type EFI_HANDLE is defined in + InstallProtocolInterface() in the UEFI 2.1 + Specification + @param[in] PciExtPolicy The pointer to platform policy with respect to other + PCI features like, the MPS, MRRS, etc. Type + EFI_PCI_PLATFORM_EXTENDED_POLICY is defined in + "Related Definitions" above. + + + @retval EFI_SUCCESS The function completed successfully, may returns + platform policy data for the given PCI component + @retval EFI_UNSUPPORTED PCI component belongs to PCI topology but not + part of chipset to provide the platform policy + @retval EFI_INVALID_PARAMETER If any of the input parameters are passed with + invalid data + + **/ +typedef +EFI_STATUS +(EFIAPI * EFI_PCI_PLATFORM_GET_DEVICE_POLICY) ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL2 *This, + IN EFI_HANDLE PciDevice, + OUT EFI_PCI_PLATFORM_EXTENDED_POLICY *PciExtPolicy +); + +/// +/// This protocol provides the interface between the PCI bus driver/PCI Host +/// Bridge Resource Allocation driver and a platform-specific driver to describe +/// the unique features of a platform. +/// +struct _EFI_PCI_PLATFORM_PROTOCOL2 { + /// + /// The notification from the PCI bus enumerator to the platform that it is about to + /// enter a certain phase during the enumeration process. + /// + EFI_PCI_PLATFORM_PHASE_NOTIFY2 PlatformNotify; + /// + /// The notification from the PCI bus enumerator to the platform for each PCI + /// controller at several predefined points during PCI controller initialization. + /// + EFI_PCI_PLATFORM_PREPROCESS_CONTROLLER2 PlatformPrepController; + /// + /// Retrieves the platform policy regarding enumeration. + /// + EFI_PCI_PLATFORM_GET_PLATFORM_POLICY2 GetPlatformPolicy; + /// + /// Gets the PCI device's option ROM from a platform-specific location. + /// + EFI_PCI_PLATFORM_GET_PCI_ROM2 GetPciRom; + /// + /// Retrieves the PCI device-specific platform policy regarding enumeration. + /// + EFI_PCI_PLATFORM_GET_DEVICE_POLICY GetDevicePolicy; + /// + /// The major version of this PCI Platform Protocol + /// + UINT8 MajorVersion; + /// + /// The minor version of this PCI Platform Protocol + /// + UINT8 MinorVersion; + +}; + +extern EFI_GUID gEfiPciPlatformProtocol2Guid; + +#endif diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index d022cc5e3e..78180db6d2 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -1022,6 +1022,12 @@ ## Include/Protocol/PciOverride.h gEfiPciOverrideProtocolGuid = { 0xb5b35764, 0x460c, 0x4a06, {0x99, 0xfc, 0x77, 0xa1, 0x7c, 0x1b, 0x5c, 0xeb }} + ## Include/Protocol/PciPlatform2.h + gEfiPciPlatformProtocol2Guid = { 0x787b0367, 0xa945, 0x4d60, { 0x8d, 0x34, 0xb9, 0xd1, 0x88, 0xd2, 0xd0, 0xb6 }} + + ## Include/Protocol/PciOverride2.h + gEfiPciOverrideProtocol2Guid = { 0xb9d5ea1, 0x66cb, 0x4546, { 0xb0, 0xbb, 0x5c, 0x6d, 0xae, 0xd9, 0x42, 0x47 }} + ## Include/Protocol/PciEnumerationComplete.h gEfiPciEnumerationCompleteProtocolGuid = { 0x30cfe3e7, 0x3de1, 0x4586, {0xbe, 0x20, 0xde, 0xab, 0xa1, 0xb3, 0xb7, 0x93}} -- 2.21.0.windows.1