From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-1.mimecast.com (us-smtp-1.mimecast.com [205.139.110.120]) by mx.groups.io with SMTP id smtpd.web09.1920.1571782566082555229 for ; Tue, 22 Oct 2019 15:16:06 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=YtsVQi2U; spf=pass (domain: redhat.com, ip: 205.139.110.120, mailfrom: lersek@redhat.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1571782565; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=GgAl0x4gAXb7/BC29VIwnolusItniEpi+nZG+ORFaco=; b=YtsVQi2U/fZcNptPpG8TtXndYtN7lw25CEQolhxvcvZnP8AJOI4XibErdpPjIz2rer15e9 mjMEv1a+aowAV60BQwP2PIy+TD5wu+BXRvgfRYdZKHRpW54nvNGLlIEME7HibH75U2niMP 54Qlp6Dt123c1tSmHI6B9dOG9x/lYV0= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-366-Ar2FOLvMNIKFTW7B9JoNvA-1; Tue, 22 Oct 2019 18:16:02 -0400 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id DAC1280183E; Tue, 22 Oct 2019 22:16:01 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (unknown [10.36.118.54]) by smtp.corp.redhat.com (Postfix) with ESMTP id BADF75DC18; Tue, 22 Oct 2019 22:16:00 +0000 (UTC) From: "Laszlo Ersek" To: edk2-devel-groups-io Cc: Ard Biesheuvel , Igor Mammedov , Jordan Justen Subject: [PATCH v2 2/3] OvmfPkg/IndustryStandard: define macros for QEMU's CPU hotplug registers Date: Wed, 23 Oct 2019 00:15:53 +0200 Message-Id: <20191022221554.14963-3-lersek@redhat.com> In-Reply-To: <20191022221554.14963-1-lersek@redhat.com> References: <20191022221554.14963-1-lersek@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-MC-Unique: Ar2FOLvMNIKFTW7B9JoNvA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable In v1.5.0, QEMU's "pc" (i440fx) board gained a "CPU present bitmap" register block. In v2.0.0, this was extended to the "q35" board. In v2.7.0, a new (read/write) register interface was laid over the "CPU present bitmap", with an option for the guest to switch the register block to the new (a.k.a. modern) interface. Both interfaces are documented in "docs/specs/acpi_cpu_hotplug.txt" in the QEMU tree. Add macros for a minimal subset of the modern interface, just so we can count the possible CPUs (as opposed to boot CPUs) in a later patch in this series. Cc: Ard Biesheuvel Cc: Igor Mammedov Cc: Jordan Justen Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1515 Signed-off-by: Laszlo Ersek --- Notes: v2: - use QEMU's existent CPU hotplug register block, rather than a new named file in fw_cfg [Igor] OvmfPkg/Include/IndustryStandard/I440FxPiix4.h | 5 +++ OvmfPkg/Include/IndustryStandard/Q35MchIch9.h | 2 + OvmfPkg/Include/IndustryStandard/QemuCpuHotplug.h | 43 +++++++++++++++++++= + 3 files changed, 50 insertions(+) diff --git a/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h b/OvmfPkg/Inclu= de/IndustryStandard/I440FxPiix4.h index e7d7fde14c65..3973ff0a95b4 100644 --- a/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h +++ b/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h @@ -44,6 +44,11 @@ BIT10 | BIT9 | BIT8 | BIT7 | BIT6) =20 #define PIIX4_PMREGMISC 0x80 #define PIIX4_PMREGMISC_PMIOSE BIT0 =20 +// +// IO ports +// +#define PIIX4_CPU_HOTPLUG_BASE 0xAF00 + #endif diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Includ= e/IndustryStandard/Q35MchIch9.h index 391cb4622226..2ac16f19c62e 100644 --- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h +++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h @@ -104,10 +104,12 @@ // IO ports // #define ICH9_APM_CNT 0xB2 #define ICH9_APM_STS 0xB3 =20 +#define ICH9_CPU_HOTPLUG_BASE 0x0CD8 + // // IO ports relative to PMBASE // #define ICH9_PMBASE_OFS_SMI_EN 0x30 #define ICH9_SMI_EN_APMC_EN BIT5 diff --git a/OvmfPkg/Include/IndustryStandard/QemuCpuHotplug.h b/OvmfPkg/In= clude/IndustryStandard/QemuCpuHotplug.h new file mode 100644 index 000000000000..cf0745610f2c --- /dev/null +++ b/OvmfPkg/Include/IndustryStandard/QemuCpuHotplug.h @@ -0,0 +1,43 @@ +/** @file + Macros for accessing QEMU's CPU hotplug register block. + + Copyright (C) 2019, Red Hat, Inc. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + + - "docs/specs/acpi_cpu_hotplug.txt" in the QEMU source tree. + + The original (now "legacy") CPU hotplug interface appeared in QEMU v1.= 5.0. + The new ("modern") hotplug interface appeared in QEMU v2.7.0. + + The macros in this header file map to the minimal subset of the modern + interface that OVMF needs. +**/ + +#ifndef QEMU_CPU_HOTPLUG_H_ +#define QEMU_CPU_HOTPLUG_H_ + +#include + +// +// Each register offset is: +// - relative to the board-dependent IO base address of the register block= , +// - named QEMU_CPUHP_(R|W|RW)_*, according to the possible access modes o= f the +// register, +// - followed by distinguished bitmasks or values in the register. +// +#define QEMU_CPUHP_R_CMD_DATA2 0x0 + +#define QEMU_CPUHP_R_CPU_STAT 0x4 +#define QEMU_CPUHP_STAT_ENABLED BIT0 + +#define QEMU_CPUHP_RW_CMD_DATA 0x8 + +#define QEMU_CPUHP_W_CPU_SEL 0x0 + +#define QEMU_CPUHP_W_CMD 0x5 +#define QEMU_CPUHP_CMD_GET_PENDING 0x0 + +#endif // QEMU_CPU_HOTPLUG_H_ --=20 2.19.1.3.g30247aa5d201