* [edk2-platforms: PATCH 0/5] Add SetCacheLib library class.
@ 2019-10-30 12:29 Chiu, Chasel
2019-10-30 12:29 ` [edk2-platforms: PATCH 1/5] MinPlatformPkg: " Chiu, Chasel
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Chiu, Chasel @ 2019-10-30 12:29 UTC (permalink / raw)
To: devel
Cc: Michael Kubacki, Nate DeSimone, Liming Gao, Jeremy Soller,
Shifei A Lu, Xiaohu Zhou, Isaac W Oram, Wei David Y,
Agyeman Prince
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2314
The MTRRs may be redundantly or incorrectly configured.
It is recommended to move this functionality to a library
class that with a NULL library by default. The board
package may provide its own library implementation.
MinPlatformPkg should contain the library class header (API)
and the NULL library class instance.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Jeremy Soller <jeremy@system76.com>
Cc: Shifei A Lu <shifei.a.lu@intel.com>
Cc: Xiaohu Zhou <bowen.zhou@intel.com>
Cc: Isaac W Oram <isaac.w.oram@intel.com>
Cc: Wei David Y <david.y.wei@intel.com>
Cc: Agyeman Prince <prince.agyeman@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Chasel Chiu (5):
MinPlatformPkg: Add SetCacheLib library class.
KabylakeOpenBoardPkg: Add SetCacheLib library class.
WhiskeylakeOpenBoardPkg: Add SetCacheLib library class.
PurleyOpenBoardPkg/BoardMtOlympus: Add SetCacheLib library class.
SimicsOpenBoardPkg/BoardX58Ich10: Add SetCacheLib library class.
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c | 640 ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.c | 325 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull.c | 37 +++++++++++++++++++++++++++++++++++++
Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.c | 149 +----------------------------------------------------------------------------------------------------------------------------------------------------
Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c | 164 ++------------------------------------------------------------------------------------------------------------------------------------------------------------------
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc | 3 ++-
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf | 67 -------------------------------------------------------------------
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 1 +
Platform/Intel/MinPlatformPkg/Include/Library/SetCacheLib.h | 34 ++++++++++++++++++++++++++++++++++
Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.inf | 44 ++++++++++++++++++++++++++++++++++++++++++++
Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull.inf | 30 ++++++++++++++++++++++++++++++
Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf | 11 +----------
Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf | 7 ++-----
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.dsc | 3 ++-
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc | 1 +
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc | 1 +
17 files changed, 484 insertions(+), 1035 deletions(-)
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c
create mode 100644 Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.c
create mode 100644 Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull.c
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
create mode 100644 Platform/Intel/MinPlatformPkg/Include/Library/SetCacheLib.h
create mode 100644 Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.inf
create mode 100644 Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull.inf
--
2.13.3.windows.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [edk2-platforms: PATCH 1/5] MinPlatformPkg: Add SetCacheLib library class.
2019-10-30 12:29 [edk2-platforms: PATCH 0/5] Add SetCacheLib library class Chiu, Chasel
@ 2019-10-30 12:29 ` Chiu, Chasel
2019-10-30 12:29 ` [edk2-platforms: PATCH 2/5] KabylakeOpenBoardPkg: " Chiu, Chasel
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Chiu, Chasel @ 2019-10-30 12:29 UTC (permalink / raw)
To: devel; +Cc: Michael Kubacki, Nate DeSimone, Liming Gao
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2314
MinPlatformPkg should contain the library class header (API)
and the NULL library class instance.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.c | 325 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull.c | 37 +++++++++++++++++++++++++++++++++++++
Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.c | 149 +----------------------------------------------------------------------------------------------------------------------------------------------------
Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c | 164 ++------------------------------------------------------------------------------------------------------------------------------------------------------------------
Platform/Intel/MinPlatformPkg/Include/Library/SetCacheLib.h | 34 ++++++++++++++++++++++++++++++++++
Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.inf | 44 ++++++++++++++++++++++++++++++++++++++++++++
Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull.inf | 30 ++++++++++++++++++++++++++++++
Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf | 11 +----------
Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf | 7 ++-----
9 files changed, 476 insertions(+), 325 deletions(-)
diff --git a/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.c b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.c
new file mode 100644
index 0000000000..b5c5041430
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.c
@@ -0,0 +1,325 @@
+/** @file
+
+SetCache library functions.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <PiPei.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MtrrLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Guid/SmramMemoryReserve.h>
+
+/**
+ Set Cache Mtrr.
+**/
+VOID
+EFIAPI
+SetCacheMtrr (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_HOB_POINTERS Hob;
+ MTRR_SETTINGS MtrrSetting;
+ UINT64 MemoryBase;
+ UINT64 MemoryLength;
+ UINT64 LowMemoryLength;
+ UINT64 HighMemoryLength;
+ EFI_BOOT_MODE BootMode;
+ EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
+ UINT64 CacheMemoryLength;
+
+ ///
+ /// Reset all MTRR setting.
+ ///
+ ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS));
+
+ ///
+ /// Cache the Flash area as WP to boost performance
+ ///
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ (UINTN) PcdGet32 (PcdFlashAreaBaseAddress),
+ (UINTN) PcdGet32 (PcdFlashAreaSize),
+ CacheWriteProtected
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ ///
+ /// Update MTRR setting from MTRR buffer for Flash Region to be WP to boost performance
+ ///
+ MtrrSetAllMtrrs (&MtrrSetting);
+
+ ///
+ /// Set low to 1 MB. Since 1MB cacheability will always be set
+ /// until override by CSM.
+ /// Initialize high memory to 0.
+ ///
+ LowMemoryLength = 0x100000;
+ HighMemoryLength = 0;
+ ResourceAttribute = (
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
+ );
+
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ if (BootMode != BOOT_ON_S3_RESUME) {
+ ResourceAttribute |= EFI_RESOURCE_ATTRIBUTE_TESTED;
+ }
+
+ Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
+ while (!END_OF_HOB_LIST (Hob)) {
+ if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
+ if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) ||
+ ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) &&
+ (Hob.ResourceDescriptor->ResourceAttribute == ResourceAttribute))
+ ) {
+ if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000000ULL) {
+ HighMemoryLength += Hob.ResourceDescriptor->ResourceLength;
+ } else if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000) {
+ LowMemoryLength += Hob.ResourceDescriptor->ResourceLength;
+ }
+ }
+ }
+
+ Hob.Raw = GET_NEXT_HOB (Hob);
+ }
+
+ DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) = %lx.\n", LowMemoryLength));
+ DEBUG ((DEBUG_INFO, "Memory Length (Above 4GB) = %lx.\n", HighMemoryLength));
+
+ ///
+ /// Assume size of main memory is multiple of 256MB
+ ///
+ MemoryLength = (LowMemoryLength + 0xFFFFFFF) & 0xF0000000;
+ MemoryBase = 0;
+
+ CacheMemoryLength = MemoryLength;
+ ///
+ /// Programming MTRRs to avoid override SPI region with UC when MAX TOLUD Length >= 3.5GB
+ ///
+ if (MemoryLength > 0xDC000000) {
+ CacheMemoryLength = 0xC0000000;
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ MemoryBase,
+ CacheMemoryLength,
+ CacheWriteBack
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ MemoryBase = 0xC0000000;
+ CacheMemoryLength = MemoryLength - 0xC0000000;
+ if (MemoryLength > 0xE0000000) {
+ CacheMemoryLength = 0x20000000;
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ MemoryBase,
+ CacheMemoryLength,
+ CacheWriteBack
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ MemoryBase = 0xE0000000;
+ CacheMemoryLength = MemoryLength - 0xE0000000;
+ }
+ }
+
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ MemoryBase,
+ CacheMemoryLength,
+ CacheWriteBack
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ if (LowMemoryLength != MemoryLength) {
+ MemoryBase = LowMemoryLength;
+ MemoryLength -= LowMemoryLength;
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ MemoryBase,
+ MemoryLength,
+ CacheUncacheable
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+
+ ///
+ /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC
+ ///
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ 0xA0000,
+ 0x20000,
+ CacheUncacheable
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ ///
+ /// Update MTRR setting from MTRR buffer
+ ///
+ MtrrSetAllMtrrs (&MtrrSetting);
+
+ return ;
+}
+
+/**
+ Update MTRR setting and set write back as default memory attribute.
+
+ @retval EFI_SUCCESS The function completes successfully.
+ @retval Others Some error occurs.
+**/
+EFI_STATUS
+EFIAPI
+SetCacheMtrrAfterEndOfPei (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ MTRR_SETTINGS MtrrSetting;
+ EFI_PEI_HOB_POINTERS Hob;
+ UINT64 MemoryBase;
+ UINT64 MemoryLength;
+ UINT64 Power2Length;
+ EFI_BOOT_MODE BootMode;
+ UINTN Index;
+ UINT64 SmramSize;
+ UINT64 SmramBase;
+ EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock;
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ if (BootMode == BOOT_ON_S3_RESUME) {
+ return EFI_SUCCESS;
+ }
+ //
+ // Clear the CAR Settings
+ //
+ ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS));
+
+ //
+ // Default Cachable attribute will be set to WB to support large memory size/hot plug memory
+ //
+ MtrrSetting.MtrrDefType &= ~((UINT64)(0xFF));
+ MtrrSetting.MtrrDefType |= (UINT64) CacheWriteBack;
+
+ //
+ // Set fixed cache for memory range below 1MB
+ //
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ 0x0,
+ 0xA0000,
+ CacheWriteBack
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ 0xA0000,
+ 0x20000,
+ CacheUncacheable
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ 0xC0000,
+ 0x40000,
+ CacheWriteProtected
+ );
+ ASSERT_EFI_ERROR ( Status);
+
+ //
+ // PI SMM IPL can't set SMRAM to WB because at that time CPU ARCH protocol is not available.
+ // Set cacheability of SMRAM to WB here to improve SMRAM initialization performance.
+ //
+ SmramSize = 0;
+ SmramBase = 0;
+ Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
+ while (!END_OF_HOB_LIST (Hob)) {
+ if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION) {
+ if (CompareGuid (&Hob.Guid->Name, &gEfiSmmSmramMemoryGuid)) {
+ SmramHobDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) (Hob.Guid + 1);
+ for (Index = 0; Index < SmramHobDescriptorBlock->NumberOfSmmReservedRegions; Index++) {
+ if (SmramHobDescriptorBlock->Descriptor[Index].PhysicalStart > 0x100000) {
+ SmramSize += SmramHobDescriptorBlock->Descriptor[Index].PhysicalSize;
+ if (SmramBase == 0 || SmramBase > SmramHobDescriptorBlock->Descriptor[Index].CpuStart) {
+ SmramBase = SmramHobDescriptorBlock->Descriptor[Index].CpuStart;
+ }
+ }
+ }
+ break;
+ }
+ }
+ Hob.Raw = GET_NEXT_HOB (Hob);
+ }
+
+ //
+ // Set non system memory as UC
+ //
+ MemoryBase = 0x100000000;
+
+ //
+ // Add IED size to set whole SMRAM as WB to save MTRR count
+ //
+ MemoryLength = MemoryBase - (SmramBase + SmramSize);
+ while (MemoryLength != 0) {
+ Power2Length = GetPowerOfTwo64 (MemoryLength);
+ MemoryBase -= Power2Length;
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ MemoryBase,
+ Power2Length,
+ CacheUncacheable
+ );
+ ASSERT_EFI_ERROR (Status);
+ MemoryLength -= Power2Length;
+ }
+
+ DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBLimit - 0x%lx\n", PcdGet64 (PcdPciReservedMemAbove4GBLimit)));
+ DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBBase - 0x%lx\n", PcdGet64 (PcdPciReservedMemAbove4GBBase)));
+ if (PcdGet64 (PcdPciReservedMemAbove4GBLimit) > PcdGet64 (PcdPciReservedMemAbove4GBBase)) {
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ PcdGet64 (PcdPciReservedMemAbove4GBBase),
+ PcdGet64 (PcdPciReservedMemAbove4GBLimit) - PcdGet64 (PcdPciReservedMemAbove4GBBase) + 1,
+ CacheUncacheable
+ );
+ ASSERT_EFI_ERROR ( Status);
+ }
+
+ DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBLimit - 0x%lx\n", PcdGet64 (PcdPciReservedPMemAbove4GBLimit)));
+ DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBBase - 0x%lx\n", PcdGet64 (PcdPciReservedPMemAbove4GBBase)));
+ if (PcdGet64 (PcdPciReservedPMemAbove4GBLimit) > PcdGet64 (PcdPciReservedPMemAbove4GBBase)) {
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ &MtrrSetting,
+ PcdGet64 (PcdPciReservedPMemAbove4GBBase),
+ PcdGet64 (PcdPciReservedPMemAbove4GBLimit) - PcdGet64 (PcdPciReservedPMemAbove4GBBase) + 1,
+ CacheUncacheable
+ );
+ ASSERT_EFI_ERROR ( Status);
+ }
+
+ //
+ // Update MTRR setting from MTRR buffer
+ //
+ MtrrSetAllMtrrs (&MtrrSetting);
+
+ return Status;
+}
diff --git a/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull.c b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull.c
new file mode 100644
index 0000000000..581bc7648b
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull.c
@@ -0,0 +1,37 @@
+/** @file
+
+NULL instances of SetCache library functions.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include <Uefi.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+/**
+ Set Cache Mtrr.
+**/
+VOID
+EFIAPI
+SetCacheMtrr (
+ VOID
+ )
+{
+ return;
+}
+
+/**
+ Update MTRR setting and set write back as default memory attribute.
+
+ @retval EFI_SUCCESS The function completes successfully.
+**/
+EFI_STATUS
+EFIAPI
+SetCacheMtrrAfterEndOfPei (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.c b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.c
index 70e6b9a495..df64d4fc0d 100644
--- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.c
+++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.c
@@ -13,8 +13,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/PeiServicesLib.h>
#include <IndustryStandard/Pci30.h>
#include <Ppi/EndOfPeiPhase.h>
-#include <Library/MtrrLib.h>
-#include <Guid/SmramMemoryReserve.h>
#include <Guid/FirmwareFileSystem2.h>
#include <Protocol/FirmwareVolumeBlock.h>
@@ -22,6 +20,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/TimerLib.h>
#include <Library/BoardInitLib.h>
#include <Library/TestPointCheckLib.h>
+#include <Library/SetCacheLib.h>
EFI_STATUS
EFIAPI
@@ -38,152 +37,6 @@ static EFI_PEI_NOTIFY_DESCRIPTOR mEndOfPeiNotifyList = {
};
/**
- Update MTRR setting and set write back as default memory attribute.
-
- @retval EFI_SUCCESS The function completes successfully.
- @retval Others Some error occurs.
-**/
-EFI_STATUS
-EFIAPI
-SetCacheMtrrAfterEndOfPei (
- VOID
- )
-{
- EFI_STATUS Status;
- MTRR_SETTINGS MtrrSetting;
- EFI_PEI_HOB_POINTERS Hob;
- UINT64 MemoryBase;
- UINT64 MemoryLength;
- UINT64 Power2Length;
- EFI_BOOT_MODE BootMode;
- UINTN Index;
- UINT64 SmramSize;
- UINT64 SmramBase;
- EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock;
- Status = PeiServicesGetBootMode (&BootMode);
- ASSERT_EFI_ERROR (Status);
-
- if (BootMode == BOOT_ON_S3_RESUME) {
- return EFI_SUCCESS;
- }
- //
- // Clear the CAR Settings
- //
- ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS));
-
- //
- // Default Cachable attribute will be set to WB to support large memory size/hot plug memory
- //
- MtrrSetting.MtrrDefType &= ~((UINT64)(0xFF));
- MtrrSetting.MtrrDefType |= (UINT64) CacheWriteBack;
-
- //
- // Set fixed cache for memory range below 1MB
- //
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- 0x0,
- 0xA0000,
- CacheWriteBack
- );
- ASSERT_EFI_ERROR (Status);
-
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- 0xA0000,
- 0x20000,
- CacheUncacheable
- );
- ASSERT_EFI_ERROR (Status);
-
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- 0xC0000,
- 0x40000,
- CacheWriteProtected
- );
- ASSERT_EFI_ERROR ( Status);
-
- //
- // PI SMM IPL can't set SMRAM to WB because at that time CPU ARCH protocol is not available.
- // Set cacheability of SMRAM to WB here to improve SMRAM initialization performance.
- //
- SmramSize = 0;
- SmramBase = 0;
- Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
- while (!END_OF_HOB_LIST (Hob)) {
- if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION) {
- if (CompareGuid (&Hob.Guid->Name, &gEfiSmmSmramMemoryGuid)) {
- SmramHobDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) (Hob.Guid + 1);
- for (Index = 0; Index < SmramHobDescriptorBlock->NumberOfSmmReservedRegions; Index++) {
- if (SmramHobDescriptorBlock->Descriptor[Index].PhysicalStart > 0x100000) {
- SmramSize += SmramHobDescriptorBlock->Descriptor[Index].PhysicalSize;
- if (SmramBase == 0 || SmramBase > SmramHobDescriptorBlock->Descriptor[Index].CpuStart) {
- SmramBase = SmramHobDescriptorBlock->Descriptor[Index].CpuStart;
- }
- }
- }
- break;
- }
- }
- Hob.Raw = GET_NEXT_HOB (Hob);
- }
-
- //
- // Set non system memory as UC
- //
- MemoryBase = 0x100000000;
-
- //
- // Add IED size to set whole SMRAM as WB to save MTRR count
- //
- MemoryLength = MemoryBase - (SmramBase + SmramSize);
- while (MemoryLength != 0) {
- Power2Length = GetPowerOfTwo64 (MemoryLength);
- MemoryBase -= Power2Length;
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- Power2Length,
- CacheUncacheable
- );
- ASSERT_EFI_ERROR (Status);
- MemoryLength -= Power2Length;
- }
-
- DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBLimit - 0x%lx\n", PcdGet64 (PcdPciReservedMemAbove4GBLimit)));
- DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBBase - 0x%lx\n", PcdGet64 (PcdPciReservedMemAbove4GBBase)));
- if (PcdGet64 (PcdPciReservedMemAbove4GBLimit) > PcdGet64 (PcdPciReservedMemAbove4GBBase)) {
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- PcdGet64 (PcdPciReservedMemAbove4GBBase),
- PcdGet64 (PcdPciReservedMemAbove4GBLimit) - PcdGet64 (PcdPciReservedMemAbove4GBBase) + 1,
- CacheUncacheable
- );
- ASSERT_EFI_ERROR ( Status);
- }
-
- DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBLimit - 0x%lx\n", PcdGet64 (PcdPciReservedPMemAbove4GBLimit)));
- DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBBase - 0x%lx\n", PcdGet64 (PcdPciReservedPMemAbove4GBBase)));
- if (PcdGet64 (PcdPciReservedPMemAbove4GBLimit) > PcdGet64 (PcdPciReservedPMemAbove4GBBase)) {
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- PcdGet64 (PcdPciReservedPMemAbove4GBBase),
- PcdGet64 (PcdPciReservedPMemAbove4GBLimit) - PcdGet64 (PcdPciReservedPMemAbove4GBBase) + 1,
- CacheUncacheable
- );
- ASSERT_EFI_ERROR ( Status);
- }
-
- //
- // Update MTRR setting from MTRR buffer
- //
- MtrrSetAllMtrrs (&MtrrSetting);
-
- return Status;
-}
-
-/**
This function handles PlatformInit task at the end of PEI
@param[in] PeiServices Pointer to PEI Services Table.
diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c
index 2690511abe..731bc234b0 100644
--- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c
+++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c
@@ -1,7 +1,7 @@
/** @file
Source code file for Platform Init Pre-Memory PEI module
-Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -15,7 +15,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/TimerLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/PeiServicesLib.h>
-#include <Library/MtrrLib.h>
#include <Library/ReportFvLib.h>
#include <Ppi/ReadOnlyVariable2.h>
#include <Ppi/MemoryDiscovered.h>
@@ -26,6 +25,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/PeiServicesTablePointerLib.h>
#include <Library/BoardInitLib.h>
#include <Library/TestPointCheckLib.h>
+#include <Library/SetCacheLib.h>
#include <Guid/MemoryTypeInformation.h>
#include <Ppi/PlatformMemorySize.h>
#include <Ppi/BaseMemoryTest.h>
@@ -319,166 +319,6 @@ Done:
return EFI_SUCCESS;
}
-/**
- Set Cache Mtrr.
-**/
-VOID
-SetCacheMtrr (
- VOID
- )
-{
- EFI_STATUS Status;
- EFI_PEI_HOB_POINTERS Hob;
- MTRR_SETTINGS MtrrSetting;
- UINT64 MemoryBase;
- UINT64 MemoryLength;
- UINT64 LowMemoryLength;
- UINT64 HighMemoryLength;
- EFI_BOOT_MODE BootMode;
- EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
- UINT64 CacheMemoryLength;
-
- ///
- /// Reset all MTRR setting.
- ///
- ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS));
-
- ///
- /// Cache the Flash area as WP to boost performance
- ///
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- (UINTN) PcdGet32 (PcdFlashAreaBaseAddress),
- (UINTN) PcdGet32 (PcdFlashAreaSize),
- CacheWriteProtected
- );
- ASSERT_EFI_ERROR (Status);
-
- ///
- /// Update MTRR setting from MTRR buffer for Flash Region to be WP to boost performance
- ///
- MtrrSetAllMtrrs (&MtrrSetting);
-
- ///
- /// Set low to 1 MB. Since 1MB cacheability will always be set
- /// until override by CSM.
- /// Initialize high memory to 0.
- ///
- LowMemoryLength = 0x100000;
- HighMemoryLength = 0;
- ResourceAttribute = (
- EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
- );
-
- Status = PeiServicesGetBootMode (&BootMode);
- ASSERT_EFI_ERROR (Status);
-
- if (BootMode != BOOT_ON_S3_RESUME) {
- ResourceAttribute |= EFI_RESOURCE_ATTRIBUTE_TESTED;
- }
-
- Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
- while (!END_OF_HOB_LIST (Hob)) {
- if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
- if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) ||
- ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) &&
- (Hob.ResourceDescriptor->ResourceAttribute == ResourceAttribute))
- ) {
- if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000000ULL) {
- HighMemoryLength += Hob.ResourceDescriptor->ResourceLength;
- } else if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000) {
- LowMemoryLength += Hob.ResourceDescriptor->ResourceLength;
- }
- }
- }
-
- Hob.Raw = GET_NEXT_HOB (Hob);
- }
-
- DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) = %lx.\n", LowMemoryLength));
- DEBUG ((DEBUG_INFO, "Memory Length (Above 4GB) = %lx.\n", HighMemoryLength));
-
- ///
- /// Assume size of main memory is multiple of 256MB
- ///
- MemoryLength = (LowMemoryLength + 0xFFFFFFF) & 0xF0000000;
- MemoryBase = 0;
-
- CacheMemoryLength = MemoryLength;
- ///
- /// Programming MTRRs to avoid override SPI region with UC when MAX TOLUD Length >= 3.5GB
- ///
- if (MemoryLength > 0xDC000000) {
- CacheMemoryLength = 0xC0000000;
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- CacheMemoryLength,
- CacheWriteBack
- );
- ASSERT_EFI_ERROR (Status);
-
- MemoryBase = 0xC0000000;
- CacheMemoryLength = MemoryLength - 0xC0000000;
- if (MemoryLength > 0xE0000000) {
- CacheMemoryLength = 0x20000000;
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- CacheMemoryLength,
- CacheWriteBack
- );
- ASSERT_EFI_ERROR (Status);
-
- MemoryBase = 0xE0000000;
- CacheMemoryLength = MemoryLength - 0xE0000000;
- }
- }
-
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- CacheMemoryLength,
- CacheWriteBack
- );
- ASSERT_EFI_ERROR (Status);
-
- if (LowMemoryLength != MemoryLength) {
- MemoryBase = LowMemoryLength;
- MemoryLength -= LowMemoryLength;
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- MemoryLength,
- CacheUncacheable
- );
- ASSERT_EFI_ERROR (Status);
- }
-
- ///
- /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC
- ///
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- 0xA0000,
- 0x20000,
- CacheUncacheable
- );
- ASSERT_EFI_ERROR (Status);
-
- ///
- /// Update MTRR setting from MTRR buffer
- ///
- MtrrSetAllMtrrs (&MtrrSetting);
-
- return ;
-}
-
VOID
ReportCpuHob (
VOID
diff --git a/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheLib.h b/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheLib.h
new file mode 100644
index 0000000000..d67426cef7
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheLib.h
@@ -0,0 +1,34 @@
+/** @file
+
+Header for SetCache library functions.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _SET_CACHE_LIB_H_
+#define _SET_CACHE_LIB_H_
+
+/**
+ Set Cache Mtrr.
+**/
+VOID
+EFIAPI
+SetCacheMtrr (
+ VOID
+ );
+
+/**
+ Update MTRR setting and set write back as default memory attribute.
+
+ @retval EFI_SUCCESS The function completes successfully.
+ @retval Others Some error occurs.
+**/
+EFI_STATUS
+EFIAPI
+SetCacheMtrrAfterEndOfPei (
+ VOID
+ );
+
+#endif
diff --git a/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.inf b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.inf
new file mode 100644
index 0000000000..a53aed858f
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.inf
@@ -0,0 +1,44 @@
+## @file
+# Component information file for Platform SetCache Library
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SetCacheLib
+ FILE_GUID = 9F2A2899-3AD7-4176-9B89-33B3AC456A99
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SetCacheLib
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ DebugLib
+ HobLib
+ MtrrLib
+ PeiServicesLib
+ BaseMemoryLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[Sources]
+ SetCacheLib.c
+
+[Guids]
+ gEfiSmmSmramMemoryGuid ## CONSUMES
+
+[Pcd]
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit ## CONSUMES
diff --git a/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull.inf b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull.inf
new file mode 100644
index 0000000000..50419b398b
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull.inf
@@ -0,0 +1,30 @@
+## @file
+# Component information file for Platform SetCache Library
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SetCacheLibNull
+ FILE_GUID = D1ED4CD7-AD20-4943-9192-3ABE766A9411
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SetCacheLib
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ DebugLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ MdePkg/MdePkg.dec
+
+[Sources]
+ SetCacheLibNull.c
+
+[Pcd]
diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
index 0736c8d494..a14f20f150 100644
--- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
+++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
@@ -23,15 +23,14 @@
BaseMemoryLib
HobLib
PeiServicesLib
- MtrrLib
BoardInitLib
TestPointCheckLib
+ SetCacheLib
[Packages]
MinPlatformPkg/MinPlatformPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- UefiCpuPkg/UefiCpuPkg.dec
[Sources]
PlatformInitPostMem.c
@@ -44,14 +43,6 @@
[Protocols]
-[Guids]
- gEfiSmmSmramMemoryGuid ## CONSUMES
-
[Depex]
gEfiPeiMemoryDiscoveredPpiGuid
-[Pcd]
- gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase
- gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit
- gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBBase
- gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit
diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
index 2c3a13106e..de5f11f829 100644
--- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
+++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
@@ -1,7 +1,7 @@
### @file
# Component information file for the Platform Init Pre-Memory PEI module.
#
-# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -22,23 +22,20 @@
HobLib
IoLib
MemoryAllocationLib
- MtrrLib
PeimEntryPoint
PeiServicesLib
ReportFvLib
TestPointCheckLib
TimerLib
+ SetCacheLib
[Packages]
MinPlatformPkg/MinPlatformPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- UefiCpuPkg/UefiCpuPkg.dec
[Pcd]
gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES
gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit ## CONSUMES
gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit ## CONSUMES
--
2.13.3.windows.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [edk2-platforms: PATCH 2/5] KabylakeOpenBoardPkg: Add SetCacheLib library class.
2019-10-30 12:29 [edk2-platforms: PATCH 0/5] Add SetCacheLib library class Chiu, Chasel
2019-10-30 12:29 ` [edk2-platforms: PATCH 1/5] MinPlatformPkg: " Chiu, Chasel
@ 2019-10-30 12:29 ` Chiu, Chasel
2019-10-30 12:29 ` [edk2-platforms: PATCH 3/5] WhiskeylakeOpenBoardPkg: " Chiu, Chasel
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Chiu, Chasel @ 2019-10-30 12:29 UTC (permalink / raw)
To: devel; +Cc: Michael Kubacki, Nate DeSimone, Liming Gao, Jeremy Soller
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2314
Kabylake boards are relying on FSP to configure MTRRs so
they can include SetCacheLibNull.
Test: internal platform can boot with FSP API and Dispatch modes.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c | 640 ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc | 3 ++-
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf | 67 -------------------------------------------------------------------
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 1 +
5 files changed, 4 insertions(+), 709 deletions(-)
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c
deleted file mode 100644
index b784026c1b..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c
+++ /dev/null
@@ -1,640 +0,0 @@
-/** @file
- Source code file for Platform Init Pre-Memory PEI module
-
-Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <Base.h>
-#include <IndustryStandard/Pci30.h>
-#include <Library/IoLib.h>
-#include <Library/DebugLib.h>
-#include <Library/HobLib.h>
-#include <Library/PcdLib.h>
-#include <Library/TimerLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/PeiServicesLib.h>
-#include <Library/MtrrLib.h>
-#include <Library/ReportFvLib.h>
-#include <Ppi/ReadOnlyVariable2.h>
-#include <Ppi/MemoryDiscovered.h>
-#include <Ppi/FirmwareVolumeInfo.h>
-#include <Ppi/BootInRecoveryMode.h>
-#include <Ppi/MasterBootMode.h>
-#include <Guid/FirmwareFileSystem2.h>
-#include <Library/PeiServicesTablePointerLib.h>
-#include <Library/BoardInitLib.h>
-#include <Library/TestPointCheckLib.h>
-#include <Guid/MemoryTypeInformation.h>
-#include <Ppi/PlatformMemorySize.h>
-#include <Ppi/BaseMemoryTest.h>
-
-EFI_STATUS
-EFIAPI
-MemoryDiscoveredPpiNotifyCallback (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
- IN VOID *Ppi
- );
-
-EFI_STATUS
-EFIAPI
-GetPlatformMemorySize (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_PLATFORM_MEMORY_SIZE_PPI *This,
- IN OUT UINT64 *MemorySize
- );
-
-/**
-
- This function checks the memory range in PEI.
-
- @param PeiServices Pointer to PEI Services.
- @param This Pei memory test PPI pointer.
- @param BeginAddress Beginning of the memory address to be checked.
- @param MemoryLength Bytes of memory range to be checked.
- @param Operation Type of memory check operation to be performed.
- @param ErrorAddress Return the address of the error memory address.
-
- @retval EFI_SUCCESS The operation completed successfully.
- @retval EFI_DEVICE_ERROR Memory test failed. It's not safe to use this range of memory.
-
-**/
-EFI_STATUS
-EFIAPI
-BaseMemoryTest (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_BASE_MEMORY_TEST_PPI *This,
- IN EFI_PHYSICAL_ADDRESS BeginAddress,
- IN UINT64 MemoryLength,
- IN PEI_MEMORY_TEST_OP Operation,
- OUT EFI_PHYSICAL_ADDRESS *ErrorAddress
- );
-
-static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList = {
- (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
- &gEfiPeiMemoryDiscoveredPpiGuid,
- (EFI_PEIM_NOTIFY_ENTRY_POINT) MemoryDiscoveredPpiNotifyCallback
-};
-
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mPpiListRecoveryBootMode = {
- (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
- &gEfiPeiBootInRecoveryModePpiGuid,
- NULL
-};
-
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mPpiBootMode = {
- (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
- &gEfiPeiMasterBootModePpiGuid,
- NULL
-};
-
-static PEI_BASE_MEMORY_TEST_PPI mPeiBaseMemoryTestPpi = { BaseMemoryTest };
-
-static PEI_PLATFORM_MEMORY_SIZE_PPI mMemoryMemorySizePpi = { GetPlatformMemorySize };
-
-static EFI_PEI_PPI_DESCRIPTOR mMemPpiList[] = {
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI,
- &gPeiBaseMemoryTestPpiGuid,
- &mPeiBaseMemoryTestPpi
- },
- {
- (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
- &gPeiPlatformMemorySizePpiGuid,
- &mMemoryMemorySizePpi
- },
-};
-
-///
-/// Memory Reserved should be between 125% to 150% of the Current required memory
-/// otherwise BdsMisc.c would do a reset to make it 125% to avoid s4 resume issues.
-///
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
- { EfiACPIReclaimMemory, FixedPcdGet32 (PcdPlatformEfiAcpiReclaimMemorySize) }, // ASL
- { EfiACPIMemoryNVS, FixedPcdGet32 (PcdPlatformEfiAcpiNvsMemorySize) }, // ACPI NVS (including S3 related)
- { EfiReservedMemoryType, FixedPcdGet32 (PcdPlatformEfiReservedMemorySize) }, // BIOS Reserved (including S3 related)
- { EfiRuntimeServicesData, FixedPcdGet32 (PcdPlatformEfiRtDataMemorySize) }, // Runtime Service Data
- { EfiRuntimeServicesCode, FixedPcdGet32 (PcdPlatformEfiRtCodeMemorySize) }, // Runtime Service Code
- { EfiMaxMemoryType, 0 }
-};
-
-VOID
-BuildMemoryTypeInformation (
- VOID
- )
-{
- EFI_STATUS Status;
- EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
- UINTN DataSize;
- EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1];
-
- //
- // Locate system configuration variable
- //
- Status = PeiServicesLocatePpi(
- &gEfiPeiReadOnlyVariable2PpiGuid, // GUID
- 0, // INSTANCE
- NULL, // EFI_PEI_PPI_DESCRIPTOR
- (VOID **) &VariableServices // PPI
- );
- ASSERT_EFI_ERROR(Status);
-
- DataSize = sizeof (MemoryData);
- Status = VariableServices->GetVariable (
- VariableServices,
- EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,
- &gEfiMemoryTypeInformationGuid,
- NULL,
- &DataSize,
- &MemoryData
- );
- if (EFI_ERROR(Status)) {
- DataSize = sizeof (mDefaultMemoryTypeInformation);
- CopyMem(MemoryData, mDefaultMemoryTypeInformation, DataSize);
- }
-
- ///
- /// Build the GUID'd HOB for DXE
- ///
- BuildGuidDataHob (
- &gEfiMemoryTypeInformationGuid,
- MemoryData,
- DataSize
- );
-}
-
-EFI_STATUS
-EFIAPI
-GetPlatformMemorySize (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_PLATFORM_MEMORY_SIZE_PPI *This,
- IN OUT UINT64 *MemorySize
- )
-{
- EFI_STATUS Status;
- EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
- UINTN DataSize;
- EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1];
- UINTN Index;
- EFI_BOOT_MODE BootMode;
- UINTN IndexNumber;
-
-#define PEI_MIN_MEMORY_SIZE (EFI_PHYSICAL_ADDRESS) ((320 * 0x100000))
-
- *MemorySize = PEI_MIN_MEMORY_SIZE;
- Status = PeiServicesLocatePpi (
- &gEfiPeiReadOnlyVariable2PpiGuid,
- 0,
- NULL,
- (VOID **)&Variable
- );
-
- ASSERT_EFI_ERROR (Status);
-
- Status = PeiServicesGetBootMode (&BootMode);
- ASSERT_EFI_ERROR (Status);
-
- DataSize = sizeof (MemoryData);
-
- Status = Variable->GetVariable (
- Variable,
- EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,
- &gEfiMemoryTypeInformationGuid,
- NULL,
- &DataSize,
- &MemoryData
- );
- IndexNumber = sizeof (mDefaultMemoryTypeInformation) / sizeof (EFI_MEMORY_TYPE_INFORMATION);
-
- //
- // Accumulate maximum amount of memory needed
- //
-
- DEBUG((DEBUG_ERROR, "PEI_MIN_MEMORY_SIZE:%dKB \n", DivU64x32(*MemorySize,1024)));
- DEBUG((DEBUG_ERROR, "IndexNumber:%d MemoryDataNumber%d \n", IndexNumber,DataSize/ sizeof (EFI_MEMORY_TYPE_INFORMATION)));
- if (EFI_ERROR (Status)) {
- //
- // Start with minimum memory
- //
- for (Index = 0; Index < IndexNumber; Index++) {
- DEBUG((DEBUG_ERROR, "Index[%d].Type = %d .NumberOfPages=0x%x\n", Index,mDefaultMemoryTypeInformation[Index].Type,mDefaultMemoryTypeInformation[Index].NumberOfPages));
- *MemorySize += mDefaultMemoryTypeInformation[Index].NumberOfPages * EFI_PAGE_SIZE;
- }
- DEBUG((DEBUG_ERROR, "No memory type, Total platform memory:%dKB \n", DivU64x32(*MemorySize,1024)));
- } else {
- //
- // Start with at least 0x200 pages of memory for the DXE Core and the DXE Stack
- //
- for (Index = 0; Index < IndexNumber; Index++) {
- DEBUG((DEBUG_ERROR, "Index[%d].Type = %d .NumberOfPages=0x%x\n", Index,MemoryData[Index].Type,MemoryData[Index].NumberOfPages));
- *MemorySize += MemoryData[Index].NumberOfPages * EFI_PAGE_SIZE;
-
- }
- DEBUG((DEBUG_ERROR, "has memory type, Total platform memory:%dKB \n", DivU64x32(*MemorySize,1024)));
- }
-
- return EFI_SUCCESS;
-}
-
-/**
-
- This function checks the memory range in PEI.
-
- @param PeiServices Pointer to PEI Services.
- @param This Pei memory test PPI pointer.
- @param BeginAddress Beginning of the memory address to be checked.
- @param MemoryLength Bytes of memory range to be checked.
- @param Operation Type of memory check operation to be performed.
- @param ErrorAddress Return the address of the error memory address.
-
- @retval EFI_SUCCESS The operation completed successfully.
- @retval EFI_DEVICE_ERROR Memory test failed. It's not safe to use this range of memory.
-
-**/
-EFI_STATUS
-EFIAPI
-BaseMemoryTest (
- IN EFI_PEI_SERVICES **PeiServices,
- IN PEI_BASE_MEMORY_TEST_PPI *This,
- IN EFI_PHYSICAL_ADDRESS BeginAddress,
- IN UINT64 MemoryLength,
- IN PEI_MEMORY_TEST_OP Operation,
- OUT EFI_PHYSICAL_ADDRESS *ErrorAddress
- )
-{
- UINT32 TestPattern;
- UINT32 SpanSize;
- EFI_PHYSICAL_ADDRESS TempAddress;
-
-#define MEMORY_TEST_PATTERN 0x5A5A5A5A
-#define MEMORY_TEST_COVER_SPAN 0x40000
-
- TestPattern = MEMORY_TEST_PATTERN;
- SpanSize = 0;
-
- //
- // Make sure we don't try and test anything above the max physical address range
- //
- ASSERT (BeginAddress + MemoryLength < MAX_ADDRESS);
-
- switch (Operation) {
- case Extensive:
- SpanSize = 0x4;
- break;
-
- case Sparse:
- case Quick:
- SpanSize = MEMORY_TEST_COVER_SPAN;
- break;
-
- case Ignore:
- goto Done;
- break;
- }
- //
- // Write the test pattern into memory range
- //
- TempAddress = BeginAddress;
- while (TempAddress < BeginAddress + MemoryLength) {
- (*(UINT32 *) (UINTN) TempAddress) = TestPattern;
- TempAddress += SpanSize;
- }
- //
- // Read pattern from memory and compare it
- //
- TempAddress = BeginAddress;
- while (TempAddress < BeginAddress + MemoryLength) {
- if ((*(UINT32 *) (UINTN) TempAddress) != TestPattern) {
- *ErrorAddress = TempAddress;
- return EFI_DEVICE_ERROR;
- }
-
- TempAddress += SpanSize;
- }
-
-Done:
-
- return EFI_SUCCESS;
-}
-
-/**
- Set Cache Mtrr.
-**/
-VOID
-SetCacheMtrr (
- VOID
- )
-{
- EFI_STATUS Status;
- EFI_PEI_HOB_POINTERS Hob;
- MTRR_SETTINGS MtrrSetting;
- UINT64 MemoryBase;
- UINT64 MemoryLength;
- UINT64 LowMemoryLength;
- UINT64 HighMemoryLength;
- EFI_BOOT_MODE BootMode;
- EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
- UINT64 CacheMemoryLength;
-
- ///
- /// Reset all MTRR setting.
- ///
- ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS));
-
- ///
- /// Cache the Flash area as WP to boost performance
- ///
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- (UINTN) PcdGet32 (PcdFlashAreaBaseAddress),
- (UINTN) PcdGet32 (PcdFlashAreaSize),
- CacheWriteProtected
- );
- ASSERT_EFI_ERROR (Status);
-
- ///
- /// Update MTRR setting from MTRR buffer for Flash Region to be WP to boost performance
- ///
- MtrrSetAllMtrrs (&MtrrSetting);
-
- ///
- /// Set low to 1 MB. Since 1MB cacheability will always be set
- /// until override by CSM.
- /// Initialize high memory to 0.
- ///
- LowMemoryLength = 0x100000;
- HighMemoryLength = 0;
- ResourceAttribute = (
- EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
- );
-
- Status = PeiServicesGetBootMode (&BootMode);
- ASSERT_EFI_ERROR (Status);
-
- if (BootMode != BOOT_ON_S3_RESUME) {
- ResourceAttribute |= EFI_RESOURCE_ATTRIBUTE_TESTED;
- }
-
- Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
- while (!END_OF_HOB_LIST (Hob)) {
- if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
- if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) ||
- ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) &&
- (Hob.ResourceDescriptor->ResourceAttribute == ResourceAttribute))
- ) {
- if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000000ULL) {
- HighMemoryLength += Hob.ResourceDescriptor->ResourceLength;
- } else if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000) {
- LowMemoryLength += Hob.ResourceDescriptor->ResourceLength;
- }
- }
- }
-
- Hob.Raw = GET_NEXT_HOB (Hob);
- }
-
- DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) = %lx.\n", LowMemoryLength));
- DEBUG ((DEBUG_INFO, "Memory Length (Above 4GB) = %lx.\n", HighMemoryLength));
-
- ///
- /// Assume size of main memory is multiple of 256MB
- ///
- MemoryLength = (LowMemoryLength + 0xFFFFFFF) & 0xF0000000;
- MemoryBase = 0;
-
- CacheMemoryLength = MemoryLength;
- ///
- /// Programming MTRRs to avoid override SPI region with UC when MAX TOLUD Length >= 3.5GB
- ///
- if (MemoryLength > 0xDC000000) {
- CacheMemoryLength = 0xC0000000;
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- CacheMemoryLength,
- CacheWriteBack
- );
- ASSERT_EFI_ERROR (Status);
-
- MemoryBase = 0xC0000000;
- CacheMemoryLength = MemoryLength - 0xC0000000;
- if (MemoryLength > 0xE0000000) {
- CacheMemoryLength = 0x20000000;
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- CacheMemoryLength,
- CacheWriteBack
- );
- ASSERT_EFI_ERROR (Status);
-
- MemoryBase = 0xE0000000;
- CacheMemoryLength = MemoryLength - 0xE0000000;
- }
- }
-
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- CacheMemoryLength,
- CacheWriteBack
- );
- ASSERT_EFI_ERROR (Status);
-
- if (LowMemoryLength != MemoryLength) {
- MemoryBase = LowMemoryLength;
- MemoryLength -= LowMemoryLength;
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- MemoryBase,
- MemoryLength,
- CacheUncacheable
- );
- ASSERT_EFI_ERROR (Status);
- }
-
- ///
- /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC
- ///
- Status = MtrrSetMemoryAttributeInMtrrSettings (
- &MtrrSetting,
- 0xA0000,
- 0x20000,
- CacheUncacheable
- );
- ASSERT_EFI_ERROR (Status);
-
- ///
- /// Update MTRR setting from MTRR buffer
- ///
- MtrrSetAllMtrrs (&MtrrSetting);
-
- return ;
-}
-
-VOID
-ReportCpuHob (
- VOID
- )
-{
- UINT8 PhysicalAddressBits;
- UINT32 RegEax;
-
- AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
- if (RegEax >= 0x80000008) {
- AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
- PhysicalAddressBits = (UINT8) RegEax;
- } else {
- PhysicalAddressBits = 36;
- }
-
- ///
- /// Create a CPU hand-off information
- ///
- BuildCpuHob (PhysicalAddressBits, 16);
-}
-
-/**
- Install Firmware Volume Hob's once there is main memory
-
- @param[in] PeiServices General purpose services available to every PEIM.
- @param[in] NotifyDescriptor Notify that this module published.
- @param[in] Ppi PPI that was installed.
-
- @retval EFI_SUCCESS The function completed successfully.
-**/
-EFI_STATUS
-EFIAPI
-MemoryDiscoveredPpiNotifyCallback (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
- IN VOID *Ppi
- )
-{
- EFI_STATUS Status;
- EFI_BOOT_MODE BootMode;
-
- Status = BoardInitAfterMemoryInit ();
- ASSERT_EFI_ERROR (Status);
-
- Status = PeiServicesGetBootMode (&BootMode);
- ASSERT_EFI_ERROR (Status);
-
-
- ReportCpuHob ();
-
- TestPointMemoryDiscoveredMtrrFunctional ();
-
- TestPointMemoryDiscoveredMemoryResourceFunctional ();
-
- ///
- /// If S3 resume, then we are done
- ///
- if (BootMode == BOOT_ON_S3_RESUME) {
- return EFI_SUCCESS;
- }
-
- TestPointMemoryDiscoveredDmaProtectionEnabled ();
-
- if (PcdGetBool (PcdStopAfterMemInit)) {
- CpuDeadLoop ();
- }
-
- return Status;
-}
-
-
-/**
- This function handles PlatformInit task after PeiReadOnlyVariable2 PPI produced
-
- @param[in] PeiServices Pointer to PEI Services Table.
-
- @retval EFI_SUCCESS The function completes successfully
- @retval others
-**/
-EFI_STATUS
-EFIAPI
-PlatformInitPreMem (
- IN CONST EFI_PEI_SERVICES **PeiServices
- )
-{
- EFI_STATUS Status;
- EFI_BOOT_MODE BootMode;
-
- //
- // Start board detection
- //
- BoardDetect ();
-
- BoardDebugInit ();
-
- TestPointDebugInitDone ();
-
- if (PcdGetBool (PcdStopAfterDebugInit)) {
- CpuDeadLoop ();
- }
-
- BootMode = BoardBootModeDetect ();
- Status = PeiServicesSetBootMode (BootMode);
- ASSERT_EFI_ERROR (Status);
- if (BootMode == BOOT_IN_RECOVERY_MODE) {
- Status = PeiServicesInstallPpi (&mPpiListRecoveryBootMode);
- }
- ///
- /// Signal possible dependent modules that there has been a
- /// final boot mode determination, it is used to build BIST
- /// Hob for Dxe use.
- ///
- Status = PeiServicesInstallPpi (&mPpiBootMode);
- ASSERT_EFI_ERROR (Status);
-
- BuildMemoryTypeInformation ();
-
- if (!PcdGetBool(PcdFspWrapperBootMode)) {
- Status = PeiServicesInstallPpi (mMemPpiList);
- ASSERT_EFI_ERROR (Status);
- }
-
- Status = BoardInitBeforeMemoryInit ();
- ASSERT_EFI_ERROR (Status);
-
- return Status;
-}
-
-
-/**
- Platform Init before memory PEI module entry point
-
- @param[in] FileHandle Not used.
- @param[in] PeiServices General purpose services available to every PEIM.
-
- @retval EFI_SUCCESS The function completes successfully
- @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database
-**/
-EFI_STATUS
-EFIAPI
-PlatformInitPreMemEntryPoint (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
- )
-{
- EFI_STATUS Status;
-
- Status = PlatformInitPreMem (PeiServices);
-
- ///
- /// After code reorangized, memorycallback will run because the PPI is already
- /// installed when code run to here, it is supposed that the InstallEfiMemory is
- /// done before.
- ///
- Status = PeiServicesNotifyPpi (&mMemDiscoveredNotifyList);
-
- return Status;
-}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
index f59248bba4..d1384d9773 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
@@ -159,6 +159,7 @@
#######################################
DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+ SetCacheLib|$(PLATFORM_PACKAGE)/Library/SetCacheLib/SetCacheLibNull.inf
#######################################
# Platform Package
@@ -260,7 +261,7 @@
# Platform Package
#######################################
$(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
- $(PROJECT)/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf {
+ $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf {
<LibraryClasses>
!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport == FALSE
BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf
index 80efab1aad..6827019c25 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf
@@ -237,7 +237,7 @@ INF MdeModulePkg/Core/Pei/PeiMain.inf
!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf
INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
-INF $(PROJECT)/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
+INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
INF $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
deleted file mode 100644
index 76dd67d1a8..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
+++ /dev/null
@@ -1,67 +0,0 @@
-### @file
-# Component information file for the Platform Init Pre-Memory PEI module.
-#
-# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-###
-
-[Defines]
- INF_VERSION = 0x00010017
- BASE_NAME = PlatformInitPreMem
- FILE_GUID = EEEE611D-F78F-4FB9-B868-55907F169280
- VERSION_STRING = 1.0
- MODULE_TYPE = PEIM
- ENTRY_POINT = PlatformInitPreMemEntryPoint
-
-[LibraryClasses]
- BaseMemoryLib
- BoardInitLib
- DebugLib
- HobLib
- IoLib
- MemoryAllocationLib
- MtrrLib
- PeimEntryPoint
- PeiServicesLib
- ReportFvLib
- TestPointCheckLib
- TimerLib
-
-[Packages]
- MinPlatformPkg/MinPlatformPkg.dec
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
- UefiCpuPkg/UefiCpuPkg.dec
-
-[Pcd]
- gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit ## CONSUMES
-
-[FixedPcd]
- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize ## CONSUMES
-
-[Sources]
- PlatformInitPreMem.c
-
-[Ppis]
- gEfiPeiMemoryDiscoveredPpiGuid
- gEfiPeiMasterBootModePpiGuid ## PRODUCES
- gEfiPeiBootInRecoveryModePpiGuid ## PRODUCES
- gEfiPeiReadOnlyVariable2PpiGuid
- gPeiBaseMemoryTestPpiGuid
- gPeiPlatformMemorySizePpiGuid
-
-[Guids]
- gEfiMemoryTypeInformationGuid
-
-[Depex]
- gEfiPeiReadOnlyVariable2PpiGuid
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
index 7e65eeda6f..6df8008215 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
@@ -208,6 +208,7 @@
!if $(TARGET) == DEBUG
TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf
!endif
+ SetCacheLib|$(PLATFORM_PACKAGE)/Library/SetCacheLib/SetCacheLibNull.inf
#######################################
# Board Package
--
2.13.3.windows.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [edk2-platforms: PATCH 3/5] WhiskeylakeOpenBoardPkg: Add SetCacheLib library class.
2019-10-30 12:29 [edk2-platforms: PATCH 0/5] Add SetCacheLib library class Chiu, Chasel
2019-10-30 12:29 ` [edk2-platforms: PATCH 1/5] MinPlatformPkg: " Chiu, Chasel
2019-10-30 12:29 ` [edk2-platforms: PATCH 2/5] KabylakeOpenBoardPkg: " Chiu, Chasel
@ 2019-10-30 12:29 ` Chiu, Chasel
2019-10-30 12:29 ` [edk2-platforms: PATCH 4/5] PurleyOpenBoardPkg/BoardMtOlympus: " Chiu, Chasel
2019-10-30 12:29 ` [edk2-platforms: PATCH 5/5] SimicsOpenBoardPkg/BoardX58Ich10: " Chiu, Chasel
4 siblings, 0 replies; 6+ messages in thread
From: Chiu, Chasel @ 2019-10-30 12:29 UTC (permalink / raw)
To: devel; +Cc: Michael Kubacki, Nate DeSimone
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2314
Whiskeylake board relying on FSP to configure MTRRs so
it can include SetCacheLibNull.
Test: internal platform can boot with FSP API modes.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc | 1 +
1 file changed, 1 insertion(+)
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
index 8e0ea2d5ce..ba06ba3c89 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
@@ -164,6 +164,7 @@
!if $(TARGET) == DEBUG
TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf
!endif
+ SetCacheLib|$(PLATFORM_PACKAGE)/Library/SetCacheLib/SetCacheLibNull.inf
#######################################
# Board Package
--
2.13.3.windows.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [edk2-platforms: PATCH 4/5] PurleyOpenBoardPkg/BoardMtOlympus: Add SetCacheLib library class.
2019-10-30 12:29 [edk2-platforms: PATCH 0/5] Add SetCacheLib library class Chiu, Chasel
` (2 preceding siblings ...)
2019-10-30 12:29 ` [edk2-platforms: PATCH 3/5] WhiskeylakeOpenBoardPkg: " Chiu, Chasel
@ 2019-10-30 12:29 ` Chiu, Chasel
2019-10-30 12:29 ` [edk2-platforms: PATCH 5/5] SimicsOpenBoardPkg/BoardX58Ich10: " Chiu, Chasel
4 siblings, 0 replies; 6+ messages in thread
From: Chiu, Chasel @ 2019-10-30 12:29 UTC (permalink / raw)
To: devel; +Cc: Shifei A Lu, Xiaohu Zhou, Isaac W Oram
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2314
Include SetCacheLib from MinPlatformPkg.
Cc: Shifei A Lu <shifei.a.lu@intel.com>
Cc: Xiaohu Zhou <bowen.zhou@intel.com>
Cc: Isaac W Oram <isaac.w.oram@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.dsc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.dsc b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.dsc
index 595ffd4144..c7be68d979 100644
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.dsc
+++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.dsc
@@ -1,6 +1,6 @@
### @file
#
-# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -135,6 +135,7 @@
!include $(RC_PKG)/RcDxeLib.dsc
!include $(SKT_PKG)/SktDxeLib.dsc
!include $(PCH_PKG)/PchDxeLib.dsc
+ SetCacheLib|MinPlatformPkg/Library/SetCacheLib/SetCacheLib.inf
[LibraryClasses.X64]
BoardAcpiTableLib|$(BOARD_PKG)/$(BOARD_NAME)/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf
--
2.13.3.windows.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [edk2-platforms: PATCH 5/5] SimicsOpenBoardPkg/BoardX58Ich10: Add SetCacheLib library class.
2019-10-30 12:29 [edk2-platforms: PATCH 0/5] Add SetCacheLib library class Chiu, Chasel
` (3 preceding siblings ...)
2019-10-30 12:29 ` [edk2-platforms: PATCH 4/5] PurleyOpenBoardPkg/BoardMtOlympus: " Chiu, Chasel
@ 2019-10-30 12:29 ` Chiu, Chasel
4 siblings, 0 replies; 6+ messages in thread
From: Chiu, Chasel @ 2019-10-30 12:29 UTC (permalink / raw)
To: devel; +Cc: Wei David Y, Agyeman Prince
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2314
Include SetCacheLib from MinPlatformPkg.
Cc: Wei David Y <david.y.wei@intel.com>
Cc: Agyeman Prince <prince.agyeman@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc | 1 +
1 file changed, 1 insertion(+)
diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
index 4f8ab4170d..85691c55dd 100644
--- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
+++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
@@ -136,6 +136,7 @@
TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf
!endif
TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointLib.inf
+ SetCacheLib|$(PLATFORM_PACKAGE)/Library/SetCacheLib/SetCacheLib.inf
[LibraryClasses.common.DXE_DRIVER]
#######################################
--
2.13.3.windows.1
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2019-10-30 12:29 [edk2-platforms: PATCH 0/5] Add SetCacheLib library class Chiu, Chasel
2019-10-30 12:29 ` [edk2-platforms: PATCH 1/5] MinPlatformPkg: " Chiu, Chasel
2019-10-30 12:29 ` [edk2-platforms: PATCH 2/5] KabylakeOpenBoardPkg: " Chiu, Chasel
2019-10-30 12:29 ` [edk2-platforms: PATCH 3/5] WhiskeylakeOpenBoardPkg: " Chiu, Chasel
2019-10-30 12:29 ` [edk2-platforms: PATCH 4/5] PurleyOpenBoardPkg/BoardMtOlympus: " Chiu, Chasel
2019-10-30 12:29 ` [edk2-platforms: PATCH 5/5] SimicsOpenBoardPkg/BoardX58Ich10: " Chiu, Chasel
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