From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga02.intel.com (mga02.intel.com []) by mx.groups.io with SMTP id smtpd.web11.718.1572481837056118480 for ; Wed, 30 Oct 2019 17:30:37 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: chasel.chiu@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Oct 2019 17:30:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,248,1569308400"; d="scan'208";a="203359797" Received: from cchiu4-mobl1.gar.corp.intel.com ([10.5.240.37]) by orsmga003.jf.intel.com with ESMTP; 30 Oct 2019 17:30:29 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Michael Kubacki , Nate DeSimone , Liming Gao Subject: [edk2-platforms: PATCH v2 2/6] MinPlatformPkg: Add SetCacheLib library class. Date: Thu, 31 Oct 2019 08:29:48 +0800 Message-Id: <20191031002952.3860-3-chasel.chiu@intel.com> X-Mailer: git-send-email 2.13.3.windows.1 In-Reply-To: <20191031002952.3860-1-chasel.chiu@intel.com> References: <20191031002952.3860-1-chasel.chiu@intel.com> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2314 MinPlatformPkg PlatformInit modules to consume SetCacheLib. Cc: Michael Kubacki Cc: Nate DeSimone Cc: Liming Gao Signed-off-by: Chasel Chiu --- Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.c | 149 +---------------------------------------------------------------------------------------------------------------------------------------------------- Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c | 164 ++------------------------------------------------------------------------------------------------------------------------------------------------------------------ Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf | 11 +---------- Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf | 7 ++----- 4 files changed, 6 insertions(+), 325 deletions(-) diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.c b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.c index 70e6b9a495..df64d4fc0d 100644 --- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.c +++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.c @@ -13,8 +13,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include -#include -#include #include #include @@ -22,6 +20,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include EFI_STATUS EFIAPI @@ -38,152 +37,6 @@ static EFI_PEI_NOTIFY_DESCRIPTOR mEndOfPeiNotifyList = { }; /** - Update MTRR setting and set write back as default memory attribute. - - @retval EFI_SUCCESS The function completes successfully. - @retval Others Some error occurs. -**/ -EFI_STATUS -EFIAPI -SetCacheMtrrAfterEndOfPei ( - VOID - ) -{ - EFI_STATUS Status; - MTRR_SETTINGS MtrrSetting; - EFI_PEI_HOB_POINTERS Hob; - UINT64 MemoryBase; - UINT64 MemoryLength; - UINT64 Power2Length; - EFI_BOOT_MODE BootMode; - UINTN Index; - UINT64 SmramSize; - UINT64 SmramBase; - EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock; - Status = PeiServicesGetBootMode (&BootMode); - ASSERT_EFI_ERROR (Status); - - if (BootMode == BOOT_ON_S3_RESUME) { - return EFI_SUCCESS; - } - // - // Clear the CAR Settings - // - ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS)); - - // - // Default Cachable attribute will be set to WB to support large memory size/hot plug memory - // - MtrrSetting.MtrrDefType &= ~((UINT64)(0xFF)); - MtrrSetting.MtrrDefType |= (UINT64) CacheWriteBack; - - // - // Set fixed cache for memory range below 1MB - // - Status = MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - 0x0, - 0xA0000, - CacheWriteBack - ); - ASSERT_EFI_ERROR (Status); - - Status = MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - 0xA0000, - 0x20000, - CacheUncacheable - ); - ASSERT_EFI_ERROR (Status); - - Status = MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - 0xC0000, - 0x40000, - CacheWriteProtected - ); - ASSERT_EFI_ERROR ( Status); - - // - // PI SMM IPL can't set SMRAM to WB because at that time CPU ARCH protocol is not available. - // Set cacheability of SMRAM to WB here to improve SMRAM initialization performance. - // - SmramSize = 0; - SmramBase = 0; - Status = PeiServicesGetHobList ((VOID **) &Hob.Raw); - while (!END_OF_HOB_LIST (Hob)) { - if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION) { - if (CompareGuid (&Hob.Guid->Name, &gEfiSmmSmramMemoryGuid)) { - SmramHobDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) (Hob.Guid + 1); - for (Index = 0; Index < SmramHobDescriptorBlock->NumberOfSmmReservedRegions; Index++) { - if (SmramHobDescriptorBlock->Descriptor[Index].PhysicalStart > 0x100000) { - SmramSize += SmramHobDescriptorBlock->Descriptor[Index].PhysicalSize; - if (SmramBase == 0 || SmramBase > SmramHobDescriptorBlock->Descriptor[Index].CpuStart) { - SmramBase = SmramHobDescriptorBlock->Descriptor[Index].CpuStart; - } - } - } - break; - } - } - Hob.Raw = GET_NEXT_HOB (Hob); - } - - // - // Set non system memory as UC - // - MemoryBase = 0x100000000; - - // - // Add IED size to set whole SMRAM as WB to save MTRR count - // - MemoryLength = MemoryBase - (SmramBase + SmramSize); - while (MemoryLength != 0) { - Power2Length = GetPowerOfTwo64 (MemoryLength); - MemoryBase -= Power2Length; - Status = MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - Power2Length, - CacheUncacheable - ); - ASSERT_EFI_ERROR (Status); - MemoryLength -= Power2Length; - } - - DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBLimit - 0x%lx\n", PcdGet64 (PcdPciReservedMemAbove4GBLimit))); - DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBBase - 0x%lx\n", PcdGet64 (PcdPciReservedMemAbove4GBBase))); - if (PcdGet64 (PcdPciReservedMemAbove4GBLimit) > PcdGet64 (PcdPciReservedMemAbove4GBBase)) { - Status = MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - PcdGet64 (PcdPciReservedMemAbove4GBBase), - PcdGet64 (PcdPciReservedMemAbove4GBLimit) - PcdGet64 (PcdPciReservedMemAbove4GBBase) + 1, - CacheUncacheable - ); - ASSERT_EFI_ERROR ( Status); - } - - DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBLimit - 0x%lx\n", PcdGet64 (PcdPciReservedPMemAbove4GBLimit))); - DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBBase - 0x%lx\n", PcdGet64 (PcdPciReservedPMemAbove4GBBase))); - if (PcdGet64 (PcdPciReservedPMemAbove4GBLimit) > PcdGet64 (PcdPciReservedPMemAbove4GBBase)) { - Status = MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - PcdGet64 (PcdPciReservedPMemAbove4GBBase), - PcdGet64 (PcdPciReservedPMemAbove4GBLimit) - PcdGet64 (PcdPciReservedPMemAbove4GBBase) + 1, - CacheUncacheable - ); - ASSERT_EFI_ERROR ( Status); - } - - // - // Update MTRR setting from MTRR buffer - // - MtrrSetAllMtrrs (&MtrrSetting); - - return Status; -} - -/** This function handles PlatformInit task at the end of PEI @param[in] PeiServices Pointer to PEI Services Table. diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c index 2690511abe..731bc234b0 100644 --- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c +++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c @@ -1,7 +1,7 @@ /** @file Source code file for Platform Init Pre-Memory PEI module -Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -15,7 +15,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include -#include #include #include #include @@ -26,6 +25,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include #include #include @@ -319,166 +319,6 @@ Done: return EFI_SUCCESS; } -/** - Set Cache Mtrr. -**/ -VOID -SetCacheMtrr ( - VOID - ) -{ - EFI_STATUS Status; - EFI_PEI_HOB_POINTERS Hob; - MTRR_SETTINGS MtrrSetting; - UINT64 MemoryBase; - UINT64 MemoryLength; - UINT64 LowMemoryLength; - UINT64 HighMemoryLength; - EFI_BOOT_MODE BootMode; - EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute; - UINT64 CacheMemoryLength; - - /// - /// Reset all MTRR setting. - /// - ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS)); - - /// - /// Cache the Flash area as WP to boost performance - /// - Status = MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - (UINTN) PcdGet32 (PcdFlashAreaBaseAddress), - (UINTN) PcdGet32 (PcdFlashAreaSize), - CacheWriteProtected - ); - ASSERT_EFI_ERROR (Status); - - /// - /// Update MTRR setting from MTRR buffer for Flash Region to be WP to boost performance - /// - MtrrSetAllMtrrs (&MtrrSetting); - - /// - /// Set low to 1 MB. Since 1MB cacheability will always be set - /// until override by CSM. - /// Initialize high memory to 0. - /// - LowMemoryLength = 0x100000; - HighMemoryLength = 0; - ResourceAttribute = ( - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE - ); - - Status = PeiServicesGetBootMode (&BootMode); - ASSERT_EFI_ERROR (Status); - - if (BootMode != BOOT_ON_S3_RESUME) { - ResourceAttribute |= EFI_RESOURCE_ATTRIBUTE_TESTED; - } - - Status = PeiServicesGetHobList ((VOID **) &Hob.Raw); - while (!END_OF_HOB_LIST (Hob)) { - if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { - if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) || - ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) && - (Hob.ResourceDescriptor->ResourceAttribute == ResourceAttribute)) - ) { - if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000000ULL) { - HighMemoryLength += Hob.ResourceDescriptor->ResourceLength; - } else if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000) { - LowMemoryLength += Hob.ResourceDescriptor->ResourceLength; - } - } - } - - Hob.Raw = GET_NEXT_HOB (Hob); - } - - DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) = %lx.\n", LowMemoryLength)); - DEBUG ((DEBUG_INFO, "Memory Length (Above 4GB) = %lx.\n", HighMemoryLength)); - - /// - /// Assume size of main memory is multiple of 256MB - /// - MemoryLength = (LowMemoryLength + 0xFFFFFFF) & 0xF0000000; - MemoryBase = 0; - - CacheMemoryLength = MemoryLength; - /// - /// Programming MTRRs to avoid override SPI region with UC when MAX TOLUD Length >= 3.5GB - /// - if (MemoryLength > 0xDC000000) { - CacheMemoryLength = 0xC0000000; - Status = MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - CacheMemoryLength, - CacheWriteBack - ); - ASSERT_EFI_ERROR (Status); - - MemoryBase = 0xC0000000; - CacheMemoryLength = MemoryLength - 0xC0000000; - if (MemoryLength > 0xE0000000) { - CacheMemoryLength = 0x20000000; - Status = MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - CacheMemoryLength, - CacheWriteBack - ); - ASSERT_EFI_ERROR (Status); - - MemoryBase = 0xE0000000; - CacheMemoryLength = MemoryLength - 0xE0000000; - } - } - - Status = MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - CacheMemoryLength, - CacheWriteBack - ); - ASSERT_EFI_ERROR (Status); - - if (LowMemoryLength != MemoryLength) { - MemoryBase = LowMemoryLength; - MemoryLength -= LowMemoryLength; - Status = MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - MemoryLength, - CacheUncacheable - ); - ASSERT_EFI_ERROR (Status); - } - - /// - /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC - /// - Status = MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - 0xA0000, - 0x20000, - CacheUncacheable - ); - ASSERT_EFI_ERROR (Status); - - /// - /// Update MTRR setting from MTRR buffer - /// - MtrrSetAllMtrrs (&MtrrSetting); - - return ; -} - VOID ReportCpuHob ( VOID diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf index 0736c8d494..a14f20f150 100644 --- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf +++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf @@ -23,15 +23,14 @@ BaseMemoryLib HobLib PeiServicesLib - MtrrLib BoardInitLib TestPointCheckLib + SetCacheLib [Packages] MinPlatformPkg/MinPlatformPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - UefiCpuPkg/UefiCpuPkg.dec [Sources] PlatformInitPostMem.c @@ -44,14 +43,6 @@ [Protocols] -[Guids] - gEfiSmmSmramMemoryGuid ## CONSUMES - [Depex] gEfiPeiMemoryDiscoveredPpiGuid -[Pcd] - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBBase - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf index 2c3a13106e..de5f11f829 100644 --- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf +++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf @@ -1,7 +1,7 @@ ### @file # Component information file for the Platform Init Pre-Memory PEI module. # -# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -22,23 +22,20 @@ HobLib IoLib MemoryAllocationLib - MtrrLib PeimEntryPoint PeiServicesLib ReportFvLib TestPointCheckLib TimerLib + SetCacheLib [Packages] MinPlatformPkg/MinPlatformPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - UefiCpuPkg/UefiCpuPkg.dec [Pcd] gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode ## CONSUMES - gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES - gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit ## CONSUMES gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit ## CONSUMES -- 2.13.3.windows.1