From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga02.intel.com (mga02.intel.com []) by mx.groups.io with SMTP id smtpd.web11.5236.1572525094034209064 for ; Thu, 31 Oct 2019 05:31:34 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: jiewen.yao@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 Oct 2019 05:31:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,250,1569308400"; d="scan'208";a="283875670" Received: from jyao1-mobl2.ccr.corp.intel.com ([10.254.211.198]) by orsmga001.jf.intel.com with ESMTP; 31 Oct 2019 05:31:33 -0700 From: "Yao, Jiewen" To: devel@edk2.groups.io Cc: Ray Ni , Rangasai V Chaganty , Yun Lou Subject: [PATCH V2 1/6] IntelSiliconPkg/Include: Add Intel PciSecurity definition. Date: Thu, 31 Oct 2019 20:31:22 +0800 Message-Id: <20191031123127.10900-2-jiewen.yao@intel.com> X-Mailer: git-send-email 2.19.2.windows.1 In-Reply-To: <20191031123127.10900-1-jiewen.yao@intel.com> References: <20191031123127.10900-1-jiewen.yao@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2303 Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Yun Lou Signed-off-by: Jiewen Yao --- Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecurity.h | 66 ++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecurity.h b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecurity.h new file mode 100644 index 0000000000..a8c5483165 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecurity.h @@ -0,0 +1,66 @@ +/** @file + Intel PCI security data structure + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __INTEL_PCI_SECURITY_H__ +#define __INTEL_PCI_SECURITY_H__ + +#pragma pack(1) + +typedef struct { + UINT16 CapId; // 0x23: DVSEC + UINT16 CapVersion:4; // 1 + UINT16 NextOffset:12; + UINT16 DvSecVendorId; // 0x8086 + UINT16 DvSecRevision:4; // 1 + UINT16 DvSecLength:12; + UINT16 DvSecId; // 0x3E: Measure +} INTEL_PCI_DIGEST_CAPABILITY_HEADER; + +#define INTEL_PCI_CAPID_DVSEC 0x23 +#define INTEL_PCI_DVSEC_VENDORID_INTEL 0x8086 +#define INTEL_PCI_DVSEC_DVSECID_MEASUREMENT 0x3E + +typedef union { + struct { + UINT8 DigestModified:1; // RW1C + UINT8 Reserved0:7; + } Bits; + UINT8 Data; +} INTEL_PCI_DIGEST_DATA_MODIFIED; + +#define INTEL_PCI_DIGEST_MODIFIED BIT0 + +typedef union { + struct { + UINT8 Digest0Valid:1; // RO + UINT8 Digest0Locked:1; // RO + UINT8 Digest1Valid:1; // RO + UINT8 Digest1Locked:1; // RO + UINT8 Reserved1:4; + } Bits; + UINT8 Data; +} INTEL_PCI_DIGEST_DATA_VALID; + +#define INTEL_PCI_DIGEST_0_VALID BIT0 +#define INTEL_PCI_DIGEST_0_LOCKED BIT1 +#define INTEL_PCI_DIGEST_1_VALID BIT2 +#define INTEL_PCI_DIGEST_1_LOCKED BIT3 + +typedef struct { + INTEL_PCI_DIGEST_DATA_MODIFIED Modified; // RW1C + INTEL_PCI_DIGEST_DATA_VALID Valid; // RO + UINT16 TcgAlgId; // RO + UINT8 FirmwareID; // RO + UINT8 Reserved; +//UINT8 Digest[]; +} INTEL_PCI_DIGEST_CAPABILITY_STRUCTURE; + +#pragma pack() + +#endif + -- 2.19.2.windows.1