From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web11.5030.1572621012589427381 for ; Fri, 01 Nov 2019 08:10:12 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.126, mailfrom: ashraf.javeed@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Nov 2019 08:10:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,256,1569308400"; d="scan'208";a="194687009" Received: from pidsbabios005.gar.corp.intel.com ([10.223.9.183]) by orsmga008.jf.intel.com with ESMTP; 01 Nov 2019 08:10:04 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Jian J Wang , Hao A Wu , Ray Ni Subject: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/12] PciBusDxe: Reorganize the PCI Platform Protocol usage code Date: Fri, 1 Nov 2019 20:39:42 +0530 Message-Id: <20191101150952.3340-3-ashraf.javeed@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20191101150952.3340-1-ashraf.javeed@intel.com> References: <20191101150952.3340-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2194 The following legacy PCI Platform Protocol usage is reorganized in the separate source files:- (1) PlatformPrepController (2) PlatformNotify (3) GetPlatformPolicy (4) GetPciRom This code changes are made to support the new PCI Platform Protocol along with the existing legacy interface in the PCI Bus driver. Signed-off-by: Ashraf Javeed Cc: Jian J Wang Cc: Hao A Wu Cc: Ray Ni --- MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c | 23 ++--------------------- MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 3 +-- MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 2 ++ MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c | 58 +++++++++++----------------------------------------------- MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c | 139 +++++++++++++++++++++++++++++++++---------------------------------------------------------------------------------------------------------- MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c | 254 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h | 109 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c | 15 +-------------- 8 files changed, 413 insertions(+), 190 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c index b020ce5..45cd64d 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c @@ -8,7 +8,7 @@ PCI Root Bridges. So it means platform needs install PCI Root Bridge IO protocol for each PCI Root Bus and install PCI Host Bridge Resource Allocation Protocol. -Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -34,8 +34,6 @@ BOOLEAN gFullEnumeration = TRUE; UINT64 gAllOne = 0xFFFFFFFFFFFFFFFFULL; UINT64 gAllZero = 0; -EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol; -EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol; EDKII_IOMMU_PROTOCOL *mIoMmuProtocol; @@ -266,24 +264,7 @@ PciBusDriverBindingStart ( // If PCI Platform protocol is available, get it now. // If the platform implements this, it must be installed before BDS phase // - gPciPlatformProtocol = NULL; - gBS->LocateProtocol ( - &gEfiPciPlatformProtocolGuid, - NULL, - (VOID **) &gPciPlatformProtocol - ); - - // - // If PCI Platform protocol doesn't exist, try to Pci Override Protocol. - // - if (gPciPlatformProtocol == NULL) { - gPciOverrideProtocol = NULL; - gBS->LocateProtocol ( - &gEfiPciOverrideProtocolGuid, - NULL, - (VOID **) &gPciOverrideProtocol - ); - } + LocatePciPlatformProtocol (); if (mIoMmuProtocol == NULL) { gBS->LocateProtocol ( diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h index 504a1b1..141c158 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h @@ -79,6 +79,7 @@ typedef enum { #include "PciPowerManagement.h" #include "PciHotPlugSupport.h" #include "PciLib.h" +#include "PciPlatformSupport.h" #define VGABASE1 0x3B0 #define VGALIMIT1 0x3BB @@ -307,8 +308,6 @@ extern UINTN gPciHostBridgeNumber; extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM]; extern UINT64 gAllOne; extern UINT64 gAllZero; -extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol; -extern EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol; extern BOOLEAN mReserveIsaAliases; extern BOOLEAN mReserveVgaAliases; diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf index 6dab970..4ce99ce 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf @@ -59,6 +59,8 @@ PciBus.h PciFeatureSupport.c PciFeatureSupport.h + PciPlatformSupport.c + PciPlatformSupport.h [Packages] MdePkg/MdePkg.dec diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c index b7832c6..149a120 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c @@ -208,8 +208,6 @@ RegisterPciDevice ( ) { EFI_STATUS Status; - VOID *PlatformOpRomBuffer; - UINTN PlatformOpRomSize; EFI_PCI_IO_PROTOCOL *PciIo; UINT8 Data8; BOOLEAN HasEfiImage; @@ -244,49 +242,16 @@ RegisterPciDevice ( // // Get the OpRom provided by platform // - if (gPciPlatformProtocol != NULL) { - Status = gPciPlatformProtocol->GetPciRom ( - gPciPlatformProtocol, - PciIoDevice->Handle, - &PlatformOpRomBuffer, - &PlatformOpRomSize - ); - if (!EFI_ERROR (Status)) { - PciIoDevice->EmbeddedRom = FALSE; - PciIoDevice->RomSize = (UINT32) PlatformOpRomSize; - PciIoDevice->PciIo.RomSize = PlatformOpRomSize; - PciIoDevice->PciIo.RomImage = PlatformOpRomBuffer; - // - // For OpROM read from gPciPlatformProtocol: - // Add the Rom Image to internal database for later PCI light enumeration - // - PciRomAddImageMapping ( - NULL, - PciIoDevice->PciRootBridgeIo->SegmentNumber, - PciIoDevice->BusNumber, - PciIoDevice->DeviceNumber, - PciIoDevice->FunctionNumber, - PciIoDevice->PciIo.RomImage, - PciIoDevice->PciIo.RomSize - ); - } - } else if (gPciOverrideProtocol != NULL) { - Status = gPciOverrideProtocol->GetPciRom ( - gPciOverrideProtocol, - PciIoDevice->Handle, - &PlatformOpRomBuffer, - &PlatformOpRomSize - ); - if (!EFI_ERROR (Status)) { - PciIoDevice->EmbeddedRom = FALSE; - PciIoDevice->RomSize = (UINT32) PlatformOpRomSize; - PciIoDevice->PciIo.RomSize = PlatformOpRomSize; - PciIoDevice->PciIo.RomImage = PlatformOpRomBuffer; - // - // For OpROM read from gPciOverrideProtocol: - // Add the Rom Image to internal database for later PCI light enumeration - // - PciRomAddImageMapping ( + Status = GetPlatformPciOptionRom ( + Controller, + PciIoDevice + ); + if (!EFI_ERROR (Status)) { + // + // For OpROM read from the PCI Platform Protocol: + // Add the Rom Image to internal database for later PCI light enumeration + // + PciRomAddImageMapping ( NULL, PciIoDevice->PciRootBridgeIo->SegmentNumber, PciIoDevice->BusNumber, @@ -294,8 +259,7 @@ RegisterPciDevice ( PciIoDevice->FunctionNumber, PciIoDevice->PciIo.RomImage, PciIoDevice->PciIo.RomSize - ); - } + ); } } diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c index 8db1ebf..aef8a3b 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c @@ -1003,7 +1003,7 @@ PciHostBridgeAdjustAllocation ( Status = RejectPciDevice (PciResNode->PciDev); if (Status == EFI_SUCCESS) { DEBUG (( - EFI_D_ERROR, + DEBUG_ERROR, "PciBus: [%02x|%02x|%02x] was rejected due to resource confliction.\n", PciResNode->PciDev->BusNumber, PciResNode->PciDev->DeviceNumber, PciResNode->PciDev->FunctionNumber )); @@ -1746,7 +1746,7 @@ NotifyPhase ( HostBridgeHandle = NULL; RootBridgeHandle = NULL; - if (gPciPlatformProtocol != NULL) { + if (CheckPciPlatformProtocolInstall()) { // // Get Host Bridge Handle. // @@ -1770,42 +1770,11 @@ NotifyPhase ( // // Call PlatformPci::PlatformNotify() if the protocol is present. // - gPciPlatformProtocol->PlatformNotify ( - gPciPlatformProtocol, - HostBridgeHandle, - Phase, - ChipsetEntry - ); - } else if (gPciOverrideProtocol != NULL){ - // - // Get Host Bridge Handle. - // - PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle); - - // - // Get the rootbridge Io protocol to find the host bridge handle - // - Status = gBS->HandleProtocol ( - RootBridgeHandle, - &gEfiPciRootBridgeIoProtocolGuid, - (VOID **) &PciRootBridgeIo - ); - - if (EFI_ERROR (Status)) { - return EFI_NOT_FOUND; - } - - HostBridgeHandle = PciRootBridgeIo->ParentHandle; - - // - // Call PlatformPci::PhaseNotify() if the protocol is present. - // - gPciOverrideProtocol->PlatformNotify ( - gPciOverrideProtocol, - HostBridgeHandle, - Phase, - ChipsetEntry - ); + PciPlatformNotifyPhase ( + HostBridgeHandle, + Phase, + ChipsetEntry + ); } Status = PciResAlloc->NotifyPhase ( @@ -1813,27 +1782,15 @@ NotifyPhase ( Phase ); - if (gPciPlatformProtocol != NULL) { + if (CheckPciPlatformProtocolInstall()) { // // Call PlatformPci::PlatformNotify() if the protocol is present. // - gPciPlatformProtocol->PlatformNotify ( - gPciPlatformProtocol, - HostBridgeHandle, - Phase, - ChipsetExit - ); - - } else if (gPciOverrideProtocol != NULL) { - // - // Call PlatformPci::PhaseNotify() if the protocol is present. - // - gPciOverrideProtocol->PlatformNotify ( - gPciOverrideProtocol, - HostBridgeHandle, - Phase, - ChipsetExit - ); + PciPlatformNotifyPhase ( + HostBridgeHandle, + Phase, + ChipsetExit + ); } return Status; @@ -1914,31 +1871,16 @@ PreprocessController ( RootBridgePciAddress.Bus = Bus; RootBridgePciAddress.ExtendedRegister = 0; - if (gPciPlatformProtocol != NULL) { - // - // Call PlatformPci::PrepController() if the protocol is present. - // - gPciPlatformProtocol->PlatformPrepController ( - gPciPlatformProtocol, - HostBridgeHandle, - RootBridgeHandle, - RootBridgePciAddress, - Phase, - ChipsetEntry - ); - } else if (gPciOverrideProtocol != NULL) { - // - // Call PlatformPci::PrepController() if the protocol is present. - // - gPciOverrideProtocol->PlatformPrepController ( - gPciOverrideProtocol, - HostBridgeHandle, - RootBridgeHandle, - RootBridgePciAddress, - Phase, - ChipsetEntry - ); - } + // + // Call PlatformPci::PrepController() if the protocol is present. + // + PciPlatformPreprocessController ( + HostBridgeHandle, + RootBridgeHandle, + RootBridgePciAddress, + Phase, + ChipsetEntry + ); Status = PciResAlloc->PreprocessController ( PciResAlloc, @@ -1947,31 +1889,16 @@ PreprocessController ( Phase ); - if (gPciPlatformProtocol != NULL) { - // - // Call PlatformPci::PrepController() if the protocol is present. - // - gPciPlatformProtocol->PlatformPrepController ( - gPciPlatformProtocol, - HostBridgeHandle, - RootBridgeHandle, - RootBridgePciAddress, - Phase, - ChipsetExit - ); - } else if (gPciOverrideProtocol != NULL) { - // - // Call PlatformPci::PrepController() if the protocol is present. - // - gPciOverrideProtocol->PlatformPrepController ( - gPciOverrideProtocol, - HostBridgeHandle, - RootBridgeHandle, - RootBridgePciAddress, - Phase, - ChipsetExit - ); - } + // + // Call PlatformPci::PrepController() if the protocol is present. + // + PciPlatformPreprocessController ( + HostBridgeHandle, + RootBridgeHandle, + RootBridgePciAddress, + Phase, + ChipsetExit + ); return EFI_SUCCESS; } diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c new file mode 100644 index 0000000..6f95794 --- /dev/null +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c @@ -0,0 +1,254 @@ +/** @file + This file encapsulate the usage of PCI Platform Protocol + + This file define the necessary hooks used to obtain the platform + level data and policies which could be used in the PCI Enumeration phases + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PciBus.h" + +EFI_PCI_PLATFORM_PROTOCOL *mPciPlatformProtocol; +EFI_PCI_OVERRIDE_PROTOCOL *mPciOverrideProtocol; + + + +/** + This function retrieves the PCI Platform Protocol published by platform driver + +**/ +VOID +LocatePciPlatformProtocol ( + ) +{ + mPciPlatformProtocol = NULL; + gBS->LocateProtocol ( + &gEfiPciPlatformProtocolGuid, + NULL, + (VOID **) &mPciPlatformProtocol + ); + + // + // If PCI Platform protocol doesn't exist, try to get Pci Override Protocol. + // + if (mPciPlatformProtocol == NULL) { + mPciOverrideProtocol = NULL; + gBS->LocateProtocol ( + &gEfiPciOverrideProtocolGuid, + NULL, + (VOID **) &mPciOverrideProtocol + ); + } +} + +/** + This function indicates the presence of PCI Platform driver + @retval TRUE or FALSE +**/ +BOOLEAN +CheckPciPlatformProtocolInstall ( + ) +{ + + if (mPciPlatformProtocol != NULL) { + return TRUE; + } else if (mPciOverrideProtocol != NULL){ + return TRUE; + } + + return FALSE; +} + +/** + Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various + stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual + PCI controllers before enumeration. + + This function is called during the PCI enumeration process. No specific action is expected from this + member function. It allows the host bridge driver to preinitialize individual PCI controllers before + enumeration. + + @param[in] HostBridgeHandle The associated PCI host bridge handle. + @param[in] RootBridgeHandle The associated PCI root bridge handle. + @param[in] RootBridgePciAddress The address of the PCI device on the PCI bus. + @param[in] Phase The phase of the PCI controller enumeration. + @param[in] ExecPhase Defines the execution phase of the PCI chipset driver. + + @retval Status returns the status from the PCI Platform protocol as is + +**/ +EFI_STATUS +PciPlatformPreprocessController ( + IN EFI_HANDLE HostBridgeHandle, + IN EFI_HANDLE RootBridgeHandle, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS RootBridgePciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_EXECUTION_PHASE ExecPhase + ) +{ + EFI_STATUS Status; + if (mPciPlatformProtocol != NULL) { + // + // Call PlatformPci::PrepController() if the protocol is present. + // + Status = mPciPlatformProtocol->PlatformPrepController ( + mPciPlatformProtocol, + HostBridgeHandle, + RootBridgeHandle, + RootBridgePciAddress, + Phase, + ExecPhase + ); + } else if (mPciOverrideProtocol != NULL) { + // + // Call PlatformPci::PrepController() if the protocol is present. + // + Status = mPciOverrideProtocol->PlatformPrepController ( + mPciOverrideProtocol, + HostBridgeHandle, + RootBridgeHandle, + RootBridgePciAddress, + Phase, + ExecPhase + ); + } else { + // + // return PCI Platform Protocol not found + // + return EFI_NOT_FOUND; + } + return Status; +} + +/** + This function notifies the PCI Platform driver about the PCI host bridge resource + allocation phase and PCI execution phase. + + @param[in] HostBridge The handle of the host bridge controller. + @param[in] Phase The phase of the PCI bus enumeration. + @param[in] ExecPhase Defines the execution phase of the PCI chipset driver. + @retval Status returns the status from the PCI Platform protocol as is + +**/ +EFI_STATUS +PciPlatformNotifyPhase ( + IN EFI_HANDLE HostBridgeHandle, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_EXECUTION_PHASE ExecPhase + ) +{ + EFI_STATUS Status; + + + if (mPciPlatformProtocol != NULL) { + Status = mPciPlatformProtocol->PlatformNotify ( + mPciPlatformProtocol, + HostBridgeHandle, + Phase, + ExecPhase + ); + } else if (mPciOverrideProtocol != NULL){ + Status = mPciOverrideProtocol->PlatformNotify ( + mPciOverrideProtocol, + HostBridgeHandle, + Phase, + ExecPhase + ); + } else { + // + // return PCI Platform Protocol not found + // + return EFI_NOT_FOUND; + } + return Status; +} + +/** + This function retrieves the PCI platform policy. + + @param PciPolicy pointer to the legacy EFI_PCI_PLATFORM_POLICY + @retval Status returns the status from the PCI Platform protocol as is + +**/ +EFI_STATUS +PciGetPlatformPolicy ( + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy + ) +{ + EFI_STATUS Status; + if (mPciPlatformProtocol != NULL) { + Status = mPciPlatformProtocol->GetPlatformPolicy ( + mPciPlatformProtocol, + PciPolicy + ); + } + + if (mPciOverrideProtocol != NULL) { + Status = mPciOverrideProtocol->GetPlatformPolicy ( + mPciOverrideProtocol, + PciPolicy + ); + } else { + // + // return PCI Platform Protocol not found + // + return EFI_NOT_FOUND; + } + return Status; +} + +/** + This function retrieves the Option ROM image and size from the Platform. + + It uses the PCI_IO_DEVICE internal fields are used to store OpROM image/size + + @param Controller An EFI handle for the PCI bus controller. + @param PciIoDevice A PCI_IO_DEVICE pointer to the PCI IO device to be registered. + + @retval EFI_SUCCESS The option ROM was available for this device and loaded into memory. + @retval EFI_NOT_FOUND No option ROM was available for this device. + @retval EFI_OUT_OF_RESOURCES No memory was available to load the option ROM. + @retval EFI_DEVICE_ERROR An error occurred in obtaining the option ROM. + +**/ +EFI_STATUS +GetPlatformPciOptionRom ( + IN EFI_HANDLE Controller, + IN PCI_IO_DEVICE *PciIoDevice + ) +{ + EFI_STATUS Status; + VOID *PlatformOpRomBuffer; + UINTN PlatformOpRomSize; + if (mPciPlatformProtocol != NULL) { + Status = mPciPlatformProtocol->GetPciRom ( + mPciPlatformProtocol, + PciIoDevice->Handle, + &PlatformOpRomBuffer, + &PlatformOpRomSize + ); + } else if (mPciOverrideProtocol != NULL) { + Status = mPciOverrideProtocol->GetPciRom ( + mPciOverrideProtocol, + PciIoDevice->Handle, + &PlatformOpRomBuffer, + &PlatformOpRomSize + ); + } else { + // + // return PCI Platform Protocol not found + // + return EFI_NOT_FOUND; + } + + if (!EFI_ERROR (Status)) { + PciIoDevice->EmbeddedRom = FALSE; + PciIoDevice->RomSize = (UINT32)PlatformOpRomSize; + PciIoDevice->PciIo.RomSize = PlatformOpRomSize; + PciIoDevice->PciIo.RomImage = PlatformOpRomBuffer; + } + return Status; +} diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h new file mode 100644 index 0000000..c0d3b49 --- /dev/null +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h @@ -0,0 +1,109 @@ +/** @file + This file encapsulate the usage of PCI Platform Protocol + + This file define the necessary hooks used to obtain the platform + level data and policies which could be used in the PCI Enumeration phases + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#ifndef _EFI_PCI_PLATFORM_SUPPORT_H_ +#define _EFI_PCI_PLATFORM_SUPPORT_H_ + +/** + This function retrieves the PCI Platform Protocol published by platform driver + +**/ +VOID +LocatePciPlatformProtocol ( + ); + +/** + This function indicates the presence of PCI Platform driver + @retval TRUE or FALSE +**/ +BOOLEAN +CheckPciPlatformProtocolInstall ( + ); + + +/** + Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various + stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual + PCI controllers before enumeration. + + This function is called during the PCI enumeration process. No specific action is expected from this + member function. It allows the host bridge driver to preinitialize individual PCI controllers before + enumeration. + + @param[in] HostBridgeHandle The associated PCI host bridge handle. + @param[in] RootBridgeHandle The associated PCI root bridge handle. + @param[in] RootBridgePciAddress The address of the PCI device on the PCI bus. + @param[in] Phase The phase of the PCI controller enumeration. + @param[in] ExecPhase Defines the execution phase of the PCI chipset driver. + + @retval Status returns the status from the PCI Platform protocol as is + +**/ +EFI_STATUS +PciPlatformPreprocessController ( + IN EFI_HANDLE HostBridgeHandle, + IN EFI_HANDLE RootBridgeHandle, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS RootBridgePciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_EXECUTION_PHASE ExecPhase + ); + +/** + This function notifies the PCI Platform driver about the PCI host bridge resource + allocation phase and PCI execution phase. + + @param[in] HostBridge The handle of the host bridge controller. + @param[in] Phase The phase of the PCI bus enumeration. + @param[in] ExecPhase Defines the execution phase of the PCI chipset driver. + @retval Status returns the status from the PCI Platform protocol as is + +**/ +EFI_STATUS +PciPlatformNotifyPhase ( + IN EFI_HANDLE HostBridgeHandle, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_EXECUTION_PHASE ExecPhase + ); + +/** + This function retrieves the PCI platform policy. + + @param PciPolicy pointer to the legacy EFI_PCI_PLATFORM_POLICY + @retval Status returns the status from the PCI Platform protocol as is + +**/ +EFI_STATUS +PciGetPlatformPolicy ( + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy + ); + +/** + This function retrieves the Option ROM image and size from the Platform. + + It uses the PCI_IO_DEVICE internal fields are used to store OpROM image/size + + @param Controller An EFI handle for the PCI bus controller. + @param PciIoDevice A PCI_IO_DEVICE pointer to the PCI IO device to be registered. + + @retval EFI_SUCCESS The option ROM was available for this device and loaded into memory. + @retval EFI_NOT_FOUND No option ROM was available for this device. + @retval EFI_OUT_OF_RESOURCES No memory was available to load the option ROM. + @retval EFI_DEVICE_ERROR An error occurred in obtaining the option ROM. + +**/ +EFI_STATUS +GetPlatformPciOptionRom ( + IN EFI_HANDLE Controller, + IN PCI_IO_DEVICE *PciIoDevice + ); + +#endif diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c index 4969ee0..be6f42a 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c @@ -198,20 +198,7 @@ CalculateApertureIo16 ( // Status = EFI_NOT_FOUND; PciPolicy = 0; - if (gPciPlatformProtocol != NULL) { - Status = gPciPlatformProtocol->GetPlatformPolicy ( - gPciPlatformProtocol, - &PciPolicy - ); - } - - if (EFI_ERROR (Status) && gPciOverrideProtocol != NULL) { - Status = gPciOverrideProtocol->GetPlatformPolicy ( - gPciOverrideProtocol, - &PciPolicy - ); - } - + Status = PciGetPlatformPolicy (&PciPolicy); if (!EFI_ERROR (Status)) { if ((PciPolicy & EFI_RESERVE_ISA_IO_ALIAS) != 0) { mReserveIsaAliases = TRUE; -- 2.21.0.windows.1