From: "Kubacki, Michael A" <michael.a.kubacki@intel.com>
To: devel@edk2.groups.io
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>,
Michael D Kinney <michael.d.kinney@intel.com>,
Shifei A Lu <shifei.a.lu@intel.com>,
Isaac W Oram <isaac.w.oram@intel.com>,
Xiaohu Zhou <bowen.zhou@intel.com>
Subject: [edk2-platforms][PATCH V1 09/19] PurleyOpenBoardPkg/Acpi/BoardAcpiDxe: Remove all files
Date: Fri, 1 Nov 2019 14:03:32 -0700 [thread overview]
Message-ID: <20191101210342.28608-10-michael.a.kubacki@intel.com> (raw)
In-Reply-To: <20191101210342.28608-1-michael.a.kubacki@intel.com>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2322
The current set of maintainers do not plan to maintain this package
moving forward. Simply leaving the code as unmaintained is
undesirable for several reasons including presence of build issues,
functional issues, and lack of consistency with other Intel
platform/silicon code in design and usage.
It is suggested that these be removed for the next stable tag due
to lack of recent testing.
This change removes the module BoardAcpiDxe in PurleyOpenBoardPkg.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Shifei A Lu <shifei.a.lu@intel.com>
Cc: Isaac W Oram <isaac.w.oram@intel.com>
Cc: Xiaohu Zhou <bowen.zhou@intel.com>
Signed-off-by: Michael Kubacki <michael.a.kubacki@intel.com>
---
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf | 73 --
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt.inf | 31 -
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.h | 82 --
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable.c | 290 -------
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c | 546 -------------
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxeDsdt.c | 516 ------------
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl | 19 -
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.asl | 77 --
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl | 134 ----
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/HostBus.asl | 256 ------
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieHotPlugGpeHandler.asl | 842 --------------------
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieRootPortHotPlug.asl | 686 ----------------
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl | 32 -
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchGbe.asl | 17 -
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl | 79 --
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/WFPPlatform.asl | 189 -----
16 files changed, 3869 deletions(-)
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
deleted file mode 100644
index 2f937fd59e..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
+++ /dev/null
@@ -1,73 +0,0 @@
-### @file
-#
-# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-###
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = BoardAcpiDxe
- FILE_GUID = F3253A17-2AFE-419E-A5DA-B95A3F7DAB25
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
- ENTRY_POINT = InstallAcpiBoard
-
-[Sources]
- Dsdt/WFPPlatform.asl
- AmlOffsetTable.c
- BoardAcpiDxe.c
- BoardAcpiDxeDsdt.c
-
-[Packages]
- PurleyOpenBoardPkg/PlatPkg.dec
- PurleySktPkg/SocketPkg.dec
- PurleyRcPkg/RcPkg.dec
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- LewisburgPkg/PchRcPkg.dec
- UefiCpuPkg/UefiCpuPkg.dec
- MinPlatformPkg/MinPlatformPkg.dec
-
-[LibraryClasses]
- UefiBootServicesTableLib
- UefiDriverEntryPoint
- BaseMemoryLib
- DebugLib
- UefiLib
- UefiRuntimeServicesTableLib
- HobLib
- PcdLib
- BoardAcpiTableLib
-
-[Protocols]
- gEfiMpServiceProtocolGuid
- gEfiIioUdsProtocolGuid
- gEfiGlobalNvsAreaProtocolGuid
- gEfiPciIoProtocolGuid
- gEfiFirmwareVolume2ProtocolGuid
- gEfiAcpiTableProtocolGuid
- gEfiPciRootBridgeIoProtocolGuid
-
-[Guids]
- gEfiMemoryMapGuid
-
-[Pcd]
- gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData
- gOemSkuTokenSpaceGuid.PcdSocketIioConfigData
- gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData
- gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData
- gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData
- gOemSkuTokenSpaceGuid.PcdAcpiGnvsAddress
- gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable
-
-[Depex]
- gEfiAcpiTableProtocolGuid AND
- gEfiMpServiceProtocolGuid
-
-[BuildOptions]
- # add -vr and -so to generate offset.h
- *_*_*_ASL_FLAGS = -oi -vr -so
-
-
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt.inf b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt.inf
deleted file mode 100644
index a480379213..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt.inf
+++ /dev/null
@@ -1,31 +0,0 @@
-### @file
-#
-# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-###
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = Dsdt
- FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
- MODULE_TYPE = USER_DEFINED
- VERSION_STRING = 1.0
-
-[Sources]
- Dsdt/WFPPlatform.asl
-
-[Packages]
- MdePkg/MdePkg.dec
- LewisburgPkg/PchRcPkg.dec
- PurleyOpenBoardPkg/PlatPkg.dec
- PurleySktPkg/SocketPkg.dec
- PurleyRcPkg/RcPkg.dec
- MinPlatformPkg/MinPlatformPkg.dec
-
-[BuildOptions]
- # add -vr and -so to generate offset.h
- *_*_*_ASL_FLAGS = -oi -vr -so
-
-
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.h b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.h
deleted file mode 100644
index fbfd9abc7f..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef _ACPI_PLATFORM_H_
-#define _ACPI_PLATFORM_H_
-
-//
-// Statements that include other header files
-//
-#include <PiDxe.h>
-#include <PchAccess.h>
-#include <IndustryStandard/Acpi.h>
-#include <IndustryStandard/Pci.h>
-#include <Protocol/AcpiSystemDescriptionTable.h>
-#include <Acpi/GlobalNvsAreaDef.h>
-#include <Protocol/IioUds.h>
-#include <Protocol/PciIo.h>
-#include <Protocol/FirmwareVolume2.h>
-#include <Protocol/SerialIo.h>
-#include <Protocol/MpService.h>
-#include <Protocol/AcpiTable.h>
-#include <Library/BaseLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiRuntimeServicesTableLib.h>
-#include <Library/DebugLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/DevicePathLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/HobLib.h>
-#include <Library/UefiLib.h>
-#include <Library/PcdLib.h>
-#include <Guid/SetupVariable.h>
-#include <Guid/PchRcVariable.h>
-#include <Guid/SocketVariable.h>
-#include <Guid/HobList.h>
-#include <Guid/MemoryMapData.h>
-#include "Platform.h"
-#include "Register/PchRegsUsb.h"
-#include <Library/PchCycleDecodingLib.h>
-#include <Library/PchInfoLib.h>
-
-#include <Uefi/UefiBaseType.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiRuntimeServicesTableLib.h>
-#include <Library/UefiLib.h>
-#include <Library/DebugLib.h>
-#include <Library/HobLib.h>
-
-#include <IndustryStandard/Acpi.h>
-
-#include <Protocol/MpService.h>
-
-#include <Protocol/AcpiSystemDescriptionTable.h>
-
-#include <Guid/MemoryMapData.h>
-#include <Guid/GlobalVariable.h>
-
-#include <Platform.h>
-#include <Acpi/GlobalNvsAreaDef.h>
-#include <Protocol/IioUds.h>
-#include <Protocol/CpuIo2.h>
-#include <Protocol/SerialIo.h>
-#include <Protocol/DevicePath.h>
-#include <IndustryStandard/Acpi.h>
-#include <IndustryStandard/AcpiAml.h>
-
-#include <Guid/SocketMpLinkVariable.h>
-#include <Guid/SocketIioVariable.h>
-#include <Guid/SocketPowermanagementVariable.h>
-#include <Guid/SocketCommonRcVariable.h>
-
-#include "Register/PchRegsUsb.h"
-
-#include <Register/Cpuid.h>
-#define EFI_FINE_GRAINED_CLOCK_MODULATION BIT5
-#define B_CPUID_POWER_MANAGEMENT_EAX_HWP_LVT_INTERRUPT_SUPPORT BIT9
-
-#endif
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable.c b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable.c
deleted file mode 100644
index abb484172e..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable.c
+++ /dev/null
@@ -1,290 +0,0 @@
-/** @file
- Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-/*
- *
- * Intel ACPI Component Architecture
- *
- *
- */
-#ifndef __AML_OFFSET_TABLE_H
-#define __AML_OFFSET_TABLE_H
-
-typedef struct {
- char *Pathname; /* Full pathname (from root) to the object */
- unsigned short ParentOpcode; /* AML opcode for the parent object */
- unsigned long NamesegOffset; /* Offset of last nameseg in the parent namepath */
- unsigned char Opcode; /* AML opcode for the data */
- unsigned long Offset; /* Offset for the data */
- unsigned long long Value; /* Original value of the data (as applicable) */
-} AML_OFFSET_TABLE_ENTRY;
-
-#endif /* __AML_OFFSET_TABLE_H */
-
-/*
- * Information specific to the supported object types:
- *
- * Integers:
- * Opcode is the integer prefix, indicates length of the data
- * (One of: BYTE, WORD, DWORD, QWORD, ZERO, ONE, ONES)
- * Offset points to the actual integer data
- * Value is the existing value in the AML
- *
- * Packages:
- * Opcode is the package or var_package opcode
- * Offset points to the package opcode
- * Value is the package element count
- *
- * Operation Regions:
- * Opcode is the address integer prefix, indicates length of the data
- * Offset points to the region address
- * Value is the existing address value in the AML
- *
- * Control Methods:
- * Offset points to the method flags byte
- * Value is the existing flags value in the AML
- *
- * Processors:
- * Offset points to the first byte of the PBlock Address
- *
- * Resource Descriptors:
- * Opcode is the descriptor type
- * Offset points to the start of the descriptor
- *
- * Scopes/Devices/ThermalZones:
- * Nameseg offset only
- */
-AML_OFFSET_TABLE_ENTRY DSDT_PLATWFP__OffsetTable[] =
-{
- {"PSYS", 0x5B80, 0x0000038B, 0x0C, 0x00000391, 0x0000000030584946}, /* OPERATIONREGION */
- {"_SB_.PC00.FIX1", 0x0011, 0x00000000, 0x88, 0x0000D187, 0x0000000000000000}, /* WORDBUSNUMBER */
- {"_SB_.PC00.FIX2", 0x0011, 0x00000000, 0x88, 0x0000D1AF, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC00.FIX5", 0x0011, 0x00000000, 0x87, 0x0000D1BF, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC00.FIX3", 0x0011, 0x00000000, 0x87, 0x0000D20D, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC00.FIX4", 0x0011, 0x00000000, 0x8A, 0x0000D227, 0x0000000000000000}, /* QWORDMEMORY */
- {"_SB_.PC01.FIX1", 0x0011, 0x00000000, 0x88, 0x0000EA9B, 0x0000000000000000}, /* WORDBUSNUMBER */
- {"_SB_.PC01.FIX5", 0x0011, 0x00000000, 0x87, 0x0000EAAB, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC01.FIX2", 0x0011, 0x00000000, 0x88, 0x0000EAC5, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC01.FIX6", 0x0011, 0x00000000, 0x88, 0x0000EAD5, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC01.FIX7", 0x0011, 0x00000000, 0x88, 0x0000EAE5, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC01.FIX3", 0x0011, 0x00000000, 0x87, 0x0000EAF5, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC01.FIX4", 0x0011, 0x00000000, 0x8A, 0x0000EB0F, 0x0000000000000000}, /* QWORDMEMORY */
- {"_SB_.PC01.BR1A.MCTL", 0x5B80, 0x0000EB91, 0x0C, 0x0000EB97, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC01.BR1B.MCTL", 0x5B80, 0x0000F3B2, 0x0C, 0x0000F3B8, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC01.BR1C.MCTL", 0x5B80, 0x0000FBD3, 0x0C, 0x0000FBD9, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC01.BR1D.MCTL", 0x5B80, 0x000103F4, 0x0C, 0x000103FA, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC02.FIX1", 0x0011, 0x00000000, 0x88, 0x00010E93, 0x0000000000000000}, /* WORDBUSNUMBER */
- {"_SB_.PC02.FIX5", 0x0011, 0x00000000, 0x87, 0x00010EA3, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC02.FIX2", 0x0011, 0x00000000, 0x88, 0x00010EBD, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC02.FIX6", 0x0011, 0x00000000, 0x88, 0x00010ECD, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC02.FIX7", 0x0011, 0x00000000, 0x88, 0x00010EDD, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC02.FIX3", 0x0011, 0x00000000, 0x87, 0x00010EED, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC02.FIX4", 0x0011, 0x00000000, 0x8A, 0x00010F07, 0x0000000000000000}, /* QWORDMEMORY */
- {"_SB_.PC02.BR2A.MCTL", 0x5B80, 0x00010F89, 0x0C, 0x00010F8F, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC02.BR2B.MCTL", 0x5B80, 0x00011969, 0x0C, 0x0001196F, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC02.BR2C.MCTL", 0x5B80, 0x0001218A, 0x0C, 0x00012190, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC02.BR2D.MCTL", 0x5B80, 0x000129AB, 0x0C, 0x000129B1, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC03.FIX1", 0x0011, 0x00000000, 0x88, 0x000133E4, 0x0000000000000000}, /* WORDBUSNUMBER */
- {"_SB_.PC03.FIX5", 0x0011, 0x00000000, 0x87, 0x000133F4, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC03.FIX2", 0x0011, 0x00000000, 0x88, 0x0001340E, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC03.FIX6", 0x0011, 0x00000000, 0x88, 0x0001341E, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC03.FIX7", 0x0011, 0x00000000, 0x88, 0x0001342E, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC03.FIX3", 0x0011, 0x00000000, 0x87, 0x0001343E, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC03.FIX4", 0x0011, 0x00000000, 0x8A, 0x00013458, 0x0000000000000000}, /* QWORDMEMORY */
- {"_SB_.PC03.BR3A.MCTL", 0x5B80, 0x000134DA, 0x0C, 0x000134E0, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC03.BR3B.MCTL", 0x5B80, 0x00013CFB, 0x0C, 0x00013D01, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC03.BR3C.MCTL", 0x5B80, 0x0001451C, 0x0C, 0x00014522, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC03.BR3D.MCTL", 0x5B80, 0x00014D3D, 0x0C, 0x00014D43, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC04.FIX1", 0x0011, 0x00000000, 0x88, 0x000156F0, 0x0000000000000000}, /* WORDBUSNUMBER */
- {"_SB_.PC04.FIX5", 0x0011, 0x00000000, 0x87, 0x00015700, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC04.FIX2", 0x0011, 0x00000000, 0x88, 0x0001571A, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC04.FIX6", 0x0011, 0x00000000, 0x88, 0x0001572A, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC04.FIX7", 0x0011, 0x00000000, 0x88, 0x0001573A, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC04.FIX3", 0x0011, 0x00000000, 0x87, 0x0001574A, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC04.FIX4", 0x0011, 0x00000000, 0x8A, 0x00015764, 0x0000000000000000}, /* QWORDMEMORY */
- {"_SB_.PC04.MCP0.MCTL", 0x5B80, 0x000157E6, 0x0C, 0x000157EC, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC05.FIX1", 0x0011, 0x00000000, 0x88, 0x0001612D, 0x0000000000000000}, /* WORDBUSNUMBER */
- {"_SB_.PC05.FIX5", 0x0011, 0x00000000, 0x87, 0x0001613D, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC05.FIX2", 0x0011, 0x00000000, 0x88, 0x00016157, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC05.FIX6", 0x0011, 0x00000000, 0x88, 0x00016167, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC05.FIX7", 0x0011, 0x00000000, 0x88, 0x00016177, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC05.FIX3", 0x0011, 0x00000000, 0x87, 0x00016187, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC05.FIX4", 0x0011, 0x00000000, 0x8A, 0x000161A1, 0x0000000000000000}, /* QWORDMEMORY */
- {"_SB_.PC05.MCP1.MCTL", 0x5B80, 0x00016223, 0x0C, 0x00016229, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC06.FIX1", 0x0011, 0x00000000, 0x88, 0x00016FD9, 0x0000000000000000}, /* WORDBUSNUMBER */
- {"_SB_.PC06.FIX5", 0x0011, 0x00000000, 0x87, 0x00016FE9, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC06.FIX2", 0x0011, 0x00000000, 0x88, 0x00017003, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC06.FIX6", 0x0011, 0x00000000, 0x88, 0x00017013, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC06.FIX7", 0x0011, 0x00000000, 0x88, 0x00017023, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC06.FIX3", 0x0011, 0x00000000, 0x87, 0x00017033, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC06.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001704D, 0x0000000000000000}, /* QWORDMEMORY */
- {"_SB_.PC06.QRP0.MCTL", 0x5B80, 0x00017149, 0x0C, 0x0001714F, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC07.FIX1", 0x0011, 0x00000000, 0x88, 0x00017BC4, 0x0000000000000000}, /* WORDBUSNUMBER */
- {"_SB_.PC07.FIX5", 0x0011, 0x00000000, 0x87, 0x00017BD4, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC07.FIX2", 0x0011, 0x00000000, 0x88, 0x00017BEE, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC07.FIX6", 0x0011, 0x00000000, 0x88, 0x00017BFE, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC07.FIX7", 0x0011, 0x00000000, 0x88, 0x00017C0E, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC07.FIX3", 0x0011, 0x00000000, 0x87, 0x00017C1E, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC07.FIX4", 0x0011, 0x00000000, 0x8A, 0x00017C38, 0x0000000000000000}, /* QWORDMEMORY */
- {"_SB_.PC07.QR1A.MCTL", 0x5B80, 0x00017CCA, 0x0C, 0x00017CD0, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC07.QR1B.MCTL", 0x5B80, 0x00018506, 0x0C, 0x0001850C, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC07.QR1C.MCTL", 0x5B80, 0x00018D42, 0x0C, 0x00018D48, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC07.QR1D.MCTL", 0x5B80, 0x0001957E, 0x0C, 0x00019584, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC08.FIX1", 0x0011, 0x00000000, 0x88, 0x0001A04E, 0x0000000000000000}, /* WORDBUSNUMBER */
- {"_SB_.PC08.FIX5", 0x0011, 0x00000000, 0x87, 0x0001A05E, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC08.FIX2", 0x0011, 0x00000000, 0x88, 0x0001A078, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC08.FIX6", 0x0011, 0x00000000, 0x88, 0x0001A088, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC08.FIX7", 0x0011, 0x00000000, 0x88, 0x0001A098, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC08.FIX3", 0x0011, 0x00000000, 0x87, 0x0001A0A8, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC08.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001A0C2, 0x0000000000000000}, /* QWORDMEMORY */
- {"_SB_.PC08.QR2A.MCTL", 0x5B80, 0x0001A154, 0x0C, 0x0001A15A, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC08.QR2B.MCTL", 0x5B80, 0x0001A990, 0x0C, 0x0001A996, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC08.QR2C.MCTL", 0x5B80, 0x0001B1CC, 0x0C, 0x0001B1D2, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC08.QR2D.MCTL", 0x5B80, 0x0001BA08, 0x0C, 0x0001BA0E, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC09.FIX1", 0x0011, 0x00000000, 0x88, 0x0001C461, 0x0000000000000000}, /* WORDBUSNUMBER */
- {"_SB_.PC09.FIX5", 0x0011, 0x00000000, 0x87, 0x0001C471, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC09.FIX2", 0x0011, 0x00000000, 0x88, 0x0001C48B, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC09.FIX6", 0x0011, 0x00000000, 0x88, 0x0001C49B, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC09.FIX7", 0x0011, 0x00000000, 0x88, 0x0001C4AB, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC09.FIX3", 0x0011, 0x00000000, 0x87, 0x0001C4BB, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC09.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001C4D5, 0x0000000000000000}, /* QWORDMEMORY */
- {"_SB_.PC09.QR3A.MCTL", 0x5B80, 0x0001C567, 0x0C, 0x0001C56D, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC09.QR3B.MCTL", 0x5B80, 0x0001CDA3, 0x0C, 0x0001CDA9, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC09.QR3C.MCTL", 0x5B80, 0x0001D5DF, 0x0C, 0x0001D5E5, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC09.QR3D.MCTL", 0x5B80, 0x0001DE1B, 0x0C, 0x0001DE21, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC10.FIX1", 0x0011, 0x00000000, 0x88, 0x0001E7EE, 0x0000000000000000}, /* WORDBUSNUMBER */
- {"_SB_.PC10.FIX5", 0x0011, 0x00000000, 0x87, 0x0001E7FE, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC10.FIX2", 0x0011, 0x00000000, 0x88, 0x0001E818, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC10.FIX6", 0x0011, 0x00000000, 0x88, 0x0001E828, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC10.FIX7", 0x0011, 0x00000000, 0x88, 0x0001E838, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC10.FIX3", 0x0011, 0x00000000, 0x87, 0x0001E848, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC10.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001E862, 0x0000000000000000}, /* QWORDMEMORY */
- {"_SB_.PC10.MCP2.MCTL", 0x5B80, 0x0001E8F4, 0x0C, 0x0001E8FA, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC11.FIX1", 0x0011, 0x00000000, 0x88, 0x0001F250, 0x0000000000000000}, /* WORDBUSNUMBER */
- {"_SB_.PC11.FIX5", 0x0011, 0x00000000, 0x87, 0x0001F260, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC11.FIX2", 0x0011, 0x00000000, 0x88, 0x0001F27A, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC11.FIX6", 0x0011, 0x00000000, 0x88, 0x0001F28A, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC11.FIX7", 0x0011, 0x00000000, 0x88, 0x0001F29A, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC11.FIX3", 0x0011, 0x00000000, 0x87, 0x0001F2AA, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC11.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001F2C4, 0x0000000000000000}, /* QWORDMEMORY */
- {"_SB_.PC11.MCP3.MCTL", 0x5B80, 0x0001F356, 0x0C, 0x0001F35C, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC12.FIX1", 0x0011, 0x00000000, 0x88, 0x0002011C, 0x0000000000000000}, /* WORDBUSNUMBER */
- {"_SB_.PC12.FIX5", 0x0011, 0x00000000, 0x87, 0x0002012C, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC12.FIX2", 0x0011, 0x00000000, 0x88, 0x00020146, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC12.FIX6", 0x0011, 0x00000000, 0x88, 0x00020156, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC12.FIX7", 0x0011, 0x00000000, 0x88, 0x00020166, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC12.FIX3", 0x0011, 0x00000000, 0x87, 0x00020176, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC12.FIX4", 0x0011, 0x00000000, 0x8A, 0x00020190, 0x0000000000000000}, /* QWORDMEMORY */
- {"_SB_.PC12.RRP0.MCTL", 0x5B80, 0x0002028C, 0x0C, 0x00020292, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC13.FIX1", 0x0011, 0x00000000, 0x88, 0x00020D07, 0x0000000000000000}, /* WORDBUSNUMBER */
- {"_SB_.PC13.FIX5", 0x0011, 0x00000000, 0x87, 0x00020D17, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC13.FIX2", 0x0011, 0x00000000, 0x88, 0x00020D31, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC13.FIX6", 0x0011, 0x00000000, 0x88, 0x00020D41, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC13.FIX7", 0x0011, 0x00000000, 0x88, 0x00020D51, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC13.FIX3", 0x0011, 0x00000000, 0x87, 0x00020D61, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC13.FIX4", 0x0011, 0x00000000, 0x8A, 0x00020D7B, 0x0000000000000000}, /* QWORDMEMORY */
- {"_SB_.PC13.RR1A.MCTL", 0x5B80, 0x00020E0D, 0x0C, 0x00020E13, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC13.RR1B.MCTL", 0x5B80, 0x00021649, 0x0C, 0x0002164F, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC13.RR1C.MCTL", 0x5B80, 0x00021E85, 0x0C, 0x00021E8B, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC13.RR1D.MCTL", 0x5B80, 0x000226C1, 0x0C, 0x000226C7, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC14.FIX1", 0x0011, 0x00000000, 0x88, 0x0002316F, 0x0000000000000000}, /* WORDBUSNUMBER */
- {"_SB_.PC14.FIX5", 0x0011, 0x00000000, 0x87, 0x0002317F, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC14.FIX2", 0x0011, 0x00000000, 0x88, 0x00023199, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC14.FIX6", 0x0011, 0x00000000, 0x88, 0x000231A9, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC14.FIX7", 0x0011, 0x00000000, 0x88, 0x000231B9, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC14.FIX3", 0x0011, 0x00000000, 0x87, 0x000231C9, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC14.FIX4", 0x0011, 0x00000000, 0x8A, 0x000231E3, 0x0000000000000000}, /* QWORDMEMORY */
- {"_SB_.PC14.RR2A.MCTL", 0x5B80, 0x00023275, 0x0C, 0x0002327B, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC14.RR2B.MCTL", 0x5B80, 0x00023AB1, 0x0C, 0x00023AB7, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC14.RR2C.MCTL", 0x5B80, 0x000242ED, 0x0C, 0x000242F3, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC14.RR2D.MCTL", 0x5B80, 0x00024B29, 0x0C, 0x00024B2F, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC15.FIX1", 0x0011, 0x00000000, 0x88, 0x00025582, 0x0000000000000000}, /* WORDBUSNUMBER */
- {"_SB_.PC15.FIX5", 0x0011, 0x00000000, 0x87, 0x00025592, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC15.FIX2", 0x0011, 0x00000000, 0x88, 0x000255AC, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC15.FIX6", 0x0011, 0x00000000, 0x88, 0x000255BC, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC15.FIX7", 0x0011, 0x00000000, 0x88, 0x000255CC, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC15.FIX3", 0x0011, 0x00000000, 0x87, 0x000255DC, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC15.FIX4", 0x0011, 0x00000000, 0x8A, 0x000255F6, 0x0000000000000000}, /* QWORDMEMORY */
- {"_SB_.PC15.RR3A.MCTL", 0x5B80, 0x00025688, 0x0C, 0x0002568E, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC15.RR3B.MCTL", 0x5B80, 0x00025EC4, 0x0C, 0x00025ECA, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC15.RR3C.MCTL", 0x5B80, 0x00026700, 0x0C, 0x00026706, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC15.RR3D.MCTL", 0x5B80, 0x00026F3C, 0x0C, 0x00026F42, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC16.FIX1", 0x0011, 0x00000000, 0x88, 0x0002790F, 0x0000000000000000}, /* WORDBUSNUMBER */
- {"_SB_.PC16.FIX5", 0x0011, 0x00000000, 0x87, 0x0002791F, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC16.FIX2", 0x0011, 0x00000000, 0x88, 0x00027939, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC16.FIX6", 0x0011, 0x00000000, 0x88, 0x00027949, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC16.FIX7", 0x0011, 0x00000000, 0x88, 0x00027959, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC16.FIX3", 0x0011, 0x00000000, 0x87, 0x00027969, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC16.FIX4", 0x0011, 0x00000000, 0x8A, 0x00027983, 0x0000000000000000}, /* QWORDMEMORY */
- {"_SB_.PC16.MCP4.MCTL", 0x5B80, 0x00027A15, 0x0C, 0x00027A1B, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC17.FIX1", 0x0011, 0x00000000, 0x88, 0x00028371, 0x0000000000000000}, /* WORDBUSNUMBER */
- {"_SB_.PC17.FIX5", 0x0011, 0x00000000, 0x87, 0x00028381, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC17.FIX2", 0x0011, 0x00000000, 0x88, 0x0002839B, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC17.FIX6", 0x0011, 0x00000000, 0x88, 0x000283AB, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC17.FIX7", 0x0011, 0x00000000, 0x88, 0x000283BB, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC17.FIX3", 0x0011, 0x00000000, 0x87, 0x000283CB, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC17.FIX4", 0x0011, 0x00000000, 0x8A, 0x000283E5, 0x0000000000000000}, /* QWORDMEMORY */
- {"_SB_.PC17.MCP5.MCTL", 0x5B80, 0x00028477, 0x0C, 0x0002847D, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC18.FIX1", 0x0011, 0x00000000, 0x88, 0x0002923D, 0x0000000000000000}, /* WORDBUSNUMBER */
- {"_SB_.PC18.FIX5", 0x0011, 0x00000000, 0x87, 0x0002924D, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC18.FIX2", 0x0011, 0x00000000, 0x88, 0x00029267, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC18.FIX6", 0x0011, 0x00000000, 0x88, 0x00029277, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC18.FIX7", 0x0011, 0x00000000, 0x88, 0x00029287, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC18.FIX3", 0x0011, 0x00000000, 0x87, 0x00029297, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC18.FIX4", 0x0011, 0x00000000, 0x8A, 0x000292B1, 0x0000000000000000}, /* QWORDMEMORY */
- {"_SB_.PC18.SRP0.MCTL", 0x5B80, 0x000293AD, 0x0C, 0x000293B3, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC19.FIX1", 0x0011, 0x00000000, 0x88, 0x00029E28, 0x0000000000000000}, /* WORDBUSNUMBER */
- {"_SB_.PC19.FIX5", 0x0011, 0x00000000, 0x87, 0x00029E38, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC19.FIX2", 0x0011, 0x00000000, 0x88, 0x00029E52, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC19.FIX6", 0x0011, 0x00000000, 0x88, 0x00029E62, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC19.FIX7", 0x0011, 0x00000000, 0x88, 0x00029E72, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC19.FIX3", 0x0011, 0x00000000, 0x87, 0x00029E82, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC19.FIX4", 0x0011, 0x00000000, 0x8A, 0x00029E9C, 0x0000000000000000}, /* QWORDMEMORY */
- {"_SB_.PC19.SR1A.MCTL", 0x5B80, 0x00029F2E, 0x0C, 0x00029F34, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC19.SR1B.MCTL", 0x5B80, 0x0002A76A, 0x0C, 0x0002A770, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC19.SR1C.MCTL", 0x5B80, 0x0002AFA6, 0x0C, 0x0002AFAC, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC19.SR1D.MCTL", 0x5B80, 0x0002B7E2, 0x0C, 0x0002B7E8, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC20.FIX1", 0x0011, 0x00000000, 0x88, 0x0002C2B2, 0x0000000000000000}, /* WORDBUSNUMBER */
- {"_SB_.PC20.FIX5", 0x0011, 0x00000000, 0x87, 0x0002C2C2, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC20.FIX2", 0x0011, 0x00000000, 0x88, 0x0002C2DC, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC20.FIX6", 0x0011, 0x00000000, 0x88, 0x0002C2EC, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC20.FIX7", 0x0011, 0x00000000, 0x88, 0x0002C2FC, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC20.FIX3", 0x0011, 0x00000000, 0x87, 0x0002C30C, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC20.FIX4", 0x0011, 0x00000000, 0x8A, 0x0002C326, 0x0000000000000000}, /* QWORDMEMORY */
- {"_SB_.PC20.SR2A.MCTL", 0x5B80, 0x0002C3B8, 0x0C, 0x0002C3BE, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC20.SR2B.MCTL", 0x5B80, 0x0002CBF4, 0x0C, 0x0002CBFA, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC20.SR2C.MCTL", 0x5B80, 0x0002D430, 0x0C, 0x0002D436, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC20.SR2D.MCTL", 0x5B80, 0x0002DC6C, 0x0C, 0x0002DC72, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC21.FIX1", 0x0011, 0x00000000, 0x88, 0x0002E6C5, 0x0000000000000000}, /* WORDBUSNUMBER */
- {"_SB_.PC21.FIX5", 0x0011, 0x00000000, 0x87, 0x0002E6D5, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC21.FIX2", 0x0011, 0x00000000, 0x88, 0x0002E6EF, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC21.FIX6", 0x0011, 0x00000000, 0x88, 0x0002E6FF, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC21.FIX7", 0x0011, 0x00000000, 0x88, 0x0002E70F, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC21.FIX3", 0x0011, 0x00000000, 0x87, 0x0002E71F, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC21.FIX4", 0x0011, 0x00000000, 0x8A, 0x0002E739, 0x0000000000000000}, /* QWORDMEMORY */
- {"_SB_.PC21.SR3A.MCTL", 0x5B80, 0x0002E7CB, 0x0C, 0x0002E7D1, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC21.SR3B.MCTL", 0x5B80, 0x0002F007, 0x0C, 0x0002F00D, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC21.SR3C.MCTL", 0x5B80, 0x0002F843, 0x0C, 0x0002F849, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC21.SR3D.MCTL", 0x5B80, 0x0003007F, 0x0C, 0x00030085, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC22.FIX1", 0x0011, 0x00000000, 0x88, 0x00030A52, 0x0000000000000000}, /* WORDBUSNUMBER */
- {"_SB_.PC22.FIX5", 0x0011, 0x00000000, 0x87, 0x00030A62, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC22.FIX2", 0x0011, 0x00000000, 0x88, 0x00030A7C, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC22.FIX6", 0x0011, 0x00000000, 0x88, 0x00030A8C, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC22.FIX7", 0x0011, 0x00000000, 0x88, 0x00030A9C, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC22.FIX3", 0x0011, 0x00000000, 0x87, 0x00030AAC, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC22.FIX4", 0x0011, 0x00000000, 0x8A, 0x00030AC6, 0x0000000000000000}, /* QWORDMEMORY */
- {"_SB_.PC22.MCP6.MCTL", 0x5B80, 0x00030B58, 0x0C, 0x00030B5E, 0x0000000038584946}, /* OPERATIONREGION */
- {"_SB_.PC23.FIX1", 0x0011, 0x00000000, 0x88, 0x000314B4, 0x0000000000000000}, /* WORDBUSNUMBER */
- {"_SB_.PC23.FIX5", 0x0011, 0x00000000, 0x87, 0x000314C4, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC23.FIX2", 0x0011, 0x00000000, 0x88, 0x000314DE, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC23.FIX6", 0x0011, 0x00000000, 0x88, 0x000314EE, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC23.FIX7", 0x0011, 0x00000000, 0x88, 0x000314FE, 0x0000000000000000}, /* WORDIO */
- {"_SB_.PC23.FIX3", 0x0011, 0x00000000, 0x87, 0x0003150E, 0x0000000000000000}, /* DWORDMEMORY */
- {"_SB_.PC23.FIX4", 0x0011, 0x00000000, 0x8A, 0x00031528, 0x0000000000000000}, /* QWORDMEMORY */
- {"_SB_.PC23.MCP7.MCTL", 0x5B80, 0x000315BA, 0x0C, 0x000315C0, 0x0000000038584946}, /* OPERATIONREGION */
- {NULL,0,0,0,0,0} /* Table terminator */
-};
-
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c
deleted file mode 100644
index 2b9e6e477d..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c
+++ /dev/null
@@ -1,546 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include "BoardAcpiDxe.h"
-
-EFI_STATUS
-PatchDsdtTable (
- IN OUT EFI_ACPI_COMMON_HEADER *Table
- );
-
-#pragma optimize("",off)
-
-BIOS_ACPI_PARAM *mAcpiParameter;
-
-EFI_IIO_UDS_PROTOCOL *mIioUds;
-
-UINT32 mNumOfBitShift;
-BOOLEAN mForceX2ApicId;
-BOOLEAN mX2ApicEnabled;
-
-struct SystemMemoryMapHob *mSystemMemoryMap;
-
-SOCKET_MP_LINK_CONFIGURATION mSocketMpLinkConfiguration;
-SOCKET_IIO_CONFIGURATION mSocketIioConfiguration;
-SOCKET_POWERMANAGEMENT_CONFIGURATION mSocketPowermanagementConfiguration;
-
-BOOLEAN mFirstNotify;
-PCH_RC_CONFIGURATION mPchRcConfiguration;
-
-UINT8 mKBPresent = 0;
-UINT8 mMousePresent = 0;
-
-/**
-
- Locate the first instance of a protocol. If the protocol requested is an
- FV protocol, then it will return the first FV that contains the ACPI table
- storage file.
-
- @param Protocol - The protocol to find.
- Instance - Return pointer to the first instance of the protocol.
- Type - The type of protocol to locate.
-
- @retval EFI_SUCCESS - The function completed successfully.
- @retval EFI_NOT_FOUND - The protocol could not be located.
- @retval EFI_OUT_OF_RESOURCES - There are not enough resources to find the protocol.
-
-**/
-EFI_STATUS
-LocateSupportProtocol (
- IN EFI_GUID *Protocol,
- IN EFI_GUID *gEfiAcpiMultiTableStorageGuid,
- OUT VOID **Instance,
- IN UINT32 Type
- )
-{
- EFI_STATUS Status;
- EFI_HANDLE *HandleBuffer;
- UINTN NumberOfHandles;
- EFI_FV_FILETYPE FileType;
- UINT32 FvStatus;
- EFI_FV_FILE_ATTRIBUTES Attributes;
- UINTN Size;
- UINTN Index;
-
- FvStatus = 0;
- //
- // Locate protocol.
- //
- Status = gBS->LocateHandleBuffer (
- ByProtocol,
- Protocol,
- NULL,
- &NumberOfHandles,
- &HandleBuffer
- );
- if (EFI_ERROR (Status)) {
- //
- // Defined errors at this time are not found and out of resources.
- //
- return Status;
- }
- //
- // Looking for FV with ACPI storage file
- //
- for (Index = 0; Index < NumberOfHandles; Index++) {
- //
- // Get the protocol on this handle
- // This should not fail because of LocateHandleBuffer
- //
- Status = gBS->HandleProtocol (
- HandleBuffer[Index],
- Protocol,
- Instance
- );
- ASSERT (!EFI_ERROR (Status));
-
- if (!Type) {
- //
- // Not looking for the FV protocol, so find the first instance of the
- // protocol. There should not be any errors because our handle buffer
- // should always contain at least one or LocateHandleBuffer would have
- // returned not found.
- //
- break;
- }
- //
- // See if it has the ACPI storage file
- //
- Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL *) (*Instance))->ReadFile (
- *Instance,
- gEfiAcpiMultiTableStorageGuid,
- NULL,
- &Size,
- &FileType,
- &Attributes,
- &FvStatus
- );
-
- //
- // If we found it, then we are done
- //
- if (!EFI_ERROR (Status)) {
- break;
- }
- }
- //
- // Our exit status is determined by the success of the previous operations
- // If the protocol was found, Instance already points to it.
- //
- //
- // Free any allocated buffers
- //
- gBS->FreePool (HandleBuffer);
-
- return Status;
-}
-
-/**
-
- GC_TODO: add routine description
-
- @param None
-
- @retval EFI_SUCCESS - GC_TODO: add retval description
-
-**/
-EFI_STATUS
-PlatformHookInit (
- VOID
- )
-{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS AcpiParameterAddr;
- UINT32 RegEax;
- UINT32 RegEbx;
- UINT32 RegEcx;
- UINT32 RegEdx;
-
- CopyMem (&mSocketMpLinkConfiguration, PcdGetPtr(PcdSocketMpLinkConfigData), sizeof(SOCKET_MP_LINK_CONFIGURATION));
- CopyMem (&mSocketPowermanagementConfiguration, PcdGetPtr(PcdSocketPowerManagementConfigData), sizeof(SOCKET_POWERMANAGEMENT_CONFIGURATION));
- CopyMem (&mSocketIioConfiguration, PcdGetPtr(PcdSocketIioConfigData), sizeof(SOCKET_IIO_CONFIGURATION));
- CopyMem (&mPchRcConfiguration, PcdGetPtr(PcdPchRcConfigurationData), sizeof(PCH_RC_CONFIGURATION));
-
- DEBUG ((DEBUG_INFO, "mX2ApicEnabled - 0x%x\n", mX2ApicEnabled));
- DEBUG ((DEBUG_INFO, "mForceX2ApicId - 0x%x\n", mForceX2ApicId));
-
- {
- UINT32 Index;
-
- for (Index = 0; Index < 4; Index++) {
- AsmCpuidEx(CPUID_EXTENDED_TOPOLOGY, Index, &RegEax, &RegEbx, &RegEcx, &RegEdx);
- DEBUG ((DEBUG_INFO, "CPUID(0xB - %d) - 0x%08x.0x%08x.0x%08x.0x%08x\n", Index, RegEax, RegEbx, RegEcx, RegEdx));
- }
- }
-
- //
- // Allocate 256 runtime memory to pass ACPI parameter
- // This Address must be < 4G because we only have 32bit in the dsdt
- //
- AcpiParameterAddr = 0xffffffff;
- Status = gBS->AllocatePages (
- AllocateMaxAddress,
- EfiACPIMemoryNVS,
- EFI_SIZE_TO_PAGES (sizeof(BIOS_ACPI_PARAM)),
- &AcpiParameterAddr
- );
- ASSERT_EFI_ERROR (Status);
- mAcpiParameter = (BIOS_ACPI_PARAM *)AcpiParameterAddr;
-
- DEBUG ((EFI_D_ERROR, "ACPI Parameter Block Address: 0x%X\n", mAcpiParameter));
- PcdSet64 (PcdAcpiGnvsAddress, (UINT64)(UINTN)mAcpiParameter);
-
- ZeroMem (mAcpiParameter, sizeof (BIOS_ACPI_PARAM));
- mAcpiParameter->PlatformId = 0;
-#if MAX_SOCKET > 4
- mAcpiParameter->IoApicEnable = PcdGet32 (PcdPcIoApicEnable);
-#else
- mAcpiParameter->IoApicEnable = (PcdGet32 (PcdPcIoApicEnable) << 1) | 1;
-#endif
- DEBUG((EFI_D_ERROR, "io apic settings:%d\n", mAcpiParameter->IoApicEnable));
-
- AsmCpuid (CPUID_VERSION_INFO, &RegEax, &RegEbx, &RegEcx, &RegEdx);
- mAcpiParameter->ProcessorId = (RegEax & 0xFFFF0);
-
- // support up to 64 threads/socket
- AsmCpuidEx(CPUID_EXTENDED_TOPOLOGY, 1, &mNumOfBitShift, NULL, NULL, NULL);
- mNumOfBitShift &= 0x1F;
-
- // Set the bit shift value for CPU SKU
- mAcpiParameter->CpuSkuNumOfBitShift = (UINT8) mNumOfBitShift;
-
- mAcpiParameter->ProcessorApicIdBase[0] = (UINT32) (0 << mNumOfBitShift);
- mAcpiParameter->ProcessorApicIdBase[1] = (UINT32) (1 << mNumOfBitShift);
- mAcpiParameter->ProcessorApicIdBase[2] = (UINT32) (2 << mNumOfBitShift);
- mAcpiParameter->ProcessorApicIdBase[3] = (UINT32) (3 << mNumOfBitShift);
- mAcpiParameter->ProcessorApicIdBase[4] = (UINT32) (4 << mNumOfBitShift);
- mAcpiParameter->ProcessorApicIdBase[5] = (UINT32) (5 << mNumOfBitShift);
- mAcpiParameter->ProcessorApicIdBase[6] = (UINT32) (6 << mNumOfBitShift);
- mAcpiParameter->ProcessorApicIdBase[7] = (UINT32) (7 << mNumOfBitShift);
-
- if(mForceX2ApicId) {
- mAcpiParameter->ProcessorApicIdBase[0] = 0x7F00;
- mAcpiParameter->ProcessorApicIdBase[1] = 0x7F20;
- mAcpiParameter->ProcessorApicIdBase[2] = 0x7F40;
- mAcpiParameter->ProcessorApicIdBase[3] = 0x7F60;
- mAcpiParameter->ProcessorApicIdBase[4] = 0x7F80;
- mAcpiParameter->ProcessorApicIdBase[5] = 0x7Fa0;
- mAcpiParameter->ProcessorApicIdBase[6] = 0x7Fc0;
- mAcpiParameter->ProcessorApicIdBase[7] = 0x7Fe0;
-
- if (mNumOfBitShift == 4) {
- mAcpiParameter->ProcessorApicIdBase[0] = 0x7F00;
- mAcpiParameter->ProcessorApicIdBase[1] = 0x7F10;
- mAcpiParameter->ProcessorApicIdBase[2] = 0x7F20;
- mAcpiParameter->ProcessorApicIdBase[3] = 0x7F30;
- mAcpiParameter->ProcessorApicIdBase[4] = 0x7F40;
- mAcpiParameter->ProcessorApicIdBase[5] = 0x7F50;
- mAcpiParameter->ProcessorApicIdBase[6] = 0x7F60;
- mAcpiParameter->ProcessorApicIdBase[7] = 0x7F70;
- } else if(mNumOfBitShift == 6) {
- mAcpiParameter->ProcessorApicIdBase[0] = 0x7E00;
- mAcpiParameter->ProcessorApicIdBase[1] = 0x7E20;
- mAcpiParameter->ProcessorApicIdBase[2] = 0x7E40;
- mAcpiParameter->ProcessorApicIdBase[3] = 0x7E60;
- mAcpiParameter->ProcessorApicIdBase[4] = 0x7E80;
- mAcpiParameter->ProcessorApicIdBase[5] = 0x7Ea0;
- mAcpiParameter->ProcessorApicIdBase[6] = 0x7Ec0;
- mAcpiParameter->ProcessorApicIdBase[7] = 0x7Ee0;
- }
- }
-
- //
- // If SNC is enabled, and NumOfCluster is 2, set the ACPI variable for PXM value
- //
- if(mIioUds->IioUdsPtr->SystemStatus.OutSncEn && (mIioUds->IioUdsPtr->SystemStatus.OutNumOfCluster == 2)){
- mAcpiParameter->SncAnd2Cluster = 1;
- } else {
- mAcpiParameter->SncAnd2Cluster = 0;
- }
-
- mAcpiParameter->MmCfg = (UINT32)mIioUds->IioUdsPtr->PlatformData.PciExpressBase;
- mAcpiParameter->TsegSize = (UINT32)(mIioUds->IioUdsPtr->PlatformData.MemTsegSize >> 20);
-
- return EFI_SUCCESS;
-}
-
-/**
-
- This function will update any runtime platform specific information.
- This currently includes:
- Setting OEM table values, ID, table ID, creator ID and creator revision.
- Enabling the proper processor entries in the APIC tables.
-
- @param Table - The table to update
-
- @retval EFI_SUCCESS - The function completed successfully.
-
-**/
-EFI_STATUS
-PlatformUpdateTables (
- IN OUT EFI_ACPI_COMMON_HEADER *Table,
- IN OUT EFI_ACPI_TABLE_VERSION *Version
- )
-{
- EFI_STATUS Status;
-
- Status = EFI_SUCCESS;
-
- //
- // By default, a table belongs in all ACPI table versions published.
- // Some tables will override this because they have different versions of the table.
- //
- *Version = EFI_ACPI_TABLE_VERSION_2_0;
- //
- // Update the processors in the APIC table
- //
- switch (Table->Signature) {
-
- case EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:
- //
- // Patch the memory resource
- //
- Status = PatchDsdtTable(Table);
- break;
-
- default:
- ASSERT(FALSE);
- break;
- }
- //
- //
- // Update the hardware signature in the FACS structure
- //
- //
- //
- return Status;
-}
-
-
-
-/**
-
- GC_TODO: Add function description
-
- @param Event - GC_TODO: add argument description
- @param Context - GC_TODO: add argument description
-
- @retval GC_TODO: add return values
-
-**/
-STATIC
-VOID
-EFIAPI
-OnReadyToBoot (
- IN EFI_EVENT Event,
- IN VOID *Context
- )
-{
- UINT32 RegEax;
- UINT32 RegEbx;
- UINT32 RegEcx;
- UINT32 RegEdx;
-
- if (mFirstNotify) {
- return ;
- }
-
- mFirstNotify = TRUE;
-
- CopyMem (&mSocketIioConfiguration, PcdGetPtr(PcdSocketIioConfigData), sizeof(SOCKET_IIO_CONFIGURATION));
- CopyMem (&mSocketPowermanagementConfiguration,PcdGetPtr(PcdSocketPowerManagementConfigData), sizeof(SOCKET_POWERMANAGEMENT_CONFIGURATION));
- CopyMem (&mPchRcConfiguration, PcdGetPtr(PcdPchRcConfigurationData), sizeof(PCH_RC_CONFIGURATION));
-
- // CpuPm.Asl: External (CSEN, FieldUnitObj)
- mAcpiParameter->CStateEnable = !mSocketPowermanagementConfiguration.ProcessorAutonomousCstateEnable;
- // CpuPm.Asl: External (C3EN, FieldUnitObj)
- mAcpiParameter->C3Enable = mSocketPowermanagementConfiguration.C3Enable;
- // CpuPm.Asl: External (C6EN, FieldUnitObj)
- if (mSocketPowermanagementConfiguration.C6Enable == PPM_AUTO) {
- mAcpiParameter->C6Enable = 1; //POR Default = Enabled
- } else {
- mAcpiParameter->C6Enable = mSocketPowermanagementConfiguration.C6Enable;
- }
- if(mAcpiParameter->C6Enable && mAcpiParameter->C3Enable) { //C3 and C6 enable are exclusive
- mAcpiParameter->C6Enable = 1;
- mAcpiParameter->C3Enable = 0;
- }
- // CpuPm.Asl: External (C7EN, FieldUnitObj)
- mAcpiParameter->C7Enable = 0;
- // CpuPm.Asl: External (OSCX, FieldUnitObj)
- mAcpiParameter->OSCX = mSocketPowermanagementConfiguration.OSCx;
- // CpuPm.Asl: External (MWOS, FieldUnitObj)
- mAcpiParameter->MonitorMwaitEnable = 1;
- // CpuPm.Asl: External (PSEN, FieldUnitObj)
- mAcpiParameter->PStateEnable = mSocketPowermanagementConfiguration.ProcessorEistEnable;
- // CpuPm.Asl: External (HWAL, FieldUnitObj)
- mAcpiParameter->HWAllEnable = 0; //Update in PatchGv3SsdtTable
-
- mAcpiParameter->KBPresent = mKBPresent;
- mAcpiParameter->MousePresent = mMousePresent;
- mAcpiParameter->TStateEnable = mSocketPowermanagementConfiguration.TStateEnable;
- //Fine grained T state
- AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &RegEax, &RegEbx, &RegEcx, &RegEdx);
- if ((RegEax & EFI_FINE_GRAINED_CLOCK_MODULATION) && (mSocketPowermanagementConfiguration.OnDieThermalThrottling > 0)){
- mAcpiParameter->TStateFineGrained = 1;
- }
- if(RegEax & B_CPUID_POWER_MANAGEMENT_EAX_HWP_LVT_INTERRUPT_SUPPORT) {
- mAcpiParameter->HwpInterrupt = 1;
- }
- // CpuPm.Asl: External (HWEN, FieldUnitObj)
- mAcpiParameter->HWPMEnable = mSocketPowermanagementConfiguration.ProcessorHWPMEnable;
- // CpuPm.Asl: External (ACEN, FieldUnitObj)
- mAcpiParameter->AutoCstate = mSocketPowermanagementConfiguration.ProcessorAutonomousCstateEnable;
-
- mAcpiParameter->EmcaEn = 0;
-
- mAcpiParameter->PcieAcpiHotPlugEnable = (UINT8) (BOOLEAN) (mSocketIioConfiguration.PcieAcpiHotPlugEnable != 0);
- //
- // Initialize USB3 mode from setup data
- //
- // If mode != manual control
- // just copy mode from setup
- if (mPchRcConfiguration.PchUsbManualMode != 1) {
- mAcpiParameter->XhciMode = mPchRcConfiguration.PchUsbManualMode;
- }
-
-}
-
-/**
-
- Entry point for Acpi platform driver.
-
- @param ImageHandle - A handle for the image that is initializing this driver.
- @param SystemTable - A pointer to the EFI system table.
-
- @retval EFI_SUCCESS - Driver initialized successfully.
- @retval EFI_LOAD_ERROR - Failed to Initialize or has been loaded.
- @retval EFI_OUT_OF_RESOURCES - Could not allocate needed resources.
-
-**/
-EFI_STATUS
-EFIAPI
-InstallAcpiBoard (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
-{
- EFI_STATUS Status;
- EFI_STATUS AcpiStatus;
- EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
- EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
- INTN Instance;
- EFI_ACPI_COMMON_HEADER *CurrentTable;
- UINTN TableHandle;
- UINT32 FvStatus;
- UINT32 Size;
- EFI_EVENT Event;
- EFI_ACPI_TABLE_VERSION TableVersion;
- EFI_HOB_GUID_TYPE *GuidHob;
-
- mFirstNotify = FALSE;
-
- TableVersion = EFI_ACPI_TABLE_VERSION_NONE;
- Instance = 0;
- CurrentTable = NULL;
- TableHandle = 0;
-
- //
- // Locate the IIO Protocol Interface
- //
- Status = gBS->LocateProtocol (&gEfiIioUdsProtocolGuid,NULL,&mIioUds);
- ASSERT_EFI_ERROR (Status);
-
- GuidHob = GetFirstGuidHob (&gEfiMemoryMapGuid);
- ASSERT (GuidHob != NULL);
- if (GuidHob == NULL) {
- return EFI_NOT_FOUND;
- }
- mSystemMemoryMap = GET_GUID_HOB_DATA(GuidHob);
-
- PlatformHookInit ();
-
- //
- // Find the AcpiTable protocol
- //
- Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, &AcpiTable);
- ASSERT_EFI_ERROR (Status);
-
- //
- // Locate the firmware volume protocol
- //
- Status = LocateSupportProtocol (
- &gEfiFirmwareVolume2ProtocolGuid,
- &gEfiCallerIdGuid,
- &FwVol,
- TRUE
- );
- ASSERT_EFI_ERROR (Status);
-
- Status = EFI_SUCCESS;
- Instance = 0;
-
- //
- // Read tables from the storage file.
- //
- while (!EFI_ERROR (Status)) {
- CurrentTable = NULL;
-
- Status = FwVol->ReadSection (
- FwVol,
- &gEfiCallerIdGuid,
- EFI_SECTION_RAW,
- Instance,
- &CurrentTable,
- (UINTN *) &Size,
- &FvStatus
- );
-
- if (!EFI_ERROR (Status)) {
- //
- // Allow platform specific code to reject the table or update it
- //
- {
- //
- // Perform any table specific updates.
- //
- AcpiStatus = PlatformUpdateTables (CurrentTable, &TableVersion);
- if (!EFI_ERROR (AcpiStatus)) {
- //
- // Add the table
- //
- TableHandle = 0;
- if (TableVersion != EFI_ACPI_TABLE_VERSION_NONE) {
- AcpiStatus = AcpiTable->InstallAcpiTable (
- AcpiTable,
- CurrentTable,
- CurrentTable->Length,
- &TableHandle
- );
- }
- ASSERT_EFI_ERROR (AcpiStatus);
- }
- }
- //
- // Increment the instance
- //
- Instance++;
- }
- }
-
- Status = EfiCreateEventReadyToBootEx(
- TPL_NOTIFY,
- OnReadyToBoot,
- NULL,
- &Event
- );
-
- //
- // Finished
- //
- return EFI_SUCCESS;
-}
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxeDsdt.c b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxeDsdt.c
deleted file mode 100644
index a4d58cab60..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxeDsdt.c
+++ /dev/null
@@ -1,516 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-//
-// Statements that include other files
-//
-
-//
-// Statements that include other header files
-//
-#include <Library/PcdLib.h>
-#include <Library/IoLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/DevicePathLib.h>
-#include <Library/PcdLib.h>
-
-#include <Guid/MemoryMapData.h>
-#include <Guid/GlobalVariable.h>
-
-#include <IndustryStandard/HighPrecisionEventTimerTable.h>
-
-#include <Platform.h>
-#include <Acpi/GlobalNvsAreaDef.h>
-#include <Protocol/IioUds.h>
-#include <Protocol/CpuIo2.h>
-#include <Protocol/SerialIo.h>
-#include <Protocol/DevicePath.h>
-#include <IndustryStandard/Acpi.h>
-#include <IndustryStandard/HighPrecisionEventTimerTable.h>
-#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
-#include <IndustryStandard/AcpiAml.h>
-
-#include <Guid/SocketMpLinkVariable.h>
-#include <Guid/SocketIioVariable.h>
-#include <Guid/SocketPowermanagementVariable.h>
-#include <Guid/SocketCommonRcVariable.h>
-
-#include "Register/PchRegsUsb.h"
-
-#include <PiDxe.h>
-#include <Uefi/UefiBaseType.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiRuntimeServicesTableLib.h>
-#include <Library/UefiLib.h>
-#include <Library/DebugLib.h>
-#include <Library/HobLib.h>
-
-#include <IndustryStandard/Acpi.h>
-
-#include <Protocol/MpService.h>
-
-#include <Protocol/AcpiSystemDescriptionTable.h>
-
-extern BOOLEAN mCpuOrderSorted;
-
-typedef struct {
- char *Pathname; /* Full pathname (from root) to the object */
- unsigned short ParentOpcode; /* AML opcode for the parent object */
- unsigned long NamesegOffset; /* Offset of last nameseg in the parent namepath */
- unsigned char Opcode; /* AML opcode for the data */
- unsigned long Offset; /* Offset for the data */
- unsigned long long Value; /* Original value of the data (as applicable) */
-} AML_OFFSET_TABLE_ENTRY;
-
-extern AML_OFFSET_TABLE_ENTRY *mAmlOffsetTablePointer;
-extern AML_OFFSET_TABLE_ENTRY DSDT_PLATWFP__OffsetTable[];
-
-#define AML_NAME_OP 0x08
-#define AML_NAME_PREFIX_SIZE 0x06
-#define AML_NAME_DWORD_SIZE 0x0C
-
-#define MEM_ADDR_SHFT_VAL 26 // For 64 MB granularity
-
-#pragma pack(1)
-
-typedef struct {
- UINT8 DescriptorType;
- UINT16 ResourceLength;
- UINT8 ResourceType;
- UINT8 Flags;
- UINT8 SpecificFlags;
- UINT64 Granularity;
- UINT64 Minimum;
- UINT64 Maximum;
- UINT64 TranslationOffset;
- UINT64 AddressLength;
-} AML_RESOURCE_ADDRESS64;
-
-
-typedef struct {
- UINT8 DescriptorType;
- UINT16 ResourceLength;
- UINT8 ResourceType;
- UINT8 Flags;
- UINT8 SpecificFlags;
- UINT32 Granularity;
- UINT32 Minimum;
- UINT32 Maximum;
- UINT32 TranslationOffset;
- UINT32 AddressLength;
-} AML_RESOURCE_ADDRESS32;
-
-
-typedef struct {
- UINT8 DescriptorType;
- UINT16 ResourceLength;
- UINT8 ResourceType;
- UINT8 Flags;
- UINT8 SpecificFlags;
- UINT16 Granularity;
- UINT16 Minimum;
- UINT16 Maximum;
- UINT16 TranslationOffset;
- UINT16 AddressLength;
-} AML_RESOURCE_ADDRESS16;
-
-#pragma pack()
-
-#define PCIE_PORT_4_DEV 0x00
-#define PCIE_PORT_5_DEV 0x00
-
-#define PORTS_PER_SOCKET 0x0F
-#define PCIE_PORT_ALL_FUNC 0x00
-
-typedef struct _PCIE_PORT_INFO {
- UINT8 Device;
- UINT8 Stack;
-} PCIE_PORT_INFO;
-
-#pragma optimize("",off)
-
-extern BIOS_ACPI_PARAM *mAcpiParameter;
-
-extern struct SystemMemoryMapHob *mSystemMemoryMap;
-extern EFI_IIO_UDS_PROTOCOL *mIioUds;
-
-
-extern SOCKET_MP_LINK_CONFIGURATION mSocketMpLinkConfiguration;
-extern SOCKET_IIO_CONFIGURATION mSocketIioConfiguration;
-extern SOCKET_POWERMANAGEMENT_CONFIGURATION mSocketPowermanagementConfiguration;
-
-extern UINT32 mNumOfBitShift;
-
-AML_OFFSET_TABLE_ENTRY *mAmlOffsetTablePointer = DSDT_PLATWFP__OffsetTable;
-
-/**
-
- Update the DSDT table
-
- @param *TableHeader - The table to be set
-
- @retval EFI_SUCCESS - DSDT updated
- @retval EFI_INVALID_PARAMETER - DSDT not updated
-
-**/
-EFI_STATUS
-PatchDsdtTable (
- IN OUT EFI_ACPI_COMMON_HEADER *Table
- )
-{
- PCIE_PORT_INFO PCIEPortDefaults[] = {
- // DMI/PCIE 0
- { PCIE_PORT_0_DEV, IIO_CSTACK },
- //IOU0
- { PCIE_PORT_1A_DEV, IIO_PSTACK0 },
- { PCIE_PORT_1B_DEV, IIO_PSTACK0 },
- { PCIE_PORT_1C_DEV, IIO_PSTACK0 },
- { PCIE_PORT_1D_DEV, IIO_PSTACK0 },
- //IOU1
- { PCIE_PORT_2A_DEV, IIO_PSTACK1 },
- { PCIE_PORT_2B_DEV, IIO_PSTACK1 },
- { PCIE_PORT_2C_DEV, IIO_PSTACK1 },
- { PCIE_PORT_2D_DEV, IIO_PSTACK1 },
- //IOU2
- { PCIE_PORT_3A_DEV, IIO_PSTACK2 },
- { PCIE_PORT_3B_DEV, IIO_PSTACK2 },
- { PCIE_PORT_3C_DEV, IIO_PSTACK2 },
- { PCIE_PORT_3D_DEV, IIO_PSTACK2 },
- //MCP0 and MCP1
- { PCIE_PORT_4_DEV, IIO_PSTACK3 },
- { PCIE_PORT_5_DEV, IIO_PSTACK4 }
- };
- EFI_STATUS Status;
- UINT8 *DsdtPointer;
- UINT32 *Signature;
- UINT32 Fixes, NodeIndex;
- UINT8 Counter;
- UINT16 i; // DSDT_PLATEXRP_OffsetTable LUT entries extends beyond 256!
- UINT64 MemoryBaseLimit = 0;
- UINT64 PciHGPEAddr = 0;
- UINT64 BusDevFunc = 0;
- UINT64 PcieHpBus = 0;
- UINT64 PcieHpDev = 0;
- UINT64 PcieHpFunc= 0;
- UINT8 PortCount = 0;
- UINT8 StackNumBus = 0;
- UINT8 StackNumIo = 0;
- UINT8 StackNumMem32 = 0;
- UINT8 StackNumMem64 = 0;
- UINT8 StackNumVgaIo0 = 1; // Start looking for Stack 1
- UINT8 StackNumVgaIo1 = 1; // Start looking for Stack 1
- UINT8 StackNumVgaMmioL = 0;
- UINT8 Stack = 0;
- UINT8 CurrSkt = 0, CurrStack = 0;
- UINT64 IioBusIndex = 0;
- UINT8 BusBase = 0, BusLimit = 0;
- UINT16 IoBase = 0, IoLimit = 0;
- UINT32 MemBase32 = 0, MemLimit32 = 0;
- UINT64 MemBase64 = 0, MemLimit64 = 0;
- AML_RESOURCE_ADDRESS16 *AmlResourceAddress16Pointer;
- AML_RESOURCE_ADDRESS32 *AmlResourceAddress32Pointer;
- AML_RESOURCE_ADDRESS64 *AmlResourceAddress64Pointer;
- EFI_ACPI_DESCRIPTION_HEADER *TableHeader;
-
- Status = EFI_SUCCESS;
- TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *)Table;
-
- if (mAmlOffsetTablePointer == NULL) return EFI_INVALID_PARAMETER;
-
- mAcpiParameter->MemoryBoardBitMask = 0;
-
- for(Counter = 0; Counter < mSystemMemoryMap->numberEntries; Counter++) {
- NodeIndex = mSystemMemoryMap->Element[Counter].NodeId;
- if((mAcpiParameter->MemoryBoardBitMask) & (1 << NodeIndex)){
- MemoryBaseLimit = mAcpiParameter->MemoryBoardRange[NodeIndex] + LShiftU64(mSystemMemoryMap->Element[Counter].ElementSize, MEM_ADDR_SHFT_VAL);
- mAcpiParameter->MemoryBoardRange[NodeIndex] = MemoryBaseLimit;
- } else {
- mAcpiParameter->MemoryBoardBitMask |= 1 << NodeIndex;
- MemoryBaseLimit = LShiftU64(mSystemMemoryMap->Element[Counter].BaseAddress, 30);
- mAcpiParameter->MemoryBoardBase[NodeIndex] = MemoryBaseLimit;
- MemoryBaseLimit = LShiftU64((mSystemMemoryMap->Element[Counter].BaseAddress + mSystemMemoryMap->Element[Counter].ElementSize), MEM_ADDR_SHFT_VAL);
- mAcpiParameter->MemoryBoardRange[NodeIndex] = MemoryBaseLimit;
- }
- }
-
- //
- // Mark all spare memory controllers as 1 in MemSpareMask bitmap.
- //
- mAcpiParameter->MemSpareMask = ~mAcpiParameter->MemoryBoardBitMask;
-
- mAcpiParameter->IioPresentBitMask = 0;
- mAcpiParameter->SocketBitMask = 0;
-
- for (Counter = 0; Counter < MAX_SOCKET; Counter++) {
- if (!mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Counter].Valid) continue;
- mAcpiParameter->SocketBitMask |= 1 << Counter;
- mAcpiParameter->IioPresentBitMask |= LShiftU64(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Counter].stackPresentBitmap, (Counter * 8));
- for (Stack = 0; Stack < MAX_IIO_STACK; Stack++) {
- mAcpiParameter->BusBase[Counter * MAX_IIO_STACK + Stack] = mIioUds->IioUdsPtr->PlatformData.IIO_resource[Counter].StackRes[Stack].BusBase;
- }
- }
-
- PciHGPEAddr = mIioUds->IioUdsPtr->PlatformData.PciExpressBase + 0x188;
- BusDevFunc = 0x00;
- PcieHpBus = 0;
- PcieHpDev = 0;
- PcieHpFunc = 0;
-
- Fixes = 0;
- //
- // Loop through the AML looking for values that we must fix up.
- //
- for (i = 0; mAmlOffsetTablePointer[i].Pathname != 0; i++) {
- //
- // Point to offset in DSDT for current item in AmlOffsetTable.
- //
- DsdtPointer = (UINT8 *) (TableHeader) + mAmlOffsetTablePointer[i].Offset;
-
- if (mAmlOffsetTablePointer[i].Opcode == AML_DWORD_PREFIX) {
- //
- // If Opcode is 0x0C, then operator is Name() or OperationRegion().
- // (TableHeader + AmlOffsetTable.Offset) is at offset for value to change.
- //
- // The assert below confirms that AML structure matches the offsets table.
- // If not then patching the AML would just corrupt it and result in OS failure.
- // If you encounter this assert something went wrong in *.offset.h files
- // generation. Remove the files and rebuild.
- //
- ASSERT(DsdtPointer[-1] == mAmlOffsetTablePointer[i].Opcode);
- //
- // AmlOffsetTable.Value has FIX tag, so check that to decide what to modify.
- //
- Signature = (UINT32 *) (&mAmlOffsetTablePointer[i].Value);
- switch (*Signature) {
- //
- // PSYS - "FIX0" OperationRegion() in Acpi\AcpiTables\Dsdt\CommonPlatform.asi
- //
- case (SIGNATURE_32 ('F', 'I', 'X', '0')):
- DEBUG ((DEBUG_INFO, "FIX0 - 0x%x\n", mAcpiParameter));
- * (UINT32 *) DsdtPointer = (UINT32) (UINTN) mAcpiParameter;
- //
- // "FIX8" OperationRegion() in Acpi\AcpiTables\Dsdt\PcieHp.asi
- //
- case (SIGNATURE_32 ('F', 'I', 'X', '8')):
- Stack = PCIEPortDefaults[PortCount % PORTS_PER_SOCKET].Stack;
- PcieHpBus = mIioUds->IioUdsPtr->PlatformData.IIO_resource[IioBusIndex].StackRes[Stack].BusBase;
- PcieHpDev = PCIEPortDefaults[PortCount % PORTS_PER_SOCKET].Device;
- PcieHpFunc = PCIE_PORT_ALL_FUNC;
-
- //DEBUG((DEBUG_ERROR,"IioBus = %x, hpDev = %x, HpFunc= %x\n",IioBusIndex, PcieHpDev,PcieHpFunc));
- PciHGPEAddr &= ~(0xFFFF000); // clear bus device func numbers
- BusDevFunc = (PcieHpBus << 8) | (PcieHpDev << 3) | PcieHpFunc;
- * (UINT32 *) DsdtPointer = (UINT32) (UINTN) (PciHGPEAddr + (BusDevFunc << 12));
- //DEBUG((DEBUG_ERROR,", BusDevFunc= %x, PortCount = %x\n",BusDevFunc, PortCount));
-
- PortCount++;
- Fixes++;
- break;
-
- default:
- break;
- }
- } else if (mAmlOffsetTablePointer[i].Opcode == AML_INDEX_OP) {
- //
- // If Opcode is 0x88, then operator is WORDBusNumber() or WORDIO().
- // (TableHeader + AmlOffsetTable.Offset) must be cast to AML_RESOURCE_ADDRESS16 to change values.
- //
- AmlResourceAddress16Pointer = (AML_RESOURCE_ADDRESS16 *) (DsdtPointer);
- //
- // The assert below confirms that AML structure matches the offsets table.
- // If not then patching the AML would just corrupt it and result in OS failure.
- // If you encounter this assert something went wrong in *.offset.h files
- // generation. Remove the files and rebuild.
- //
- ASSERT(AmlResourceAddress16Pointer->DescriptorType == mAmlOffsetTablePointer[i].Opcode);
-
- //
- // Last 4 chars of AmlOffsetTable.Pathname has FIX tag.
- //
- Signature = (UINT32 *) (mAmlOffsetTablePointer[i].Pathname + AsciiStrLen(mAmlOffsetTablePointer[i].Pathname) - 4);
- switch (*Signature) {
- //
- // "FIX1" BUS resource for PCXX in Acpi\AcpiTables\Dsdt\SysBus.asi and PCXX.asi
- //
- case (SIGNATURE_32 ('F', 'I', 'X', '1')):
- CurrSkt = StackNumBus / MAX_IIO_STACK;
- CurrStack = StackNumBus % MAX_IIO_STACK;
- BusBase = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].BusBase;
- BusLimit = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].BusLimit;
- AmlResourceAddress16Pointer->Granularity = 0;
- if (BusLimit > BusBase) {
- AmlResourceAddress16Pointer->Minimum = (UINT16) BusBase;
- AmlResourceAddress16Pointer->Maximum = (UINT16) BusLimit;
- AmlResourceAddress16Pointer->AddressLength = (UINT16) (BusLimit - BusBase + 1);
- }
- //DEBUG((DEBUG_ERROR,", FIX1 BusBase = 0x%x, BusLimit = 0x%x\n",BusBase, BusLimit));
- StackNumBus++;
- Fixes++;
- break;
-
- //
- // "FIX2" IO resource for for PCXX in Acpi\AcpiTables\Dsdt\SysBus.asi and PCXX.asi
- //
- case (SIGNATURE_32 ('F', 'I', 'X', '2')):
- AmlResourceAddress16Pointer->Granularity = 0;
- CurrSkt = StackNumIo / MAX_IIO_STACK;
- CurrStack = StackNumIo % MAX_IIO_STACK;
- IoBase = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].PciResourceIoBase;
- IoLimit = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].PciResourceIoLimit;
- if (IoLimit > IoBase) {
- AmlResourceAddress16Pointer->Minimum = (UINT16) IoBase;
- AmlResourceAddress16Pointer->Maximum = (UINT16) IoLimit;
- AmlResourceAddress16Pointer->AddressLength = (UINT16) (IoLimit - IoBase + 1);
- }
- //DEBUG((DEBUG_ERROR,", FIX2 IoBase = 0x%x, IoLimit = 0x%x\n",IoBase, IoLimit));
- StackNumIo++;
- Fixes++;
- break;
-
- //
- // "FIX6" IO resource for PCXX in Acpi\AcpiTables\Dsdt\PCXX.asi
- //
- case (SIGNATURE_32 ('F', 'I', 'X', '6')):
- AmlResourceAddress16Pointer->Granularity = 0;
- CurrSkt = StackNumVgaIo0 / MAX_IIO_STACK;
- CurrStack = StackNumVgaIo0 % MAX_IIO_STACK;
- if ((mSocketMpLinkConfiguration.LegacyVgaSoc == CurrSkt) &&
- (mSocketMpLinkConfiguration.LegacyVgaStack == CurrStack)){
- AmlResourceAddress16Pointer->Minimum = (UINT16) 0x03b0;
- AmlResourceAddress16Pointer->Maximum = (UINT16) 0x03bb;
- AmlResourceAddress16Pointer->AddressLength = (UINT16) 0x000C;
- }
- StackNumVgaIo0++;
- Fixes++;
- break;
-
- //
- // "FIX7" IO resource for PCXX in Acpi\AcpiTables\Dsdt\PCXX.asi
- //
- case (SIGNATURE_32 ('F', 'I', 'X', '7')):
- AmlResourceAddress16Pointer->Granularity = 0;
- CurrSkt = StackNumVgaIo1 / MAX_IIO_STACK;
- CurrStack = StackNumVgaIo1 % MAX_IIO_STACK;
- if ((mSocketMpLinkConfiguration.LegacyVgaSoc == CurrSkt) &&
- (mSocketMpLinkConfiguration.LegacyVgaStack == CurrStack)) {
- AmlResourceAddress16Pointer->Minimum = (UINT16) 0x03c0;
- AmlResourceAddress16Pointer->Maximum = (UINT16) 0x03df;
- AmlResourceAddress16Pointer->AddressLength = (UINT16) 0x0020;
- }
- StackNumVgaIo1++;
- Fixes++;
- break;
-
- default:
- break;
- }
- } else if (mAmlOffsetTablePointer[i].Opcode == AML_SIZE_OF_OP) {
- //
- // If Opcode is 0x87, then operator is DWORDMemory().
- // (TableHeader + AmlOffsetTable.Offset) must be cast to AML_RESOURCE_ADDRESS32 to change values.
- //
- AmlResourceAddress32Pointer = (AML_RESOURCE_ADDRESS32 *) (DsdtPointer);
- //
- // The assert below confirms that AML structure matches the offsets table.
- // If not then patching the AML would just corrupt it and result in OS failure.
- // If you encounter this assert something went wrong in *.offset.h files
- // generation. Remove the files and rebuild.
- //
- ASSERT(AmlResourceAddress32Pointer->DescriptorType == mAmlOffsetTablePointer[i].Opcode);
- //
- // Last 4 chars of AmlOffsetTable.Pathname has FIX tag.
- //
- Signature = (UINT32 *) (mAmlOffsetTablePointer[i].Pathname + AsciiStrLen(mAmlOffsetTablePointer[i].Pathname) - 4);
- switch (*Signature) {
- //
- // "FIX3" PCI32 resource for PCXX in Acpi\AcpiTables\Dsdt\SysBus.asi and PCXX.asi
- //
- case (SIGNATURE_32 ('F', 'I', 'X', '3')):
- AmlResourceAddress32Pointer->Granularity = 0;
- CurrSkt = StackNumMem32 / MAX_IIO_STACK;
- CurrStack = StackNumMem32 % MAX_IIO_STACK;
- MemBase32 = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].PciResourceMem32Base;
- MemLimit32 = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].PciResourceMem32Limit;
- if (MemLimit32 > MemBase32) {
- AmlResourceAddress32Pointer->Minimum = (UINT32) MemBase32;
- AmlResourceAddress32Pointer->Maximum = (UINT32) MemLimit32;
- AmlResourceAddress32Pointer->AddressLength = (UINT32) (MemLimit32 - MemBase32 + 1);
- }
- //DEBUG((DEBUG_ERROR,", FIX3 MemBase32 = 0x%08x, MemLimit32 = 0x%08x\n",MemBase32, MemLimit32));
- StackNumMem32++;
- Fixes++;
- break;
-
- //
- // "FIX5" IO resource for PCXX in Acpi\AcpiTables\Dsdt\PCXX.asi
- //
- case (SIGNATURE_32 ('F', 'I', 'X', '5')):
- AmlResourceAddress32Pointer->Granularity = 0;
- CurrSkt = StackNumVgaMmioL / MAX_IIO_STACK;
- CurrStack = StackNumVgaMmioL % MAX_IIO_STACK;
- if ((mSocketMpLinkConfiguration.LegacyVgaSoc == CurrSkt) &&
- (mSocketMpLinkConfiguration.LegacyVgaStack == CurrStack)) {
- AmlResourceAddress32Pointer->Minimum = 0x000a0000;
- AmlResourceAddress32Pointer->Maximum = 0x000bffff;
- AmlResourceAddress32Pointer->AddressLength = 0x00020000;
- }
- StackNumVgaMmioL++;
- Fixes++;
- break;
-
- default:
- break;
- }
- } else if (mAmlOffsetTablePointer[i].Opcode == AML_CREATE_DWORD_FIELD_OP) {
- //
- // If Opcode is 0x8A, then operator is QWORDMemory().
- // (TableHeader + AmlOffsetTable.Offset) must be cast to AML_RESOURCE_ADDRESS64 to change values.
- //
- AmlResourceAddress64Pointer = (AML_RESOURCE_ADDRESS64 *) (DsdtPointer);
- //
- // The assert below confirms that AML structure matches the offsets table.
- // If not then patching the AML would just corrupt it and result in OS failure.
- // If you encounter this assert something went wrong in *.offset.h files
- // generation. Remove the files and rebuild.
- //
- ASSERT(AmlResourceAddress64Pointer->DescriptorType == mAmlOffsetTablePointer[i].Opcode);
- //
- // Last 4 chars of AmlOffsetTable.Pathname has FIX tag.
- //
- Signature = (UINT32 *) (mAmlOffsetTablePointer[i].Pathname + AsciiStrLen(mAmlOffsetTablePointer[i].Pathname) - 4);
- switch (*Signature) {
- //
- // "FIX4" PCI64 resource for PCXX in Acpi\AcpiTables\Dsdt\SysBus.asi and PCXX.asi
- //
- case (SIGNATURE_32 ('F', 'I', 'X', '4')):
- DEBUG((DEBUG_ERROR,"Pci64BitResourceAllocation = 0x%x\n",mSocketIioConfiguration.Pci64BitResourceAllocation));
- if (mSocketIioConfiguration.Pci64BitResourceAllocation) {
- AmlResourceAddress64Pointer->Granularity = 0;
- CurrSkt = StackNumMem64 / MAX_IIO_STACK;
- CurrStack = StackNumMem64 % MAX_IIO_STACK;
- MemBase64 = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].PciResourceMem64Base;
- MemLimit64 = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].PciResourceMem64Limit;
- if (MemLimit64 > MemBase64) {
- AmlResourceAddress64Pointer->Minimum = (UINT64) MemBase64;
- AmlResourceAddress64Pointer->Maximum = (UINT64) MemLimit64;
- AmlResourceAddress64Pointer->AddressLength = (UINT64) (MemLimit64 - MemBase64 + 1);
- }
- DEBUG((DEBUG_ERROR,", FIX4 MemBase64 = 0x%x, MemLimit64 = 0x%x\n",MemBase64, MemLimit64));
- StackNumMem64++;
- Fixes++;
- }
- break;
- default:
- break;
- }
- }
- }
-
- //return Status;
- return EFI_SUCCESS;
-
-}
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl
deleted file mode 100644
index b76b062a94..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl
+++ /dev/null
@@ -1,19 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-
-///////////////////////////////////////////////////////////////////////////////////
-//Values are set like this to have ASL compiler reserve enough space for objects
-///////////////////////////////////////////////////////////////////////////////////
-//
-// Available Sleep states
-//
-Name(SS1,0)
-Name(SS2,0)
-Name(SS3,1)
-Name(SS4,1)
-
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.asl
deleted file mode 100644
index 55b4c11741..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.asl
+++ /dev/null
@@ -1,77 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-
-// Comment out includes as ifdefs don't work at trim stage
-
-//
-//
-
-Scope(\_SB) {
- //
- //---------------------------------------------------------------------------
- // List of IRQ resource buffers compatible with _PRS return format.
- //---------------------------------------------------------------------------
- // Naming legend:
- // RSxy, PRSy - name of the IRQ resource buffer to be returned by _PRS, "xy" - last two characters of IRQ Link name.
- // Note. PRSy name is generated if IRQ Link name starts from "LNK".
- // HLxy , LLxy - reference names, can be used to access bit mask of available IRQs. HL and LL stand for active High(Low) Level triggered Irq model.
- //---------------------------------------------------------------------------
- Name(PRSA, ResourceTemplate(){ // Link name: LNKA
- IRQ(Level, ActiveLow, Shared, LLKA) {3,4,5,6,10,11,12,14,15}
- })
- Alias(PRSA,PRSB) // Link name: LNKB
- Alias(PRSA,PRSC) // Link name: LNKC
- Alias(PRSA,PRSD) // Link name: LNKD
- Alias(PRSA,PRSE) // Link name: LNKE
- Alias(PRSA,PRSF) // Link name: LNKF
- Alias(PRSA,PRSG) // Link name: LNKG
- Alias(PRSA,PRSH) // Link name: LNKH
-}
-
-//
-//
-
- Scope(\_SB.PC00) {
- //
- // PCI-specific method's GUID
- //
- Name(PCIG, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))
- //
- // PCI's _DSM - an attempt at modular _DSM implementation
- // When writing your own _DSM function that needs to include PCI-specific methods, do this:
- //
- // Method(_YOUR_DSM,4){
- // if(Lequal(Arg0,PCIG)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }
- // ...continue your _DSM by checking different GUIDs...
- // else { return(0) }
- // }
- //
- Method(PCID, 4, Serialized) {
- If(LEqual(Arg0, PCIG)) { // PCIE capabilities UUID
- If(LGreaterEqual(Arg1,3)) { // revision at least 3
- If(LEqual(Arg2,0)) { Return (Buffer(2){0x01,0x03}) } // function 0: list of supported functions
- If(LEqual(Arg2,8)) { Return (1) } // function 8: Avoiding Power-On Reset Delay Duplication on Sx Resume
- If(LEqual(Arg2,9)) { Return (Package(5){50000,Ones,Ones,50000,Ones}) } // function 9: Specifying Device Readiness Durations
- }
- }
- return (Buffer(1){0})
- }
- }//scope
-Scope(\_SB.PC00) {
- //PciCheck, Arg0=UUID, returns true if support for 'PCI delays optimization ECR' is enabled and the UUID is correct
- Method(PCIC,1,Serialized) {
- If(LEqual(ECR1,1)) {
- If(LEqual(Arg0, PCIG)) {
- return (1)
- }
- }
- return (0)
- }
-}
-
-
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl
deleted file mode 100644
index 97a3ba0eb3..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl
+++ /dev/null
@@ -1,134 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
- // General Purpose Events. This Scope handles the Run-time and
- // Wake-time SCIs. The specific method called will be determined by
- // the _Lxx value, where xx equals the bit location in the General
- // Purpose Event register(s).
-
- //
- // If the Root Port is enabled, run PCI_EXP_STS handler
- //
- If(LNotEqual(\_SB.PC00.RP01.VDID,0xFFFFFFFF))
- {
- \_SB.PC00.RP01.HPME()
- Notify(\_SB.PC00.RP01, 0x02)
- }
-
- If(LNotEqual(\_SB.PC00.RP02.VDID,0xFFFFFFFF))
- {
- \_SB.PC00.RP02.HPME()
- Notify(\_SB.PC00.RP02, 0x02)
- }
-
- If(LNotEqual(\_SB.PC00.RP03.VDID,0xFFFFFFFF))
- {
- \_SB.PC00.RP03.HPME()
- Notify(\_SB.PC00.RP03, 0x02)
- }
-
- If(LNotEqual(\_SB.PC00.RP04.VDID,0xFFFFFFFF))
- {
- \_SB.PC00.RP04.HPME()
- Notify(\_SB.PC00.RP04, 0x02)
- }
-
- If(LNotEqual(\_SB.PC00.RP05.VDID,0xFFFFFFFF))
- {
- \_SB.PC00.RP05.HPME()
- Notify(\_SB.PC00.RP05, 0x02)
- }
-
- If(LNotEqual(\_SB.PC00.RP06.VDID,0xFFFFFFFF))
- {
- \_SB.PC00.RP06.HPME()
- Notify(\_SB.PC00.RP06, 0x02)
- }
-
- If(LNotEqual(\_SB.PC00.RP07.VDID,0xFFFFFFFF))
- {
- \_SB.PC00.RP07.HPME()
- Notify(\_SB.PC00.RP07, 0x02)
- }
-
- If(LNotEqual(\_SB.PC00.RP08.VDID,0xFFFFFFFF))
- {
- \_SB.PC00.RP08.HPME()
- Notify(\_SB.PC00.RP08, 0x02)
- }
-
- If(LNotEqual(\_SB.PC00.RP09.VDID,0xFFFFFFFF))
- {
- \_SB.PC00.RP09.HPME()
- Notify(\_SB.PC00.RP09, 0x02)
- }
-
- If(LNotEqual(\_SB.PC00.RP10.VDID,0xFFFFFFFF))
- {
- \_SB.PC00.RP10.HPME()
- Notify(\_SB.PC00.RP10, 0x02)
- }
-
- If(LNotEqual(\_SB.PC00.RP11.VDID,0xFFFFFFFF))
- {
- \_SB.PC00.RP11.HPME()
- Notify(\_SB.PC00.RP11, 0x02)
- }
-
- If(LNotEqual(\_SB.PC00.RP12.VDID,0xFFFFFFFF))
- {
- \_SB.PC00.RP12.HPME()
- Notify(\_SB.PC00.RP12, 0x02)
- }
-
- If(LNotEqual(\_SB.PC00.RP13.VDID,0xFFFFFFFF))
- {
- \_SB.PC00.RP13.HPME()
- Notify(\_SB.PC00.RP13, 0x02)
- }
-
- If(LNotEqual(\_SB.PC00.RP14.VDID,0xFFFFFFFF))
- {
- \_SB.PC00.RP14.HPME()
- Notify(\_SB.PC00.RP14, 0x02)
- }
-
- If(LNotEqual(\_SB.PC00.RP15.VDID,0xFFFFFFFF))
- {
- \_SB.PC00.RP15.HPME()
- Notify(\_SB.PC00.RP15, 0x02)
- }
-
- If(LNotEqual(\_SB.PC00.RP16.VDID,0xFFFFFFFF))
- {
- \_SB.PC00.RP16.HPME()
- Notify(\_SB.PC00.RP16, 0x02)
- }
-
- If(LNotEqual(\_SB.PC00.RP17.VDID,0xFFFFFFFF))
- {
- \_SB.PC00.RP17.HPME()
- Notify(\_SB.PC00.RP17, 0x02)
- }
-
- If(LNotEqual(\_SB.PC00.RP18.VDID,0xFFFFFFFF))
- {
- \_SB.PC00.RP18.HPME()
- Notify(\_SB.PC00.RP18, 0x02)
- }
-
- If(LNotEqual(\_SB.PC00.RP19.VDID,0xFFFFFFFF))
- {
- \_SB.PC00.RP19.HPME()
- Notify(\_SB.PC00.RP19, 0x02)
- }
-
- If(LNotEqual(\_SB.PC00.RP20.VDID,0xFFFFFFFF))
- {
- \_SB.PC00.RP20.HPME()
- Notify(\_SB.PC00.RP20, 0x02)
- }
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/HostBus.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/HostBus.asl
deleted file mode 100644
index daf80171a1..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/HostBus.asl
+++ /dev/null
@@ -1,256 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-//
-// Define various System Agent (SA) PCI Configuration Space
-// registers which will be used to dynamically produce all
-// resources in the Host Bus _CRS.
-//
-OperationRegion (HBUS, PCI_Config, 0x00, 0x100)
-Field (HBUS, DWordAcc, NoLock, Preserve)
-{
- Offset(0x40), // EPBAR (0:0:0:40)
- EPEN, 1, // Enable
- , 11,
- EPBR, 20, // EPBAR [31:12]
-
- Offset(0x48), // MCHBAR (0:0:0:48)
- MHEN, 1, // Enable
- , 14,
- MHBR, 17, // MCHBAR [31:15]
-
- Offset(0x50), // GGC (0:0:0:50)
- GCLK, 1, // GGCLCK
-
- Offset(0x54), // DEVEN (0:0:0:54)
- D0EN, 1, // DEV0 Enable
- D1F2, 1, // DEV1 FUN2 Enable
- D1F1, 1, // DEV1 FUN1 Enable
- D1F0, 1, // DEV1 FUN0 Enable
-
- Offset(0x60), // PCIEXBAR (0:0:0:60)
- PXEN, 1, // Enable
- PXSZ, 2, // PCI Express Size
- , 23,
- PXBR, 6, // PCI Express BAR [31:26]
-
- Offset(0x68), // DMIBAR (0:0:0:68)
- DIEN, 1, // Enable
- , 11,
- DIBR, 20, // DMIBAR [31:12]
-
- Offset(0x70), // MESEG_BASE (0:0:0:70)
- , 20,
- MEBR, 12, // MESEG_BASE [31:20]
-
- Offset(0x80), // PAM0 Register (0:0:0:80)
- , 4,
- PM0H, 2, // PAM 0, High Nibble
- , 2,
-
- Offset(0x81), // PAM1 Register (0:0:0:81)
- PM1L, 2, // PAM1, Low Nibble
- , 2,
- PM1H, 2, // PAM1, High Nibble
- , 2,
-
- Offset(0x82), // PAM2 Register (0:0:0:82)
- PM2L, 2, // PAM2, Low Nibble
- , 2,
- PM2H, 2, // PAM2, High Nibble
- , 2,
-
- Offset(0x83), // PAM3 Register (0:0:0:83)
- PM3L, 2, // PAM3, Low Nibble
- , 2,
- PM3H, 2, // PAM3, High Nibble
- , 2,
-
- Offset(0x84), // PAM4 Register (0:0:0:84)
- PM4L, 2, // PAM4, Low Nibble
- , 2,
- PM4H, 2, // PAM4, High Nibble
- , 2,
-
- Offset(0x85), // PAM5 Register (0:0:0:85)
- PM5L, 2, // PAM5, Low Nibble
- , 2,
- PM5H, 2, // PAM5, High Nibble
- , 2,
-
- Offset(0x86), // PAM6 Register (0:0:0:86)
- PM6L, 2, // PAM6, Low Nibble
- , 2,
- PM6H, 2, // PAM6, High Nibble
- , 2,
-
- Offset(0xA8), // Top of Upper Usable DRAM Register (0:0:0:A8)
- , 20,
- TUUD, 19, // TOUUD [38:20]
-
- Offset(0xBC), // Top of Lower Usable DRAM Register (0:0:0:BC)
- , 20,
- TLUD, 12, // TOLUD [31:20]
-
- Offset(0xC8), // ERRSTS register (0:0:0:C8)
- , 7,
- HTSE, 1 // Host Thermal Sensor Event for SMI/SCI/SERR
-}
-//
-// Define a buffer that will store all the bus, memory, and IO information
-// relating to the Host Bus. This buffer will be dynamically altered in
-// the _CRS and passed back to the OS.
-//
-Name(BUF0,ResourceTemplate()
-{
- //
- // Bus Number Allocation: Bus 0 to 0xFF
- //
- WORDBusNumber(ResourceProducer,MinFixed,MaxFixed,PosDecode,0x00,
- 0x0000,0x00FF,0x00,0x0100,,,PB00)
-
- //
- // I/O Region Allocation 0 ( 0x0000 - 0x0CF7 )
- //
- DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange,
- 0x00,0x0000,0x0CF7,0x00,0x0CF8,,,PI00)
-
- //
- // PCI Configuration Registers ( 0x0CF8 - 0x0CFF )
- //
- Io(Decode16,0x0CF8,0x0CF8,1,0x08)
-
- //
- // I/O Region Allocation 1 ( 0x0D00 - 0xFFFF )
- //
- DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange,
- 0x00,0x0D00,0xFFFF,0x00,0xF300,,,PI01)
-
- //
- // Video Buffer Area ( 0xA0000 - 0xBFFFF )
- //
- DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
- ReadWrite,0x00,0xA0000,0xBFFFF,0x00,0x20000,,,A000)
-
- //
- // ISA Add-on BIOS Area ( 0xC0000 - 0xC3FFF )
- //
- DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
- ReadWrite,0x00,0xC0000,0xC3FFF,0x00,0x4000,,,C000)
-
- //
- // ISA Add-on BIOS Area ( 0xC4000 - 0xC7FFF )
- //
- DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
- ReadWrite,0x00,0xC4000,0xC7FFF,0x00,0x4000,,,C400)
-
- //
- // ISA Add-on BIOS Area ( 0xC8000 - 0xCBFFF )
- //
- DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
- ReadWrite,0x00,0xC8000,0xCBFFF,0x00,0x4000,,,C800)
-
- //
- // ISA Add-on BIOS Area ( 0xCC000 - 0xCFFFF )
- //
- DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
- ReadWrite,0x00,0xCC000,0xCFFFF,0x00,0x4000,,,CC00)
-
- //
- // ISA Add-on BIOS Area ( 0xD0000 - 0xD3FFF )
- //
- DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
- ReadWrite,0x00,0xD0000,0xD3FFF,0x00,0x4000,,,D000)
-
- //
- // ISA Add-on BIOS Area ( 0xD4000 - 0xD7FFF )
- //
- DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
- ReadWrite,0x00,0xD4000,0xD7FFF,0x00,0x4000,,,D400)
-
- //
- // ISA Add-on BIOS Area ( 0xD8000 - 0xDBFFF )
- //
- DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
- ReadWrite,0x00,0xD8000,0xDBFFF,0x00,0x4000,,,D800)
-
- //
- // ISA Add-on BIOS Area ( 0xDC000 - 0xDFFFF )
- //
- DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
- ReadWrite,0x00,0xDC000,0xDFFFF,0x00,0x4000,,,DC00)
-
- //
- // BIOS Extension Area ( 0xE0000 - 0xE3FFF )
- //
- DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
- ReadWrite,0x00,0xE0000,0xE3FFF,0x00,0x4000,,,E000)
-
- //
- // BIOS Extension Area ( 0xE4000 - 0xE7FFF )
- //
- DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
- ReadWrite,0x00,0xE4000,0xE7FFF,0x00,0x4000,,,E400)
-
- //
- // BIOS Extension Area ( 0xE8000 - 0xEBFFF )
- //
- DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
- ReadWrite,0x00,0xE8000,0xEBFFF,0x00,0x4000,,,E800)
-
- //
- // BIOS Extension Area ( 0xEC000 - 0xEFFFF )
- //
- DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
- ReadWrite,0x00,0xEC000,0xEFFFF,0x00,0x4000,,,EC00)
-
- //
- // BIOS Area ( 0xF0000 - 0xFFFFF )
- //
- DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
- ReadWrite,0x00,0xF0000,0xFFFFF,0x00,0x10000,,,F000)
-
-// //
-// // Memory Hole Region ( 0xF00000 - 0xFFFFFF )
-// //
-// DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
-// ReadWrite,0x00,0xF00000,0xFFFFFF,0x00,0x100000,,,HOLE)
-
- //
- // PCI Memory Region ( TOLUD - 0xFEAFFFFF )
- //
- DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
- ReadWrite,0x00,0x00000000,0xFEAFFFFF,0x00,0xFEB00000,,,PM01)
-
- //
- // PCI Memory Region ( TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE) )
- // (This is dummy range for OS compatibility, will patch it in _CRS)
- //
- QWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
- ReadWrite,0x00,0x10000,0x1FFFF,0x00,0x10000,,,PM02)
-})
-
-Name(EP_B, 0) // to store EP BAR
-Name(MH_B, 0) // to store MCH BAR
-Name(PC_B, 0) // to store PCIe BAR
-Name(PC_L, 0) // to store PCIe BAR Length
-Name(DM_B, 0) // to store DMI BAR
-
-
-//
-// Get PCIe BAR
-//
-Method(GPCB,0,Serialized)
-{
- if(LEqual(PC_B,0))
- {
- //ShiftLeft(\_SB.PC00.PXBR,26,PC_B)
- Store(MCFG,PC_B)
- }
- Return(PC_B)
-}
-
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieHotPlugGpeHandler.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieHotPlugGpeHandler.asl
deleted file mode 100644
index 9631d8cee3..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieHotPlugGpeHandler.asl
+++ /dev/null
@@ -1,842 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
- //
- // Delay introduced as initial delay after entering ACPI hotplug method
- //
- Sleep (200)
- Store (0x01, IO80)
- Sleep (10)
- Store (0,Local1)
-
- // PC01 Port 1A PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC01.BR1A.PMEP,1) ) {
- Store(\_SB.PC01.BR1A.PMEH(1), Local0)
- } else {
- Store (\_SB.PC01.BR1A.HPEH(1), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(1, Local1)
- Notify(\_SB.PC01.BR1A, Local0)
- }
-
- // PC01 Port 1B PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC01.BR1B.PMEP,1) ) {
- Store(\_SB.PC01.BR1B.PMEH(2), Local0)
- } else {
- Store (\_SB.PC01.BR1B.HPEH(2), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(2, Local1)
- Notify(\_SB.PC01.BR1B, Local0)
- }
-
- // PC01 Port 1C PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC01.BR1C.PMEP,1) ) {
- Store(\_SB.PC01.BR1C.PMEH(3), Local0)
- } else {
- Store (\_SB.PC01.BR1C.HPEH(3), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(3, Local1)
- Notify(\_SB.PC01.BR1C, Local0)
- }
-
- // PC01 Port 1D PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC01.BR1D.PMEP,1) ) {
- Store(\_SB.PC01.BR1D.PMEH(4), Local0)
- } else {
- Store (\_SB.PC01.BR1D.HPEH(4), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(4, Local1)
- Notify(\_SB.PC01.BR1D, Local0)
- }
-
- // PC02 Port 2A PCI-Ex Hot Plug
- If( LEqual(\_SB.PC02.BR2A.PMEP,1) ) {
- Store(\_SB.PC02.BR2A.PMEH(5), Local0)
- } else {
- Store (\_SB.PC02.BR2A.HPEH(5), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(5, Local1)
- Notify(\_SB.PC02.BR2A, Local0)
- }
-
- // PC02 Port 2B PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC02.BR2B.PMEP,1) ) {
- Store(\_SB.PC02.BR2B.PMEH(6), Local0)
- } else {
- Store (\_SB.PC02.BR2B.HPEH(6), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(6, Local1)
- Notify(\_SB.PC02.BR2B, Local0)
- }
-
- // PC02 Port 2C PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC02.BR2C.PMEP,1) ) {
- Store(\_SB.PC02.BR2C.PMEH(7), Local0)
- } else {
- Store (\_SB.PC02.BR2C.HPEH(7), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(7, Local1)
- Notify(\_SB.PC02.BR2C, Local0)
- }
-
- // PC02 Port 2D PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC02.BR2D.PMEP,1) ) {
- Store(\_SB.PC02.BR2D.PMEH(8), Local0)
- } else {
- Store (\_SB.PC02.BR2D.HPEH(8), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(8, Local1)
- Notify(\_SB.PC02.BR2D, Local0)
- }
-
- // PC03 Port 3A PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC03.BR3A.PMEP,1) ) {
- Store(\_SB.PC03.BR3A.PMEH(9), Local0)
- } else {
- Store (\_SB.PC03.BR3A.HPEH(9), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(9, Local1)
- Notify(\_SB.PC03.BR3A, Local0)
- }
-
- // PC03 Port 3B PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC03.BR3B.PMEP,10) ) {
- Store(\_SB.PC03.BR3B.PMEH(10), Local0)
- } else {
- Store (\_SB.PC03.BR3B.HPEH(10), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(10, Local1)
- Notify(\_SB.PC03.BR3B, Local0)
- }
-
- // PC03 Port 3C PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC03.BR3C.PMEP,1) ) {
- Store(\_SB.PC03.BR3C.PMEH(11), Local0)
- } else {
- Store (\_SB.PC03.BR3C.HPEH(11), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(11, Local1)
- Notify(\_SB.PC03.BR3C, Local0)
- }
-
- // PC03 Port 3D PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC03.BR3D.PMEP,1) ) {
- Store(\_SB.PC03.BR3D.PMEH(12), Local0)
- } else {
- Store (\_SB.PC03.BR3D.HPEH(12), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(12, Local1)
- Notify(\_SB.PC03.BR3D, Local0)
- }
-
- // PC06 Port 0 PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC06.QRP0.PMEP,1) ) {
- Store(\_SB.PC06.QRP0.PMEH(1), Local0)
- } else {
- Store (\_SB.PC06.QRP0.HPEH(1), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(1, Local1)
- Notify(\_SB.PC06.QRP0, Local0)
- }
-
- // PC07 Port 1A PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC07.QR1A.PMEP,1) ) {
- Store(\_SB.PC07.QR1A.PMEH(1), Local0)
- } else {
- Store (\_SB.PC07.QR1A.HPEH(1), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(1, Local1)
- Notify(\_SB.PC07.QR1A, Local0)
- }
-
- // PC07 Port 1B PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC07.QR1B.PMEP,1) ) {
- Store(\_SB.PC07.QR1B.PMEH(2), Local0)
- } else {
- Store (\_SB.PC07.QR1B.HPEH(2), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(2, Local1)
- Notify(\_SB.PC07.QR1B, Local0)
- }
-
- // PC07 Port 1C PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC07.QR1C.PMEP,1) ) {
- Store(\_SB.PC07.QR1C.PMEH(3), Local0)
- } else {
- Store (\_SB.PC07.QR1C.HPEH(3), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(3, Local1)
- Notify(\_SB.PC07.QR1C, Local0)
- }
-
- // PC07 Port 1D PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC07.QR1D.PMEP,1) ) {
- Store(\_SB.PC07.QR1D.PMEH(4), Local0)
- } else {
- Store (\_SB.PC07.QR1D.HPEH(4), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(4, Local1)
- Notify(\_SB.PC07.QR1D, Local0)
- }
-
- // PC08 Port 2A PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC08.QR2A.PMEP,1) ) {
- Store(\_SB.PC08.QR2A.PMEH(5), Local0)
- } else {
- Store (\_SB.PC08.QR2A.HPEH(5), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(5, Local1)
- Notify(\_SB.PC08.QR2A, Local0)
- }
-
- // PC08 Port 2B PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC08.QR2B.PMEP,1) ) {
- Store(\_SB.PC08.QR2B.PMEH(6), Local0)
- } else {
- Store (\_SB.PC08.QR2B.HPEH(6), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(6, Local1)
- Notify(\_SB.PC08.QR2B, Local0)
- }
-
- // PC08 Port 2C PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC08.QR2C.PMEP,1) ) {
- Store(\_SB.PC08.QR2C.PMEH(7), Local0)
- } else {
- Store (\_SB.PC08.QR2C.HPEH(7), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(7, Local1)
- Notify(\_SB.PC08.QR2C, Local0)
- }
-
- // PC08 Port 2D PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC08.QR2D.PMEP,1) ) {
- Store(\_SB.PC08.QR2D.PMEH(8), Local0)
- } else {
- Store (\_SB.PC08.QR2D.HPEH(8), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(8, Local1)
- Notify(\_SB.PC08.QR2D, Local0)
- }
-
- // PC09 Port 3A PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC09.QR3A.PMEP,1) ) {
- Store(\_SB.PC09.QR3A.PMEH(9), Local0)
- } else {
- Store (\_SB.PC09.QR3A.HPEH(9), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(9, Local1)
- Notify(\_SB.PC09.QR3A, Local0)
- }
-
- // PC09 Port 3B PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC09.QR3B.PMEP,1) ) {
- Store(\_SB.PC09.QR3B.PMEH(10), Local0)
- } else {
- Store (\_SB.PC09.QR3B.HPEH(10), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(10, Local1)
- Notify(\_SB.PC09.QR3B, Local0)
- }
-
- // PC09 Port 3C PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC09.QR3C.PMEP,1) ) {
- Store(\_SB.PC09.QR3C.PMEH(11), Local0)
- } else {
- Store (\_SB.PC09.QR3C.HPEH(11), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(11, Local1)
- Notify(\_SB.PC09.QR3C, Local0)
- }
-
- // PC09 Port 3D PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC09.QR3D.PMEP,1) ) {
- Store(\_SB.PC09.QR3D.PMEH(12), Local0)
- } else {
- Store (\_SB.PC09.QR3D.HPEH(12), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(12, Local1)
- Notify(\_SB.PC09.QR3D, Local0)
- }
-
- // PC12 Port 0 PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC12.RRP0.PMEP,1) ) {
- Store(\_SB.PC12.RRP0.PMEH(1), Local0)
- } else {
- Store (\_SB.PC12.RRP0.HPEH(1), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(1, Local1)
- Notify(\_SB.PC12.RRP0, Local0)
- }
-
- // PC13 Port 1A PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC13.RR1A.PMEP,1) ) {
- Store(\_SB.PC13.RR1A.PMEH(1), Local0)
- } else {
- Store (\_SB.PC13.RR1A.HPEH(1), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(1, Local1)
- Notify(\_SB.PC13.RR1A, Local0)
- }
-
- // PC13 Port 1B PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC13.RR1B.PMEP,1) ) {
- Store(\_SB.PC13.RR1B.PMEH(2), Local0)
- } else {
- Store (\_SB.PC13.RR1B.HPEH(2), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(2, Local1)
- Notify(\_SB.PC13.RR1B, Local0)
- }
-
- // PC13 Port 1C PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC13.RR1C.PMEP,1) ) {
- Store(\_SB.PC13.RR1C.PMEH(3), Local0)
- } else {
- Store (\_SB.PC13.RR1C.HPEH(3), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(3, Local1)
- Notify(\_SB.PC13.RR1C, Local0)
- }
-
- // PC13 Port 1D PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC13.RR1D.PMEP,1) ) {
- Store(\_SB.PC13.RR1D.PMEH(4), Local0)
- } else {
- Store (\_SB.PC13.RR1D.HPEH(4), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(4, Local1)
- Notify(\_SB.PC13.RR1D, Local0)
- }
-
- // PC14 Port 2A PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC14.RR2A.PMEP,1) ) {
- Store(\_SB.PC14.RR2A.PMEH(5), Local0)
- } else {
- Store (\_SB.PC14.RR2A.HPEH(5), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(5, Local1)
- Notify(\_SB.PC14.RR2A, Local0)
- }
-
- // PC14 Port 2B PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC14.RR2B.PMEP,1) ) {
- Store(\_SB.PC14.RR2B.PMEH(6), Local0)
- } else {
- Store (\_SB.PC14.RR2B.HPEH(6), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(6, Local1)
- Notify(\_SB.PC14.RR2B, Local0)
- }
-
- // PC14 Port 2C PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC14.RR2C.PMEP,1) ) {
- Store(\_SB.PC14.RR2C.PMEH(7), Local0)
- } else {
- Store (\_SB.PC14.RR2C.HPEH(7), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(7, Local1)
- Notify(\_SB.PC14.RR2C, Local0)
- }
-
- // PC15 Port 2D PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC14.RR2D.PMEP,1) ) {
- Store(\_SB.PC14.RR2D.PMEH(8), Local0)
- } else {
- Store (\_SB.PC14.RR2D.HPEH(8), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(8, Local1)
- Notify(\_SB.PC14.RR2D, Local0)
- }
-
- // PC15 Port 3A PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC15.RR3A.PMEP,1) ) {
- Store(\_SB.PC15.RR3A.PMEH(9), Local0)
- } else {
- Store (\_SB.PC15.RR3A.HPEH(9), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(9, Local1)
- Notify(\_SB.PC15.RR3A, Local0)
- }
-
- // PC15 Port 3B PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC15.RR3B.PMEP,1) ) {
- Store(\_SB.PC15.RR3B.PMEH(10), Local0)
- } else {
- Store (\_SB.PC15.RR3B.HPEH(10), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(10, Local1)
- Notify(\_SB.PC15.RR3B, Local0)
- }
-
- // PC15 Port 3C PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC15.RR3C.PMEP,1) ) {
- Store(\_SB.PC15.RR3C.PMEH(11), Local0)
- } else {
- Store (\_SB.PC15.RR3C.HPEH(11), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(11, Local1)
- Notify(\_SB.PC15.RR3C, Local0)
- }
-
- // PC15 Port 3D PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC15.RR3D.PMEP,1) ) {
- Store(\_SB.PC15.RR3D.PMEH(12), Local0)
- } else {
- Store (\_SB.PC15.RR3D.HPEH(12), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(12, Local1)
- Notify(\_SB.PC15.RR3D, Local0)
- }
-
- // PC18 Port 0 PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC18.SRP0.PMEP,1) ) {
- Store(\_SB.PC18.SRP0.PMEH(1), Local0)
- } else {
- Store (\_SB.PC18.SRP0.HPEH(1), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(1, Local1)
- Notify(\_SB.PC18.SRP0, Local0)
- }
-
- // PC19 Port 1A PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC19.SR1A.PMEP,1) ) {
- Store(\_SB.PC19.SR1A.PMEH(1), Local0)
- } else {
- Store (\_SB.PC19.SR1A.HPEH(1), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(1, Local1)
- Notify(\_SB.PC19.SR1A, Local0)
- }
-
- // PC19 Port 1B PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC19.SR1B.PMEP,1) ) {
- Store(\_SB.PC19.SR1B.PMEH(2), Local0)
- } else {
- Store (\_SB.PC19.SR1B.HPEH(2), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(2, Local1)
- Notify(\_SB.PC19.SR1B, Local0)
- }
-
- // PC19 Port 1C PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC19.SR1C.PMEP,1) ) {
- Store(\_SB.PC19.SR1C.PMEH(3), Local0)
- } else {
- Store (\_SB.PC19.SR1C.HPEH(3), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(3, Local1)
- Notify(\_SB.PC19.SR1C, Local0)
- }
-
- // PC19 Port 1D PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC19.SR1D.PMEP,1) ) {
- Store(\_SB.PC19.SR1D.PMEH(4), Local0)
- } else {
- Store (\_SB.PC19.SR1D.HPEH(4), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(4, Local1)
- Notify(\_SB.PC19.SR1D, Local0)
- }
-
- // PC20 Port 2A PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC20.SR2A.PMEP,1) ) {
- Store(\_SB.PC20.SR2A.PMEH(5), Local0)
- } else {
- Store (\_SB.PC20.SR2A.HPEH(5), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(5, Local1)
- Notify(\_SB.PC20.SR2A, Local0)
- }
-
- // PC20 Port 2B PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC20.SR2B.PMEP,1) ) {
- Store(\_SB.PC20.SR2B.PMEH(6), Local0)
- } else {
- Store (\_SB.PC20.SR2B.HPEH(6), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(6, Local1)
- Notify(\_SB.PC20.SR2B, Local0)
- }
-
- // PC20 Port 2C PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC20.SR2C.PMEP,1) ) {
- Store(\_SB.PC20.SR2C.PMEH(7), Local0)
- } else {
- Store (\_SB.PC20.SR2C.HPEH(7), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(7, Local1)
- Notify(\_SB.PC20.SR2C, Local0)
- }
-
- // PC20 Port 2D PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC20.SR2D.PMEP,1) ) {
- Store(\_SB.PC20.SR2D.PMEH(8), Local0)
- } else {
- Store (\_SB.PC20.SR2D.HPEH(8), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(8, Local1)
- Notify(\_SB.PC20.SR2D, Local0)
- }
-
- // PC21 Port 3A PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC21.SR3A.PMEP,1) ) {
- Store(\_SB.PC21.SR3A.PMEH(9), Local0)
- } else {
- Store (\_SB.PC21.SR3A.HPEH(9), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(9, Local1)
- Notify(\_SB.PC21.SR3A, Local0)
- }
-
- // PC21 Port 3B PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC21.SR3B.PMEP,1) ) {
- Store(\_SB.PC21.SR3B.PMEH(10), Local0)
- } else {
- Store (\_SB.PC21.SR3B.HPEH(10), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(10, Local1)
- Notify(\_SB.PC21.SR3B, Local0)
- }
-
- // PC21 Port 3C PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC21.SR3C.PMEP,1) ) {
- Store(\_SB.PC21.SR3C.PMEH(11), Local0)
- } else {
- Store (\_SB.PC21.SR3C.HPEH(11), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(11, Local1)
- Notify(\_SB.PC21.SR3C, Local0)
- }
-
- // PC21 Port 3D PCI-Ex Hot Plug
- // If PM_PME event clear INTs and AttnBtnPressed
- If( LEqual(\_SB.PC21.SR3D.PMEP,1) ) {
- Store(\_SB.PC21.SR3D.PMEH(12), Local0)
- } else {
- Store (\_SB.PC21.SR3D.HPEH(12), Local0)
- }
- If(Lnot(LEqual(Local0,0xFF))) {
- Store(12, Local1)
- Notify(\_SB.PC21.SR3D, Local0)
- }
-
- //If a hotplug event was serviced check if this was generated by PM_PME
- If (Lnot (LEqual(Local0, 0))) {
- //Clear the status bit 16 of PMEStatus
- //Clear the PME Pending bit 17 of PMEStatus
- If( LEqual(Local1, 1)) {
- Store(1, \_SB.PC01.BR1A.PMES)
- Store(1, \_SB.PC01.BR1A.PMEP)
- }
- If( LEqual(Local1, 2)) {
- Store(1, \_SB.PC01.BR1B.PMES)
- Store(1, \_SB.PC01.BR1B.PMEP)
- }
- If( LEqual(Local1, 3)) {
- Store(1, \_SB.PC01.BR1C.PMES)
- Store(1, \_SB.PC01.BR1C.PMEP)
- }
- If( LEqual(Local1, 4)) {
- Store(1, \_SB.PC01.BR1D.PMES)
- Store(1, \_SB.PC01.BR1D.PMEP)
- }
-
- If( LEqual(Local1, 5)) {
- Store(1, \_SB.PC02.BR2A.PMES)
- Store(1, \_SB.PC02.BR2A.PMEP)
- }
- If( LEqual(Local1, 6)) {
- Store(1, \_SB.PC02.BR2B.PMES)
- Store(1, \_SB.PC02.BR2B.PMEP)
- }
- If( LEqual(Local1, 7)) {
- Store(1, \_SB.PC02.BR2C.PMES)
- Store(1, \_SB.PC02.BR2C.PMEP)
- }
- If( LEqual(Local1, 8)) {
- Store(1, \_SB.PC02.BR2D.PMES)
- Store(1, \_SB.PC02.BR2D.PMEP)
- }
- If( LEqual(Local1, 9)) {
- Store(1, \_SB.PC03.BR3A.PMES)
- Store(1, \_SB.PC03.BR3A.PMEP)
- }
- If( LEqual(Local1, 10)) {
- Store(1, \_SB.PC03.BR3B.PMES)
- Store(1, \_SB.PC03.BR3B.PMEP)
- }
- If( LEqual(Local1, 11)) {
- Store(1, \_SB.PC03.BR3C.PMES)
- Store(1, \_SB.PC03.BR3C.PMEP)
- }
- If( LEqual(Local1, 12)) {
- Store(1, \_SB.PC03.BR3D.PMES)
- Store(1, \_SB.PC03.BR3D.PMEP)
- }
-
- If( LEqual(Local1, 1)) {
- Store(1, \_SB.PC06.QRP0.PMES)
- Store(1, \_SB.PC06.QRP0.PMEP)
- }
- If( LEqual(Local1, 1)) {
- Store(1, \_SB.PC07.QR1A.PMES)
- Store(1, \_SB.PC07.QR1A.PMEP)
- }
- If( LEqual(Local1, 2)) {
- Store(1, \_SB.PC07.QR1B.PMES)
- Store(1, \_SB.PC07.QR1B.PMEP)
- }
- If( LEqual(Local1, 3)) {
- Store(1, \_SB.PC07.QR1C.PMES)
- Store(1, \_SB.PC07.QR1C.PMEP)
- }
- If( LEqual(Local1, 4)) {
- Store(1, \_SB.PC07.QR1D.PMES)
- Store(1, \_SB.PC07.QR1D.PMEP)
- }
- If( LEqual(Local1, 5)) {
- Store(1, \_SB.PC08.QR2A.PMES)
- Store(1, \_SB.PC08.QR2A.PMEP)
- }
- If( LEqual(Local1, 6)) {
- Store(1, \_SB.PC08.QR2B.PMES)
- Store(1, \_SB.PC08.QR2B.PMEP)
- }
- If( LEqual(Local1, 7)) {
- Store(1, \_SB.PC08.QR2C.PMES)
- Store(1, \_SB.PC08.QR2C.PMEP)
- }
- If( LEqual(Local1, 8)) {
- Store(1, \_SB.PC08.QR2D.PMES)
- Store(1, \_SB.PC08.QR2D.PMEP)
- }
- If( LEqual(Local1, 9)) {
- Store(1, \_SB.PC09.QR3A.PMES)
- Store(1, \_SB.PC09.QR3A.PMEP)
- }
- If( LEqual(Local1, 10)) {
- Store(1, \_SB.PC09.QR3B.PMES)
- Store(1, \_SB.PC09.QR3B.PMEP)
- }
- If( LEqual(Local1, 11)) {
- Store(1, \_SB.PC09.QR3C.PMES)
- Store(1, \_SB.PC09.QR3C.PMEP)
- }
- If( LEqual(Local1, 12)) {
- Store(1, \_SB.PC09.QR3D.PMES)
- Store(1, \_SB.PC09.QR3D.PMEP)
- }
-
- If( LEqual(Local1, 1)) {
- Store(1, \_SB.PC12.RRP0.PMES)
- Store(1, \_SB.PC12.RRP0.PMEP)
- }
- If( LEqual(Local1, 1)) {
- Store(1, \_SB.PC13.RR1A.PMES)
- Store(1, \_SB.PC13.RR1A.PMEP)
- }
- If( LEqual(Local1, 2)) {
- Store(1, \_SB.PC13.RR1B.PMES)
- Store(1, \_SB.PC13.RR1B.PMEP)
- }
- If( LEqual(Local1, 3)) {
- Store(1, \_SB.PC13.RR1C.PMES)
- Store(1, \_SB.PC13.RR1C.PMEP)
- }
- If( LEqual(Local1, 4)) {
- Store(1, \_SB.PC13.RR1D.PMES)
- Store(1, \_SB.PC13.RR1D.PMEP)
- }
- If( LEqual(Local1, 5)) {
- Store(1, \_SB.PC14.RR2A.PMES)
- Store(1, \_SB.PC14.RR2A.PMEP)
- }
- If( LEqual(Local1, 6)) {
- Store(1, \_SB.PC14.RR2B.PMES)
- Store(1, \_SB.PC14.RR2B.PMEP)
- }
- If( LEqual(Local1, 7)) {
- Store(1, \_SB.PC14.RR2C.PMES)
- Store(1, \_SB.PC14.RR2C.PMEP)
- }
- If( LEqual(Local1, 8)) {
- Store(1, \_SB.PC14.RR2D.PMES)
- Store(1, \_SB.PC14.RR2D.PMEP)
- }
- If( LEqual(Local1, 9)) {
- Store(1, \_SB.PC15.RR3A.PMES)
- Store(1, \_SB.PC15.RR3A.PMEP)
- }
- If( LEqual(Local1, 10)) {
- Store(1, \_SB.PC15.RR3B.PMES)
- Store(1, \_SB.PC15.RR3B.PMEP)
- }
- If( LEqual(Local1, 11)) {
- Store(1, \_SB.PC15.RR3C.PMES)
- Store(1, \_SB.PC15.RR3C.PMEP)
- }
- If( LEqual(Local1, 12)) {
- Store(1, \_SB.PC15.RR3D.PMES)
- Store(1, \_SB.PC15.RR3D.PMEP)
- }
-
- If( LEqual(Local1, 1)) {
- Store(1, \_SB.PC18.SRP0.PMES)
- Store(1, \_SB.PC18.SRP0.PMEP)
- }
- If( LEqual(Local1, 1)) {
- Store(1, \_SB.PC19.SR1A.PMES)
- Store(1, \_SB.PC19.SR1A.PMEP)
- }
- If( LEqual(Local1, 2)) {
- Store(1, \_SB.PC19.SR1B.PMES)
- Store(1, \_SB.PC19.SR1B.PMEP)
- }
- If( LEqual(Local1, 3)) {
- Store(1, \_SB.PC19.SR1C.PMES)
- Store(1, \_SB.PC19.SR1C.PMEP)
- }
- If( LEqual(Local1, 4)) {
- Store(1, \_SB.PC19.SR1D.PMES)
- Store(1, \_SB.PC19.SR1D.PMEP)
- }
- If( LEqual(Local1, 5)) {
- Store(1, \_SB.PC20.SR2A.PMES)
- Store(1, \_SB.PC20.SR2A.PMEP)
- }
- If( LEqual(Local1, 6)) {
- Store(1, \_SB.PC20.SR2B.PMES)
- Store(1, \_SB.PC20.SR2B.PMEP)
- }
- If( LEqual(Local1, 7)) {
- Store(1, \_SB.PC20.SR2C.PMES)
- Store(1, \_SB.PC20.SR2C.PMEP)
- }
- If( LEqual(Local1, 8)) {
- Store(1, \_SB.PC20.SR2D.PMES)
- Store(1, \_SB.PC20.SR2D.PMEP)
- }
- If( LEqual(Local1, 9)) {
- Store(1, \_SB.PC21.SR3A.PMES)
- Store(1, \_SB.PC21.SR3A.PMEP)
- }
- If( LEqual(Local1, 10)) {
- Store(1, \_SB.PC21.SR3B.PMES)
- Store(1, \_SB.PC21.SR3B.PMEP)
- }
- If( LEqual(Local1, 11)) {
- Store(1, \_SB.PC21.SR3C.PMES)
- Store(1, \_SB.PC21.SR3C.PMEP)
- }
- If( LEqual(Local1, 12)) {
- Store(1, \_SB.PC21.SR3D.PMES)
- Store(1, \_SB.PC21.SR3D.PMEP)
- }
-
- Store(0x01,PEES) //Clear bit 9 of Status
- Store(0x00,PMEE) //Clear bit 9 of GPE0_EN
- }
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieRootPortHotPlug.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieRootPortHotPlug.asl
deleted file mode 100644
index 2dd9357359..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieRootPortHotPlug.asl
+++ /dev/null
@@ -1,686 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-
-//;************************************************************************;
-//; IMPORTANT NOTE:
-//; Code in this file should be generic/common for any IIO PCIe root port.
-//; DO NOT use hard-coded Bus/Dev/Function # in this file.
-//;
-//;************************************************************************;
-
-
-
- Name(DBFL, 0) // Debug flag 0/1 = disable/enable debug checkpoints in this file
-
-
-
- //;************************************************************************;
- //; This DVPS() method detects if the root port is present and hot-plug capable.
- //; Input : None
- //; Output: Non-zero - Root port is present and hot-plug capable
- //; Zero - otherwise
- //;************************************************************************;
- Method(DVPS,0) {
- // Check if VID/DID = 3C0x_8086 to see if the root port exists
- If (LNotEqual(VID, 0x8086)) { Return(Zero) }
- //If( LNotEqual(And(DID, 0xFFF0), 0x3C00)) { Return(Zero) }
- If( LNotEqual(And(DID, 0xFFF0), 0x2F00)) { Return(Zero) } //HSX
- // Check the root port to see if slot is implemented and Hot-Plug Capable
- If(LNot(And(SLIP, HPCP))) { Return(Zero) }
- Return (One)
- }
-
-
- //;************************************************************************;
- //; This HPEN() method programs "Enable ACPI mode for Hot-plug" bit based on input Arg0
- //; See IIO PCIe rootport MISCCTRLSTS register 188h[3] definition
- //; Input : 0/1 bit value to set "Enable ACPI mode for Hot-plug" (IIO PCIe rootport register 188h[3])
- //; Output: None
- //;************************************************************************;
- Method (HPEN, 1, Serialized) {
-
- DB55(0x71, 0) // debug point
-
- // get Bus/Dev/Func information of this root port
- Store(^^_BBN, Local0) // Local0 = Bus# of parent Host bus
- //Store(_BBN, Local0) // implicit reference to PC00._BBN
- ShiftRight(_ADR, 16, Local1) // Local1 = self Device #
- And(_ADR, 0x0000ffff, Local2) // Local2 = self Function #
-
- // Calculate MMCFG config address of MISCCTRLSTS register at B:D:F:offset 188h
- //Name (MISR, 0xC0000188)
- Name (MISR, 0) // create a pointer to MMCFG region space
- Add(MMBS, 0x188, MISR) // MISR = MMCFG_BASE_ADDR + Offset of MISCCTRLSTS CSR
- Add(ShiftLeft(Local0, 20), MISR, MISR) // Build bus/dev/func number fields of MISR
- Add(ShiftLeft(Local1, 15), MISR, MISR)
- Add(ShiftLeft(Local2, 12), MISR, MISR)
-
- DB55(0x77, MISR) // debug point
-
-
- // Create OpRegion for MISCCTRLSTS register at B:D:F:offset 188h
- OperationRegion (OP37, SystemMemory, MISR, 0x04)
- Field (OP37, DWordAcc, NoLock, Preserve) {
- , 3,
- HGPE, 1, // "Enable ACPI mode for Hot-plug" (register 188h[3])
- }
-
- // Program "Enable ACPI mode for Hot-plug" bit to input Arg0
- Store(Arg0, HGPE)
- }
-
- //;************************************************************************;
- //; This DB55() method is a debug method
- //; Input : Arg0 Postcode to be sent to IO Port 80h
- //; Arg1 DWord data to be copied to debug memory location
- //; in BIOS Data Area (DBA) 40:42
- //; Output: None
- //;************************************************************************;
- Method (DB55, 2, NotSerialized) {
-
- If (DBFL) { // if debug is enabled
- Store(Arg0, IO80) // send postcode to port 80h
- Store(Arg1, MDWD) // store Arg1 to debug memory location
- Sleep(4000) // stall for 4 seconds
- }
- }
-
- OperationRegion (OP38, SystemMemory, 0x442, 0x04)
- Field (OP38, AnyAcc, NoLock, Preserve) {
- MDWD, 32, // dword at BIOS Data Area (BDA) 40:42 (floppy task-file), used as debug memory location
- }
-
-
- Method (_INI, 0, NotSerialized) {
-
- If (LEqual(Zero,DVPS)) {
- Return // Do nothing if this root port is not "Present and Hot-plugable"
- }
- HPEN(1) // No. Enable ACPI Hot-plug events
- }
-
-
-/* Greencity code
- OperationRegion (MCTL, SystemMemory, 0xA0048188, 0x04)
- Field (MCTL, ByteAcc, NoLock, Preserve) {
- , 3,
- HGPE, 1,
- , 7,
- , 8,
- , 8
- }
-
- Method (_INI, 0, NotSerialized) {
- Store (0x01, HGPE) //enable GPE message generation for ACPI hotplug support
- }
-*/
-
-//MCWU Changed ^HP02 to HP02 to avoid re-definition when this file is included under multiple BRxx devices
- //Name(^HP02, Package(4){0x08, 0x40, 1, 0} )
- Name(HP02, Package(4){0x08, 0x40, 1, 0} )
- Method(_HPP, 0) { return(HP02) }
-
- //
- // begin hotplug code
- //
- Name(SHPC, 0x40) // Slot Hot-plug Capable
-
- Name(SPDS, 0x040) // Slot Presence Detect State
-
- Name(MRLS, 0x0) // MRL Closed, Standby Power to slot is on
- Name(CCOM, 0x010) // Command Complete
- Name(SPDC, 0x08) // Slot Presence Detect Changes
- Name(MRLC, 0x04) // Slot MRL Changed
- Name(SPFD, 0x02) // Slot Power Fault Detected
- Name(SABP, 0x01) // Slot Attention Button Pressed
-
- Name(SPOF, 0x10) // Slot Power Off
- Name(SPON, 0x0F) // Slot Power On Mask
-
- Name(ALMK, 0x1C) // Slot Atten. LED Mask
- Name(ALON, 0x01) // Slot Atten. LED On
- Name(ALBL, 0x02) // Slot Atten LED Blink
- Name(ALOF, 0x03) // Slot Atten LED Off
-
- Name(PLMK, 0x13) // Slot Pwr. LED Mask
- Name(PLON, 0x04) // Slot Pwr. LED On
- Name(PLBL, 0x08) // Slot Pwr. LED Blink
- Name(PLOF, 0x0C) // Slot Pwr. LED Off
-
- //;*************************************
- //; Bit 3 = Presence Detect Event
- //; Bit 2 = MRL Sensor Event
- //; Bit 1 = PWR Fault Event
- //; Bit 0 = Attention Button Event
- //;*************************************
- Name(HPEV, 0xF) // Possible interrupt events (all)
-
- //;************************************************************************;
- //;
- //; PCIe Slot Capabilities Register A4-A7h
- //; Bit - 31-7 - Not used
- //; Bit - 6 - Hot-Plug Capable
- //; Bit - 5 - Hot-Plug Surprise
- //; Bit - 4 - Power Indicator Present.
- //; Bit - 3 - Attention Indicator Present.
- //; Bit - 2 - MRL Sensor Present.
- //; Bit - 1 - Power Controller Present.
- //; Bit - 0 - Attention Button Present.
- //;
- //; PCIe Slot control Register A8-A9h
- //;
- //; Bit - 10 - PWR Control Disable
- //; Bit - 9:8 - Attn Indicator
- //; Bit - 7:6 - PWR Indicator
- //; Bit - 5 - Hot-Plug Interrupt Event Enable
- //; Bit - 4 - Command Complete Interrupt enable
- //; Bit - 3 - Presence Detect Changed Interrupt enable
- //; Bit - 2 - MRL Sensor Changed Interrupt enable
- //; Bit - 1 - PwrFault Detect Interrupt enable
- //; Bit - 0 - Attention Button Pressed Interrupt Enable
- //;
- //; PCIe Slot Status Registers AA-ADh
- //;
- //; Bit - 6 - Presence Detect State.
- //; Bit - 5 - MRL Sensor State.
- //; Bit - 4 - Command Completed.
- //;
- //; RWC Status Bits
- //;
- //; Bit - 3 - Presence Detect Changed.
- //; Bit - 2 - MRL Sensor Changed.
- //; Bit - 1 - Power Fault Detected.
- //; Bit - 0 - Attention Button Pressed.
- //;************************************************************************;
-
- OperationRegion(PPA4, PCI_Config, 0x00, 0x0ff)
- Field(PPA4,ByteAcc,NoLock,Preserve) {
-
- Offset(0x00), // VenderID/DeviceID register
- VID, 16, // VID = 0x8086
- DID, 16, // Device IDs for IIO PCI Express root ports are as follows:
- // 0x3C00: DMI mode 0x3C01: the DMI port running in PCIe mode
- // 0x3C02: Port 1a
- // 0x3C03: Port 1b
- // 0x3C04: Port 2a
- // 0x3C05: Port 2b
- // 0x3C06: Port 2c
- // 0x3C07: Port 2d
- // 0x3C08: Port 3a in PCIe mode
- // 0x3C09: Port 3b
- // 0x3C0A: Port 3c
- // 0x3C0B: Port 3d
- // (0x3C0F: IIO NTB Secondary Endpoint)
-
- Offset(0x92), // PXPCAP - PCIe CAP Register
- , 8,
- SLIP, 1, // bit8 Slot Implemented
-
- offset(0xA4), // SLTCAP - Slot Capabilities Register
- ATBP,1, // bit0 Attention Button Present
- PWCP,1, // bit1 Power Controller Present
- MRSP,1, // bit2 MRL Sensor Present
- ATIP,1, // bit3 Attention Indicator Present
- PWIP,1, // bit4 Power Indicator Present
- HPSR,1, // bit5 Hot-Plug Surprise
- HPCP,1, // bit6 Hot-Plug Capable
-
- offset(0xA8), // SLTCON - PCIE Slot Control Register
- ABIE,1, // bit0 Attention Button Pressed Interrupt Enable
- PFIE,1, // bit1 Power Fault Detected Interrupt Enable
- MSIE,1, // bit2 MRL Sensor Changed Interrupt Enable
- PDIE,1, // bit3 Presence Detect Changed Interrupt Enable.
- CCIE,1, // bit4 Command Complete Interrupt Enable.
- HPIE,1, // bit5 Hot-plug Interrupt Enable.
- SCTL,5, // bit[10:6] Attn/Power indicator and Power controller.
-
- offset(0xAA), // SLTSTS - PCIE Slot Status Register
- SSTS,7, // The status bits in Slot Status Reg
- ,1,
-}
-
- OperationRegion(PPA8, PCI_Config, 0x00, 0x0ff)
- Field(PPA8,ByteAcc,NoLock,Preserve) {
- Offset(0xA8), // SLTCON - PCIE Slot Control Register
- ,6,
- ATID,2, // bit[7:6] Attention Indicator Control.
- PWID,2, // bit[9:8] Power Indicator Control.
- PWCC,1, // bit[10] Power Controller Control.
- ,5,
- Offset(0xAA), // SLTSTS - PCIE Slot status Register (WRC)
- ABPS,1, // bit0 Attention Button Pressed Status (RWC)
- PFDS,1, // bit1 Power Fault Detect Status (RWC)
- MSCS,1, // bit2 MRL Sensor Changed Status
- PDCS,1, // bit3 Presence Detect Changed Status
- CMCS,1, // bit4 Command Complete Status
- MSSC,1, // bit5 MRL Sensor State
- PRDS,1, // bit6 Presence Detect State
- ,1,
- }
-
- //;************************************************************************;
- //; This OSHP (Operating System Hot Plug) method is provided for each HPC
- //; which is controlled by ACPI. This method disables ACPI access to the
- //; HPC and restores the normal System Interrupt and Wakeup Signal
- //; connection.
- //;************************************************************************;
- Method(OSHP) { // OS call to unhook Legacy ASL PCI-Express HP code.
- Store(0, SSTS) // Clear any status
-// Store(0x0, HGPE) // Disable GPE generation
- HPEN(0) // Disable GPE generation
- }
-
- //;************************************************************************;
- //; Hot Plug Controller Command Method
- //;
- //; Input: Arg0 - Command to issue
- //;
- //;************************************************************************;
- Method(HPCC,1) {
- Store(SCTL, Local0) // get current command state
- Store(0, Local1) // reset the timeout value
- If(LNotEqual(Arg0, Local0)) { // see if state is different
- Store(Arg0, SCTL) // Update the Slot Control
- While(LAnd (LNot(CMCS), LNotEqual(100, Local1))) { // spin while CMD complete bit is not set,
- // check for timeout to avoid dead loop
- Store(0x2C, IO80)
- Sleep(2) // allow processor time slice
- Add(Local1, 2, Local1)
- }
- Store(0x1, CMCS) // Clear the command complete status
- }
- }
-
- //;************************************************************************;
- //; Attention Indicator Command
- //;
- //; Input: Arg0 - Command to issue
- //; 1 = ON
- //; 2 = Blink
- //; 3 = OFF
- //;************************************************************************;
- Method(ATCM,1) {
- Store(SCTL, Local0) // Get Slot Control
- And(Local0, ALMK, Local0) // Mask the Attention Indicator Bits
- If(LEqual(Arg0, 0x1)){ // Attenion indicator "ON?"
- Or(Local0, ALON, Local0) // Set the Attention Indicator to "ON"
- }
- If(LEqual(Arg0, 0x2)){ // Attenion indicator "BLINK?"
- Or(Local0, ALBL, Local0) // Set the Attention Indicator to "BLINK"
- }
- If(LEqual(Arg0, 0x3)){ // Attenion indicator "OFF?"
- Or(Local0, ALOF, Local0) // Set the Attention Indicator to "OFF"
- }
- HPCC(Local0)
- }
-
- //;************************************************************************;
- //; Power Indicator Command
- //;
- //; Input: Arg0 - Command to issue
- //; 1 = ON
- //; 2 = Blink
- //; 3 = OFF
- //;************************************************************************;
- Method(PWCM,1){
- Store(SCTL, Local0) // Get Slot Control
- And(Local0, PLMK, Local0) // Mask the Power Indicator Bits
- If(LEqual(Arg0, 0x1)){ // Power indicator "ON?"
- Or(Local0, PLON, Local0) // Set the Power Indicator to "ON"
- }
- If(LEqual(Arg0, 0x2)){ // Power indicator "BLINK?"
- Or(Local0, PLBL, Local0) // Set the Power Indicator to "BLINK"
- }
- If(LEqual(Arg0, 0x3)){ // Power indicator "OFF?"
- Or(Local0, PLOF, Local0) // Set the Power Indicator to "OFF"
- }
- HPCC(Local0)
- }
-
- //;************************************************************************;
- //; Power Slot Command
- //;
- //; Input: Arg0 - Command to issue
- //; 1 = Slot Power ON
- //; 2 = Slot Power Off
- //;************************************************************************;
- Method(PWSL,1){
- Store(SCTL, Local0) // Get Slot Control
- If(Arg0){ // Power Slot "ON" Arg0 = 1
- And(Local0, SPON, Local0) // Turns the Power "ON"
- } Else { // Power Slot "OFF"
- Or(Local0, SPOF, Local0) // Turns the Power "OFF"
- }
- HPCC(Local0)
- }
-
- //;************************************************************************;
- //; _OST Methods to indicate that the device Eject/insert request is
- //; pending, OS could not complete it
- //;
- //; Input: Arg0 - Value used in Notify to OS
- //; 0x00 - card insert
- //; 0x03 - card eject
- //; Arg1 - status of Notify
- //; 0 - success
- //; 0x80 - Ejection not supported by OSPM
- //; 0x81 - Device in use
- //; 0x82 - Device Busy
- //; 0x84 - Ejection in progress-pending
- //;************************************************************************;
- Method(_OST,3,Serialized) {
- Switch(And(Arg0,0xFF)) { // Mask to retain low byte
- Case(0x03) { // Ejection Request
- Switch(ToInteger(Arg1)) {
- Case(Package() {0x80, 0x81, 0x82, 0x83}) {
- //
- // Ejection Failure for some reason
- //
- If (Lnot(PWCC)) { // if slot is powered
- PWCM(0x1) // Set PowerIndicator to ON
- Store(0x1,ABIE) // Set AttnBtn Interrupt ON
- }
- }
- }
- }
- }
- } // End _OST
-
- //;************************************************************************;
- //; Eject Control Methods to indicate that the device is hot-ejectable and
- //; should "eject" the device.
- //;
- //; Input: Arg0 - Not use.
- //;
- //;************************************************************************;
- Method(EJ02, 1){
- Store(0xFF, IO80)
- Store(SCTL, Local0) // Get IOH Port 9/SLot3 Control state
- if( LNot( LEqual( ATID, 1))) { // Check if Attention LED is not solid "ON"
- And(Local0, ALMK, Local0) // Mask the Attention Indicator Bits
- Or(Local0, ALBL, Local0) // Set the Attention Indicator to blink
- }
- HPCC(Local0) // issue command
-
- Store(SCTL, Local0) // Get IOH Port 9/SLot3 Control state
- Or(Local0, SPOF, Local0) // Set the Power Controller Control to Power Off
- HPCC(Local0)
-
- Store(SCTL, Local0) // Get PEXH Port 9/SLot3 Control state
- Or(Local0, PLOF, Local0) // Set the Power Indicator to Off.
- HPCC(Local0)
- } // End of EJ02
-
- //;************************************************************************;
- //; PM_PME Wake Handler for Slot 3 only
- //;
- //; Input: Arg0 - Slot Number
- //;
- //;************************************************************************;
- Method(PMEH,1){ // Handler for PCI-E PM_PME Wake Event/Interrupt (GPI xxh)
- If(And(HPEV, SSTS)){ // Check for Hot-Plug Events
- If(ABPS) {
- Store (Arg0, IO80) // Send slot number to Port 80
- Store(0x1, ABPS) // Clear the interrupt status
- Sleep(200) // delay 200ms
- }
- }
- Return (0xff) // Indicate that this controller did not interrupt
- } // End of Method PMEH
-
- //;************************************************************************;
- //; Hot-Plug Handler for an IIO PCIe root port slot
- //;
- //; Input: Arg0 - Slot Numnber (not used)
- //; Output:
- //; 0xFF - No hotplug event detected
- //; 0x03 - Eject Request detected
- //; 0x00 - Device Presence Changed
- //;
- //;************************************************************************;
- Method(HPEH,1){ // Handler for PCI-E Hot-Plug Event/Interupt Called from \_SB.GPE._L01()
-
- If (LEqual(Zero,DVPS)) {
- Return (0xff) // Do nothing if root port is not "Present and Hot-plugable"
- }
-
- Store(0x22, IO80)
- Sleep(100)
- Store(0,CCIE) // Disable command interrupt
- If(And(HPEV, SSTS)){ // Check for Hot-Plug Events
- Store(0x3A, IO80)
- Sleep(10)
- Store(PP3H(0x0), Local0) // Call the Slot 3 Hot plug Interrupt Handler
- Return(Local0) // Return PP2H information
- }
- Else{
- Return (0xff) // Indicate that this controller did not interrupt
- }
- Store(0x2F, IO80)
- Sleep(10)
- } // End of Method HPEH
-
- //;************************************************************************;
- //; Interrut Event Handler
- //;
- //; Input: Arg0 - Slot Numnber
- //;
- //;************************************************************************;
- Method(PP3H,1){ // Slot 3 Hot plug Interrupt Handler
- //
- // Check for the Atention Button Press, Slot Empty/Presence, Power Controller Control.
- //
- Sleep(200) // HW Workaround for AttentionButton Status to stabilise
- If(ABPS) { // Check if Attention Button Pressed for Device 4
- If(LNot(PRDS)) { // See if nothing installed (no card in slot)
- PWSL(0x0) // make sure Power is Off
- PWCM(0x3) // Set Power Indicator to "OFF"
- //
- // Check for MRL here and set attn indicator accordingly
- //
- If(LEqual(MSSC,MRLS)) { // Standby power is on - MRL closed
- ATCM(0x2) // Set Attention Indicator to "BLINK"
- } else { // Standby power is off - MRL open
- ATCM(0x3) // set attention indicator "OFF"
- }
- Store(0x0, ABIE) // set Attention Button Interrupt to disable
- Store(0x1, ABPS) // Clear the interrupt status
- Sleep(200) // delay 200ms
- Return(0xff) // Attn Button pressed without card in slot. Do nothing
- }
- //
- // Card is present in slot so....
- //
- Store(0x0, ABIE) // set Attention Button Interrupt to disable
- // Attn Btn Interrupt has to be enabled only after an insert oprn
- Store(0x1, ABPS) // Clear the interrupt status
- Sleep(200) // delay 200ms
- //
- // Check for MRL here - only if SPWR is OFF blink AttnInd and retun 0xff
- //
- If(LNot(LEqual(MSSC,MRLS))) { // Standby power is off
- PWSL(0x0) // make sure Power is Off
- PWCM(0x3) // Set Power Indicator to "OFF"
- ATCM(0x2) // Set Attention Indicator to "BLINK"
- Return(0xff) // Attn Button pressed with card in slot, but MRL open. Do nothing
- }
- //Card Present, if StandbyPwr is ON proceed as below with Eject Sequence
- If(PWCC) { // Slot not Powered
- PWCM(0x3) // Set Power Indicator to "OFF"
- ATCM(0x2) // Set Attention Indicator to "BLINK"
- Return(0xff) // Attn Button pressed with card in slot, MRL closed, Slot not powered. Do nothing
- } else { // See if Slot is already Powered
- PWCM(0x2) // Set power Indicator to BLINK
- Sleep(600) // Wait 100ms
- Store(600, Local0) // set 5 second accumulator to 0
- Store(0x1, ABPS) // Clear the interrupt status
- Sleep(200) // delay 200ms
- While(LNot(ABPS)) { // check for someone pressing Attention
- Sleep(200) // Wait 200ms
- Add(Local0, 200, Local0)
- If(LEqual(5000, Local0)) { // heck if 5sec has passed without pressing attnetion btn
- Store(0x1, ABPS) // Clear the interrupt status
- Sleep(200) // delay 200ms
- Return (0x3) // continue with Eject request
- }
- }
- PWCM(0x1) // Set power Indicator baCK "ON"
- Store(0x1, ABPS) // Clear the Attention status
- Sleep(200) // delay 200ms
- Store(0x1, ABIE) // set Attention Button Interrupt to enable
- Return (0xff) // do nothing and abort
- }
- } // End if for the Attention Button Hot Plug Interrupt.
-
- If(PFDS) { // Check if Power Fault Detected
- Store(0x1, PFDS) // Clear the Power Fault Status
- PWSL(0x0) // set Power Off
- PWCM(0x3) // set power indicator to OFF
- ATCM(0x1) // set attention indicator "ON"
- Return(0x03) // Eject request.
- } // End if for the Power Fault Interrupt.
-
- If(MSCS) { // Check interrupt caused by the MRL Sensor
- Store(0x1, MSCS) // Clear the MRL Status
- If(LEqual(MSSC,MRLS)) { // Standby power is on - MRL closed
- If(PRDS) { // Card is Present
- // Slot Power is Off, so power up the slot
- ATCM(0x3) // Set Attention Indicator to off
- PWCM(0x2) // Set Power Indicator to Blink
- Sleep(600) // Wait 100ms
- Store(600, Local0) // set 5 second accumulator to 0
- Store(0x1, ABPS) // Clear the interrupt status
- While(LNot(ABPS)) { // check for someone pressing Attention
- Sleep(200) // Wait 200ms
- Add(Local0, 200, Local0)
- If(LEqual(5000, Local0)) { // Check if 5 sec elapsed
- Store(0x1, ABIE) // Enable Attention button interrupt
- ATCM(0x3) // set attention indicator "OFF"
- PWSL(0x1) // Power the Slot
- Sleep(500) // Wait for .5 Sec for the Power to Stabilize.
- // Check for the Power Fault Detection
- If(LNot(PFDS)) { // No Power Fault
- PWCM(0x1) // Set Power Indicator to "ON"
- // Or(LVLS, 0x000010000, LVLS) // Enable the Device 4 Slot Clock (GPIO16)
- // Notify the OS to load the Driver for the card
- Store(0x00, Local1)
- Store(0x1, ABIE) // Enable Attention button interrupt
- } Else { // Power Fault present
- PWSL(0x0) // set Slot Power Off
- PWCM(0x3) // set power indicator to OFF
- ATCM(0x1) // set attention indicator "ON"
- // And (LVLS, 0x0FFFEFFFF, LVLS) // Disable the Device 4 Slot Clock (GPIO16)
- Store(0x03, Local1) // Eject request.
- } // End if for the Slot Power Fault
- Store(0x1, ABPS) // Clear the Attention status
- Sleep(200) // delay 200ms
- Return(Local1)
- }
- }
- //
- // someone pressed Attention Button
- //
- Store(0x1, ABPS) // Clear the Attention status
- Sleep(200) // delay 200ms
- PWSL(0x0) // Set Slot Power off
- PWCM(0x3) // Set Power Indicator back to "OFF"
- ATCM(02) // Set Attention Indicator to "BLINK"
- Return(0xff) // leave it off
- // End of Insert sequence
- }
- //MRL is closed, Card is not present
- PWSL(0x0) // Set Slot Power off
- PWCM(0x3) // Set Power Indicator back to "OFF"
- ATCM(02) // Set Attention Indicator to "BLINK"
- Return(0xff) // leave it off
- } else { // MRL is open i.e Stdby power is turned off
- If(PRDS) {
- //card present MRL switched off
- ATCM(0x2) // Set Attention Indicator to "BLINK"
- If(Lnot(PWCC)) { // If slot is powered
- // This event is not supported and someone has opened the MRL and dumped the power
- // on the slot with possible pending transactions. This could hose the OS.
- // Try to Notify the OS to unload the drivers.
- PWSL(0x0) // Set Slot Power off
- PWCM(0x3) // Set Power Indicator back to "OFF"
- Return(0x03) // Eject request.
- } else { // Slot not powered, MRL is opened, card still in slot - Eject not fully complete
- Return(0xFF)
- }
- }
- //no card present and Stdby power switched off, turn AI off
- ATCM(0x3) // Set Attention Indicator to "OFF"
- Return(0xff) // leave it off
- } // End of MRL switch open/close state
- } // End of MRL Sensor State Change
-
- If(PDCS) { // Check if Presence Detect Changed Status
- Store(0x1, PDCS) // Clear the Presence Detect Changed Status
- If(LNot(PRDS)) { // Slot is Empty
- PWSL(0x0) // Set Slot Power "OFF"
- PWCM(0x3) // set power indicator to "OFF"
- If(LEqual(MSSC,MRLS)) { // If Standby power is on
- ATCM(0x2) // Set Attention Indicator to "Blink"
- } else {
- ATCM(0x3) // Set Attention Indicator to "OFF"
- }
- Return(0xFF) // Do nothing
- } Else { // Slot Card is inserted
- // Irrespective of MRL state blink indicator
- PWSL(0x0) // Set Slot Power off
- PWCM(0x3) // Set Power Indicator back to "OFF"
- ATCM(0x2) // Set Attention Indicator to "Blink"
- Return(0xFF) // Do nothing
- }
- } // End if for the Presence Detect Changed Hot Plug Interrupt.
- Return(0xff) // should not get here, but do device check if it does.
- } // End of method PP5H
- //
- // End of hotplug code
- //
-
- Device(H000) {
- Name(_ADR, 0x00000000)
- Name(_SUN, 0x0002) // Slot User Number
- Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot
- }
- Device(H001) {
- Name(_ADR, 0x00000001)
- Name(_SUN, 0x0002) // Slot User Number
- Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot
- }
- Device(H002) {
- Name(_ADR, 0x00000002)
- Name(_SUN, 0x0002) // Slot User Number
- Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot
- }
- Device(H003) {
- Name(_ADR, 0x00000003)
- Name(_SUN, 0x0002) // Slot User Number
- Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot
- }
- Device(H004) {
- Name(_ADR, 0x00000004)
- Name(_SUN, 0x0002) // Slot User Number
- Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot
- }
- Device(H005) {
- Name(_ADR, 0x00000005)
- Name(_SUN, 0x0002) // Slot User Number
- Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot
- }
- Device(H006) {
- Name(_ADR, 0x00000006)
- Name(_SUN, 0x0002) // Slot User Number
- Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot
- }
- Device(H007) {
- Name(_ADR, 0x00000007)
- Name(_SUN, 0x0002) // Slot User Number
- Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot
- }
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl
deleted file mode 100644
index af3f6581db..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl
+++ /dev/null
@@ -1,32 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-// ITSS
-// Define the needed ITSS registers used by ASL on Interrupt
-// mapping.
-
-scope(\_SB){
- OperationRegion(ITSS, SystemMemory, 0xfdc43100, 0x208)
- Field(ITSS, ByteAcc, NoLock, Preserve)
- {
- PARC, 8,
- PBRC, 8,
- PCRC, 8,
- PDRC, 8,
- PERC, 8,
- PFRC, 8,
- PGRC, 8,
- PHRC, 8,
- Offset(0x200), // Offset 3300h ITSSPRC - ITSS Power Reduction Control
- , 1,
- , 1,
- SCGE, 1, // ITSSPRC[2]: 8254 Static Clock Gating Enable (8254CGE)
-
- }
-}
-
-
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchGbe.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchGbe.asl
deleted file mode 100644
index 8ae7c7b8be..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchGbe.asl
+++ /dev/null
@@ -1,17 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-///
-/// Gbe Ethernet ASL methods and structures
-///
-
- //
- // GPE bit 13 indicates wake from this device, can wakeup from S4 state
- //
- Method(_PRW, 0) {
- Return(Package() {13, 4})
- }
\ No newline at end of file
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl
deleted file mode 100644
index 40cc31b86a..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl
+++ /dev/null
@@ -1,79 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-
-// Interrupt specific registers
-include("Itss.asl")
-//
-// Original file line: 163
-//
-
-Method(ADBG,1,Serialized)
-{
- Return(0)
-}
-
-//
-// Original file line: 1460
-//
-Scope (\)
-{
- //
- // Global Name, returns current Interrupt controller mode;
- // updated from _PIC control method
- //
-
- //
- // Procedure: GPRW
- //
- // Description: Generic Wake up Control Method ("Big brother")
- // to detect the Max Sleep State available in ASL Name scope
- // and Return the Package compatible with _PRW format.
- // Input: Arg0 = bit offset within GPE register space device event will be triggered to.
- // Arg1 = Max Sleep state, device can resume the System from.
- // If Arg1 = 0, Update Arg1 with Max _Sx state enabled in the System.
- // Output: _PRW package
- //
- Name(PRWP, Package(){Zero, Zero}) // _PRW Package
-
- Method(GPRW, 2)
- {
- Store(Arg0, Index(PRWP, 0)) // copy GPE#
- //
- // SS1-SS4 - enabled in BIOS Setup Sleep states
- //
- Store(ShiftLeft(SS1,1),Local0) // S1 ?
- Or(Local0,ShiftLeft(SS2,2),Local0) // S2 ?
- Or(Local0,ShiftLeft(SS3,3),Local0) // S3 ?
- Or(Local0,ShiftLeft(SS4,4),Local0) // S4 ?
- //
- // Local0 has a bit mask of enabled Sx(1 based)
- // bit mask of enabled in BIOS Setup Sleep states(1 based)
- //
- If(And(ShiftLeft(1, Arg1), Local0))
- {
- //
- // Requested wake up value (Arg1) is present in Sx list of available Sleep states
- //
- Store(Arg1, Index(PRWP, 1)) // copy Sx#
- }
- Else
- {
- //
- // Not available -> match Wake up value to the higher Sx state
- //
- ShiftRight(Local0, 1, Local0)
- // If(LOr(LEqual(OSFL, 1), LEqual(OSFL, 2))) { // ??? Win9x
- // FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 == Max Sx
- // } Else { // ??? Win2k / XP
- FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 == Min Sx
- // }
- }
-
- Return(PRWP)
- }
-}
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/WFPPlatform.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/WFPPlatform.asl
deleted file mode 100644
index 254806cbc8..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/WFPPlatform.asl
+++ /dev/null
@@ -1,189 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-DefinitionBlock ("WFPPlatform.asl","DSDT",2,"INTEL","PLATWFP ",3)
-{
-
- #include "CommonPlatform.asi"
- #include "PlatformPciTree_WFP.asi"
- #include "AMLUPD.asl"
- #include "DSDT.ASL"
- #include "Pch.asl" //This is in another package (PchPkg)
- #include "Platform.asl"
- #include "PlatformGpe.asi"
- #include "PcieSeg.asi"
-
- Scope (\_SB.PC00.XHCI.RHUB) {
-
-
-
- //
- // Method for creating generic _PLD buffers
- // _PLD contains lots of data, but for purpose of internal validation we care only about
- // ports' visibility and pairing (this requires group position)
- // so these are the only 2 configurable parameters (User Visible, Group Position)
- //
- Method(GPLD, 2, Serialized) {
- Name(PCKG, Package() { Buffer(0x10) {} } )
- CreateField(DerefOf(Index(PCKG,0)), 0, 7, REV)
- Store(1,REV)
- CreateField(DerefOf(Index(PCKG,0)), 64, 1, VISI)
- Store(Arg0, VISI)
- CreateField(DerefOf(Index(PCKG,0)), 87, 8, GPOS)
- Store(Arg1, GPOS)
-
-
- return (PCKG)
- }
-
- //
- // Method for creating generic _UPC buffers
- // Similar to _PLD, for internal testing we only care about 1 parameter (port connectable)
- //
- Method(GUPC, 1, Serialized) {
- Name(PCKG, Package(4) { 0, 0xFF, 0, 0 } )
- Store(Arg0,Index(PCKG,0))
-
-
- return (PCKG)
- }
-
-
-
- } //end scope RHUB
-
- Scope (\_SB.PC00.XHCI.RHUB.HS01) {
- Method(_UPC) { Return (GUPC(1)) }
- Method(_PLD) { Return (GPLD(1,1)) } //Rear Panel A [CONN27] - Upper - usb2 port
- }
-
- Scope (\_SB.PC00.XHCI.RHUB.HS02) {
- Method(_UPC) { Return (GUPC(1)) }
- Method(_PLD) { Return (GPLD(1,2)) } //Rear Panel A [CONN27] - Center - usb2 port
- }
-
- Scope (\_SB.PC00.XHCI.RHUB.HS03) {
- Method(_UPC) { Return (GUPC(1)) }
- Method(_PLD) { Return (GPLD(1,3)) } //Rear Panel A [CONN27] - Bottom - usb2 port
- }
-
- Scope (\_SB.PC00.XHCI.RHUB.HS04) {
- Method(_UPC) { Return (GUPC(1)) }
- Method(_PLD) { Return (GPLD(1,4)) } //Internal A1 [CONN9] - Right - usb2 port
- }
-
- Scope (\_SB.PC00.XHCI.RHUB.HS05) {
- Method(_UPC) { Return (GUPC(1)) }
- Method(_PLD) { Return (GPLD(1,5)) } //Front Panel [CONN20] - Right - usb2 port
- }
-
- Scope (\_SB.PC00.XHCI.RHUB.HS06) {
- Method(_UPC) { Return (GUPC(1)) }
- Method(_PLD) { Return (GPLD(1,6)) } //Front Panel [CONN20] - Left - usb2 port
- }
-
- Scope (\_SB.PC00.XHCI.RHUB.HS07) {
- Method(_UPC) { Return (GUPC(1)) }
- Method(_PLD) { Return (GPLD(1,7)) } //Internal Type A3 [CONN4] - ? - usb2 port
- }
-
- Scope (\_SB.PC00.XHCI.RHUB.HS08) {
- Method(_UPC) { Return (GUPC(1)) }
- Method(_PLD) { Return (GPLD(1,8)) } //Internal Type A3 [CONN4] - ? - usb2 port
- }
-
- Scope (\_SB.PC00.XHCI.RHUB.HS09) {
- Method(_UPC) { Return (GUPC(1)) }
- Method(_PLD) { Return (GPLD(1,9)) } //Jacksonville [CONN22] - Bottom - usb2 port
- }
-
- Scope (\_SB.PC00.XHCI.RHUB.HS10) {
- Method(_UPC) { Return (GUPC(1)) }
- Method(_PLD) { Return (GPLD(1,10)) } //Usb daughter card [CONN14] - ? - usb2 port
- }
-
- Scope (\_SB.PC00.XHCI.RHUB.HS11) {
- Method(_UPC) { Return (GUPC(1)) }
- Method(_PLD) { Return (GPLD(0,11)) } //Jacksonville [CONN22] - Center - usb2 port
- }
-
- Scope (\_SB.PC00.XHCI.RHUB.HS12) {
- Method(_UPC) { Return (GUPC(1)) }
- Method(_PLD) { Return (GPLD(0,12)) } //Usb daughter card [CONN14] - ? - usb2 port
- }
-
- Scope (\_SB.PC00.XHCI.RHUB.HS13) {
- Method(_UPC) { Return (GUPC(1)) }
- Method(_PLD) { Return (GPLD(1,13)) } //Internal A1 [CONN4] - Left - usb2 port
- }
-
- Scope (\_SB.PC00.XHCI.RHUB.HS14) {
- Method(_UPC) { Return (GUPC(1)) }
- Method(_PLD) { Return (GPLD(1,14)) } //Usb daughter card [CONN14] - ? - usb2 port
- }
-
- Scope (\_SB.PC00.XHCI.RHUB.USR1) {
- Method(_UPC) { Return (GUPC(0)) }
- Method(_PLD) { Return (GPLD(0,0)) }
- }
-
- Scope (\_SB.PC00.XHCI.RHUB.USR2) {
- Method(_UPC) { Return (GUPC(0)) }
- Method(_PLD) { Return (GPLD(0,0)) }
- }
-
- Scope (\_SB.PC00.XHCI.RHUB.SS01) {
- Method(_UPC) { Return (GUPC(1)) }
- Method(_PLD) { Return (GPLD(1,1)) } //Rear Panel A [CONN27] - Upper - usb3 port
- }
-
- Scope (\_SB.PC00.XHCI.RHUB.SS02) {
- Method(_UPC) { Return (GUPC(1)) }
- Method(_PLD) { Return (GPLD(1,2)) } //Rear Panel A [CONN27] - Center - usb3 port
- }
-
- Scope (\_SB.PC00.XHCI.RHUB.SS03) {
- Method(_UPC) { Return (GUPC(1)) }
- Method(_PLD) { Return (GPLD(1,3)) } //Rear Panel A [CONN27] - Bottom - usb3 port
- }
-
- Scope (\_SB.PC00.XHCI.RHUB.SS04) {
- Method(_UPC) { Return (GUPC(1)) }
- Method(_PLD) { Return (GPLD(1,4)) } //Internal A1 [CONN9] - Right - usb3 port
- }
-
- Scope (\_SB.PC00.XHCI.RHUB.SS05) {
- Method(_UPC) { Return (GUPC(1)) }
- Method(_PLD) { Return (GPLD(1,5)) } //Front Panel [CONN20] - Right - usb3 port
- }
-
- Scope (\_SB.PC00.XHCI.RHUB.SS06) {
- Method(_UPC) { Return (GUPC(1)) }
- Method(_PLD) { Return (GPLD(1,6)) } //Front Panel [CONN20] - Left - usb3 port
- }
-
- Scope (\_SB.PC00.XHCI.RHUB.SS07) {
- Method(_UPC) { Return (GUPC(0)) }
- Method(_PLD) { Return (GPLD(0,0)) } //N/A
- }
-
- Scope (\_SB.PC00.XHCI.RHUB.SS08) {
- Method(_UPC) { Return (GUPC(0)) }
- Method(_PLD) { Return (GPLD(0,0)) } //N/A
- }
-
- Scope (\_SB.PC00.XHCI.RHUB.SS09) {
- Method(_UPC) { Return (GUPC(0)) }
- Method(_PLD) { Return (GPLD(0,0)) } //N/A
- }
-
- Scope (\_SB.PC00.XHCI.RHUB.SS10) {
- Method(_UPC) { Return (GUPC(0)) }
- Method(_PLD) { Return (GPLD(0,0)) } //N/A
- }
-
-} // end of DSDT
--
2.16.2.windows.1
next prev parent reply other threads:[~2019-11-01 21:05 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-01 21:03 [edk2-platforms][PATCH V1 00/19] Remove Intel server packages Kubacki, Michael A
2019-11-01 21:03 ` [edk2-platforms][PATCH V1 01/19] Readme.md: Remove PurleyOpenBoardPkg Kubacki, Michael A
2019-11-01 21:03 ` [edk2-platforms][PATCH V1 02/19] Platform/Intel/build.cfg: Remove BoardMtOlympus Kubacki, Michael A
2019-11-01 21:03 ` [edk2-platforms][PATCH V1 03/19] PurleyOpenBoardPkg: Remove StructureConfig.dsc Kubacki, Michael A
2019-11-01 21:03 ` [edk2-platforms][PATCH V1 04/19] PurleyOpenBoardPkg: Remove package build files Kubacki, Michael A
2019-11-01 21:03 ` [edk2-platforms][PATCH V1 05/19] PurleyOpenBoardPkg/BoardMtOlympus: Remove all files Kubacki, Michael A
2019-11-01 21:03 ` [edk2-platforms][PATCH V1 06/19] PurleyOpenBoardPkg/Acpi/BoardAcpiDxe: Remove PlatformPciTree_WFP.asi Kubacki, Michael A
2019-11-01 21:03 ` [edk2-platforms][PATCH V1 07/19] PurleyOpenBoardPkg/Acpi/BoardAcpiDxe: Remove PCxx .asi files Kubacki, Michael A
2019-11-01 21:03 ` [edk2-platforms][PATCH V1 08/19] PurleyOpenBoardPkg/Acpi/BoardAcpiDxe: Remove " Kubacki, Michael A
2019-11-01 21:03 ` Kubacki, Michael A [this message]
2019-11-01 21:03 ` [edk2-platforms][PATCH V1 10/19] PurleyOpenBoardPkg: Remove all modules Kubacki, Michael A
2019-11-01 21:03 ` [edk2-platforms][PATCH V1 11/19] PurleyOpenBoardPkg: Remove all includes and libraries Kubacki, Michael A
2019-11-01 21:03 ` [edk2-platforms][PATCH V1 12/19] PurleyRcPkg: Remove the package Kubacki, Michael A
2019-11-01 21:03 ` [edk2-platforms][PATCH V1 13/19] PurleySktPkg: " Kubacki, Michael A
2019-11-01 21:03 ` [edk2-platforms][PATCH V1 14/19] LewisburgPkg: Remove DEC and DSC files Kubacki, Michael A
2019-11-01 21:03 ` [edk2-platforms][PATCH V1 15/19] LewisburgPkg/AcpiTables: Remove all files Kubacki, Michael A
2019-11-01 21:03 ` [edk2-platforms][PATCH V1 16/19] LewisburgPkg/Include/Register: " Kubacki, Michael A
2019-11-01 21:03 ` [edk2-platforms][PATCH V1 17/19] LewisburgPkg/Include: " Kubacki, Michael A
2019-11-01 21:03 ` [edk2-platforms][PATCH V1 18/19] LewisburgPkg: Remove all libraries Kubacki, Michael A
2019-11-01 21:03 ` [edk2-platforms][PATCH V1 19/19] Maintainers.txt: Update Intel package maintainers Kubacki, Michael A
2019-11-01 21:35 ` [edk2-platforms][PATCH V1 00/19] Remove Intel server packages Oram, Isaac W
2019-11-01 21:58 ` Nate DeSimone
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