From: "Yao, Jiewen" <jiewen.yao@intel.com>
To: devel@edk2.groups.io
Cc: Ray Ni <ray.ni@intel.com>,
Rangasai V Chaganty <rangasai.v.chaganty@intel.com>,
Yun Lou <yun.lou@intel.com>
Subject: [PATCH V3 1/6] IntelSiliconPkg/Include: Add Intel PciSecurity definition.
Date: Thu, 7 Nov 2019 21:38:26 +0800 [thread overview]
Message-ID: <20191107133831.22412-2-jiewen.yao@intel.com> (raw)
In-Reply-To: <20191107133831.22412-1-jiewen.yao@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2303
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Yun Lou <yun.lou@intel.com>
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
---
.../IndustryStandard/IntelPciSecurity.h | 92 +++++++++++++++++++
1 file changed, 92 insertions(+)
create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecurity.h
diff --git a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecurity.h b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecurity.h
new file mode 100644
index 0000000000..f2bdb7ee2d
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecurity.h
@@ -0,0 +1,92 @@
+/** @file
+ Intel PCI security data structure definition from
+ PCIe* Device Security Enhancements Specification.
+
+ https://www.intel.com/content/www/us/en/io/pci-express/pcie-device-security-enhancements-spec.html
+
+ NOTE: The data structure is not fully match the current specification,
+ because it is aligned with the real hardware implementation with minor adjustment
+ on INTEL_PCI_DIGEST_CAPABILITY_STRUCTURE, INTEL_PCI_DIGEST_DATA_MODIFIED and
+ INTEL_PCI_DIGEST_DATA_VALID.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __INTEL_PCI_SECURITY_H__
+#define __INTEL_PCI_SECURITY_H__
+
+#pragma pack(1)
+
+///
+/// The PCIE capability structure header for Intel PCI DVSEC extension.
+///
+typedef struct {
+ UINT16 CapId; // 0x23: DVSEC
+ UINT16 CapVersion:4; // 1
+ UINT16 NextOffset:12;
+ UINT16 DvSecVendorId; // 0x8086
+ UINT16 DvSecRevision:4; // 1
+ UINT16 DvSecLength:12;
+ UINT16 DvSecId; // 0x3E: Measure
+} INTEL_PCI_DIGEST_CAPABILITY_HEADER;
+
+#define INTEL_PCI_CAPID_DVSEC 0x23
+#define INTEL_PCI_DVSEC_VENDORID_INTEL 0x8086
+#define INTEL_PCI_DVSEC_DVSECID_MEASUREMENT 0x3E
+
+///
+/// The Intel PCI digest modified macro.
+///
+#define INTEL_PCI_DIGEST_MODIFIED BIT0
+
+///
+/// The Intel PCI DVSEC digest data modified structure.
+///
+typedef union {
+ struct {
+ UINT8 DigestModified:1; // RW1C
+ UINT8 Reserved0:7;
+ } Bits;
+ UINT8 Data;
+} INTEL_PCI_DIGEST_DATA_MODIFIED;
+
+///
+/// The Intel PCI digest valid macro.
+///
+#define INTEL_PCI_DIGEST_0_VALID BIT0
+#define INTEL_PCI_DIGEST_0_LOCKED BIT1
+#define INTEL_PCI_DIGEST_1_VALID BIT2
+#define INTEL_PCI_DIGEST_1_LOCKED BIT3
+
+///
+/// The Intel PCI DVSEC digest data valid structure.
+///
+typedef union {
+ struct {
+ UINT8 Digest0Valid:1; // RO
+ UINT8 Digest0Locked:1; // RO
+ UINT8 Digest1Valid:1; // RO
+ UINT8 Digest1Locked:1; // RO
+ UINT8 Reserved1:4;
+ } Bits;
+ UINT8 Data;
+} INTEL_PCI_DIGEST_DATA_VALID;
+
+///
+/// The PCIE capability structure for Intel PCI DVSEC extension with digest.
+///
+typedef struct {
+ INTEL_PCI_DIGEST_DATA_MODIFIED Modified; // RW1C
+ INTEL_PCI_DIGEST_DATA_VALID Valid; // RO
+ UINT16 TcgAlgId; // RO
+ UINT8 FirmwareID; // RO
+ UINT8 Reserved;
+//UINT8 Digest[];
+} INTEL_PCI_DIGEST_CAPABILITY_STRUCTURE;
+
+#pragma pack()
+
+#endif
+
--
2.19.2.windows.1
next prev parent reply other threads:[~2019-11-07 13:38 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-07 13:38 [PATCH V3 0/6] Add Device Security driver Yao, Jiewen
2019-11-07 13:38 ` Yao, Jiewen [this message]
2019-11-08 6:58 ` [PATCH V3 1/6] IntelSiliconPkg/Include: Add Intel PciSecurity definition Ni, Ray
2019-11-07 13:38 ` [PATCH V3 2/6] IntelSiliconPkg/Include: Add Platform Device Security Policy protocol Yao, Jiewen
2019-11-08 6:59 ` Ni, Ray
2019-11-08 7:01 ` Yao, Jiewen
2019-11-08 7:10 ` Ni, Ray
2019-11-09 7:12 ` Yao, Jiewen
2019-11-07 13:38 ` [PATCH V3 3/6] IntelSiliconPkg/dec: Add ProtocolGuid definition Yao, Jiewen
2019-11-08 7:01 ` Ni, Ray
2019-11-07 13:38 ` [PATCH V3 4/6] IntelSiliconPkg/IntelPciDeviceSecurityDxe: Add PciSecurity Yao, Jiewen
2019-11-11 8:19 ` Ni, Ray
2019-11-11 10:16 ` Yao, Jiewen
2019-11-11 14:40 ` Ni, Ray
2019-11-07 13:38 ` [PATCH V3 5/6] IntelSiliconPkg/SamplePlatformDevicePolicyDxe: Add sample policy Yao, Jiewen
2019-11-11 8:23 ` Ni, Ray
2019-11-07 13:38 ` [PATCH V3 6/6] IntelSiliconPkg/dsc: Add Device Security component Yao, Jiewen
2019-11-11 8:23 ` Ni, Ray
2019-11-08 4:23 ` [edk2-devel] [PATCH V3 0/6] Add Device Security driver Javeed, Ashraf
2019-11-08 5:14 ` Yao, Jiewen
2019-11-08 10:25 ` Javeed, Ashraf
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