From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web11.413.1573712557549508303 for ; Wed, 13 Nov 2019 22:22:37 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: nathaniel.l.desimone@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Nov 2019 22:22:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,302,1569308400"; d="scan'208";a="216641626" Received: from nldesimo-desk1.amr.corp.intel.com ([10.7.159.63]) by orsmga002.jf.intel.com with ESMTP; 13 Nov 2019 22:22:34 -0800 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Michael Kubacki , Chasel Chiu , Liming Gao Subject: [edk2-platforms] [PATCH V1 10/13] MinPlatformPkg: Coding style cleanups in MinPlatformPkg.dec Date: Wed, 13 Nov 2019 22:06:52 -0800 Message-Id: <20191114060655.5161-11-nathaniel.l.desimone@intel.com> X-Mailer: git-send-email 2.23.0.windows.1 In-Reply-To: <20191114060655.5161-1-nathaniel.l.desimone@intel.com> References: <20191114060655.5161-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Cc: Michael Kubacki Cc: Chasel Chiu Cc: Liming Gao Signed-off-by: Nate DeSimone --- .../Intel/MinPlatformPkg/MinPlatformPkg.dec | 281 +++++++++--------- 1 file changed, 139 insertions(+), 142 deletions(-) diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec b/Platform/In= tel/MinPlatformPkg/MinPlatformPkg.dec index 856c17f737..c6b5881646 100644 --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec @@ -14,184 +14,182 @@ =0D =0D [Defines]=0D -DEC_SPECIFICATION =3D 0x00010017=0D -PACKAGE_NAME =3D MinPlatformPkg=0D -PACKAGE_VERSION =3D 0.1=0D -PACKAGE_GUID =3D 463B3B00-0D18-4a5f-90C0-D5B851D2574B=0D -=0D + DEC_SPECIFICATION =3D 0x00010017=0D + PACKAGE_NAME =3D MinPlatformPkg=0D + PACKAGE_VERSION =3D 0.1=0D + PACKAGE_GUID =3D 463B3B00-0D18-4a5f-90C0-D5B851D2574B=0D =0D [Includes]=0D -Include=0D + Include=0D =0D [Ppis]=0D -gEdkiiSiliconInitializedPpiGuid =3D {0x82a72dc8, 0x61ec, 0x403e, {0xb1, 0x= 5a, 0x8d, 0x7a, 0x3a, 0x71, 0x84, 0x98}}=0D + gEdkiiSiliconInitializedPpiGuid =3D {0x82a72dc8, 0x61ec, 0x403e, {0xb1= , 0x5a, 0x8d, 0x7a, 0x3a, 0x71, 0x84, 0x98}}=0D =0D -gPeiBaseMemoryTestPpiGuid =3D { 0xb6ec423c, 0x21d2, 0x490d, { 0x85, = 0xc6, 0xdd, 0x58, 0x64, 0xea, 0xa6, 0x74 } }=0D -gPeiPlatformMemorySizePpiGuid =3D { 0x9a7ef41e, 0xc140, 0x4bd1, { 0xb8, = 0x84, 0x1e, 0x11, 0x24, 0x0b, 0x4c, 0xe6 } }=0D + gPeiBaseMemoryTestPpiGuid =3D {0xb6ec423c, 0x21d2, 0x490d, {0x85= , 0xc6, 0xdd, 0x58, 0x64, 0xea, 0xa6, 0x74}}=0D + gPeiPlatformMemorySizePpiGuid =3D {0x9a7ef41e, 0xc140, 0x4bd1, {0xb8= , 0x84, 0x1e, 0x11, 0x24, 0x0b, 0x4c, 0xe6}}=0D =0D [Guids]=0D -gMinPlatformPkgTokenSpaceGuid =3D {0x69d13bf0, 0xaf91, 0x4d96, {0= xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}}=0D + gMinPlatformPkgTokenSpaceGuid =3D {0x69d13bf0, 0xaf91, 0x4d96, {0xaa= , 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}}=0D =0D -gAdapterInfoPlatformTestPointGuid =3D {0x5381e3ea, 0xb77, 0x4580, {0xad, 0= xdf, 0xa9, 0x1c, 0x8, 0x3b, 0xf2, 0x97}}=0D + gAdapterInfoPlatformTestPointGuid =3D {0x5381e3ea, 0x0b77, 0x4580, {0xad= , 0xdf, 0xa9, 0x1c, 0x08, 0x3b, 0xf2, 0x97}}=0D =0D -gBoardDetectGuid =3D {0x1792429d, 0x9d94, 0x4e08, {0xa0, 0x99, 0= x73, 0xa2, 0x86, 0xae, 0xb4, 0x35}}=0D -gBoardPreMemInitGuid =3D {0x191dcfcf, 0xe16e, 0x43bb, {0x9b, 0xc3, 0= x6e, 0xee, 0x6f, 0xab, 0x3a, 0x27}}=0D -gBoardPostMemInitGuid =3D {0xa0e933ea, 0xa69, 0x47fb, {0xb2, 0xab, 0= xa1, 0x6f, 0x71, 0x2d, 0x6f, 0x58}}=0D -gBoardNotificationInitGuid =3D {0x78dbcabf, 0xc544, 0x4e6f, {0xaf, 0x3a, 0= x71, 0x17, 0xd9, 0x42, 0x4e, 0xd1}}=0D + gBoardDetectGuid =3D {0x1792429d, 0x9d94, 0x4e08, {0xa0= , 0x99, 0x73, 0xa2, 0x86, 0xae, 0xb4, 0x35}}=0D + gBoardPreMemInitGuid =3D {0x191dcfcf, 0xe16e, 0x43bb, {0x9b= , 0xc3, 0x6e, 0xee, 0x6f, 0xab, 0x3a, 0x27}}=0D + gBoardPostMemInitGuid =3D {0xa0e933ea, 0xa69, 0x47fb, {0xb2= , 0xab, 0xa1, 0x6f, 0x71, 0x2d, 0x6f, 0x58}}=0D + gBoardNotificationInitGuid =3D {0x78dbcabf, 0xc544, 0x4e6f, {0xaf= , 0x3a, 0x71, 0x17, 0xd9, 0x42, 0x4e, 0xd1}}=0D =0D -gBoardAcpiTableGuid =3D {0xd70e9f57, 0x69f, 0x4bef, {0x96, 0xc0, 0= x84, 0x74, 0xf4, 0xa2, 0x5f, 0x3a}}=0D -gBoardAcpiEnableGuid =3D {0x9727b610, 0xf645, 0x4429, {0x89, 0x21, 0= x2c, 0x2b, 0x58, 0xdc, 0xbb, 0xa}}=0D + gBoardAcpiTableGuid =3D {0xd70e9f57, 0x69f, 0x4bef, {0x96= , 0xc0, 0x84, 0x74, 0xf4, 0xa2, 0x5f, 0x3a}}=0D + gBoardAcpiEnableGuid =3D {0x9727b610, 0xf645, 0x4429, {0x89= , 0x21, 0x2c, 0x2b, 0x58, 0xdc, 0xbb, 0x0a}}=0D =0D -gDefaultDataFileGuid =3D { 0x1ae42876, 0x008f, 0x41= 61, { 0xb2, 0xb7, 0x1c, 0x0d, 0x15, 0xc5, 0xef, 0x43 }}=0D -gDefaultDataOptSizeFileGuid =3D { 0x003e7b41, 0x98a2, 0x4b= e2, { 0xb2, 0x7a, 0x6c, 0x30, 0xc7, 0x65, 0x52, 0x25 }}=0D + gDefaultDataFileGuid =3D {0x1ae42876, 0x008f, 0x4161, {0xb2= , 0xb7, 0x1c, 0x0d, 0x15, 0xc5, 0xef, 0x43}}=0D + gDefaultDataOptSizeFileGuid =3D {0x003e7b41, 0x98a2, 0x4be2, {0xb2= , 0x7a, 0x6c, 0x30, 0xc7, 0x65, 0x52, 0x25}}=0D =0D [LibraryClasses]=0D =0D -PeiLib|Include/Library/PeiLib.h=0D + PeiLib|Include/Library/PeiLib.h=0D =0D -AslUpdateLib|Include/Library/AslUpdateLib.h=0D -BoardAcpiEnableLib|Include/Library/BoardAcpiEnableLib.h=0D -BoardAcpiTableLib|Include/Library/BoardAcpiTableLib.h=0D + AslUpdateLib|Include/Library/AslUpdateLib.h=0D + BoardAcpiEnableLib|Include/Library/BoardAcpiEnableLib.h=0D + BoardAcpiTableLib|Include/Library/BoardAcpiTableLib.h=0D =0D -SiliconPolicyInitLib|Include/Library/SiliconPolicyInitLib.h=0D -SiliconPolicyUpdateLib|Include/Library/SiliconPolicyUpdateLib.h=0D + SiliconPolicyInitLib|Include/Library/SiliconPolicyInitLib.h=0D + SiliconPolicyUpdateLib|Include/Library/SiliconPolicyUpdateLib.h=0D =0D -SpiFlashCommonLib|Include/Library/SpiFlashCommonLib.h=0D + SpiFlashCommonLib|Include/Library/SpiFlashCommonLib.h=0D =0D -BoardInitLib|Include/Library/BoardInitLib.h=0D -MultiBoardInitSupportLib|Include/Library/MultiBoardInitSupportLib.h=0D -SecBoardInitLib|Include/Library/SecBoardInitLib.h=0D + BoardInitLib|Include/Library/BoardInitLib.h=0D + MultiBoardInitSupportLib|Include/Library/MultiBoardInitSupportLib.h=0D + SecBoardInitLib|Include/Library/SecBoardInitLib.h=0D =0D -TestPointLib|Include/Library/TestPointLib.h=0D -TestPointCheckLib|Include/Library/TestPointCheckLib.h=0D + TestPointLib|Include/Library/TestPointLib.h=0D + TestPointCheckLib|Include/Library/TestPointCheckLib.h=0D =0D SetCacheMtrrLib|Include/Library/SetCacheMtrrLib.h=0D =0D [PcdsFixedAtBuild, PcdsPatchableInModule]=0D =0D -gMinPlatformPkgTokenSpaceGuid.PcdFspMaxUpdSize|0x00000000|UINT32|0x8000000= 0=0D -gMinPlatformPkgTokenSpaceGuid.PcdFspReservedSizeOnStackTop|0x00000040|UINT= 32|0x80000001=0D -gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0x00000000|UINT32|0x8000= 0002=0D + gMinPlatformPkgTokenSpaceGuid.PcdFspMaxUpdSize|0x00000000|UINT32|0x80000= 000=0D + gMinPlatformPkgTokenSpaceGuid.PcdFspReservedSizeOnStackTop|0x00000040|UI= NT32|0x80000001=0D + gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0x00000000|UINT32|0x80= 000002=0D =0D -gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000|UINT32|0x9000= 000B=0D -gMinPlatformPkgTokenSpaceGuid.PcdLocalApicMmioSize|0x1000|UINT32|0x9000000= C=0D + gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000|UINT32|0x90= 00000B=0D + gMinPlatformPkgTokenSpaceGuid.PcdLocalApicMmioSize|0x1000|UINT32|0x90000= 00C=0D =0D -gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress|0xFEC00000|UINT32|0x9000000= D=0D -gMinPlatformPkgTokenSpaceGuid.PcdIoApicMmioSize|0x1000|UINT32|0x9000000E=0D -gMinPlatformPkgTokenSpaceGuid.PcdIoApicId|0x02|UINT8|0x90000014=0D + gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress|0xFEC00000|UINT32|0x90000= 00D=0D + gMinPlatformPkgTokenSpaceGuid.PcdIoApicMmioSize|0x1000|UINT32|0x9000000E= =0D + gMinPlatformPkgTokenSpaceGuid.PcdIoApicId|0x02|UINT8|0x90000014=0D =0D -gMinPlatformPkgTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x90000012=0D -gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x90000013=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x90000012=0D + gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x90000013= =0D =0D -gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|0|UINT8|0x90000015=0D -gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase|0x09|UINT8|0x90000016=0D -gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000|UINT32|0x9= 0000017=0D -gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicInterruptBase|24|UINT32|0x9000001= 8=0D + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|0|UINT8|0x90000015=0D + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase|0x09|UINT8|0x90000016=0D + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000|UINT32|0= x90000017=0D + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicInterruptBase|24|UINT32|0x90000= 018=0D =0D -gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2|UINT32|0x90000021=0D -gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8|UINT32|0x90000022=0D -gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|4|UINT32|0x90000023=0D + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2|UINT32|0x90000021=0D + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8|UINT32|0x90000022=0D + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|4|UINT32|0x90000023=0D =0D -gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x02|UINT8|0x90000= 025=0D -gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0001|UINT16|0x90000026= =0D -gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000086A5|UINT32|0x90000027=0D + gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x02|UINT8|0x900= 00025=0D + gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0001|UINT16|0x900000= 26=0D + gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000086A5|UINT32|0x90000027= =0D =0D -gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0x65|UIN= T32|0x20000500=0D -gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0x30|UINT32|= 0x20000501=0D -gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402|UINT3= 2|0x20000502=0D -gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b|UINT32|0= x20000503=0D -gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x25|UINT32|0= x20000504=0D + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0x65|U= INT32|0x20000500=0D + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0x30|UINT3= 2|0x20000501=0D + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402|UIN= T32|0x20000502=0D + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b|UINT32= |0x20000503=0D + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x25|UINT32= |0x20000504=0D =0D -#=0D -# The PCDs are used to control the Windows SMM Security Mitigations Table = - Protection Flags=0D -#=0D -# BIT0: If set, expresses that for all synchronous SMM entries,SMM will va= lidate that input and output buffers lie entirely within the expected fixed= memory regions.=0D -# BIT1: If set, expresses that for all synchronous SMM entries, SMM will v= alidate that input and output pointers embedded within the fixed communicat= ion buffer only refer to address ranges \=0D -# that lie entirely within the expected fixed memory regions.=0D -# BIT2: Firmware setting this bit is an indication that it will not allow = reconfiguration of system resources via non-architectural mechanisms.=0D -# BIT3-31: Reserved=0D -#=0D -gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0|UINT32|0x10001006=0D + #=0D + # The PCDs are used to control the Windows SMM Security Mitigations Tabl= e - Protection Flags=0D + #=0D + # BIT0: If set, expresses that for all synchronous SMM entries,SMM will = validate that input and output buffers lie entirely within the expected fix= ed memory regions.=0D + # BIT1: If set, expresses that for all synchronous SMM entries, SMM will= validate that input and output pointers embedded within the fixed communic= ation buffer only refer to address ranges \=0D + # that lie entirely within the expected fixed memory regions.=0D + # BIT2: Firmware setting this bit is an indication that it will not allo= w reconfiguration of system resources via non-architectural mechanisms.=0D + # BIT3-31: Reserved=0D + #=0D + gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0|UINT32|0x10001006= =0D =0D -gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable|TRUE|BOOLEAN|0x0= 0100206=0D + gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable|TRUE|BOOLEAN|0= x00100206=0D =0D -#=0D -# See HstiIbvFeatureBit.h for the definition=0D -#=0D -# #define HSTI_BYTE_ BIT=0D -#=0D -# It means BYTE BIT is for feature .=0D -#=0D -gMinPlatformPkgTokenSpaceGuid.PcdHstiIbvPlatformFeature|{0x00, 0x00, 0x00}= |VOID*|0x00100301=0D + #=0D + # See HstiIbvFeatureBit.h for the definition=0D + #=0D + # #define HSTI_BYTE_ BIT=0D + #=0D + # It means BYTE BIT is for feature .=0D + #=0D + gMinPlatformPkgTokenSpaceGuid.PcdHstiIbvPlatformFeature|{0x00, 0x00, 0x0= 0}|VOID*|0x00100301=0D =0D -#=0D -# See TestPointCheckLib.h for the definition=0D -#=0D -# #define TEST_POINT_BYTE_ BIT=0D -#=0D -# It means BYTE BIT is for feature .=0D -# BYTE0 BYTE= 1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 BYTE8=0D -# Stage debug: {0x03, 0x0= 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, = 0x00, 0x00}=0D -# Stage memory: {0x03, 0x0= 7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, = 0x00, 0x00}=0D -# Stage UEFI boot: {0x03, 0x0= 7, 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, = 0x00, 0x00}=0D -# Stage OS boot: {0x03, 0x0= 7, 0x03, 0x05, 0x3F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, = 0x00, 0x00}=0D -# Stage Secure boot: {0x03, 0x0= F, 0x03, 0x1D, 0x3F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, = 0x00, 0x00}=0D -# Stage Advanced: {0x03, 0x0= F, 0x03, 0x1D, 0x3F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, = 0x00, 0x00}=0D -gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, = 0x03, 0x1D, 0x3F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0= 0, 0x00}|VOID*|0x00100302=0D + #=0D + # See TestPointCheckLib.h for the definition=0D + #=0D + # #define TEST_POINT_BYTE_ BIT=0D + #=0D + # It means BYTE BIT is for feature .=0D + # BYTE0 BY= TE1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 BYTE8=0D + # Stage debug: {0x03, 0= x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00= , 0x00, 0x00}=0D + # Stage memory: {0x03, 0= x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00= , 0x00, 0x00}=0D + # Stage UEFI boot: {0x03, 0= x07, 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00= , 0x00, 0x00}=0D + # Stage OS boot: {0x03, 0= x07, 0x03, 0x05, 0x3F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00= , 0x00, 0x00}=0D + # Stage Secure boot: {0x03, 0= x0F, 0x03, 0x1D, 0x3F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00= , 0x00, 0x00}=0D + # Stage Advanced: {0x03, 0= x0F, 0x03, 0x1D, 0x3F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00= , 0x00, 0x00}=0D + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F= , 0x03, 0x1D, 0x3F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00}|VOID*|0x00100302=0D =0D -[PcdsFixedAtBuild, PcdsPatchableInModule]=0D -##=0D -## The Flash relevant PCD are ineffective and will be patched basing on FD= F definitions during build.=0D -## Set all of them to 0 here to prevent from confusion.=0D -##=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFF800000|UINT32|0x= 10000001=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize|0x00800000|UINT32|0x1000000= 2=0D -=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0xFFE60000|UINT32|0x= 30000004=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x000A0000|UINT32|0x= 30000005=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset|0x00660000|UINT32|= 0x30000006=0D -=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|0x00000000|UINT32|0x= 20000004=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize|0x00000000|UINT32|0x= 20000005=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|0x00000000|UINT32|= 0x20000006=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|0x00000000|UINT32|0= x20000007=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize|0x00000000|UINT32|0= x20000008=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|0x00000000|UINT32= |0x20000009=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|0x00000000|UINT32|0x2= 000000A=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize|0x00000000|UINT32|0x2= 000000B=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|0x00000000|UINT32|0= x2000000C=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|0x00000000|UINT32|0x200= 0000D=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize|0x00000000|UINT32|0x200= 0000E=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|0x00000000|UINT32|0x2= 000000F=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|0x00000000|UINT32|0x2= 0000010=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize|0x00000000|UINT32|0x2= 0000011=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|0x00000000|UINT32|0= x20000012=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|0x00000000|UINT32|0x2= 0000013=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize|0x00000000|UINT32|0x2= 0000014=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|0x00000000|UINT32|0= x20000015=0D -=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageBase|0x00000000|UINT32|0x20= 000016=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize|0x00000000|UINT32|0x20= 000017=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset|0x00000000|UINT32|0x= 20000018=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|0x00000000|U= INT32|0x20000019=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|0x00000000|U= INT32|0x2000001A=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|0x00000000= |UINT32|0x2000001B=0D -=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|0x00000000|UINT32|0x20000= 021=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize|0x00000000|UINT32|0x20000= 022=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|0x00000000|UINT32|0x200= 00023=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|0x00000000|UINT32|0x20000= 024=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize|0x00000000|UINT32|0x20000= 025=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|0x00000000|UINT32|0x200= 00026=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|0x00000000|UINT32|0x20000= 027=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize|0x00000000|UINT32|0x20000= 028=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|0x00000000|UINT32|0x200= 00029=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUBase|0x00000000|UINT32|0x20000= 02A=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUSize|0x00000000|UINT32|0x20000= 02B=0D -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUOffset|0x00000000|UINT32|0x200= 0002C=0D + ##=0D + ## The Flash relevant PCD are ineffective and will be patched basing on = FDF definitions during build.=0D + ## Set all of them to 0 here to prevent from confusion.=0D + ##=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFF800000|UINT32|= 0x10000001=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize|0x00800000|UINT32|0x10000= 002=0D +=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0xFFE60000|UINT32|= 0x30000004=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x000A0000|UINT32|= 0x30000005=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset|0x00660000|UINT3= 2|0x30000006=0D +=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|0x00000000|UINT32|= 0x20000004=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize|0x00000000|UINT32|= 0x20000005=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|0x00000000|UINT3= 2|0x20000006=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|0x00000000|UINT32= |0x20000007=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize|0x00000000|UINT32= |0x20000008=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|0x00000000|UINT= 32|0x20000009=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|0x00000000|UINT32|0= x2000000A=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize|0x00000000|UINT32|0= x2000000B=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|0x00000000|UINT32= |0x2000000C=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|0x00000000|UINT32|0x2= 000000D=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize|0x00000000|UINT32|0x2= 000000E=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|0x00000000|UINT32|0= x2000000F=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|0x00000000|UINT32|0= x20000010=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize|0x00000000|UINT32|0= x20000011=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|0x00000000|UINT32= |0x20000012=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|0x00000000|UINT32|0= x20000013=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize|0x00000000|UINT32|0= x20000014=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|0x00000000|UINT32= |0x20000015=0D +=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageBase|0x00000000|UINT32|0x= 20000016=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize|0x00000000|UINT32|0x= 20000017=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset|0x00000000|UINT32|= 0x20000018=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|0x00000000= |UINT32|0x20000019=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|0x00000000= |UINT32|0x2000001A=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|0x000000= 00|UINT32|0x2000001B=0D +=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|0x00000000|UINT32|0x200= 00021=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize|0x00000000|UINT32|0x200= 00022=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|0x00000000|UINT32|0x2= 0000023=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|0x00000000|UINT32|0x200= 00024=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize|0x00000000|UINT32|0x200= 00025=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|0x00000000|UINT32|0x2= 0000026=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|0x00000000|UINT32|0x200= 00027=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize|0x00000000|UINT32|0x200= 00028=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|0x00000000|UINT32|0x2= 0000029=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUBase|0x00000000|UINT32|0x200= 0002A=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUSize|0x00000000|UINT32|0x200= 0002B=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUOffset|0x00000000|UINT32|0x2= 000002C=0D =0D [PcdsDynamic, PcdsDynamicEx]=0D -gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UINT32|0x90000019=0D + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UINT32|0x90000019=0D =0D [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]=0D =0D @@ -261,7 +259,7 @@ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UIN= T32|0x90000019 =0D [PcdsFixedAtBuild]=0D =0D - #=0D + ## MinPlatform Boot Stage Selector=0D # Stage 1 - enable debug (system deadloop after debug init)=0D # Stage 2 - mem init (system deadloop after mem init)=0D # Stage 3 - boot to shell only=0D @@ -305,4 +303,3 @@ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UIN= T32|0x90000019 gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable |FALSE|BOOLEAN|0= xF00000A5=0D gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE|BOOLEAN|0= xF00000A6=0D gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable |FALSE|BOOLEAN|0= xF00000A7=0D -=0D --=20 2.23.0.windows.1