* [edk2-platforms] [PATCH V1 00/13] SecFspWrapperPlatformSecLib Cleanup
@ 2019-11-14 6:06 Nate DeSimone
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 01/13] KabylakeSiliconPkg: Change MODULE_TYPE of SiliconInitLib to PEIM Nate DeSimone
` (12 more replies)
0 siblings, 13 replies; 44+ messages in thread
From: Nate DeSimone @ 2019-11-14 6:06 UTC (permalink / raw)
To: devel
Cc: Chasel Chiu, Michael Kubacki, Sai Chaganty, Liming Gao,
Isaac W Oram, Jeremy Soller
This patch series cleans up two outstanding problems with
SecFspWrapperPlatformSecLib:
1. There are several copies of SecFspWrapperPlatformSecLib
thoughout the codebase, this patch series consolidates
the various implementations down to a single implementation
contained in MinPlatformPkg.
The WhiskeylakeOpenBoardPkg implementation of
SecFspWrapperPlatformSecLib diverged from MinPlatformPkg by
halting the TCO watch dog timer early in SEC instead of
early in PEI. Analysis of this change has shown that it is
unnessesary, so this patch series move that code back to PEI.
The KabylakeOpenBoardPkg implementation of
SecFspWrapperPlatformSecLib contains support for FSP dispatch
mode. This was integrated into MinPlatformPkg, eliminating the
need for KabylakeOpenBoardPkg version.
2. Due to EFI_PEI_TEMPORARY_RAM_DONE_PPI being implemented
by SecMain, the BoardInitLib event callbacks for
BeforeTempRamExit() and AfterTempRamExit() are currently
linked by PlatformSecLib. Linking BoardInitLib in SEC
phase places a lot of restrictions on how BoardInitLib
is implemented. To mitigate this, the BoardInitLib calls
have been moved to a PlatformInitPreMem.
PlatformInitPreMem is invoked by PlatformSecLib using the
new PLATFORM_INIT_TEMP_RAM_EXIT_PPI, which then invokes
the BoardInitLib event callbacks.
This patch series also includes some general cleanup.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Isaac W Oram <isaac.w.oram@intel.com>
Cc: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Nate DeSimone (13):
KabylakeSiliconPkg: Change MODULE_TYPE of SiliconInitLib to PEIM
KabylakeOpenBoardPkg: Update location of SiliconInitLib
KabylakeSiliconPkg: Cleanup old comments
CoffeeLakeSiliconPkg: Move TcoWdtHob.h
CoffeelakeSiliconPkg: Add SiliconInitLib
WhiskeylakeOpenBoardPkg: Add SiliconInitLib APIs to BoardInitLib
WhiskeylakeOpenBoardPkg: Whitespace cleanup in BoardInitLib
WhiskeylakeOpenBoardPkg: Remove SecFspWrapperPlatformSecLib override
MinPlatformPkg: FSP Dispatch Mode Support for PlatformSecLib
MinPlatformPkg: Coding style cleanups in MinPlatformPkg.dec
KabylakeOpenBoardPkg: Add support for PcdFspDispatchModeUseFspPeiMain
KabylakeOpenBoardPkg: Remove SecFspWrapperPlatformSecLib override
MinPlatformPkg: Remove BoardInitLib dependency from PlatformSecLib
.../FspWrapperPlatformSecLib.c | 186 ---------
.../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 40 --
.../SecFspWrapperPlatformSecLib/Ia32/Fsp.h | 42 --
.../Ia32/PeiCoreEntry.nasm | 130 -------
.../Ia32/SecEntry.nasm | 361 ------------------
.../Ia32/Stack.nasm | 72 ----
.../PlatformInit.c | 47 ---
.../SecFspWrapperPlatformSecLib.inf | 97 -----
.../SecGetPerformance.c | 89 -----
.../SecPlatformInformation.c | 78 ----
.../SecRamInitData.c | 36 --
.../SecTempRamDone.c | 73 ----
.../GalagoPro3/OpenBoardPkg.dsc | 4 +-
.../KabylakeRvp3/OpenBoardPkg.dsc | 4 +-
.../KabylakeRvp3/OpenBoardPkg.fdf | 5 +-
.../KabylakeRvp3/OpenBoardPkgPcd.dsc | 20 +
.../FspWrapperPlatformSecLib.c | 34 +-
.../SecFspWrapperPlatformSecLib.inf | 8 +-
.../SecTempRamDone.c | 72 +++-
.../Include/Ppi/PlatformInitTempRamExitPpi.h | 55 +++
.../Intel/MinPlatformPkg/MinPlatformPkg.dec | 311 ++++++++-------
.../PlatformInitPei/PlatformInitPreMem.c | 76 +++-
.../PlatformInitPei/PlatformInitPreMem.inf | 1 +
.../FspWrapperPlatformSecLib.c | 163 --------
.../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 40 --
.../SecFspWrapperPlatformSecLib/Ia32/Fsp.h | 43 ---
.../Ia32/PeiCoreEntry.nasm | 130 -------
.../Ia32/SecEntry.nasm | 361 ------------------
.../Ia32/Stack.nasm | 72 ----
.../PlatformInit.c | 54 ---
.../SecFspWrapperPlatformSecLib.inf | 97 -----
.../SecGetPerformance.c | 90 -----
.../SecPlatformInformation.c | 79 ----
.../SecRamInitData.c | 37 --
.../SecTempRamDone.c | 48 ---
.../BoardInitLib/PeiBoardInitPostMemLib.inf | 1 +
.../BoardInitLib/PeiBoardInitPreMemLib.inf | 1 +
.../PeiMultiBoardInitPostMemLib.inf | 1 +
.../PeiMultiBoardInitPreMemLib.inf | 2 +-
.../PeiWhiskeylakeURvpInitPostMemLib.c | 191 +++++----
.../PeiWhiskeylakeURvpInitPreMemLib.c | 346 +++++++----------
.../BoardInitLib/WhiskeylakeURvpInit.h | 1 +
.../WhiskeylakeURvp/OpenBoardPkg.dsc | 7 +-
.../Include/Guid/TcoWdtHob.h | 0
.../Include/Library/SiliconInitLib.h | 28 ++
.../PeiSiliconInitLib/PeiSiliconInitLib.inf | 46 +++
.../Library/PeiSiliconInitLib/SiliconInit.c | 19 +
.../PeiSiliconInitLib/SiliconInitPreMem.c | 109 ++++++
.../PeiSiliconInitLib.inf} | 3 +-
.../SiliconInit.c | 0
.../SiliconInitPreMem.c | 4 +-
51 files changed, 863 insertions(+), 2951 deletions(-)
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c
create mode 100644 Platform/Intel/MinPlatformPkg/Include/Ppi/PlatformInitTempRamExitPpi.h
delete mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c
delete mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
delete mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h
delete mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
delete mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
delete mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
delete mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c
delete mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
delete mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c
delete mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c
delete mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
delete mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c
rename {Platform/Intel/WhiskeylakeOpenBoardPkg => Silicon/Intel/CoffeelakeSiliconPkg}/Include/Guid/TcoWdtHob.h (100%)
create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.h
create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c
create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMem.c
rename Silicon/Intel/KabylakeSiliconPkg/Library/{SiliconInitLib/SiliconInitLib.inf => PeiSiliconInitLib/PeiSiliconInitLib.inf} (91%)
rename Silicon/Intel/KabylakeSiliconPkg/Library/{SiliconInitLib => PeiSiliconInitLib}/SiliconInit.c (100%)
rename Silicon/Intel/KabylakeSiliconPkg/Library/{SiliconInitLib => PeiSiliconInitLib}/SiliconInitPreMem.c (95%)
--
2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* [edk2-platforms] [PATCH V1 01/13] KabylakeSiliconPkg: Change MODULE_TYPE of SiliconInitLib to PEIM
2019-11-14 6:06 [edk2-platforms] [PATCH V1 00/13] SecFspWrapperPlatformSecLib Cleanup Nate DeSimone
@ 2019-11-14 6:06 ` Nate DeSimone
2019-11-14 15:15 ` Chiu, Chasel
` (2 more replies)
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 02/13] KabylakeOpenBoardPkg: Update location of SiliconInitLib Nate DeSimone
` (11 subsequent siblings)
12 siblings, 3 replies; 44+ messages in thread
From: Nate DeSimone @ 2019-11-14 6:06 UTC (permalink / raw)
To: devel; +Cc: Chasel Chiu, Michael Kubacki, Sai Chaganty
This library contains PEI phase only code. For example,
ClearIchSmiAndWake() calls PeiServicesGetBootMode().
Accordingly, this library should have never been marked as
a BASE library.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
.../PeiSiliconInitLib.inf} | 3 ++-
.../{SiliconInitLib => PeiSiliconInitLib}/SiliconInit.c | 0
.../{SiliconInitLib => PeiSiliconInitLib}/SiliconInitPreMem.c | 0
3 files changed, 2 insertions(+), 1 deletion(-)
rename Silicon/Intel/KabylakeSiliconPkg/Library/{SiliconInitLib/SiliconInitLib.inf => PeiSiliconInitLib/PeiSiliconInitLib.inf} (91%)
rename Silicon/Intel/KabylakeSiliconPkg/Library/{SiliconInitLib => PeiSiliconInitLib}/SiliconInit.c (100%)
rename Silicon/Intel/KabylakeSiliconPkg/Library/{SiliconInitLib => PeiSiliconInitLib}/SiliconInitPreMem.c (100%)
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
similarity index 91%
rename from Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf
rename to Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
index 132080e876..ff83bf2835 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf
+++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
@@ -11,8 +11,9 @@
BASE_NAME = SiliconInitLib
FILE_GUID = 72CD3A7B-FEA5-4F5E-9165-4DD12187BB13
VERSION_STRING = 1.0
- MODULE_TYPE = BASE
+ MODULE_TYPE = PEIM
LIBRARY_CLASS = SiliconInitLib
+
#
# The following information is for reference only and not required by the build tools.
#
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInit.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c
similarity index 100%
rename from Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInit.c
rename to Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitPreMem.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMem.c
similarity index 100%
rename from Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitPreMem.c
rename to Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMem.c
--
2.23.0.windows.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [edk2-platforms] [PATCH V1 02/13] KabylakeOpenBoardPkg: Update location of SiliconInitLib
2019-11-14 6:06 [edk2-platforms] [PATCH V1 00/13] SecFspWrapperPlatformSecLib Cleanup Nate DeSimone
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 01/13] KabylakeSiliconPkg: Change MODULE_TYPE of SiliconInitLib to PEIM Nate DeSimone
@ 2019-11-14 6:06 ` Nate DeSimone
2019-11-14 15:15 ` Chiu, Chasel
2019-11-16 2:53 ` Kubacki, Michael A
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 03/13] KabylakeSiliconPkg: Cleanup old comments Nate DeSimone
` (10 subsequent siblings)
12 siblings, 2 replies; 44+ messages in thread
From: Nate DeSimone @ 2019-11-14 6:06 UTC (permalink / raw)
To: devel; +Cc: Chasel Chiu, Michael Kubacki, Jeremy Soller
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc | 2 +-
.../Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
index e43c944201..2bc2b4126b 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
@@ -105,7 +105,7 @@
# Silicon Initialization Package
#######################################
ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.inf
- SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/SiliconInitLib/SiliconInitLib.inf
+ SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf
#####################################
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
index 1ce473432a..77e4a6a610 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
@@ -133,7 +133,7 @@
# Silicon Initialization Package
#######################################
ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.inf
- SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/SiliconInitLib/SiliconInitLib.inf
+ SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
#
--
2.23.0.windows.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [edk2-platforms] [PATCH V1 03/13] KabylakeSiliconPkg: Cleanup old comments
2019-11-14 6:06 [edk2-platforms] [PATCH V1 00/13] SecFspWrapperPlatformSecLib Cleanup Nate DeSimone
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 01/13] KabylakeSiliconPkg: Change MODULE_TYPE of SiliconInitLib to PEIM Nate DeSimone
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 02/13] KabylakeOpenBoardPkg: Update location of SiliconInitLib Nate DeSimone
@ 2019-11-14 6:06 ` Nate DeSimone
2019-11-14 15:16 ` Chiu, Chasel
` (2 more replies)
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 04/13] CoffeeLakeSiliconPkg: Move TcoWdtHob.h Nate DeSimone
` (9 subsequent siblings)
12 siblings, 3 replies; 44+ messages in thread
From: Nate DeSimone @ 2019-11-14 6:06 UTC (permalink / raw)
To: devel; +Cc: Chasel Chiu, Michael Kubacki, Sai Chaganty
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
.../Library/PeiSiliconInitLib/SiliconInitPreMem.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMem.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMem.c
index 65a67a6795..384877fba3 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMem.c
+++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMem.c
@@ -31,9 +31,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/PeiServicesTablePointerLib.h>
#include <Library/PchSerialIoLib.h>
-//@todo it should be moved to Si Pkg.
/**
- Early Platform PCH initialization
+ Early PCH initialization
**/
VOID
EarlySiliconInit (
@@ -233,4 +232,3 @@ SiliconInit (
}
}
-
--
2.23.0.windows.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [edk2-platforms] [PATCH V1 04/13] CoffeeLakeSiliconPkg: Move TcoWdtHob.h
2019-11-14 6:06 [edk2-platforms] [PATCH V1 00/13] SecFspWrapperPlatformSecLib Cleanup Nate DeSimone
` (2 preceding siblings ...)
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 03/13] KabylakeSiliconPkg: Cleanup old comments Nate DeSimone
@ 2019-11-14 6:06 ` Nate DeSimone
2019-11-14 15:16 ` Chiu, Chasel
` (2 more replies)
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 05/13] CoffeelakeSiliconPkg: Add SiliconInitLib Nate DeSimone
` (8 subsequent siblings)
12 siblings, 3 replies; 44+ messages in thread
From: Nate DeSimone @ 2019-11-14 6:06 UTC (permalink / raw)
To: devel; +Cc: Chasel Chiu, Michael Kubacki, Sai Chaganty
Moves TcoWdtHob.h from WhiskeylakeOpenBoardPkg to CoffeelakeSiliconPkg.
Oddly, gTcoWdtHobGuid was defined in CoffeelakeSiliconPkg/SiPkg.dec
while the HOB definition itself was in WhiskeylakeOpenBoardPkg,
this change cleans up the disparity.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
.../Intel/CoffeelakeSiliconPkg}/Include/Guid/TcoWdtHob.h | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename {Platform/Intel/WhiskeylakeOpenBoardPkg => Silicon/Intel/CoffeelakeSiliconPkg}/Include/Guid/TcoWdtHob.h (100%)
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Guid/TcoWdtHob.h b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Guid/TcoWdtHob.h
similarity index 100%
rename from Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Guid/TcoWdtHob.h
rename to Silicon/Intel/CoffeelakeSiliconPkg/Include/Guid/TcoWdtHob.h
--
2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* [edk2-platforms] [PATCH V1 05/13] CoffeelakeSiliconPkg: Add SiliconInitLib
2019-11-14 6:06 [edk2-platforms] [PATCH V1 00/13] SecFspWrapperPlatformSecLib Cleanup Nate DeSimone
` (3 preceding siblings ...)
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 04/13] CoffeeLakeSiliconPkg: Move TcoWdtHob.h Nate DeSimone
@ 2019-11-14 6:06 ` Nate DeSimone
2019-11-14 15:16 ` Chiu, Chasel
` (2 more replies)
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 06/13] WhiskeylakeOpenBoardPkg: Add SiliconInitLib APIs to BoardInitLib Nate DeSimone
` (7 subsequent siblings)
12 siblings, 3 replies; 44+ messages in thread
From: Nate DeSimone @ 2019-11-14 6:06 UTC (permalink / raw)
To: devel; +Cc: Chasel Chiu, Michael Kubacki, Sai Chaganty
SiliconInitLib contains Silicon Init APIs that can be reused
by BoardInitLib. It is expected that several implementations
of BoardInitLib exist for a given SOC, these APIs allow the
various BoardInitLib implementations to reuse common silicon
initialization code. This matches the implementation already
found in KabylakeSiliconPkg. This change also adds halting
the TCO watch dog timer to PEI, which was previously done in SEC.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
.../Include/Library/SiliconInitLib.h | 28 +++++
.../PeiSiliconInitLib/PeiSiliconInitLib.inf | 46 ++++++++
.../Library/PeiSiliconInitLib/SiliconInit.c | 19 +++
.../PeiSiliconInitLib/SiliconInitPreMem.c | 109 ++++++++++++++++++
4 files changed, 202 insertions(+)
create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.h
create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c
create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMem.c
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.h
new file mode 100644
index 0000000000..a3411126a7
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.h
@@ -0,0 +1,28 @@
+/** @file
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _SILICON_INIT_LIB_H_
+#define _SILICON_INIT_LIB_H_
+
+#include <PiPei.h>
+
+VOID
+EarlySiliconInit (
+ VOID
+ );
+
+VOID
+SiliconInit (
+ VOID
+ );
+
+VOID
+LateSiliconInit (
+ VOID
+ );
+
+#endif
\ No newline at end of file
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
new file mode 100644
index 0000000000..47da5f608b
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
@@ -0,0 +1,46 @@
+### @file
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = SiliconInitLib
+ FILE_GUID = 82F2ACF0-2EBE-48C8-AC58-9D0F8BC1E16E
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ LIBRARY_CLASS = SiliconInitLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ HobLib
+ IoLib
+ PcdLib
+ PeiServicesLib
+ PchCycleDecodingLib
+ PmcLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ SiliconInit.c
+ SiliconInitPreMem.c
+
+[Guids]
+ gTcoWdtHobGuid ## CONSUMES
+
+[Pcd]
+ gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ## CONSUMES
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c
new file mode 100644
index 0000000000..122c02a3e5
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c
@@ -0,0 +1,19 @@
+/** @file
+ Silicon Init APIs for MinPlatform BoardInitLib implementations.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+
+/**
+ Late PCH Init
+**/
+VOID
+LateSiliconInit (
+ VOID
+ )
+{
+}
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMem.c b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMem.c
new file mode 100644
index 0000000000..23e4a3d4a0
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMem.c
@@ -0,0 +1,109 @@
+/** @file
+ Silicon Init APIs for MinPlatform BoardInitLib implementations.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Guid/TcoWdtHob.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PmcLib.h>
+#include <Register/PchRegsLpc.h>
+#include <Register/PchRegsPmc.h>
+
+/**
+ Early PCH initialization
+**/
+VOID
+EarlySiliconInit (
+ VOID
+ )
+{
+ UINT16 Data16;
+ UINT8 Data8;
+ UINT8 TcoRebootHappened;
+ TCO_WDT_HOB *TcoWdtHobPtr;
+ EFI_STATUS Status;
+
+ ///
+ /// LPC I/O Configuration
+ ///
+ PchLpcIoDecodeRangesSet (
+ (V_LPC_CFG_IOD_LPT_378 << N_LPC_CFG_IOD_LPT) |
+ (V_LPC_CFG_IOD_COMB_3E8 << N_LPC_CFG_IOD_COMB) |
+ (V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA)
+ );
+
+ PchLpcIoEnableDecodingSet (
+ B_LPC_CFG_IOE_ME2 |
+ B_LPC_CFG_IOE_SE |
+ B_LPC_CFG_IOE_ME1 |
+ B_LPC_CFG_IOE_KE |
+ B_LPC_CFG_IOE_HGE |
+ B_LPC_CFG_IOE_LGE |
+ B_LPC_CFG_IOE_FDE |
+ B_LPC_CFG_IOE_PPE |
+ B_LPC_CFG_IOE_CBE |
+ B_LPC_CFG_IOE_CAE
+ );
+
+ ///
+ /// Halt the TCO timer
+ ///
+ Data16 = IoRead16 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT);
+ Data16 |= B_TCO_IO_TCO1_CNT_TMR_HLT;
+ IoWrite16 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT, Data16);
+
+ ///
+ /// Read the Second TO status bit
+ ///
+ Data8 = IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS);
+ if ((Data8 & B_TCO_IO_TCO2_STS_SECOND_TO) == B_TCO_IO_TCO2_STS_SECOND_TO) {
+ TcoRebootHappened = 1;
+ DEBUG ((DEBUG_INFO, "PlatformInitPreMem - TCO Second TO status bit is set. This might be a TCO reboot\n"));
+ }
+ else {
+ TcoRebootHappened = 0;
+ }
+
+ ///
+ /// Create HOB
+ ///
+ Status = PeiServicesCreateHob (EFI_HOB_TYPE_GUID_EXTENSION, sizeof(TCO_WDT_HOB), (VOID **)&TcoWdtHobPtr);
+ if (!EFI_ERROR (Status)) {
+ TcoWdtHobPtr->Header.Name = gTcoWdtHobGuid;
+ TcoWdtHobPtr->TcoRebootHappened = TcoRebootHappened;
+ }
+
+ ///
+ /// Clear the Second TO status bit
+ ///
+ IoWrite8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS, B_TCO_IO_TCO2_STS_SECOND_TO);
+}
+
+/**
+ Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal inversion registers
+
+**/
+VOID
+SiliconInit (
+ VOID
+ )
+{
+ UINT16 ABase;
+
+ ABase = PmcGetAcpiBase ();
+
+ ///
+ /// Clear all pending SMI. On S3 clear power button enable so it will not generate an SMI.
+ ///
+ IoWrite16 (ABase + R_ACPI_IO_PM1_EN, 0);
+ IoWrite32 (ABase + R_ACPI_IO_GPE0_EN_127_96, 0);
+}
--
2.23.0.windows.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [edk2-platforms] [PATCH V1 06/13] WhiskeylakeOpenBoardPkg: Add SiliconInitLib APIs to BoardInitLib
2019-11-14 6:06 [edk2-platforms] [PATCH V1 00/13] SecFspWrapperPlatformSecLib Cleanup Nate DeSimone
` (4 preceding siblings ...)
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 05/13] CoffeelakeSiliconPkg: Add SiliconInitLib Nate DeSimone
@ 2019-11-14 6:06 ` Nate DeSimone
2019-11-14 15:16 ` Chiu, Chasel
2019-11-16 2:53 ` Kubacki, Michael A
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 07/13] WhiskeylakeOpenBoardPkg: Whitespace cleanup in BoardInitLib Nate DeSimone
` (6 subsequent siblings)
12 siblings, 2 replies; 44+ messages in thread
From: Nate DeSimone @ 2019-11-14 6:06 UTC (permalink / raw)
To: devel; +Cc: Chasel Chiu, Michael Kubacki
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
.../BoardInitLib/PeiBoardInitPostMemLib.inf | 1 +
.../BoardInitLib/PeiBoardInitPreMemLib.inf | 1 +
.../PeiMultiBoardInitPostMemLib.inf | 1 +
.../PeiMultiBoardInitPreMemLib.inf | 2 +-
.../PeiWhiskeylakeURvpInitPostMemLib.c | 6 +-
.../PeiWhiskeylakeURvpInitPreMemLib.c | 89 ++-----------------
.../BoardInitLib/WhiskeylakeURvpInit.h | 1 +
.../WhiskeylakeURvp/OpenBoardPkg.dsc | 5 ++
8 files changed, 24 insertions(+), 82 deletions(-)
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
index 9bf4d127c5..affc5c56ad 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
@@ -26,6 +26,7 @@
HdaVerbTableLib
MemoryAllocationLib
PcdLib
+ SiliconInitLib
[Packages]
MinPlatformPkg/MinPlatformPkg.dec
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
index 4ab80f9eb3..40e20285e0 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
@@ -23,6 +23,7 @@
BaseMemoryLib
MemoryAllocationLib
PcdLib
+ SiliconInitLib
[Packages]
MinPlatformPkg/MinPlatformPkg.dec
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
index c043e32638..21dc2f70c0 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
@@ -30,6 +30,7 @@
PeiPlatformHookLib
PeiPolicyInitLib
PchInfoLib
+ SiliconInitLib
[Packages]
MinPlatformPkg/MinPlatformPkg.dec
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
index cd0315377a..7389f1dfcd 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
@@ -31,6 +31,7 @@
PeiPlatformHookLib
PeiPolicyInitLib
PlatformHookLib
+ SiliconInitLib
StallPpiLib
[Packages]
@@ -57,7 +58,6 @@
[Guids]
gPchGeneralPreMemConfigGuid ## CONSUMES
- gTcoWdtHobGuid ## CONSUMES
[Pcd]
gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPostMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
index 9413620a4a..248a6657d5 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
@@ -430,6 +430,10 @@ WhiskeylakeURvpBoardInitBeforeSiliconInit (
//
Status = UpdateChipsetInitPtr();
+ ///
+ /// Do Late PCH init
+ ///
+ LateSiliconInit ();
+
return EFI_SUCCESS;
}
-
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPreMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
index 0124888244..055d731651 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
@@ -45,7 +45,6 @@
#include <Library/PciSegmentLib.h>
#include <PeiPlatformHookLib.h>
#include <FirwmareConfigurations.h>
-#include <Guid/TcoWdtHob.h>
#include <Library/OcWdtLib.h>
///
@@ -232,50 +231,8 @@ BoardMiscInitPreMem(
return EFI_SUCCESS;
}
-//@todo it should be moved to Si Pkg.
-/**
-Early Platform PCH initialization
-**/
-VOID
-EarlyPlatformPchInit(
- VOID
-)
-{
- UINT8 Data8;
- UINT8 TcoRebootHappened;
- TCO_WDT_HOB *TcoWdtHobPtr;
- EFI_STATUS Status;
-
- ///
- /// Read the Second TO status bit
- ///
- Data8 = IoRead8(PcdGet16(PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS);
- if ((Data8 & B_TCO_IO_TCO2_STS_SECOND_TO) == B_TCO_IO_TCO2_STS_SECOND_TO) {
- TcoRebootHappened = 1;
- DEBUG((DEBUG_INFO, "PlatformInitPreMem - TCO Second TO status bit is set. This might be a TCO reboot\n"));
- }
- else {
- TcoRebootHappened = 0;
- }
-
- ///
- /// Create HOB
- ///
- Status = PeiServicesCreateHob(EFI_HOB_TYPE_GUID_EXTENSION, sizeof(TCO_WDT_HOB), (VOID **)&TcoWdtHobPtr);
- if (!EFI_ERROR(Status)) {
- TcoWdtHobPtr->Header.Name = gTcoWdtHobGuid;
- TcoWdtHobPtr->TcoRebootHappened = TcoRebootHappened;
- }
-
- ///
- /// Clear the Second TO status bit
- ///
- IoWrite8(PcdGet16(PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS, B_TCO_IO_TCO2_STS_SECOND_TO);
-}
-
/**
Board configuration initialization in the pre-memory boot phase.
-
**/
VOID
BoardConfigInitPreMem (
@@ -341,7 +298,6 @@ PlatformInitPreMemCallBack(
)
{
EFI_STATUS Status;
- UINT16 ABase;
UINT8 FwConfig;
//
@@ -378,16 +334,8 @@ PlatformInitPreMemCallBack(
///
/// Configure GPIO and SIO
///
- Status = BoardInitPreMem();
- ASSERT_EFI_ERROR(Status);
-
- ABase = PmcGetAcpiBase();
-
- ///
- /// Clear all pending SMI. On S3 clear power button enable so it will not generate an SMI.
- ///
- IoWrite16(ABase + R_ACPI_IO_PM1_EN, 0);
- IoWrite32(ABase + R_ACPI_IO_GPE0_EN_127_96, 0);
+ Status = BoardInitPreMem ();
+ ASSERT_EFI_ERROR (Status);
///
/// Install Pre Memory PPIs
@@ -550,12 +498,6 @@ WhiskeylakeURvpInitPreMem (
Status = InstallStallPpi();
ASSERT_EFI_ERROR(Status);
- ///@todo it should be moved to Si Pkg.
- ///
- /// Do Early PCH init
- ///
- EarlyPlatformPchInit();
-
//
// Install PCH RESET PPI and EFI RESET2 PeiService
//
@@ -588,6 +530,11 @@ WhiskeylakeURvpBoardInitBeforeMemoryInit (
VOID
)
{
+ ///
+ /// Do basic PCH init
+ ///
+ SiliconInit ();
+
WhiskeylakeURvpInitPreMem ();
return EFI_SUCCESS;
@@ -600,27 +547,9 @@ WhiskeylakeURvpBoardDebugInit (
)
{
///
- /// LPC I/O Configuration
+ /// Do Early PCH init
///
- PchLpcIoDecodeRangesSet (
- (V_LPC_CFG_IOD_LPT_378 << N_LPC_CFG_IOD_LPT) |
- (V_LPC_CFG_IOD_COMB_3E8 << N_LPC_CFG_IOD_COMB) |
- (V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA)
- );
-
- PchLpcIoEnableDecodingSet (
- B_LPC_CFG_IOE_ME2 |
- B_LPC_CFG_IOE_SE |
- B_LPC_CFG_IOE_ME1 |
- B_LPC_CFG_IOE_KE |
- B_LPC_CFG_IOE_HGE |
- B_LPC_CFG_IOE_LGE |
- B_LPC_CFG_IOE_FDE |
- B_LPC_CFG_IOE_PPE |
- B_LPC_CFG_IOE_CBE |
- B_LPC_CFG_IOE_CAE
- );
-
+ EarlySiliconInit ();
return EFI_SUCCESS;
}
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/WhiskeylakeURvpInit.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/WhiskeylakeURvpInit.h
index 325bcb41df..d3a709b2a9 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/WhiskeylakeURvpInit.h
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/WhiskeylakeURvpInit.h
@@ -15,6 +15,7 @@
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Library/GpioLib.h>
+#include <Library/SiliconInitLib.h>
#include <Ppi/SiPolicy.h>
#include <PchHsioPtssTables.h>
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
index cdaf47b6f7..3cd0478021 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
@@ -154,6 +154,11 @@
TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLib.inf
[LibraryClasses.common.PEIM]
+ #######################################
+ # Silicon Initialization Package
+ #######################################
+ SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
+
#######################################
# Platform Package
#######################################
--
2.23.0.windows.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [edk2-platforms] [PATCH V1 07/13] WhiskeylakeOpenBoardPkg: Whitespace cleanup in BoardInitLib
2019-11-14 6:06 [edk2-platforms] [PATCH V1 00/13] SecFspWrapperPlatformSecLib Cleanup Nate DeSimone
` (5 preceding siblings ...)
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 06/13] WhiskeylakeOpenBoardPkg: Add SiliconInitLib APIs to BoardInitLib Nate DeSimone
@ 2019-11-14 6:06 ` Nate DeSimone
2019-11-14 15:17 ` Chiu, Chasel
2019-11-16 2:53 ` Kubacki, Michael A
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 08/13] WhiskeylakeOpenBoardPkg: Remove SecFspWrapperPlatformSecLib override Nate DeSimone
` (5 subsequent siblings)
12 siblings, 2 replies; 44+ messages in thread
From: Nate DeSimone @ 2019-11-14 6:06 UTC (permalink / raw)
To: devel; +Cc: Chasel Chiu, Michael Kubacki
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
.../PeiWhiskeylakeURvpInitPostMemLib.c | 185 ++++++-------
.../PeiWhiskeylakeURvpInitPreMemLib.c | 257 +++++++++---------
2 files changed, 216 insertions(+), 226 deletions(-)
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPostMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
index 248a6657d5..827af6bb57 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
@@ -33,16 +33,16 @@
#include "WhiskeylakeURvpInit.h"
EFI_STATUS
-BoardFunctionInit(
+BoardFunctionInit (
IN UINT16 BoardId
-);
+ );
/**
-GPIO init function for PEI post memory phase.
+ GPIO init function for PEI post memory phase.
-@param[in] BoardId An unsigned integrer represent the board id.
+ @param[in] BoardId An unsigned integrer represent the board id.
-@retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_SUCCESS The function completed successfully.
**/
EFI_STATUS
BoardGpioInit(
@@ -72,48 +72,48 @@ BoardGpioInit(
}
/**
-Touch panel GPIO init function for PEI post memory phase.
+ Touch panel GPIO init function for PEI post memory phase.
-@param[in] BoardId An unsigned integrer represent the board id.
+ @param[in] BoardId An unsigned integrer represent the board id.
-@retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_SUCCESS The function completed successfully.
**/
EFI_STATUS
-TouchPanelGpioInit(
+TouchPanelGpioInit (
IN UINT16 BoardId
-)
+ )
{
switch (BoardId) {
default:
- PcdSet32S(PcdBoardGpioTableTouchPanel, 0);
+ PcdSet32S (PcdBoardGpioTableTouchPanel, 0);
break;
}
return EFI_SUCCESS;
}
/**
-Misc. init function for PEI post memory phase.
+ Misc. init function for PEI post memory phase.
-@param[in] BoardId An unsigned integrer represent the board id.
+ @param[in] BoardId An unsigned integrer represent the board id.
-@retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_SUCCESS The function completed successfully.
**/
EFI_STATUS
-BoardMiscInit(
+BoardMiscInit (
IN UINT16 BoardId
-)
+ )
{
- PcdSetBoolS(PcdDebugUsbUartEnable, FALSE);
+ PcdSetBoolS (PcdDebugUsbUartEnable, FALSE);
switch (BoardId) {
case BoardIdWhiskeyLakeRvp:
- PcdSetBoolS(PcdMipiCamGpioEnable, TRUE);
+ PcdSetBoolS (PcdMipiCamGpioEnable, TRUE);
break;
default:
- PcdSetBoolS(PcdMipiCamGpioEnable, FALSE);
+ PcdSetBoolS (PcdMipiCamGpioEnable, FALSE);
break;
}
@@ -121,25 +121,22 @@ BoardMiscInit(
}
/**
-Security GPIO init function for PEI post memory phase.
+ Security GPIO init function for PEI post memory phase.
-@param[in] BoardId An unsigned integrer represent the board id.
+ @param[in] BoardId An unsigned integrer represent the board id.
-@retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_SUCCESS The function completed successfully.
**/
EFI_STATUS
BoardSecurityInit (
IN UINT16 BoardId
-)
+ )
{
switch (BoardId) {
-
case BoardIdWhiskeyLakeRvp:
-
// TPM interrupt connects to GPIO_CNL_H_GPP_A_7
PcdSet32S (PcdTpm2CurrentIrqNum, 0x1F);
break;
-
}
return EFI_SUCCESS;
@@ -147,7 +144,6 @@ BoardSecurityInit (
/**
Board configuration initialization in the post-memory boot phase.
-
**/
VOID
BoardConfigInit (
@@ -178,27 +174,26 @@ BoardConfigInit (
ASSERT_EFI_ERROR (Status);
}
-//@todo Review this functionality and if it is required for WHL SDS
/**
-Create the HOB for hotkey status for 'Attempt USB First' feature
+ Create the HOB for hotkey status for 'Attempt USB First' feature
-@retval EFI_SUCCESS HOB Creating successful.
-@retval Others HOB Creating failed.
+ @retval EFI_SUCCESS HOB Creating successful.
+ @retval Others HOB Creating failed.
**/
EFI_STATUS
-CreateAttemptUsbFirstHotkeyInfoHob(
+CreateAttemptUsbFirstHotkeyInfoHob (
VOID
-)
+ )
{
EFI_STATUS Status;
ATTEMPT_USB_FIRST_HOTKEY_INFO AttemptUsbFirstHotkeyInfo;
Status = EFI_SUCCESS;
- ZeroMem(
+ ZeroMem (
&AttemptUsbFirstHotkeyInfo,
- sizeof(AttemptUsbFirstHotkeyInfo)
- );
+ sizeof (AttemptUsbFirstHotkeyInfo)
+ );
AttemptUsbFirstHotkeyInfo.RevisonId = 0;
AttemptUsbFirstHotkeyInfo.HotkeyTriggered = FALSE;
@@ -206,29 +201,29 @@ CreateAttemptUsbFirstHotkeyInfoHob(
///
/// Build HOB for Attempt USB First feature
///
- BuildGuidDataHob(
+ BuildGuidDataHob (
&gAttemptUsbFirstHotkeyInfoHobGuid,
&(AttemptUsbFirstHotkeyInfo),
- sizeof(ATTEMPT_USB_FIRST_HOTKEY_INFO)
- );
+ sizeof (ATTEMPT_USB_FIRST_HOTKEY_INFO)
+ );
return Status;
}
/**
-Search and identify the physical address of a
-file module inside the FW_BINARIES_FV_SIGNED FV
+ Search and identify the physical address of a
+ file module inside the FW_BINARIES_FV_SIGNED FV
-@retval EFI_SUCCESS If address has been found
-@retval Others If address has not been found
+ @retval EFI_SUCCESS If address has been found
+ @retval Others If address has not been found
**/
EFI_STATUS
-FindModuleInFlash2(
+FindModuleInFlash2 (
IN EFI_FIRMWARE_VOLUME_HEADER *FvHeader,
IN EFI_GUID *GuidPtr,
IN OUT UINT32 *ModulePtr,
IN OUT UINT32 *ModuleSize
-)
+ )
{
EFI_FFS_FILE_HEADER *FfsHeader;
EFI_FV_FILE_INFO FileInfo;
@@ -246,57 +241,57 @@ FindModuleInFlash2(
//
// Locate FV_IMAGE file type in the FW_BINARIES_FV_SIGNED firmware volume
//
- Status = PeiServicesFfsFindNextFile(EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE, FvHeader, &FileHandle);
- if (EFI_ERROR(Status)) {
+ Status = PeiServicesFfsFindNextFile (EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE, FvHeader, &FileHandle);
+ if (EFI_ERROR (Status)) {
// unable to find FV_IMAGE file in this FV
break;
}
FfsHeader = (EFI_FFS_FILE_HEADER*)FileHandle;
- DEBUG((DEBUG_INFO, "FfsHeader 0x%X:\n", FfsHeader));
- DEBUG((DEBUG_INFO, " Name = 0x%g\n", &FfsHeader->Name));
- DEBUG((DEBUG_INFO, " Type = 0x%X\n", FfsHeader->Type));
- if (IS_FFS_FILE2(FfsHeader)) {
- DEBUG((DEBUG_INFO, " Size = 0x%X\n", FFS_FILE2_SIZE(FfsHeader)));
+ DEBUG ((DEBUG_INFO, "FfsHeader 0x%X:\n", FfsHeader));
+ DEBUG ((DEBUG_INFO, " Name = 0x%g\n", &FfsHeader->Name));
+ DEBUG ((DEBUG_INFO, " Type = 0x%X\n", FfsHeader->Type));
+ if (IS_FFS_FILE2 (FfsHeader)) {
+ DEBUG ((DEBUG_INFO, " Size = 0x%X\n", FFS_FILE2_SIZE(FfsHeader)));
}
else {
- DEBUG((DEBUG_INFO, " Size = 0x%X\n", FFS_FILE_SIZE(FfsHeader)));
+ DEBUG ((DEBUG_INFO, " Size = 0x%X\n", FFS_FILE_SIZE(FfsHeader)));
}
//
// Locate FW_BINARIES_FV FV_IMAGE Section
//
- Status = PeiServicesFfsFindSectionData(EFI_SECTION_FIRMWARE_VOLUME_IMAGE, FileHandle, &FileBuffer);
- if (EFI_ERROR(Status)) {
+ Status = PeiServicesFfsFindSectionData (EFI_SECTION_FIRMWARE_VOLUME_IMAGE, FileHandle, &FileBuffer);
+ if (EFI_ERROR (Status)) {
// continue to search for the next FV_IMAGE file
- DEBUG((DEBUG_INFO, "FW_BINARIES_FV section not found. Status = %r\n", Status));
+ DEBUG ((DEBUG_INFO, "FW_BINARIES_FV section not found. Status = %r\n", Status));
continue;
}
SectionHeader = (EFI_COMMON_SECTION_HEADER *)FileBuffer;
- DEBUG((DEBUG_INFO, "GUIDED SectionHeader 0x%X:\n",
+ DEBUG ((DEBUG_INFO, "GUIDED SectionHeader 0x%X:\n",
(UINT32)(UINT8 *)SectionHeader));
if (IS_SECTION2(SectionHeader)) {
- DEBUG((DEBUG_INFO, " Guid = 0x%g\n",
+ DEBUG ((DEBUG_INFO, " Guid = 0x%g\n",
&((EFI_GUID_DEFINED_SECTION2 *)SectionHeader)->SectionDefinitionGuid));
- DEBUG((DEBUG_INFO, " DataOfset = 0x%X\n",
+ DEBUG ((DEBUG_INFO, " DataOfset = 0x%X\n",
((EFI_GUID_DEFINED_SECTION2 *)SectionHeader)->DataOffset));
}
else {
- DEBUG((DEBUG_INFO, " Guid = 0x%g\n",
+ DEBUG ((DEBUG_INFO, " Guid = 0x%g\n",
&((EFI_GUID_DEFINED_SECTION *)SectionHeader)->SectionDefinitionGuid));
- DEBUG((DEBUG_INFO, " DataOfset = 0x%X\n",
+ DEBUG ((DEBUG_INFO, " DataOfset = 0x%X\n",
((EFI_GUID_DEFINED_SECTION *)SectionHeader)->DataOffset));
}
- DEBUG((DEBUG_INFO, " Type = 0x%X\n", SectionHeader->Type));
+ DEBUG ((DEBUG_INFO, " Type = 0x%X\n", SectionHeader->Type));
//
// Locate Firmware File System file within Firmware Volume
//
- Status = PeiServicesFfsFindFileByName(GuidPtr, FileBuffer, (VOID **)&FfsHeader);
- if (EFI_ERROR(Status)) {
+ Status = PeiServicesFfsFindFileByName (GuidPtr, FileBuffer, (VOID **)&FfsHeader);
+ if (EFI_ERROR (Status)) {
// continue to search for the next FV_IMAGE file
- DEBUG((DEBUG_INFO, "Module not found. Status = %r\n", Status));
+ DEBUG ((DEBUG_INFO, "Module not found. Status = %r\n", Status));
continue;
}
@@ -305,10 +300,10 @@ FindModuleInFlash2(
//
// Get File Information
//
- Status = PeiServicesFfsGetFileInfo(FfsHeader, &FileInfo);
- if (!EFI_ERROR(Status)) {
+ Status = PeiServicesFfsGetFileInfo (FfsHeader, &FileInfo);
+ if (!EFI_ERROR (Status)) {
*ModuleSize = (UINT32)FileInfo.BufferSize;
- DEBUG((DEBUG_INFO, "Module {0x%g} found at = 0x%X, Size = 0x%X\n",
+ DEBUG ((DEBUG_INFO, "Module {0x%g} found at = 0x%X, Size = 0x%X\n",
&FfsHeader->Name, *ModulePtr, *ModuleSize));
return Status;
}
@@ -318,15 +313,15 @@ FindModuleInFlash2(
}
/**
-Get the ChipsetInit Binary pointer.
+ Get the ChipsetInit Binary pointer.
-@retval EFI_SUCCESS - ChipsetInit Binary found.
-@retval EFI_NOT_FOUND - ChipsetInit Binary not found.
+ @retval EFI_SUCCESS - ChipsetInit Binary found.
+ @retval EFI_NOT_FOUND - ChipsetInit Binary not found.
**/
EFI_STATUS
-UpdateChipsetInitPtr(
+UpdateChipsetInitPtr (
VOID
-)
+ )
{
EFI_STATUS Status;
PCH_STEPPING PchStep;
@@ -339,18 +334,18 @@ UpdateChipsetInitPtr(
ModuleAddr = 0;
ModuleSize = 0;
- PchStep = PchStepping();
+ PchStep = PchStepping ();
- Status = PeiServicesLocatePpi(
+ Status = PeiServicesLocatePpi (
&gSiPolicyPpiGuid,
0,
NULL,
(VOID **)&SiPolicyPpi
- );
- ASSERT_EFI_ERROR(Status);
+ );
+ ASSERT_EFI_ERROR (Status);
- Status = GetConfigBlock((VOID *)SiPolicyPpi, &gHsioConfigGuid, (VOID *)&HsioConfig);
- ASSERT_EFI_ERROR(Status);
+ Status = GetConfigBlock ((VOID *)SiPolicyPpi, &gHsioConfigGuid, (VOID *)&HsioConfig);
+ ASSERT_EFI_ERROR (Status);
ChipsetInitBinaryGuidPtr = NULL;
if (IsPchLp()) {
@@ -358,22 +353,20 @@ UpdateChipsetInitPtr(
case PCH_D0:
case PCH_D1:
ChipsetInitBinaryGuidPtr = &gCnlPchLpChipsetInitTableDxGuid;
- DEBUG((DEBUG_INFO, "Using CnlPchLpChipsetInitTable_Dx table \n"));
+ DEBUG ((DEBUG_INFO, "Using CnlPchLpChipsetInitTable_Dx table \n"));
break;
default:
return EFI_NOT_FOUND;
}
- }
- else {
+ } else {
return EFI_NOT_FOUND;
}
//
// Locate Firmware Volume header
//
- // FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)GetFvBinaryBase();
- FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *) FixedPcdGet32(PcdFlashFvPostMemoryBase);
- Status = FindModuleInFlash2(FvHeader, ChipsetInitBinaryGuidPtr, &ModuleAddr, &ModuleSize);
+ FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *) FixedPcdGet32 (PcdFlashFvPostMemoryBase);
+ Status = FindModuleInFlash2 (FvHeader, ChipsetInitBinaryGuidPtr, &ModuleAddr, &ModuleSize);
//
// Get ChipsetInit Binary Pointer
//
@@ -384,8 +377,8 @@ UpdateChipsetInitPtr(
//
HsioConfig->ChipsetInitBinLen = ModuleSize;
- DEBUG((DEBUG_INFO, "ChipsetInit Binary Location: %x\n", HsioConfig->ChipsetInitBinPtr));
- DEBUG((DEBUG_INFO, "ChipsetInit Binary Size: %x\n", HsioConfig->ChipsetInitBinLen));
+ DEBUG ((DEBUG_INFO, "ChipsetInit Binary Location: %x\n", HsioConfig->ChipsetInitBinPtr));
+ DEBUG ((DEBUG_INFO, "ChipsetInit Binary Size: %x\n", HsioConfig->ChipsetInitBinLen));
return Status;
}
@@ -401,34 +394,34 @@ WhiskeylakeURvpBoardInitBeforeSiliconInit (
VOID
)
{
- EFI_STATUS Status;
- UINT8 FwConfig;
+ EFI_STATUS Status;
+ UINT8 FwConfig;
- BoardConfigInit();
+ BoardConfigInit ();
//
// Configure GPIO and SIO
//
- Status = BoardInit();
- ASSERT_EFI_ERROR(Status);
+ Status = BoardInit ();
+ ASSERT_EFI_ERROR (Status);
FwConfig = FwConfigProduction;
- PeiPolicyInit(FwConfig);
+ PeiPolicyInit (FwConfig);
//
// Create USB Boot First hotkey information HOB
//
- CreateAttemptUsbFirstHotkeyInfoHob();
+ CreateAttemptUsbFirstHotkeyInfoHob ();
//
// Initializing Platform Specific Programming
//
- Status = PlatformSpecificInit();
+ Status = PlatformSpecificInit ();
ASSERT_EFI_ERROR(Status);
//
// Update ChipsetInitPtr
//
- Status = UpdateChipsetInitPtr();
+ Status = UpdateChipsetInitPtr ();
///
/// Do Late PCH init
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPreMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
index 055d731651..75813ff351 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
@@ -68,84 +68,84 @@ GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorSklRvp1[SA_MRC_MAX_RCOMP
GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetSklRvp1[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 40, 23, 40 };
GLOBAL_REMOVE_IF_UNREFERENCED MEMORY_MAP MmioMap[] = {
- { FixedPcdGet64(PcdApicLocalAddress), FixedPcdGet32(PcdApicLocalMmioSize) },
- { FixedPcdGet64(PcdMchBaseAddress), FixedPcdGet32(PcdMchMmioSize) },
- { FixedPcdGet64(PcdDmiBaseAddress), FixedPcdGet32(PcdDmiMmioSize) },
- { FixedPcdGet64(PcdEpBaseAddress), FixedPcdGet32(PcdEpMmioSize) },
- { FixedPcdGet64(PcdGdxcBaseAddress), FixedPcdGet32(PcdGdxcMmioSize) }
+ { FixedPcdGet64 (PcdApicLocalAddress), FixedPcdGet32 (PcdApicLocalMmioSize) },
+ { FixedPcdGet64 (PcdMchBaseAddress), FixedPcdGet32 (PcdMchMmioSize) },
+ { FixedPcdGet64 (PcdDmiBaseAddress), FixedPcdGet32 (PcdDmiMmioSize) },
+ { FixedPcdGet64 (PcdEpBaseAddress), FixedPcdGet32 (PcdEpMmioSize) },
+ { FixedPcdGet64 (PcdGdxcBaseAddress), FixedPcdGet32 (PcdGdxcMmioSize) }
};
EFI_STATUS
-MrcConfigInit(
+MrcConfigInit (
IN UINT16 BoardId
-);
+ );
EFI_STATUS
-SaGpioConfigInit(
+SaGpioConfigInit (
IN UINT16 BoardId
-);
+ );
EFI_STATUS
- SaMiscConfigInit(
-IN UINT16 BoardId
-);
+SaMiscConfigInit (
+ IN UINT16 BoardId
+ );
EFI_STATUS
- RootPortClkInfoInit(
-IN UINT16 BoardId
-);
+RootPortClkInfoInit (
+ IN UINT16 BoardId
+ );
EFI_STATUS
- UsbConfigInit(
-IN UINT16 BoardId
-);
+UsbConfigInit (
+ IN UINT16 BoardId
+ );
EFI_STATUS
-GpioGroupTierInit(
+GpioGroupTierInit (
IN UINT16 BoardId
-);
+ );
EFI_STATUS
-GpioTablePreMemInit(
+GpioTablePreMemInit (
IN UINT16 BoardId
-);
+ );
EFI_STATUS
-PchPmConfigInit(
+PchPmConfigInit (
IN UINT16 BoardId
-);
+ );
EFI_STATUS
-SaDisplayConfigInit(
+SaDisplayConfigInit (
IN UINT16 BoardId
-);
+ );
EFI_STATUS
-BoardFunctionInitPreMem(
+BoardFunctionInitPreMem (
IN UINT16 BoardId
-);
+ );
EFI_STATUS
EFIAPI
-PlatformInitPreMemCallBack(
+PlatformInitPreMemCallBack (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
IN VOID *Ppi
-);
+ );
EFI_STATUS
EFIAPI
-MemoryDiscoveredPpiNotify(
+MemoryDiscoveredPpiNotify (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
IN VOID *Ppi
-);
+ );
EFI_STATUS
EFIAPI
-PchReset(
+PchReset (
IN CONST EFI_PEI_SERVICES **PeiServices
-);
+ );
static EFI_PEI_RESET_PPI mResetPpi = {
PchReset
@@ -172,16 +172,16 @@ static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList = {
};
/**
-Board misc init function for PEI pre-memory phase.
+ Board misc init function for PEI pre-memory phase.
-@param[in] BoardId An unsigned integer represent the board id.
+ @param[in] BoardId An unsigned integer represent the board id.
-@retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_SUCCESS The function completed successfully.
**/
EFI_STATUS
-BoardMiscInitPreMem(
+BoardMiscInitPreMem (
IN UINT16 BoardId
-)
+ )
{
PCD64_BLOB PcdData;
@@ -211,22 +211,22 @@ BoardMiscInitPreMem(
// power. An alternative way to contol modem power is to toggle FCP_OFF via GPP_D13
// but board rework is required.
//
- PcdSet32S(PcdWwanFullCardPowerOffGpio, GPIO_CNL_LP_GPP_D16);
- PcdSet32S(PcdWwanBbrstGpio, GPIO_CNL_LP_GPP_F1);
- PcdSet32S(PcdWwanPerstGpio, GPIO_CNL_LP_GPP_E15);
- PcdSet8S(PcdWwanPerstGpioPolarity, 1);
+ PcdSet32S (PcdWwanFullCardPowerOffGpio, GPIO_CNL_LP_GPP_D16);
+ PcdSet32S (PcdWwanBbrstGpio, GPIO_CNL_LP_GPP_F1);
+ PcdSet32S (PcdWwanPerstGpio, GPIO_CNL_LP_GPP_E15);
+ PcdSet8S (PcdWwanPerstGpioPolarity, 1);
break;
default:
break;
}
- PcdSet64S(PcdRecoveryModeGpio, PcdData.Blob);
+ PcdSet64S (PcdRecoveryModeGpio, PcdData.Blob);
//
// Pc8374SioKbc Present
//
- PcdSetBoolS(PcdPc8374SioKbcPresent, FALSE);
+ PcdSetBoolS (PcdPc8374SioKbcPresent, FALSE);
return EFI_SUCCESS;
}
@@ -279,23 +279,23 @@ BoardConfigInitPreMem (
}
/**
-This function handles PlatformInit task after PeiReadOnlyVariable2 PPI produced
+ This function handles PlatformInit task after PeiReadOnlyVariable2 PPI produced
-@param[in] PeiServices Pointer to PEI Services Table.
-@param[in] NotifyDesc Pointer to the descriptor for the Notification event that
- caused this function to execute.
-@param[in] Ppi Pointer to the PPI data associated with this function.
+ @param[in] PeiServices Pointer to PEI Services Table.
+ @param[in] NotifyDesc Pointer to the descriptor for the Notification event that
+ caused this function to execute.
+ @param[in] Ppi Pointer to the PPI data associated with this function.
-@retval EFI_SUCCESS The function completes successfully
-@retval others
+ @retval EFI_SUCCESS The function completes successfully
+ @retval others Failure
**/
EFI_STATUS
EFIAPI
-PlatformInitPreMemCallBack(
+PlatformInitPreMemCallBack (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
IN VOID *Ppi
-)
+ )
{
EFI_STATUS Status;
UINT8 FwConfig;
@@ -303,33 +303,33 @@ PlatformInitPreMemCallBack(
//
// Init Board Config Pcd.
//
- BoardConfigInitPreMem();
+ BoardConfigInitPreMem ();
- DEBUG((DEBUG_ERROR, "Fail to get System Configuration and set the configuration to production mode!\n"));
+ DEBUG ((DEBUG_ERROR, "Fail to get System Configuration and set the configuration to production mode!\n"));
FwConfig = FwConfigProduction;
- PcdSetBoolS(PcdPcieWwanEnable, FALSE);
- PcdSetBoolS(PcdWwanResetWorkaround, FALSE);
+ PcdSetBoolS (PcdPcieWwanEnable, FALSE);
+ PcdSetBoolS (PcdWwanResetWorkaround, FALSE);
//
// Early Board Configuration before memory is ready.
//
- Status = BoardInitEarlyPreMem();
- ASSERT_EFI_ERROR(Status);
+ Status = BoardInitEarlyPreMem ();
+ ASSERT_EFI_ERROR (Status);
///
/// If there was unexpected reset but no WDT expiration and no resume from S3/S4,
/// clear unexpected reset status and enforce expiration. This is to inform Firmware
/// which has no access to unexpected reset status bit, that something went wrong.
///
- OcWdtResetCheck();
+ OcWdtResetCheck ();
- Status = OcWdtInit();
- ASSERT_EFI_ERROR(Status);
+ Status = OcWdtInit ();
+ ASSERT_EFI_ERROR (Status);
//
// Initialize Intel PEI Platform Policy
//
- PeiPolicyInitPreMem(FwConfig);
+ PeiPolicyInitPreMem (FwConfig);
///
/// Configure GPIO and SIO
@@ -340,56 +340,55 @@ PlatformInitPreMemCallBack(
///
/// Install Pre Memory PPIs
///
- Status = PeiServicesInstallPpi(&mPreMemPpiList[0]);
- ASSERT_EFI_ERROR(Status);
+ Status = PeiServicesInstallPpi (&mPreMemPpiList[0]);
+ ASSERT_EFI_ERROR (Status);
return Status;
}
/**
-Provide hard reset PPI service.
-To generate full hard reset, write 0x0E to PCH RESET_GENERATOR_PORT (0xCF9).
+ Provide hard reset PPI service.
+ To generate full hard reset, write 0x0E to PCH RESET_GENERATOR_PORT (0xCF9).
-@param[in] PeiServices General purpose services available to every PEIM.
+ @param[in] PeiServices General purpose services available to every PEIM.
-@retval Not return System reset occured.
-@retval EFI_DEVICE_ERROR Device error, could not reset the system.
+ @retval Not return System reset occured.
+ @retval EFI_DEVICE_ERROR Device error, could not reset the system.
**/
EFI_STATUS
EFIAPI
-PchReset(
+PchReset (
IN CONST EFI_PEI_SERVICES **PeiServices
-)
+ )
{
- DEBUG((DEBUG_INFO, "Perform Cold Reset\n"));
- IoWrite8(RESET_GENERATOR_PORT, 0x0E);
+ DEBUG ((DEBUG_INFO, "Perform Cold Reset\n"));
+ IoWrite8 (RESET_GENERATOR_PORT, 0x0E);
- CpuDeadLoop();
+ CpuDeadLoop ();
///
/// System reset occured, should never reach at this line.
///
- ASSERT_EFI_ERROR(EFI_DEVICE_ERROR);
-
+ ASSERT_EFI_ERROR (EFI_DEVICE_ERROR);
return EFI_DEVICE_ERROR;
}
/**
-Install Firmware Volume Hob's once there is main memory
+ Install Firmware Volume Hob's once there is main memory
-@param[in] PeiServices General purpose services available to every PEIM.
-@param[in] NotifyDescriptor Notify that this module published.
-@param[in] Ppi PPI that was installed.
+ @param[in] PeiServices General purpose services available to every PEIM.
+ @param[in] NotifyDescriptor Notify that this module published.
+ @param[in] Ppi PPI that was installed.
-@retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_SUCCESS The function completed successfully.
**/
EFI_STATUS
EFIAPI
-MemoryDiscoveredPpiNotify(
+MemoryDiscoveredPpiNotify (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
IN VOID *Ppi
-)
+ )
{
EFI_STATUS Status;
EFI_BOOT_MODE BootMode;
@@ -400,12 +399,12 @@ MemoryDiscoveredPpiNotify(
Index = 0;
- Status = PeiServicesGetBootMode(&BootMode);
- ASSERT_EFI_ERROR(Status);
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
- AsmCpuid(0x80000000, &RegEax, NULL, NULL, NULL);
+ AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
if (RegEax >= 0x80000008) {
- AsmCpuid(0x80000008, &RegEax, NULL, NULL, NULL);
+ AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
PhysicalAddressBits = (UINT8)RegEax;
}
else {
@@ -415,69 +414,69 @@ MemoryDiscoveredPpiNotify(
///
/// Create a CPU hand-off information
///
- BuildCpuHob(PhysicalAddressBits, 16);
+ BuildCpuHob (PhysicalAddressBits, 16);
///
/// Build Memory Mapped IO Resource which is used to build E820 Table in LegacyBios.
///
- PcieMmioMap.BaseAddress = FixedPcdGet64(PcdPciExpressBaseAddress);
- PcieMmioMap.Length = PcdGet32(PcdPciExpressRegionLength);
+ PcieMmioMap.BaseAddress = FixedPcdGet64 (PcdPciExpressBaseAddress);
+ PcieMmioMap.Length = PcdGet32 (PcdPciExpressRegionLength);
- BuildResourceDescriptorHob(
+ BuildResourceDescriptorHob (
EFI_RESOURCE_MEMORY_MAPPED_IO,
- (EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
PcieMmioMap.BaseAddress,
PcieMmioMap.Length
- );
- BuildMemoryAllocationHob(
+ );
+ BuildMemoryAllocationHob (
PcieMmioMap.BaseAddress,
PcieMmioMap.Length,
EfiMemoryMappedIO
- );
+ );
for (Index = 0; Index < sizeof(MmioMap) / (sizeof(MEMORY_MAP)); Index++) {
- BuildResourceDescriptorHob(
+ BuildResourceDescriptorHob (
EFI_RESOURCE_MEMORY_MAPPED_IO,
- (EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
MmioMap[Index].BaseAddress,
MmioMap[Index].Length
- );
- BuildMemoryAllocationHob(
+ );
+ BuildMemoryAllocationHob (
MmioMap[Index].BaseAddress,
MmioMap[Index].Length,
EfiMemoryMappedIO
- );
+ );
}
//
// Report resource HOB for flash FV
//
- BuildResourceDescriptorHob(
+ BuildResourceDescriptorHob (
EFI_RESOURCE_MEMORY_MAPPED_IO,
- (EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
- (UINTN)FixedPcdGet32(PcdFlashAreaBaseAddress),
- (UINTN)FixedPcdGet32(PcdFlashAreaSize)
- );
- BuildMemoryAllocationHob(
- (UINTN)FixedPcdGet32(PcdFlashAreaBaseAddress),
- (UINTN)FixedPcdGet32(PcdFlashAreaSize),
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
+ (UINTN) FixedPcdGet32 (PcdFlashAreaBaseAddress),
+ (UINTN) FixedPcdGet32 (PcdFlashAreaSize)
+ );
+
+ BuildMemoryAllocationHob (
+ (UINTN) FixedPcdGet32 (PcdFlashAreaBaseAddress),
+ (UINTN) FixedPcdGet32 (PcdFlashAreaSize),
EfiMemoryMappedIO
- );
+ );
- BuildFvHob(
- (UINTN)FixedPcdGet32(PcdFlashAreaBaseAddress),
- (UINTN)FixedPcdGet32(PcdFlashAreaSize)
- );
+ BuildFvHob (
+ (UINTN)FixedPcdGet32 (PcdFlashAreaBaseAddress),
+ (UINTN)FixedPcdGet32 (PcdFlashAreaSize)
+ );
return Status;
}
-
/**
Board configuration init function for PEI pre-memory phase.
@@ -495,26 +494,26 @@ WhiskeylakeURvpInitPreMem (
///
/// Install Stall PPI
///
- Status = InstallStallPpi();
- ASSERT_EFI_ERROR(Status);
+ Status = InstallStallPpi ();
+ ASSERT_EFI_ERROR (Status);
//
// Install PCH RESET PPI and EFI RESET2 PeiService
//
- Status = PchInitializeReset();
- ASSERT_EFI_ERROR(Status);
+ Status = PchInitializeReset ();
+ ASSERT_EFI_ERROR (Status);
///
/// Performing PlatformInitPreMemCallBack after PeiReadOnlyVariable2 PPI produced
///
- Status = PeiServicesNotifyPpi(&mPreMemNotifyList);
+ Status = PeiServicesNotifyPpi (&mPreMemNotifyList);
///
/// After code reorangized, memorycallback will run because the PPI is already
/// installed when code run to here, it is supposed that the InstallEfiMemory is
/// done before.
///
- Status = PeiServicesNotifyPpi(&mMemDiscoveredNotifyList);
+ Status = PeiServicesNotifyPpi (&mMemDiscoveredNotifyList);
return EFI_SUCCESS;
}
@@ -561,5 +560,3 @@ WhiskeylakeURvpBoardBootModeDetect (
{
return BOOT_WITH_FULL_CONFIGURATION;
}
-
-
--
2.23.0.windows.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [edk2-platforms] [PATCH V1 08/13] WhiskeylakeOpenBoardPkg: Remove SecFspWrapperPlatformSecLib override
2019-11-14 6:06 [edk2-platforms] [PATCH V1 00/13] SecFspWrapperPlatformSecLib Cleanup Nate DeSimone
` (6 preceding siblings ...)
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 07/13] WhiskeylakeOpenBoardPkg: Whitespace cleanup in BoardInitLib Nate DeSimone
@ 2019-11-14 6:06 ` Nate DeSimone
2019-11-14 15:17 ` Chiu, Chasel
2019-11-16 2:53 ` Kubacki, Michael A
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 09/13] MinPlatformPkg: FSP Dispatch Mode Support for PlatformSecLib Nate DeSimone
` (4 subsequent siblings)
12 siblings, 2 replies; 44+ messages in thread
From: Nate DeSimone @ 2019-11-14 6:06 UTC (permalink / raw)
To: devel; +Cc: Chasel Chiu, Michael Kubacki
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
.../FspWrapperPlatformSecLib.c | 163 --------
.../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 40 --
.../SecFspWrapperPlatformSecLib/Ia32/Fsp.h | 43 ---
.../Ia32/PeiCoreEntry.nasm | 130 -------
.../Ia32/SecEntry.nasm | 361 ------------------
.../Ia32/Stack.nasm | 72 ----
.../PlatformInit.c | 54 ---
.../SecFspWrapperPlatformSecLib.inf | 97 -----
.../SecGetPerformance.c | 90 -----
.../SecPlatformInformation.c | 79 ----
.../SecRamInitData.c | 37 --
.../SecTempRamDone.c | 48 ---
.../WhiskeylakeURvp/OpenBoardPkg.dsc | 2 +-
13 files changed, 1 insertion(+), 1215 deletions(-)
delete mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c
delete mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
delete mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h
delete mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
delete mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
delete mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
delete mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c
delete mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
delete mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c
delete mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c
delete mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
delete mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c
deleted file mode 100644
index a767289bc5..0000000000
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/** @file
- Provide FSP wrapper platform sec related function.
-
-
- Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-**/
-
-#include <PiPei.h>
-
-#include <Ppi/SecPlatformInformation.h>
-#include <Ppi/SecPerformance.h>
-#include <Ppi/FirmwareVolumeInfo.h>
-#include <Ppi/TopOfTemporaryRam.h>
-#include <Guid/FirmwareFileSystem2.h>
-
-#include <Library/LocalApicLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/DebugLib.h>
-#include <Library/IoLib.h>
-
-/**
- This interface conveys state information out of the Security (SEC) phase into PEI.
-
- @param[in] PeiServices Pointer to the PEI Services Table.
- @param[in,out] StructureSize Pointer to the variable describing size of the input buffer.
- @param[out] PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
-
- @retval EFI_SUCCESS The data was successfully returned.
- @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
-
-**/
-EFI_STATUS
-EFIAPI
-SecPlatformInformation (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN OUT UINT64 *StructureSize,
- OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
- );
-
-/**
- This interface conveys performance information out of the Security (SEC) phase into PEI.
-
- This service is published by the SEC phase. The SEC phase handoff has an optional
- EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the
- PEI Foundation. As such, if the platform supports collecting performance data in SEC,
- this information is encapsulated into the data structure abstracted by this service.
- This information is collected for the boot-strap processor (BSP) on IA-32.
-
- @param[in] PeiServices The pointer to the PEI Services Table.
- @param[in] This The pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.
- @param[out] Performance The pointer to performance data collected in SEC phase.
-
- @retval EFI_SUCCESS The data was successfully returned.
-
-**/
-EFI_STATUS
-EFIAPI
-SecGetPerformance (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN PEI_SEC_PERFORMANCE_PPI *This,
- OUT FIRMWARE_SEC_PERFORMANCE *Performance
- );
-
-PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi = {
- SecGetPerformance
-};
-
-EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] = {
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI,
- &gTopOfTemporaryRamPpiGuid,
- NULL // To be patched later.
- },
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
- &gPeiSecPerformancePpiGuid,
- &mSecPerformancePpi
- },
-};
-
-#define LEGACY_8259_MASK_REGISTER_MASTER 0x21
-#define LEGACY_8259_MASK_REGISTER_SLAVE 0xA1
-#define LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER 0x4D0
-#define LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE 0x4D1
-
-/**
- Write to mask and edge/level triggered registers of master and slave 8259 PICs.
-
- @param[in] Mask low byte for master PIC mask register,
- high byte for slave PIC mask register.
- @param[in] EdgeLevel low byte for master PIC edge/level triggered register,
- high byte for slave PIC edge/level triggered register.
-
-**/
-VOID
-Interrupt8259WriteMask (
- IN UINT16 Mask,
- IN UINT16 EdgeLevel
- )
-{
- IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, (UINT8) Mask);
- IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, (UINT8) (Mask >> 8));
- IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER, (UINT8) EdgeLevel);
- IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE, (UINT8) (EdgeLevel >> 8));
-}
-
-/**
- A developer supplied function to perform platform specific operations.
-
- It's a developer supplied function to perform any operations appropriate to a
- given platform. It's invoked just before passing control to PEI core by SEC
- core. Platform developer may modify the SecCoreData passed to PEI Core.
- It returns a platform specific PPI list that platform wishes to pass to PEI core.
- The Generic SEC core module will merge this list to join the final list passed to
- PEI core.
-
- @param[in,out] SecCoreData The same parameter as passing to PEI core. It
- could be overridden by this function.
-
- @return The platform specific PPI list to be passed to PEI core or
- NULL if there is no need of such platform specific PPI list.
-
-**/
-EFI_PEI_PPI_DESCRIPTOR *
-EFIAPI
-SecPlatformMain (
- IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData
- )
-{
- EFI_PEI_PPI_DESCRIPTOR *PpiList;
-
- DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeBase - 0x%x\n", SecCoreData->BootFirmwareVolumeBase));
- DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeSize - 0x%x\n", SecCoreData->BootFirmwareVolumeSize));
- DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamBase - 0x%x\n", SecCoreData->TemporaryRamBase));
- DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamSize - 0x%x\n", SecCoreData->TemporaryRamSize));
- DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamBase - 0x%x\n", SecCoreData->PeiTemporaryRamBase));
- DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamSize - 0x%x\n", SecCoreData->PeiTemporaryRamSize));
- DEBUG ((DEBUG_INFO, "FSP Wrapper StackBase - 0x%x\n", SecCoreData->StackBase));
- DEBUG ((DEBUG_INFO, "FSP Wrapper StackSize - 0x%x\n", SecCoreData->StackSize));
-
- InitializeApicTimer (0, (UINT32) -1, TRUE, 5);
-
- //
- // Set all 8259 interrupts to edge triggered and disabled
- //
- Interrupt8259WriteMask (0xFFFF, 0x0000);
-
- //
- // Use middle of Heap as temp buffer, it will be copied by caller.
- // Do not use Stack, because it will cause wrong calculation on stack by PeiCore
- //
- PpiList = (VOID *)((UINTN)SecCoreData->PeiTemporaryRamBase + (UINTN)SecCoreData->PeiTemporaryRamSize/2);
- CopyMem (PpiList, mPeiSecPlatformPpi, sizeof(mPeiSecPlatformPpi));
-
- //
- // Patch TopOfTemporaryRamPpi
- //
- PpiList[0].Ppi = (VOID *)((UINTN)SecCoreData->TemporaryRamBase + SecCoreData->TemporaryRamSize);
-
- return PpiList;
-}
-
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
deleted file mode 100644
index e7b5ed952b..0000000000
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/** @file
-
- Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-**/
-
-#ifndef __FSPT_CORE_UPD_H__
-#define __FSPT_CORE_UPD_H__
-
-#pragma pack(1)
-
-/** Fsp T Core UPD
-**/
-typedef struct {
-
-/** Offset 0x0020
-**/
- UINT32 MicrocodeRegionBase;
-
-/** Offset 0x0024
-**/
- UINT32 MicrocodeRegionSize;
-
-/** Offset 0x0028
-**/
- UINT32 CodeRegionBase;
-
-/** Offset 0x002C
-**/
- UINT32 CodeRegionSize;
-
-/** Offset 0x0030
-**/
- UINT8 Reserved[16];
-} FSPT_CORE_UPD;
-
-#pragma pack()
-
-#endif
-
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h
deleted file mode 100644
index 1c88285a1d..0000000000
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/** @file
- Fsp related definitions
-
-
- Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-**/
-
-#ifndef __FSP_H__
-#define __FSP_H__
-
-//
-// Fv Header
-//
-#define FVH_SIGINATURE_OFFSET 0x28
-#define FVH_SIGINATURE_VALID_VALUE 0x4856465F // valid signature:_FVH
-#define FVH_HEADER_LENGTH_OFFSET 0x30
-#define FVH_EXTHEADER_OFFSET_OFFSET 0x34
-#define FVH_EXTHEADER_SIZE_OFFSET 0x10
-
-//
-// Ffs Header
-//
-#define FSP_HEADER_GUID_DWORD1 0x912740BE
-#define FSP_HEADER_GUID_DWORD2 0x47342284
-#define FSP_HEADER_GUID_DWORD3 0xB08471B9
-#define FSP_HEADER_GUID_DWORD4 0x0C3F3527
-#define FFS_HEADER_SIZE_VALUE 0x18
-
-//
-// Section Header
-//
-#define SECTION_HEADER_TYPE_OFFSET 0x03
-#define RAW_SECTION_HEADER_SIZE_VALUE 0x04
-
-//
-// Fsp Header
-//
-#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C
-#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30
-
-#endif
-
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
deleted file mode 100644
index 5c5b788085..0000000000
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
+++ /dev/null
@@ -1,130 +0,0 @@
-;------------------------------------------------------------------------------
-;
-; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
-; SPDX-License-Identifier: BSD-2-Clause-Patent
-;
-; Module Name:
-;
-; PeiCoreEntry.nasm
-;
-; Abstract:
-;
-; Find and call SecStartup
-;
-;------------------------------------------------------------------------------
-
-SECTION .text
-
-extern ASM_PFX(SecStartup)
-extern ASM_PFX(PlatformInit)
-
-global ASM_PFX(CallPeiCoreEntryPoint)
-ASM_PFX(CallPeiCoreEntryPoint):
- ;
- ; Obtain the hob list pointer
- ;
- mov eax, [esp+4]
- ;
- ; Obtain the stack information
- ; ECX: start of range
- ; EDX: end of range
- ;
- mov ecx, [esp+8]
- mov edx, [esp+0xC]
-
- ;
- ; Platform init
- ;
- pushad
- push edx
- push ecx
- push eax
- call ASM_PFX(PlatformInit)
- pop eax
- pop eax
- pop eax
- popad
-
- ;
- ; Set stack top pointer
- ;
- mov esp, edx
-
- ;
- ; Push the hob list pointer
- ;
- push eax
-
- ;
- ; Save the value
- ; ECX: start of range
- ; EDX: end of range
- ;
- mov ebp, esp
- push ecx
- push edx
-
- ;
- ; Push processor count to stack first, then BIST status (AP then BSP)
- ;
- mov eax, 1
- cpuid
- shr ebx, 16
- and ebx, 0xFF
- cmp bl, 1
- jae PushProcessorCount
-
- ;
- ; Some processors report 0 logical processors. Effectively 0 = 1.
- ; So we fix up the processor count
- ;
- inc ebx
-
-PushProcessorCount:
- push ebx
-
- ;
- ; We need to implement a long-term solution for BIST capture. For now, we just copy BSP BIST
- ; for all processor threads
- ;
- xor ecx, ecx
- mov cl, bl
-PushBist:
- movd eax, mm0
- push eax
- loop PushBist
-
- ; Save Time-Stamp Counter
- movd eax, mm5
- push eax
-
- movd eax, mm6
- push eax
-
- ;
- ; Pass entry point of the PEI core
- ;
- mov edi, 0xFFFFFFE0
- push DWORD [edi]
-
- ;
- ; Pass BFV into the PEI Core
- ;
- mov edi, 0xFFFFFFFC
- push DWORD [edi]
-
- ;
- ; Pass stack size into the PEI Core
- ;
- mov ecx, [ebp - 4]
- mov edx, [ebp - 8]
- push ecx ; RamBase
-
- sub edx, ecx
- push edx ; RamSize
-
- ;
- ; Pass Control into the PEI Core
- ;
- call ASM_PFX(SecStartup)
-
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
deleted file mode 100644
index 7f6d771e41..0000000000
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
+++ /dev/null
@@ -1,361 +0,0 @@
-;------------------------------------------------------------------------------
-;
-; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
-; SPDX-License-Identifier: BSD-2-Clause-Patent
-; Module Name:
-;
-; SecEntry.nasm
-;
-; Abstract:
-;
-; This is the code that goes from real-mode to protected mode.
-; It consumes the reset vector, calls TempRamInit API from FSP binary.
-;
-;------------------------------------------------------------------------------
-
-#include "Fsp.h"
-
-SECTION .text
-
-extern ASM_PFX(CallPeiCoreEntryPoint)
-extern ASM_PFX(FsptUpdDataPtr)
-extern ASM_PFX(BoardBeforeTempRamInit)
-; Pcds
-extern ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))
-extern ASM_PFX(PcdGet32 (PcdFsptBaseAddress))
-
-;----------------------------------------------------------------------------
-;
-; Procedure: _ModuleEntryPoint
-;
-; Input: None
-;
-; Output: None
-;
-; Destroys: Assume all registers
-;
-; Description:
-;
-; Transition to non-paged flat-model protected mode from a
-; hard-coded GDT that provides exactly two descriptors.
-; This is a bare bones transition to protected mode only
-; used for a while in PEI and possibly DXE.
-;
-; After enabling protected mode, a far jump is executed to
-; transfer to PEI using the newly loaded GDT.
-;
-; Return: None
-;
-; MMX Usage:
-; MM0 = BIST State
-; MM5 = Save time-stamp counter value high32bit
-; MM6 = Save time-stamp counter value low32bit.
-;
-;----------------------------------------------------------------------------
-
-BITS 16
-align 4
-global ASM_PFX(_ModuleEntryPoint)
-ASM_PFX(_ModuleEntryPoint):
- fninit ; clear any pending Floating point exceptions
- ;
- ; Store the BIST value in mm0
- ;
- movd mm0, eax
- cli
-
- ;
- ; Check INIT# is asserted by port 0xCF9
- ;
- mov dx, 0CF9h
- in al, dx
- cmp al, 04h
- jnz NotWarmStart
-
-
- ;
- ; @note Issue warm reset, since if CPU only reset is issued not all MSRs are restored to their defaults
- ;
- mov dx, 0CF9h
- mov al, 06h
- out dx, al
-
-NotWarmStart:
- ;
- ; Save time-stamp counter value
- ; rdtsc load 64bit time-stamp counter to EDX:EAX
- ;
- rdtsc
- movd mm5, edx
- movd mm6, eax
-
- ;
- ; Load the GDT table in GdtDesc
- ;
- mov esi, GdtDesc
- DB 66h
- lgdt [cs:si]
-
- ;
- ; Transition to 16 bit protected mode
- ;
- mov eax, cr0 ; Get control register 0
- or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1)
- mov cr0, eax ; Activate protected mode
-
- mov eax, cr4 ; Get control register 4
- or eax, 00000600h ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
- mov cr4, eax
-
- ;
- ; Now we're in 16 bit protected mode
- ; Set up the selectors for 32 bit protected mode entry
- ;
- mov ax, SYS_DATA_SEL
- mov ds, ax
- mov es, ax
- mov fs, ax
- mov gs, ax
- mov ss, ax
-
- ;
- ; Transition to Flat 32 bit protected mode
- ; The jump to a far pointer causes the transition to 32 bit mode
- ;
- mov esi, ProtectedModeEntryLinearAddress
- jmp dword far [cs:si]
-
-;----------------------------------------------------------------------------
-;
-; Procedure: ProtectedModeEntryPoint
-;
-; Input: None
-;
-; Output: None
-;
-; Destroys: Assume all registers
-;
-; Description:
-;
-; This function handles:
-; Call two basic APIs from FSP binary
-; Initializes stack with some early data (BIST, PEI entry, etc)
-;
-; Return: None
-;
-;----------------------------------------------------------------------------
-
-BITS 32
-align 4
-ProtectedModeEntryPoint:
- ;
- ; Early board hooks
- ;
- mov esp, BoardBeforeTempRamInitRet
- jmp ASM_PFX(BoardBeforeTempRamInit)
-
-BoardBeforeTempRamInitRet:
-
- ; Find the fsp info header
- mov edi, [ASM_PFX(PcdGet32 (PcdFsptBaseAddress))]
-
- mov eax, dword [edi + FVH_SIGINATURE_OFFSET]
- cmp eax, FVH_SIGINATURE_VALID_VALUE
- jnz FspHeaderNotFound
-
- xor eax, eax
- mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET]
- cmp ax, 0
- jnz FspFvExtHeaderExist
-
- xor eax, eax
- mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header
- add edi, eax
- jmp FspCheckFfsHeader
-
-FspFvExtHeaderExist:
- add edi, eax
- mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Header
- add edi, eax
-
- ; Round up to 8 byte alignment
- mov eax, edi
- and al, 07h
- jz FspCheckFfsHeader
-
- and edi, 0FFFFFFF8h
- add edi, 08h
-
-FspCheckFfsHeader:
- ; Check the ffs guid
- mov eax, dword [edi]
- cmp eax, FSP_HEADER_GUID_DWORD1
- jnz FspHeaderNotFound
-
- mov eax, dword [edi + 4]
- cmp eax, FSP_HEADER_GUID_DWORD2
- jnz FspHeaderNotFound
-
- mov eax, dword [edi + 8]
- cmp eax, FSP_HEADER_GUID_DWORD3
- jnz FspHeaderNotFound
-
- mov eax, dword [edi + 0Ch]
- cmp eax, FSP_HEADER_GUID_DWORD4
- jnz FspHeaderNotFound
-
- add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header
-
- ; Check the section type as raw section
- mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET]
- cmp al, 019h
- jnz FspHeaderNotFound
-
- add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header
- jmp FspHeaderFound
-
-FspHeaderNotFound:
- jmp $
-
-FspHeaderFound:
- ; Get the fsp TempRamInit Api address
- mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]
- add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
-
- ; Setup the hardcode stack
- mov esp, TempRamInitStack
-
- ; Call the fsp TempRamInit Api
- jmp eax
-
-TempRamInitDone:
- cmp eax, 8000000Eh ;Check if EFI_NOT_FOUND returned. Error code for Microcode Update not found.
- je CallSecFspInit ;If microcode not found, don't hang, but continue.
-
- cmp eax, 0 ;Check if EFI_SUCCESS retuned.
- jnz FspApiFailed
-
- ; ECX: start of range
- ; EDX: end of range
-CallSecFspInit:
- sub edx, [ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))] ; TemporaryRam for FSP
- xor eax, eax
- mov esp, edx
-
- ; Align the stack at DWORD
- add esp, 3
- and esp, 0FFFFFFFCh
-
- push edx
- push ecx
- push eax ; zero - no hob list yet
- call ASM_PFX(CallPeiCoreEntryPoint)
-
-FspApiFailed:
- jmp $
-
-align 10h
-TempRamInitStack:
- DD TempRamInitDone
- DD ASM_PFX(FsptUpdDataPtr); TempRamInitParams
-
-;
-; ROM-based Global-Descriptor Table for the Tiano PEI Phase
-;
-align 16
-global ASM_PFX(BootGdtTable)
-
-;
-; GDT[0]: 0x00: Null entry, never used.
-;
-NULL_SEL EQU $ - GDT_BASE ; Selector [0]
-GDT_BASE:
-ASM_PFX(BootGdtTable):
- DD 0
- DD 0
-;
-; Linear data segment descriptor
-;
-LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8]
- DW 0FFFFh ; limit 0xFFFFF
- DW 0 ; base 0
- DB 0
- DB 092h ; present, ring 0, data, expand-up, writable
- DB 0CFh ; page-granular, 32-bit
- DB 0
-;
-; Linear code segment descriptor
-;
-LINEAR_CODE_SEL EQU $ - GDT_BASE ; Selector [0x10]
- DW 0FFFFh ; limit 0xFFFFF
- DW 0 ; base 0
- DB 0
- DB 09Bh ; present, ring 0, data, expand-up, not-writable
- DB 0CFh ; page-granular, 32-bit
- DB 0
-;
-; System data segment descriptor
-;
-SYS_DATA_SEL EQU $ - GDT_BASE ; Selector [0x18]
- DW 0FFFFh ; limit 0xFFFFF
- DW 0 ; base 0
- DB 0
- DB 093h ; present, ring 0, data, expand-up, not-writable
- DB 0CFh ; page-granular, 32-bit
- DB 0
-
-;
-; System code segment descriptor
-;
-SYS_CODE_SEL EQU $ - GDT_BASE ; Selector [0x20]
- DW 0FFFFh ; limit 0xFFFFF
- DW 0 ; base 0
- DB 0
- DB 09Ah ; present, ring 0, data, expand-up, writable
- DB 0CFh ; page-granular, 32-bit
- DB 0
-;
-; Spare segment descriptor
-;
-SYS16_CODE_SEL EQU $ - GDT_BASE ; Selector [0x28]
- DW 0FFFFh ; limit 0xFFFFF
- DW 0 ; base 0
- DB 0Eh ; Changed from F000 to E000.
- DB 09Bh ; present, ring 0, code, expand-up, writable
- DB 00h ; byte-granular, 16-bit
- DB 0
-;
-; Spare segment descriptor
-;
-SYS16_DATA_SEL EQU $ - GDT_BASE ; Selector [0x30]
- DW 0FFFFh ; limit 0xFFFF
- DW 0 ; base 0
- DB 0
- DB 093h ; present, ring 0, data, expand-up, not-writable
- DB 00h ; byte-granular, 16-bit
- DB 0
-
-;
-; Spare segment descriptor
-;
-SPARE5_SEL EQU $ - GDT_BASE ; Selector [0x38]
- DW 0 ; limit 0
- DW 0 ; base 0
- DB 0
- DB 0 ; present, ring 0, data, expand-up, writable
- DB 0 ; page-granular, 32-bit
- DB 0
-GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes
-
-;
-; GDT Descriptor
-;
-GdtDesc: ; GDT descriptor
- DW GDT_SIZE - 1 ; GDT limit
- DD GDT_BASE ; GDT base address
-
-
-ProtectedModeEntryLinearAddress:
-ProtectedModeEntryLinear:
- DD ProtectedModeEntryPoint ; Offset of our 32 bit code
- DW LINEAR_CODE_SEL
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
deleted file mode 100644
index 47db32d64c..0000000000
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
+++ /dev/null
@@ -1,72 +0,0 @@
-;------------------------------------------------------------------------------
-;
-; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
-; SPDX-License-Identifier: BSD-2-Clause-Patent
-; Abstract:
-;
-; Switch the stack from temporary memory to permanent memory.
-;
-;------------------------------------------------------------------------------
-
- SECTION .text
-
-;------------------------------------------------------------------------------
-; VOID
-; EFIAPI
-; SecSwitchStack (
-; UINT32 TemporaryMemoryBase,
-; UINT32 PermanentMemoryBase
-; );
-;------------------------------------------------------------------------------
-global ASM_PFX(SecSwitchStack)
-ASM_PFX(SecSwitchStack):
- ;
- ; Save three register: eax, ebx, ecx
- ;
- push eax
- push ebx
- push ecx
- push edx
-
- ;
- ; !!CAUTION!! this function address's is pushed into stack after
- ; migration of whole temporary memory, so need save it to permanent
- ; memory at first!
- ;
-
- mov ebx, [esp + 20] ; Save the first parameter
- mov ecx, [esp + 24] ; Save the second parameter
-
- ;
- ; Save this function's return address into permanent memory at first.
- ; Then, Fixup the esp point to permanent memory
- ;
- mov eax, esp
- sub eax, ebx
- add eax, ecx
- mov edx, dword [esp] ; copy pushed register's value to permanent memory
- mov dword [eax], edx
- mov edx, dword [esp + 4]
- mov dword [eax + 4], edx
- mov edx, dword [esp + 8]
- mov dword [eax + 8], edx
- mov edx, dword [esp + 12]
- mov dword [eax + 12], edx
- mov edx, dword [esp + 16] ; Update this function's return address into permanent memory
- mov dword [eax + 16], edx
- mov esp, eax ; From now, esp is pointed to permanent memory
-
- ;
- ; Fixup the ebp point to permanent memory
- ;
- mov eax, ebp
- sub eax, ebx
- add eax, ecx
- mov ebp, eax ; From now, ebp is pointed to permanent memory
-
- pop edx
- pop ecx
- pop ebx
- pop eax
- ret
-
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c
deleted file mode 100644
index 06ca63c19a..0000000000
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/** @file
- Provide platform init function.
-
-
- Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-**/
-
-#include <PiPei.h>
-#include <Library/DebugLib.h>
-#include <Library/SerialPortLib.h>
-#include <Library/SecBoardInitLib.h>
-#include <Library/TestPointCheckLib.h>
-#include <Register/PchRegsPmc.h>
-#include <Library/IoLib.h>
-
-/**
- Platform initialization.
-
- @param[in] FspHobList HobList produced by FSP.
- @param[in] StartOfRange Start of temporary RAM.
- @param[in] EndOfRange End of temporary RAM.
-**/
-VOID
-EFIAPI
-PlatformInit (
- IN VOID *FspHobList,
- IN VOID *StartOfRange,
- IN VOID *EndOfRange
- )
-{
- ///
- /// Halt the TCO timer as early as possible
- ///
- IoWrite16 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT, B_TCO_IO_TCO1_CNT_TMR_HLT);
-
- //
- // Platform initialization
- // Enable Serial port here
- //
- if (PcdGetBool(PcdSecSerialPortDebugEnable)) {
- SerialPortInitialize ();
- }
-
- DEBUG ((DEBUG_INFO, "PrintPeiCoreEntryPointParam in PlatformInit\n"));
- DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList));
- DEBUG ((DEBUG_INFO, "StartOfRange - 0x%x\n", StartOfRange));
- DEBUG ((DEBUG_INFO, "EndOfRange - 0x%x\n", EndOfRange));
-
- BoardAfterTempRamInit ();
-
- TestPointTempMemoryFunction (StartOfRange, EndOfRange);
-}
-
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
deleted file mode 100644
index 06489a6336..0000000000
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+++ /dev/null
@@ -1,97 +0,0 @@
-## @file
-# Provide FSP wrapper platform sec related function.
-#
-#
-# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-#
-##
-
-################################################################################
-#
-# Defines Section - statements that will be processed to create a Makefile.
-#
-################################################################################
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = SecFspWrapperPlatformSecLib
- FILE_GUID = 4E1C4F95-90EA-47de-9ACC-B8920189A1F5
- MODULE_TYPE = SEC
- VERSION_STRING = 1.0
- LIBRARY_CLASS = PlatformSecLib
-
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IA32 X64
-#
-
-################################################################################
-#
-# Sources Section - list of files that are required for the build to succeed.
-#
-################################################################################
-
-[Sources]
- FspWrapperPlatformSecLib.c
- SecRamInitData.c
- SecPlatformInformation.c
- SecGetPerformance.c
- SecTempRamDone.c
- PlatformInit.c
-
-[Sources.IA32]
- Ia32/SecEntry.nasm
- Ia32/PeiCoreEntry.nasm
- Ia32/Stack.nasm
- Ia32/Fsp.h
-
-################################################################################
-#
-# Package Dependency Section - list of Package files that are required for
-# this module.
-#
-################################################################################
-
-[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- UefiCpuPkg/UefiCpuPkg.dec
- IntelFsp2Pkg/IntelFsp2Pkg.dec
- IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
- MinPlatformPkg/MinPlatformPkg.dec
- CoffeelakeSiliconPkg/SiPkg.dec
-
-[LibraryClasses]
- LocalApicLib
- SerialPortLib
- FspWrapperPlatformLib
- FspWrapperApiLib
- BoardInitLib
- SecBoardInitLib
- TestPointCheckLib
- IoLib
-
-[Ppis]
- gEfiSecPlatformInformationPpiGuid ## CONSUMES
- gPeiSecPerformancePpiGuid ## CONSUMES
- gTopOfTemporaryRamPpiGuid ## PRODUCES
- gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES
-
-[Pcd]
- gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress ## CONSUMES
- gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ## CONSUMES
- gSiPkgTokenSpaceGuid.PcdTcoBaseAddress
-
-[FixedPcd]
- gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize ## CONSUMES
-
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c
deleted file mode 100644
index 67bdd232bb..0000000000
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/** @file
- Sample to provide SecGetPerformance function.
-
-
- Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-**/
-
-#include <PiPei.h>
-
-#include <Ppi/SecPerformance.h>
-#include <Ppi/TopOfTemporaryRam.h>
-
-#include <Library/BaseMemoryLib.h>
-#include <Library/TimerLib.h>
-#include <Library/DebugLib.h>
-
-/**
- This interface conveys performance information out of the Security (SEC) phase into PEI.
-
- This service is published by the SEC phase. The SEC phase handoff has an optional
- EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the
- PEI Foundation. As such, if the platform supports collecting performance data in SEC,
- this information is encapsulated into the data structure abstracted by this service.
- This information is collected for the boot-strap processor (BSP) on IA-32.
-
- @param[in] PeiServices The pointer to the PEI Services Table.
- @param[in] This The pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.
- @param[out] Performance The pointer to performance data collected in SEC phase.
-
- @retval EFI_SUCCESS The data was successfully returned.
-
-**/
-EFI_STATUS
-EFIAPI
-SecGetPerformance (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN PEI_SEC_PERFORMANCE_PPI *This,
- OUT FIRMWARE_SEC_PERFORMANCE *Performance
- )
-{
- UINT32 Size;
- UINT32 Count;
- UINT32 TopOfTemporaryRam;
- UINT64 Ticker;
- VOID *TopOfTemporaryRamPpi;
- EFI_STATUS Status;
-
- DEBUG ((DEBUG_INFO, "SecGetPerformance\n"));
-
- Status = (*PeiServices)->LocatePpi (
- PeiServices,
- &gTopOfTemporaryRamPpiGuid,
- 0,
- NULL,
- (VOID **) &TopOfTemporaryRamPpi
- );
- if (EFI_ERROR (Status)) {
- return EFI_NOT_FOUND;
- }
- //
- // |--------------| <- TopOfTemporaryRam - BL
- // | List Ptr |
- // |--------------|
- // | BL RAM Start |
- // |--------------|
- // | BL RAM End |
- // |--------------|
- // |Number of BSPs|
- // |--------------|
- // | BIST |
- // |--------------|
- // | .... |
- // |--------------|
- // | TSC[63:32] |
- // |--------------|
- // | TSC[31:00] |
- // |--------------|
- //
- TopOfTemporaryRam = (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof(UINT32);
- TopOfTemporaryRam -= sizeof(UINT32) * 2;
- Count = *(UINT32 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32));
- Size = Count * sizeof (UINT32);
-
- Ticker = *(UINT64 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32) - Size - sizeof (UINT32) * 2);
- Performance->ResetEnd = GetTimeInNanoSecond (Ticker);
-
- return EFI_SUCCESS;
-}
-
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c
deleted file mode 100644
index e05daa8784..0000000000
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/** @file
- Provide SecPlatformInformation function.
-
-
- Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-**/
-
-#include <PiPei.h>
-
-#include <Ppi/SecPlatformInformation.h>
-#include <Ppi/TopOfTemporaryRam.h>
-
-#include <Library/BaseMemoryLib.h>
-#include <Library/DebugLib.h>
-
-/**
- This interface conveys state information out of the Security (SEC) phase into PEI.
-
- @param[in] PeiServices Pointer to the PEI Services Table.
- @param[in,out] StructureSize Pointer to the variable describing size of the input buffer.
- @param[out] PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
-
- @retval EFI_SUCCESS The data was successfully returned.
- @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
-
-**/
-EFI_STATUS
-EFIAPI
-SecPlatformInformation (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN OUT UINT64 *StructureSize,
- OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
- )
-{
- UINT32 *Bist;
- UINT32 Size;
- UINT32 Count;
- UINT32 TopOfTemporaryRam;
- VOID *TopOfTemporaryRamPpi;
- EFI_STATUS Status;
-
- DEBUG ((DEBUG_INFO, "SecPlatformInformation\n"));
-
- Status = (*PeiServices)->LocatePpi (
- PeiServices,
- &gTopOfTemporaryRamPpiGuid,
- 0,
- NULL,
- (VOID **) &TopOfTemporaryRamPpi
- );
- if (EFI_ERROR (Status)) {
- return EFI_NOT_FOUND;
- }
-
- //
- // The entries of BIST information, together with the number of them,
- // reside in the bottom of stack, left untouched by normal stack operation.
- // This routine copies the BIST information to the buffer pointed by
- // PlatformInformationRecord for output.
- //
- TopOfTemporaryRam = (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof (UINT32);
- TopOfTemporaryRam -= sizeof(UINT32) * 2;
- Count = *((UINT32 *)(UINTN) (TopOfTemporaryRam - sizeof (UINT32)));
- Size = Count * sizeof (IA32_HANDOFF_STATUS);
-
- if ((*StructureSize) < (UINT64) Size) {
- *StructureSize = Size;
- return EFI_BUFFER_TOO_SMALL;
- }
-
- *StructureSize = Size;
- Bist = (UINT32 *) (TopOfTemporaryRam - sizeof (UINT32) - Size);
-
- CopyMem (PlatformInformationRecord, Bist, Size);
-
- return EFI_SUCCESS;
-}
-
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
deleted file mode 100644
index 04f12a9438..0000000000
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/** @file
- Provide TempRamInitParams data.
-
-
- Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-**/
-
-#include <Library/PcdLib.h>
-#include <FspEas.h>
-#include "FsptCoreUpd.h"
-
-typedef struct {
- FSP_UPD_HEADER FspUpdHeader;
- FSPT_CORE_UPD FsptCoreUpd;
-} FSPT_UPD_CORE_DATA;
-
-GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA FsptUpdDataPtr = {
- {
- 0x4450555F54505346,
- 0x00,
- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
- }
- },
- {
- ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + FixedPcdGet32 (PcdFlashMicrocodeOffset)),
- ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet32 (PcdFlashMicrocodeOffset)),
- 0, // Set CodeRegionBase as 0, so that caching will be 4GB-(CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used.
- FixedPcdGet32 (PcdFlashCodeCacheSize),
- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
- }
- }
-};
-
-
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c
deleted file mode 100644
index 6d65d7d23f..0000000000
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/** @file
- Provide SecTemporaryRamDone function.
-
-
- Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
-**/
-
-#include <PiPei.h>
-
-#include <Ppi/TemporaryRamDone.h>
-
-#include <Library/BaseMemoryLib.h>
-#include <Library/DebugLib.h>
-#include <Library/PcdLib.h>
-#include <Library/DebugAgentLib.h>
-#include <Library/FspWrapperPlatformLib.h>
-#include <Library/FspWrapperApiLib.h>
-#include <Library/BoardInitLib.h>
-
-/**
-This interface disables temporary memory in SEC Phase.
-**/
-VOID
-EFIAPI
-SecPlatformDisableTemporaryMemory (
- VOID
- )
-{
- EFI_STATUS Status;
- VOID *TempRamExitParam;
-
- DEBUG((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n"));
-
- Status = BoardInitBeforeTempRamExit ();
- ASSERT_EFI_ERROR (Status);
-
- TempRamExitParam = UpdateTempRamExitParam ();
- Status = CallTempRamExit (TempRamExitParam);
- DEBUG((DEBUG_INFO, "TempRamExit status: 0x%x\n", Status));
- ASSERT_EFI_ERROR(Status);
-
- Status = BoardInitAfterTempRamExit ();
- ASSERT_EFI_ERROR (Status);
-
- return ;
-}
-
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
index 3cd0478021..127147c734 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
@@ -127,7 +127,7 @@
GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.inf
HdaVerbTableLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.inf
I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAccessLib.inf
- PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+ PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLib.inf
# Thunderbolt
!if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
--
2.23.0.windows.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [edk2-platforms] [PATCH V1 09/13] MinPlatformPkg: FSP Dispatch Mode Support for PlatformSecLib
2019-11-14 6:06 [edk2-platforms] [PATCH V1 00/13] SecFspWrapperPlatformSecLib Cleanup Nate DeSimone
` (7 preceding siblings ...)
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 08/13] WhiskeylakeOpenBoardPkg: Remove SecFspWrapperPlatformSecLib override Nate DeSimone
@ 2019-11-14 6:06 ` Nate DeSimone
2019-11-14 15:17 ` Chiu, Chasel
2019-11-16 2:54 ` Kubacki, Michael A
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 10/13] MinPlatformPkg: Coding style cleanups in MinPlatformPkg.dec Nate DeSimone
` (3 subsequent siblings)
12 siblings, 2 replies; 44+ messages in thread
From: Nate DeSimone @ 2019-11-14 6:06 UTC (permalink / raw)
To: devel; +Cc: Michael Kubacki, Chasel Chiu, Liming Gao
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
.../FspWrapperPlatformSecLib.c | 34 ++++++++++++---
.../SecFspWrapperPlatformSecLib.inf | 7 +++-
.../SecTempRamDone.c | 42 +++++++++++++++----
.../Intel/MinPlatformPkg/MinPlatformPkg.dec | 28 ++++++++++++-
4 files changed, 95 insertions(+), 16 deletions(-)
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c
index 303f3aac40..876c073fc4 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c
@@ -1,7 +1,7 @@
/** @file
Provide FSP wrapper platform sec related function.
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -12,6 +12,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Ppi/SecPerformance.h>
#include <Ppi/FirmwareVolumeInfo.h>
#include <Ppi/TopOfTemporaryRam.h>
+#include <Ppi/PeiCoreFvLocation.h>
#include <Guid/FirmwareFileSystem2.h>
#include <Library/LocalApicLib.h>
@@ -66,6 +67,18 @@ PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi = {
SecGetPerformance
};
+EFI_PEI_CORE_FV_LOCATION_PPI mPeiCoreFvLocationPpi = {
+ (VOID *) (UINTN) FixedPcdGet32 (PcdFspmBaseAddress)
+};
+
+EFI_PEI_PPI_DESCRIPTOR mPeiCoreFvLocationPpiList[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gEfiPeiCoreFvLocationPpiGuid,
+ &mPeiCoreFvLocationPpi
+ }
+};
+
EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] = {
{
EFI_PEI_PPI_DESCRIPTOR_PPI,
@@ -129,6 +142,8 @@ SecPlatformMain (
)
{
EFI_PEI_PPI_DESCRIPTOR *PpiList;
+ UINT8 TopOfTemporaryRamPpiIndex;
+ UINT8 *CopyDestinationPointer;
DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeBase - 0x%x\n", SecCoreData->BootFirmwareVolumeBase));
DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeSize - 0x%x\n", SecCoreData->BootFirmwareVolumeSize));
@@ -150,13 +165,22 @@ SecPlatformMain (
// Use middle of Heap as temp buffer, it will be copied by caller.
// Do not use Stack, because it will cause wrong calculation on stack by PeiCore
//
- PpiList = (VOID *)((UINTN)SecCoreData->PeiTemporaryRamBase + (UINTN)SecCoreData->PeiTemporaryRamSize/2);
- CopyMem (PpiList, mPeiSecPlatformPpi, sizeof(mPeiSecPlatformPpi));
-
+ PpiList = (VOID *)((UINTN) SecCoreData->PeiTemporaryRamBase + (UINTN) SecCoreData->PeiTemporaryRamSize/2);
+ CopyDestinationPointer = (UINT8 *) PpiList;
+ TopOfTemporaryRamPpiIndex = 0;
+ if ((PcdGet8 (PcdFspModeSelection) == 0) && PcdGetBool (PcdFspDispatchModeUseFspPeiMain)) {
+ //
+ // In Dispatch mode, wrapper should provide PeiCoreFvLocationPpi.
+ //
+ CopyMem (CopyDestinationPointer, mPeiCoreFvLocationPpiList, sizeof (mPeiCoreFvLocationPpiList));
+ TopOfTemporaryRamPpiIndex = 1;
+ CopyDestinationPointer += sizeof (mPeiCoreFvLocationPpiList);
+ }
+ CopyMem (CopyDestinationPointer, mPeiSecPlatformPpi, sizeof(mPeiSecPlatformPpi));
//
// Patch TopOfTemporaryRamPpi
//
- PpiList[0].Ppi = (VOID *)((UINTN)SecCoreData->TemporaryRamBase + SecCoreData->TemporaryRamSize);
+ PpiList[TopOfTemporaryRamPpiIndex].Ppi = (VOID *)((UINTN) SecCoreData->TemporaryRamBase + SecCoreData->TemporaryRamSize);
return PpiList;
}
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
index 3f5a63f273..02c720c73d 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
@@ -72,18 +72,20 @@
BoardInitLib
SecBoardInitLib
TestPointCheckLib
+ PeiServicesTablePointerLib
[Ppis]
gEfiSecPlatformInformationPpiGuid ## CONSUMES
gPeiSecPerformancePpiGuid ## CONSUMES
gTopOfTemporaryRamPpiGuid ## PRODUCES
gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES
+ gFspTempRamExitPpiGuid ## CONSUMES
[Pcd]
gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize ## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress ## CONSUMES
gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ## CONSUMES
[FixedPcd]
gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## CONSUMES
@@ -91,3 +93,6 @@
gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset ## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize ## CONSUMES
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## CONSUMES
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain ## CONSUMES
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c
index cde8a80a4e..922e4ec204 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c
@@ -1,7 +1,7 @@
/** @file
Provide SecTemporaryRamDone function.
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -9,6 +9,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <PiPei.h>
#include <Ppi/TemporaryRamDone.h>
+#include <Ppi/TempRamExitPpi.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
@@ -17,6 +18,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/FspWrapperPlatformLib.h>
#include <Library/FspWrapperApiLib.h>
#include <Library/BoardInitLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
/**
This interface disables temporary memory in SEC Phase.
@@ -29,17 +31,41 @@ SecPlatformDisableTemporaryMemory (
{
EFI_STATUS Status;
VOID *TempRamExitParam;
+ CONST EFI_PEI_SERVICES **PeiServices;
+ FSP_TEMP_RAM_EXIT_PPI *TempRamExitPpi;
+
+ DEBUG ((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n"));
- DEBUG((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n"));
-
Status = BoardInitBeforeTempRamExit ();
ASSERT_EFI_ERROR (Status);
- TempRamExitParam = UpdateTempRamExitParam ();
- Status = CallTempRamExit (TempRamExitParam);
- DEBUG((DEBUG_INFO, "TempRamExit status: 0x%x\n", Status));
- ASSERT_EFI_ERROR(Status);
-
+ if (PcdGet8 (PcdFspModeSelection) == 1) {
+ //
+ // FSP API mode
+ //
+ TempRamExitParam = UpdateTempRamExitParam ();
+ Status = CallTempRamExit (TempRamExitParam);
+ DEBUG ((DEBUG_INFO, "TempRamExit status: 0x%x\n", Status));
+ ASSERT_EFI_ERROR (Status);
+ } else {
+ //
+ // FSP Dispatch mode
+ //
+ PeiServices = GetPeiServicesTablePointer ();
+ Status = (*PeiServices)->LocatePpi (
+ PeiServices,
+ &gFspTempRamExitPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &TempRamExitPpi
+ );
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+ TempRamExitPpi->TempRamExit (NULL);
+ }
+
Status = BoardInitAfterTempRamExit ();
ASSERT_EFI_ERROR (Status);
diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
index a851021c0b..856c17f737 100644
--- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
+++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
@@ -69,8 +69,6 @@ SetCacheMtrrLib|Include/Library/SetCacheMtrrLib.h
[PcdsFixedAtBuild, PcdsPatchableInModule]
-gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|FALSE|BOOLEAN|0x80000008
-
gMinPlatformPkgTokenSpaceGuid.PcdFspMaxUpdSize|0x00000000|UINT32|0x80000000
gMinPlatformPkgTokenSpaceGuid.PcdFspReservedSizeOnStackTop|0x00000040|UINT32|0x80000001
gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0x00000000|UINT32|0x80000002
@@ -272,6 +270,32 @@ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UINT32|0x90000019
#
gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4|UINT8|0xF00000A0
+ ## FSP Boot Mode Selector
+ # FALSE: The board is not a FSP wrapper (FSP binary not used)
+ # TRUE: The board is a FSP wrapper (FSP binary is used)
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|FALSE|BOOLEAN|0x80000008
+
+ ## FSP Dispatch Mode: Use the PEI Main Binary Included in FSP-M
+ # FALSE: The PEI Main included in FvPreMemory is used to dispatch all PEIMs
+ # (both inside FSP and outside FSP).
+ # Pros:
+ # * PEI Main is re-built from source and is always the latest version
+ # * Platform code can link any desired LibraryClass to PEI Main
+ # (Ex: Custom DebugLib instance, SerialPortLib, etc.)
+ # Cons:
+ # * The PEI Main being used to execute FSP PEIMs is not the PEI Main
+ # that the FSP PEIMs were tested with, adding risk of breakage.
+ # * Two copies of PEI Main will exist in the final binary,
+ # #1 in FSP-M, #2 in FvPreMemory. The copy in FSP-M is never
+ # executed, wasting space.
+ #
+ # <b>TRUE</b>: The PEI Main included in FSP is used to dispatch all PEIMs
+ # (both inside FSP and outside FSP). PEI Main will not be included in
+ # FvPreMemory. This is the default and is the recommended choice.
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE|BOOLEAN|0xF00000A8
+
[PcdsFeatureFlag]
gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit |FALSE|BOOLEAN|0xF00000A1
--
2.23.0.windows.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [edk2-platforms] [PATCH V1 10/13] MinPlatformPkg: Coding style cleanups in MinPlatformPkg.dec
2019-11-14 6:06 [edk2-platforms] [PATCH V1 00/13] SecFspWrapperPlatformSecLib Cleanup Nate DeSimone
` (8 preceding siblings ...)
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 09/13] MinPlatformPkg: FSP Dispatch Mode Support for PlatformSecLib Nate DeSimone
@ 2019-11-14 6:06 ` Nate DeSimone
2019-11-14 15:17 ` Chiu, Chasel
2019-11-16 2:54 ` Kubacki, Michael A
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 11/13] KabylakeOpenBoardPkg: Add support for PcdFspDispatchModeUseFspPeiMain Nate DeSimone
` (2 subsequent siblings)
12 siblings, 2 replies; 44+ messages in thread
From: Nate DeSimone @ 2019-11-14 6:06 UTC (permalink / raw)
To: devel; +Cc: Michael Kubacki, Chasel Chiu, Liming Gao
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
.../Intel/MinPlatformPkg/MinPlatformPkg.dec | 281 +++++++++---------
1 file changed, 139 insertions(+), 142 deletions(-)
diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
index 856c17f737..c6b5881646 100644
--- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
+++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
@@ -14,184 +14,182 @@
[Defines]
-DEC_SPECIFICATION = 0x00010017
-PACKAGE_NAME = MinPlatformPkg
-PACKAGE_VERSION = 0.1
-PACKAGE_GUID = 463B3B00-0D18-4a5f-90C0-D5B851D2574B
-
+ DEC_SPECIFICATION = 0x00010017
+ PACKAGE_NAME = MinPlatformPkg
+ PACKAGE_VERSION = 0.1
+ PACKAGE_GUID = 463B3B00-0D18-4a5f-90C0-D5B851D2574B
[Includes]
-Include
+ Include
[Ppis]
-gEdkiiSiliconInitializedPpiGuid = {0x82a72dc8, 0x61ec, 0x403e, {0xb1, 0x5a, 0x8d, 0x7a, 0x3a, 0x71, 0x84, 0x98}}
+ gEdkiiSiliconInitializedPpiGuid = {0x82a72dc8, 0x61ec, 0x403e, {0xb1, 0x5a, 0x8d, 0x7a, 0x3a, 0x71, 0x84, 0x98}}
-gPeiBaseMemoryTestPpiGuid = { 0xb6ec423c, 0x21d2, 0x490d, { 0x85, 0xc6, 0xdd, 0x58, 0x64, 0xea, 0xa6, 0x74 } }
-gPeiPlatformMemorySizePpiGuid = { 0x9a7ef41e, 0xc140, 0x4bd1, { 0xb8, 0x84, 0x1e, 0x11, 0x24, 0x0b, 0x4c, 0xe6 } }
+ gPeiBaseMemoryTestPpiGuid = {0xb6ec423c, 0x21d2, 0x490d, {0x85, 0xc6, 0xdd, 0x58, 0x64, 0xea, 0xa6, 0x74}}
+ gPeiPlatformMemorySizePpiGuid = {0x9a7ef41e, 0xc140, 0x4bd1, {0xb8, 0x84, 0x1e, 0x11, 0x24, 0x0b, 0x4c, 0xe6}}
[Guids]
-gMinPlatformPkgTokenSpaceGuid = {0x69d13bf0, 0xaf91, 0x4d96, {0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}}
+ gMinPlatformPkgTokenSpaceGuid = {0x69d13bf0, 0xaf91, 0x4d96, {0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}}
-gAdapterInfoPlatformTestPointGuid = {0x5381e3ea, 0xb77, 0x4580, {0xad, 0xdf, 0xa9, 0x1c, 0x8, 0x3b, 0xf2, 0x97}}
+ gAdapterInfoPlatformTestPointGuid = {0x5381e3ea, 0x0b77, 0x4580, {0xad, 0xdf, 0xa9, 0x1c, 0x08, 0x3b, 0xf2, 0x97}}
-gBoardDetectGuid = {0x1792429d, 0x9d94, 0x4e08, {0xa0, 0x99, 0x73, 0xa2, 0x86, 0xae, 0xb4, 0x35}}
-gBoardPreMemInitGuid = {0x191dcfcf, 0xe16e, 0x43bb, {0x9b, 0xc3, 0x6e, 0xee, 0x6f, 0xab, 0x3a, 0x27}}
-gBoardPostMemInitGuid = {0xa0e933ea, 0xa69, 0x47fb, {0xb2, 0xab, 0xa1, 0x6f, 0x71, 0x2d, 0x6f, 0x58}}
-gBoardNotificationInitGuid = {0x78dbcabf, 0xc544, 0x4e6f, {0xaf, 0x3a, 0x71, 0x17, 0xd9, 0x42, 0x4e, 0xd1}}
+ gBoardDetectGuid = {0x1792429d, 0x9d94, 0x4e08, {0xa0, 0x99, 0x73, 0xa2, 0x86, 0xae, 0xb4, 0x35}}
+ gBoardPreMemInitGuid = {0x191dcfcf, 0xe16e, 0x43bb, {0x9b, 0xc3, 0x6e, 0xee, 0x6f, 0xab, 0x3a, 0x27}}
+ gBoardPostMemInitGuid = {0xa0e933ea, 0xa69, 0x47fb, {0xb2, 0xab, 0xa1, 0x6f, 0x71, 0x2d, 0x6f, 0x58}}
+ gBoardNotificationInitGuid = {0x78dbcabf, 0xc544, 0x4e6f, {0xaf, 0x3a, 0x71, 0x17, 0xd9, 0x42, 0x4e, 0xd1}}
-gBoardAcpiTableGuid = {0xd70e9f57, 0x69f, 0x4bef, {0x96, 0xc0, 0x84, 0x74, 0xf4, 0xa2, 0x5f, 0x3a}}
-gBoardAcpiEnableGuid = {0x9727b610, 0xf645, 0x4429, {0x89, 0x21, 0x2c, 0x2b, 0x58, 0xdc, 0xbb, 0xa}}
+ gBoardAcpiTableGuid = {0xd70e9f57, 0x69f, 0x4bef, {0x96, 0xc0, 0x84, 0x74, 0xf4, 0xa2, 0x5f, 0x3a}}
+ gBoardAcpiEnableGuid = {0x9727b610, 0xf645, 0x4429, {0x89, 0x21, 0x2c, 0x2b, 0x58, 0xdc, 0xbb, 0x0a}}
-gDefaultDataFileGuid = { 0x1ae42876, 0x008f, 0x4161, { 0xb2, 0xb7, 0x1c, 0x0d, 0x15, 0xc5, 0xef, 0x43 }}
-gDefaultDataOptSizeFileGuid = { 0x003e7b41, 0x98a2, 0x4be2, { 0xb2, 0x7a, 0x6c, 0x30, 0xc7, 0x65, 0x52, 0x25 }}
+ gDefaultDataFileGuid = {0x1ae42876, 0x008f, 0x4161, {0xb2, 0xb7, 0x1c, 0x0d, 0x15, 0xc5, 0xef, 0x43}}
+ gDefaultDataOptSizeFileGuid = {0x003e7b41, 0x98a2, 0x4be2, {0xb2, 0x7a, 0x6c, 0x30, 0xc7, 0x65, 0x52, 0x25}}
[LibraryClasses]
-PeiLib|Include/Library/PeiLib.h
+ PeiLib|Include/Library/PeiLib.h
-AslUpdateLib|Include/Library/AslUpdateLib.h
-BoardAcpiEnableLib|Include/Library/BoardAcpiEnableLib.h
-BoardAcpiTableLib|Include/Library/BoardAcpiTableLib.h
+ AslUpdateLib|Include/Library/AslUpdateLib.h
+ BoardAcpiEnableLib|Include/Library/BoardAcpiEnableLib.h
+ BoardAcpiTableLib|Include/Library/BoardAcpiTableLib.h
-SiliconPolicyInitLib|Include/Library/SiliconPolicyInitLib.h
-SiliconPolicyUpdateLib|Include/Library/SiliconPolicyUpdateLib.h
+ SiliconPolicyInitLib|Include/Library/SiliconPolicyInitLib.h
+ SiliconPolicyUpdateLib|Include/Library/SiliconPolicyUpdateLib.h
-SpiFlashCommonLib|Include/Library/SpiFlashCommonLib.h
+ SpiFlashCommonLib|Include/Library/SpiFlashCommonLib.h
-BoardInitLib|Include/Library/BoardInitLib.h
-MultiBoardInitSupportLib|Include/Library/MultiBoardInitSupportLib.h
-SecBoardInitLib|Include/Library/SecBoardInitLib.h
+ BoardInitLib|Include/Library/BoardInitLib.h
+ MultiBoardInitSupportLib|Include/Library/MultiBoardInitSupportLib.h
+ SecBoardInitLib|Include/Library/SecBoardInitLib.h
-TestPointLib|Include/Library/TestPointLib.h
-TestPointCheckLib|Include/Library/TestPointCheckLib.h
+ TestPointLib|Include/Library/TestPointLib.h
+ TestPointCheckLib|Include/Library/TestPointCheckLib.h
SetCacheMtrrLib|Include/Library/SetCacheMtrrLib.h
[PcdsFixedAtBuild, PcdsPatchableInModule]
-gMinPlatformPkgTokenSpaceGuid.PcdFspMaxUpdSize|0x00000000|UINT32|0x80000000
-gMinPlatformPkgTokenSpaceGuid.PcdFspReservedSizeOnStackTop|0x00000040|UINT32|0x80000001
-gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0x00000000|UINT32|0x80000002
+ gMinPlatformPkgTokenSpaceGuid.PcdFspMaxUpdSize|0x00000000|UINT32|0x80000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFspReservedSizeOnStackTop|0x00000040|UINT32|0x80000001
+ gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0x00000000|UINT32|0x80000002
-gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000|UINT32|0x9000000B
-gMinPlatformPkgTokenSpaceGuid.PcdLocalApicMmioSize|0x1000|UINT32|0x9000000C
+ gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000|UINT32|0x9000000B
+ gMinPlatformPkgTokenSpaceGuid.PcdLocalApicMmioSize|0x1000|UINT32|0x9000000C
-gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress|0xFEC00000|UINT32|0x9000000D
-gMinPlatformPkgTokenSpaceGuid.PcdIoApicMmioSize|0x1000|UINT32|0x9000000E
-gMinPlatformPkgTokenSpaceGuid.PcdIoApicId|0x02|UINT8|0x90000014
+ gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress|0xFEC00000|UINT32|0x9000000D
+ gMinPlatformPkgTokenSpaceGuid.PcdIoApicMmioSize|0x1000|UINT32|0x9000000E
+ gMinPlatformPkgTokenSpaceGuid.PcdIoApicId|0x02|UINT8|0x90000014
-gMinPlatformPkgTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x90000012
-gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x90000013
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x90000012
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x90000013
-gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|0|UINT8|0x90000015
-gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase|0x09|UINT8|0x90000016
-gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000|UINT32|0x90000017
-gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicInterruptBase|24|UINT32|0x90000018
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|0|UINT8|0x90000015
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase|0x09|UINT8|0x90000016
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000|UINT32|0x90000017
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicInterruptBase|24|UINT32|0x90000018
-gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2|UINT32|0x90000021
-gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8|UINT32|0x90000022
-gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|4|UINT32|0x90000023
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2|UINT32|0x90000021
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8|UINT32|0x90000022
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|4|UINT32|0x90000023
-gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x02|UINT8|0x90000025
-gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0001|UINT16|0x90000026
-gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000086A5|UINT32|0x90000027
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x02|UINT8|0x90000025
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0001|UINT16|0x90000026
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000086A5|UINT32|0x90000027
-gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0x65|UINT32|0x20000500
-gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0x30|UINT32|0x20000501
-gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402|UINT32|0x20000502
-gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b|UINT32|0x20000503
-gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x25|UINT32|0x20000504
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0x65|UINT32|0x20000500
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0x30|UINT32|0x20000501
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402|UINT32|0x20000502
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b|UINT32|0x20000503
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x25|UINT32|0x20000504
-#
-# The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags
-#
-# BIT0: If set, expresses that for all synchronous SMM entries,SMM will validate that input and output buffers lie entirely within the expected fixed memory regions.
-# BIT1: If set, expresses that for all synchronous SMM entries, SMM will validate that input and output pointers embedded within the fixed communication buffer only refer to address ranges \
-# that lie entirely within the expected fixed memory regions.
-# BIT2: Firmware setting this bit is an indication that it will not allow reconfiguration of system resources via non-architectural mechanisms.
-# BIT3-31: Reserved
-#
-gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0|UINT32|0x10001006
+ #
+ # The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags
+ #
+ # BIT0: If set, expresses that for all synchronous SMM entries,SMM will validate that input and output buffers lie entirely within the expected fixed memory regions.
+ # BIT1: If set, expresses that for all synchronous SMM entries, SMM will validate that input and output pointers embedded within the fixed communication buffer only refer to address ranges \
+ # that lie entirely within the expected fixed memory regions.
+ # BIT2: Firmware setting this bit is an indication that it will not allow reconfiguration of system resources via non-architectural mechanisms.
+ # BIT3-31: Reserved
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0|UINT32|0x10001006
-gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable|TRUE|BOOLEAN|0x00100206
+ gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable|TRUE|BOOLEAN|0x00100206
-#
-# See HstiIbvFeatureBit.h for the definition
-#
-# #define HSTI_BYTE<X>_<AAA> BIT<Y>
-#
-# It means BYTE<X> BIT<Y> is for feature <AAA>.
-#
-gMinPlatformPkgTokenSpaceGuid.PcdHstiIbvPlatformFeature|{0x00, 0x00, 0x00}|VOID*|0x00100301
+ #
+ # See HstiIbvFeatureBit.h for the definition
+ #
+ # #define HSTI_BYTE<X>_<AAA> BIT<Y>
+ #
+ # It means BYTE<X> BIT<Y> is for feature <AAA>.
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdHstiIbvPlatformFeature|{0x00, 0x00, 0x00}|VOID*|0x00100301
-#
-# See TestPointCheckLib.h for the definition
-#
-# #define TEST_POINT_BYTE<X>_<AAA> BIT<Y>
-#
-# It means BYTE<X> BIT<Y> is for feature <AAA>.
-# BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 BYTE8
-# Stage debug: {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-# Stage memory: {0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-# Stage UEFI boot: {0x03, 0x07, 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-# Stage OS boot: {0x03, 0x07, 0x03, 0x05, 0x3F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-# Stage Secure boot: {0x03, 0x0F, 0x03, 0x1D, 0x3F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-# Stage Advanced: {0x03, 0x0F, 0x03, 0x1D, 0x3F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
-gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x03, 0x1D, 0x3F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00100302
+ #
+ # See TestPointCheckLib.h for the definition
+ #
+ # #define TEST_POINT_BYTE<X>_<AAA> BIT<Y>
+ #
+ # It means BYTE<X> BIT<Y> is for feature <AAA>.
+ # BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 BYTE8
+ # Stage debug: {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ # Stage memory: {0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ # Stage UEFI boot: {0x03, 0x07, 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ # Stage OS boot: {0x03, 0x07, 0x03, 0x05, 0x3F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ # Stage Secure boot: {0x03, 0x0F, 0x03, 0x1D, 0x3F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ # Stage Advanced: {0x03, 0x0F, 0x03, 0x1D, 0x3F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x03, 0x1D, 0x3F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00100302
-[PcdsFixedAtBuild, PcdsPatchableInModule]
-##
-## The Flash relevant PCD are ineffective and will be patched basing on FDF definitions during build.
-## Set all of them to 0 here to prevent from confusion.
-##
-gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFF800000|UINT32|0x10000001
-gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize|0x00800000|UINT32|0x10000002
-
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0xFFE60000|UINT32|0x30000004
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x000A0000|UINT32|0x30000005
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset|0x00660000|UINT32|0x30000006
-
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|0x00000000|UINT32|0x20000004
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize|0x00000000|UINT32|0x20000005
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|0x00000000|UINT32|0x20000006
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|0x00000000|UINT32|0x20000007
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize|0x00000000|UINT32|0x20000008
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|0x00000000|UINT32|0x20000009
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|0x00000000|UINT32|0x2000000A
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize|0x00000000|UINT32|0x2000000B
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|0x00000000|UINT32|0x2000000C
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|0x00000000|UINT32|0x2000000D
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize|0x00000000|UINT32|0x2000000E
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|0x00000000|UINT32|0x2000000F
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|0x00000000|UINT32|0x20000010
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize|0x00000000|UINT32|0x20000011
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|0x00000000|UINT32|0x20000012
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|0x00000000|UINT32|0x20000013
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize|0x00000000|UINT32|0x20000014
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|0x00000000|UINT32|0x20000015
-
-gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageBase|0x00000000|UINT32|0x20000016
-gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize|0x00000000|UINT32|0x20000017
-gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset|0x00000000|UINT32|0x20000018
-gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|0x00000000|UINT32|0x20000019
-gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|0x00000000|UINT32|0x2000001A
-gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|0x00000000|UINT32|0x2000001B
-
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|0x00000000|UINT32|0x20000021
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize|0x00000000|UINT32|0x20000022
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|0x00000000|UINT32|0x20000023
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|0x00000000|UINT32|0x20000024
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize|0x00000000|UINT32|0x20000025
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|0x00000000|UINT32|0x20000026
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|0x00000000|UINT32|0x20000027
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize|0x00000000|UINT32|0x20000028
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|0x00000000|UINT32|0x20000029
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUBase|0x00000000|UINT32|0x2000002A
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUSize|0x00000000|UINT32|0x2000002B
-gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUOffset|0x00000000|UINT32|0x2000002C
+ ##
+ ## The Flash relevant PCD are ineffective and will be patched basing on FDF definitions during build.
+ ## Set all of them to 0 here to prevent from confusion.
+ ##
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFF800000|UINT32|0x10000001
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize|0x00800000|UINT32|0x10000002
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0xFFE60000|UINT32|0x30000004
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x000A0000|UINT32|0x30000005
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset|0x00660000|UINT32|0x30000006
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|0x00000000|UINT32|0x20000004
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize|0x00000000|UINT32|0x20000005
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|0x00000000|UINT32|0x20000006
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|0x00000000|UINT32|0x20000007
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize|0x00000000|UINT32|0x20000008
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|0x00000000|UINT32|0x20000009
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|0x00000000|UINT32|0x2000000A
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize|0x00000000|UINT32|0x2000000B
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|0x00000000|UINT32|0x2000000C
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|0x00000000|UINT32|0x2000000D
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize|0x00000000|UINT32|0x2000000E
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|0x00000000|UINT32|0x2000000F
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|0x00000000|UINT32|0x20000010
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize|0x00000000|UINT32|0x20000011
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|0x00000000|UINT32|0x20000012
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|0x00000000|UINT32|0x20000013
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize|0x00000000|UINT32|0x20000014
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|0x00000000|UINT32|0x20000015
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageBase|0x00000000|UINT32|0x20000016
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize|0x00000000|UINT32|0x20000017
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset|0x00000000|UINT32|0x20000018
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|0x00000000|UINT32|0x20000019
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|0x00000000|UINT32|0x2000001A
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|0x00000000|UINT32|0x2000001B
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|0x00000000|UINT32|0x20000021
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize|0x00000000|UINT32|0x20000022
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|0x00000000|UINT32|0x20000023
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|0x00000000|UINT32|0x20000024
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize|0x00000000|UINT32|0x20000025
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|0x00000000|UINT32|0x20000026
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|0x00000000|UINT32|0x20000027
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize|0x00000000|UINT32|0x20000028
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|0x00000000|UINT32|0x20000029
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUBase|0x00000000|UINT32|0x2000002A
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUSize|0x00000000|UINT32|0x2000002B
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUOffset|0x00000000|UINT32|0x2000002C
[PcdsDynamic, PcdsDynamicEx]
-gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UINT32|0x90000019
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UINT32|0x90000019
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
@@ -261,7 +259,7 @@ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UINT32|0x90000019
[PcdsFixedAtBuild]
- #
+ ## MinPlatform Boot Stage Selector
# Stage 1 - enable debug (system deadloop after debug init)
# Stage 2 - mem init (system deadloop after mem init)
# Stage 3 - boot to shell only
@@ -305,4 +303,3 @@ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UINT32|0x90000019
gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable |FALSE|BOOLEAN|0xF00000A5
gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE|BOOLEAN|0xF00000A6
gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable |FALSE|BOOLEAN|0xF00000A7
-
--
2.23.0.windows.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [edk2-platforms] [PATCH V1 11/13] KabylakeOpenBoardPkg: Add support for PcdFspDispatchModeUseFspPeiMain
2019-11-14 6:06 [edk2-platforms] [PATCH V1 00/13] SecFspWrapperPlatformSecLib Cleanup Nate DeSimone
` (9 preceding siblings ...)
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 10/13] MinPlatformPkg: Coding style cleanups in MinPlatformPkg.dec Nate DeSimone
@ 2019-11-14 6:06 ` Nate DeSimone
2019-11-14 15:18 ` Chiu, Chasel
2019-11-16 2:54 ` Kubacki, Michael A
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 12/13] KabylakeOpenBoardPkg: Remove SecFspWrapperPlatformSecLib override Nate DeSimone
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 13/13] MinPlatformPkg: Remove BoardInitLib dependency from PlatformSecLib Nate DeSimone
12 siblings, 2 replies; 44+ messages in thread
From: Nate DeSimone @ 2019-11-14 6:06 UTC (permalink / raw)
To: devel; +Cc: Chasel Chiu, Michael Kubacki
If PcdFspDispatchModeUseFspPeiMain is FALSE, then the BoardPkg
should include PeiMain in FvPreMemory.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
.../KabylakeRvp3/OpenBoardPkg.fdf | 5 +++--
.../KabylakeRvp3/OpenBoardPkgPcd.dsc | 20 +++++++++++++++++++
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
index 98eb7dcb5a..3b3b153b68 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
@@ -229,10 +229,11 @@ READ_LOCK_STATUS = TRUE
FvNameGuid = FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D
INF UefiCpuPkg/SecCore/SecCore.inf
-!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
+!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || (gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain == FALSE) || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
#
# PeiMain is needed only for FSP API mode or EDK2 build,
-# in FSP dispatch mode the one inside FSP Binary is launched.
+# in FSP dispatch mode the one inside FSP Binary is launched
+# unless requested otherwise (PcdFspDispatchModeUseFspPeiMain == FALSE).
#
INF MdeModulePkg/Core/Pei/PeiMain.inf
!endif
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
index 580504cbc1..5474edd01c 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
@@ -39,6 +39,26 @@
#
gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
+ #
+ # FALSE: The PEI Main included in FvPreMemory is used to dispatch all PEIMs
+ # (both inside FSP and outside FSP).
+ # Pros:
+ # * PEI Main is re-built from source and is always the latest version
+ # * Platform code can link any desired LibraryClass to PEI Main
+ # (Ex: Custom DebugLib instance, SerialPortLib, etc.)
+ # Cons:
+ # * The PEI Main being used to execute FSP PEIMs is not the PEI Main
+ # that the FSP PEIMs were tested with, adding risk of breakage.
+ # * Two copies of PEI Main will exist in the final binary,
+ # #1 in FSP-M, #2 in FvPreMemory. The copy in FSP-M is never
+ # executed, wasting space.
+ #
+ # <b>TRUE</b>: The PEI Main included in FSP is used to dispatch all PEIMs
+ # (both inside FSP and outside FSP). PEI Main will not be included in
+ # FvPreMemory. This is the default and is the recommended choice.
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE
+
#
# FSP Base address PCD will be updated in FDF basing on flash map.
#
--
2.23.0.windows.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [edk2-platforms] [PATCH V1 12/13] KabylakeOpenBoardPkg: Remove SecFspWrapperPlatformSecLib override
2019-11-14 6:06 [edk2-platforms] [PATCH V1 00/13] SecFspWrapperPlatformSecLib Cleanup Nate DeSimone
` (10 preceding siblings ...)
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 11/13] KabylakeOpenBoardPkg: Add support for PcdFspDispatchModeUseFspPeiMain Nate DeSimone
@ 2019-11-14 6:06 ` Nate DeSimone
2019-11-14 15:18 ` Chiu, Chasel
2019-11-16 2:54 ` Kubacki, Michael A
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 13/13] MinPlatformPkg: Remove BoardInitLib dependency from PlatformSecLib Nate DeSimone
12 siblings, 2 replies; 44+ messages in thread
From: Nate DeSimone @ 2019-11-14 6:06 UTC (permalink / raw)
To: devel; +Cc: Chasel Chiu, Michael Kubacki, Jeremy Soller
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
.../FspWrapperPlatformSecLib.c | 186 ---------
.../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 40 --
.../SecFspWrapperPlatformSecLib/Ia32/Fsp.h | 42 --
.../Ia32/PeiCoreEntry.nasm | 130 -------
.../Ia32/SecEntry.nasm | 361 ------------------
.../Ia32/Stack.nasm | 72 ----
.../PlatformInit.c | 47 ---
.../SecFspWrapperPlatformSecLib.inf | 97 -----
.../SecGetPerformance.c | 89 -----
.../SecPlatformInformation.c | 78 ----
.../SecRamInitData.c | 36 --
.../SecTempRamDone.c | 73 ----
.../GalagoPro3/OpenBoardPkg.dsc | 2 +-
.../KabylakeRvp3/OpenBoardPkg.dsc | 2 +-
14 files changed, 2 insertions(+), 1253 deletions(-)
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c
deleted file mode 100644
index d40eecae95..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/** @file
- Provide FSP wrapper platform sec related function.
-
-Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <PiPei.h>
-
-#include <Ppi/SecPlatformInformation.h>
-#include <Ppi/SecPerformance.h>
-#include <Ppi/FirmwareVolumeInfo.h>
-#include <Ppi/TopOfTemporaryRam.h>
-#include <Ppi/PeiCoreFvLocation.h>
-#include <Guid/FirmwareFileSystem2.h>
-
-#include <Library/LocalApicLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/DebugLib.h>
-#include <Library/IoLib.h>
-
-/**
- This interface conveys state information out of the Security (SEC) phase into PEI.
-
- @param[in] PeiServices Pointer to the PEI Services Table.
- @param[in,out] StructureSize Pointer to the variable describing size of the input buffer.
- @param[out] PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
-
- @retval EFI_SUCCESS The data was successfully returned.
- @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
-
-**/
-EFI_STATUS
-EFIAPI
-SecPlatformInformation (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN OUT UINT64 *StructureSize,
- OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
- );
-
-/**
- This interface conveys performance information out of the Security (SEC) phase into PEI.
-
- This service is published by the SEC phase. The SEC phase handoff has an optional
- EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the
- PEI Foundation. As such, if the platform supports collecting performance data in SEC,
- this information is encapsulated into the data structure abstracted by this service.
- This information is collected for the boot-strap processor (BSP) on IA-32.
-
- @param[in] PeiServices The pointer to the PEI Services Table.
- @param[in] This The pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.
- @param[out] Performance The pointer to performance data collected in SEC phase.
-
- @retval EFI_SUCCESS The data was successfully returned.
-
-**/
-EFI_STATUS
-EFIAPI
-SecGetPerformance (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN PEI_SEC_PERFORMANCE_PPI *This,
- OUT FIRMWARE_SEC_PERFORMANCE *Performance
- );
-
-PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi = {
- SecGetPerformance
-};
-
-EFI_PEI_CORE_FV_LOCATION_PPI mPeiCoreFvLocationPpi = {
- (VOID *) (UINTN) FixedPcdGet32 (PcdFspmBaseAddress)
-};
-
-EFI_PEI_PPI_DESCRIPTOR mPeiCoreFvLocationPpiList[] = {
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI,
- &gEfiPeiCoreFvLocationPpiGuid,
- &mPeiCoreFvLocationPpi
- }
-};
-
-EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] = {
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI,
- &gTopOfTemporaryRamPpiGuid,
- NULL // To be patched later.
- },
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
- &gPeiSecPerformancePpiGuid,
- &mSecPerformancePpi
- },
-};
-
-#define LEGACY_8259_MASK_REGISTER_MASTER 0x21
-#define LEGACY_8259_MASK_REGISTER_SLAVE 0xA1
-#define LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER 0x4D0
-#define LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE 0x4D1
-
-/**
- Write to mask and edge/level triggered registers of master and slave 8259 PICs.
-
- @param[in] Mask low byte for master PIC mask register,
- high byte for slave PIC mask register.
- @param[in] EdgeLevel low byte for master PIC edge/level triggered register,
- high byte for slave PIC edge/level triggered register.
-
-**/
-VOID
-Interrupt8259WriteMask (
- IN UINT16 Mask,
- IN UINT16 EdgeLevel
- )
-{
- IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, (UINT8) Mask);
- IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, (UINT8) (Mask >> 8));
- IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER, (UINT8) EdgeLevel);
- IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE, (UINT8) (EdgeLevel >> 8));
-}
-
-/**
- A developer supplied function to perform platform specific operations.
-
- It's a developer supplied function to perform any operations appropriate to a
- given platform. It's invoked just before passing control to PEI core by SEC
- core. Platform developer may modify the SecCoreData passed to PEI Core.
- It returns a platform specific PPI list that platform wishes to pass to PEI core.
- The Generic SEC core module will merge this list to join the final list passed to
- PEI core.
-
- @param[in,out] SecCoreData The same parameter as passing to PEI core. It
- could be overridden by this function.
-
- @return The platform specific PPI list to be passed to PEI core or
- NULL if there is no need of such platform specific PPI list.
-
-**/
-EFI_PEI_PPI_DESCRIPTOR *
-EFIAPI
-SecPlatformMain (
- IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData
- )
-{
- EFI_PEI_PPI_DESCRIPTOR *PpiList;
- UINT8 TopOfTemporaryRamPpiIndex;
- UINT8 *CopyDestinationPointer;
-
- DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeBase - 0x%x\n", SecCoreData->BootFirmwareVolumeBase));
- DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeSize - 0x%x\n", SecCoreData->BootFirmwareVolumeSize));
- DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamBase - 0x%x\n", SecCoreData->TemporaryRamBase));
- DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamSize - 0x%x\n", SecCoreData->TemporaryRamSize));
- DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamBase - 0x%x\n", SecCoreData->PeiTemporaryRamBase));
- DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamSize - 0x%x\n", SecCoreData->PeiTemporaryRamSize));
- DEBUG ((DEBUG_INFO, "FSP Wrapper StackBase - 0x%x\n", SecCoreData->StackBase));
- DEBUG ((DEBUG_INFO, "FSP Wrapper StackSize - 0x%x\n", SecCoreData->StackSize));
-
- InitializeApicTimer (0, (UINT32) -1, TRUE, 5);
-
- //
- // Set all 8259 interrupts to edge triggered and disabled
- //
- Interrupt8259WriteMask (0xFFFF, 0x0000);
-
- //
- // Use middle of Heap as temp buffer, it will be copied by caller.
- // Do not use Stack, because it will cause wrong calculation on stack by PeiCore
- //
- PpiList = (VOID *)((UINTN) SecCoreData->PeiTemporaryRamBase + (UINTN) SecCoreData->PeiTemporaryRamSize/2);
- CopyDestinationPointer = (UINT8 *) PpiList;
- TopOfTemporaryRamPpiIndex = 0;
- if (PcdGet8 (PcdFspModeSelection) == 0) {
- //
- // In Dispatch mode, wrapper should provide PeiCoreFvLocationPpi.
- //
- CopyMem (CopyDestinationPointer, mPeiCoreFvLocationPpiList, sizeof (mPeiCoreFvLocationPpiList));
- TopOfTemporaryRamPpiIndex = 1;
- CopyDestinationPointer += sizeof (mPeiCoreFvLocationPpiList);
- }
- CopyMem (CopyDestinationPointer, mPeiSecPlatformPpi, sizeof(mPeiSecPlatformPpi));
- //
- // Patch TopOfTemporaryRamPpi
- //
- PpiList[TopOfTemporaryRamPpiIndex].Ppi = (VOID *)((UINTN) SecCoreData->TemporaryRamBase + SecCoreData->TemporaryRamSize);
-
- return PpiList;
-}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
deleted file mode 100644
index 7c0f605b92..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/** @file
-
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef __FSPT_CORE_UPD_H__
-#define __FSPT_CORE_UPD_H__
-
-#pragma pack(1)
-
-/** Fsp T Core UPD
-**/
-typedef struct {
-
-/** Offset 0x0020
-**/
- UINT32 MicrocodeRegionBase;
-
-/** Offset 0x0024
-**/
- UINT32 MicrocodeRegionSize;
-
-/** Offset 0x0028
-**/
- UINT32 CodeRegionBase;
-
-/** Offset 0x002C
-**/
- UINT32 CodeRegionSize;
-
-/** Offset 0x0030
-**/
- UINT8 Reserved[16];
-} FSPT_CORE_UPD;
-
-#pragma pack()
-
-#endif
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h
deleted file mode 100644
index 9f6cdcf476..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/** @file
- Fsp related definitions
-
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef __FSP_H__
-#define __FSP_H__
-
-//
-// Fv Header
-//
-#define FVH_SIGINATURE_OFFSET 0x28
-#define FVH_SIGINATURE_VALID_VALUE 0x4856465F // valid signature:_FVH
-#define FVH_HEADER_LENGTH_OFFSET 0x30
-#define FVH_EXTHEADER_OFFSET_OFFSET 0x34
-#define FVH_EXTHEADER_SIZE_OFFSET 0x10
-
-//
-// Ffs Header
-//
-#define FSP_HEADER_GUID_DWORD1 0x912740BE
-#define FSP_HEADER_GUID_DWORD2 0x47342284
-#define FSP_HEADER_GUID_DWORD3 0xB08471B9
-#define FSP_HEADER_GUID_DWORD4 0x0C3F3527
-#define FFS_HEADER_SIZE_VALUE 0x18
-
-//
-// Section Header
-//
-#define SECTION_HEADER_TYPE_OFFSET 0x03
-#define RAW_SECTION_HEADER_SIZE_VALUE 0x04
-
-//
-// Fsp Header
-//
-#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C
-#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30
-
-#endif
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
deleted file mode 100644
index 5c5b788085..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
+++ /dev/null
@@ -1,130 +0,0 @@
-;------------------------------------------------------------------------------
-;
-; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
-; SPDX-License-Identifier: BSD-2-Clause-Patent
-;
-; Module Name:
-;
-; PeiCoreEntry.nasm
-;
-; Abstract:
-;
-; Find and call SecStartup
-;
-;------------------------------------------------------------------------------
-
-SECTION .text
-
-extern ASM_PFX(SecStartup)
-extern ASM_PFX(PlatformInit)
-
-global ASM_PFX(CallPeiCoreEntryPoint)
-ASM_PFX(CallPeiCoreEntryPoint):
- ;
- ; Obtain the hob list pointer
- ;
- mov eax, [esp+4]
- ;
- ; Obtain the stack information
- ; ECX: start of range
- ; EDX: end of range
- ;
- mov ecx, [esp+8]
- mov edx, [esp+0xC]
-
- ;
- ; Platform init
- ;
- pushad
- push edx
- push ecx
- push eax
- call ASM_PFX(PlatformInit)
- pop eax
- pop eax
- pop eax
- popad
-
- ;
- ; Set stack top pointer
- ;
- mov esp, edx
-
- ;
- ; Push the hob list pointer
- ;
- push eax
-
- ;
- ; Save the value
- ; ECX: start of range
- ; EDX: end of range
- ;
- mov ebp, esp
- push ecx
- push edx
-
- ;
- ; Push processor count to stack first, then BIST status (AP then BSP)
- ;
- mov eax, 1
- cpuid
- shr ebx, 16
- and ebx, 0xFF
- cmp bl, 1
- jae PushProcessorCount
-
- ;
- ; Some processors report 0 logical processors. Effectively 0 = 1.
- ; So we fix up the processor count
- ;
- inc ebx
-
-PushProcessorCount:
- push ebx
-
- ;
- ; We need to implement a long-term solution for BIST capture. For now, we just copy BSP BIST
- ; for all processor threads
- ;
- xor ecx, ecx
- mov cl, bl
-PushBist:
- movd eax, mm0
- push eax
- loop PushBist
-
- ; Save Time-Stamp Counter
- movd eax, mm5
- push eax
-
- movd eax, mm6
- push eax
-
- ;
- ; Pass entry point of the PEI core
- ;
- mov edi, 0xFFFFFFE0
- push DWORD [edi]
-
- ;
- ; Pass BFV into the PEI Core
- ;
- mov edi, 0xFFFFFFFC
- push DWORD [edi]
-
- ;
- ; Pass stack size into the PEI Core
- ;
- mov ecx, [ebp - 4]
- mov edx, [ebp - 8]
- push ecx ; RamBase
-
- sub edx, ecx
- push edx ; RamSize
-
- ;
- ; Pass Control into the PEI Core
- ;
- call ASM_PFX(SecStartup)
-
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
deleted file mode 100644
index 7f6d771e41..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
+++ /dev/null
@@ -1,361 +0,0 @@
-;------------------------------------------------------------------------------
-;
-; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
-; SPDX-License-Identifier: BSD-2-Clause-Patent
-; Module Name:
-;
-; SecEntry.nasm
-;
-; Abstract:
-;
-; This is the code that goes from real-mode to protected mode.
-; It consumes the reset vector, calls TempRamInit API from FSP binary.
-;
-;------------------------------------------------------------------------------
-
-#include "Fsp.h"
-
-SECTION .text
-
-extern ASM_PFX(CallPeiCoreEntryPoint)
-extern ASM_PFX(FsptUpdDataPtr)
-extern ASM_PFX(BoardBeforeTempRamInit)
-; Pcds
-extern ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))
-extern ASM_PFX(PcdGet32 (PcdFsptBaseAddress))
-
-;----------------------------------------------------------------------------
-;
-; Procedure: _ModuleEntryPoint
-;
-; Input: None
-;
-; Output: None
-;
-; Destroys: Assume all registers
-;
-; Description:
-;
-; Transition to non-paged flat-model protected mode from a
-; hard-coded GDT that provides exactly two descriptors.
-; This is a bare bones transition to protected mode only
-; used for a while in PEI and possibly DXE.
-;
-; After enabling protected mode, a far jump is executed to
-; transfer to PEI using the newly loaded GDT.
-;
-; Return: None
-;
-; MMX Usage:
-; MM0 = BIST State
-; MM5 = Save time-stamp counter value high32bit
-; MM6 = Save time-stamp counter value low32bit.
-;
-;----------------------------------------------------------------------------
-
-BITS 16
-align 4
-global ASM_PFX(_ModuleEntryPoint)
-ASM_PFX(_ModuleEntryPoint):
- fninit ; clear any pending Floating point exceptions
- ;
- ; Store the BIST value in mm0
- ;
- movd mm0, eax
- cli
-
- ;
- ; Check INIT# is asserted by port 0xCF9
- ;
- mov dx, 0CF9h
- in al, dx
- cmp al, 04h
- jnz NotWarmStart
-
-
- ;
- ; @note Issue warm reset, since if CPU only reset is issued not all MSRs are restored to their defaults
- ;
- mov dx, 0CF9h
- mov al, 06h
- out dx, al
-
-NotWarmStart:
- ;
- ; Save time-stamp counter value
- ; rdtsc load 64bit time-stamp counter to EDX:EAX
- ;
- rdtsc
- movd mm5, edx
- movd mm6, eax
-
- ;
- ; Load the GDT table in GdtDesc
- ;
- mov esi, GdtDesc
- DB 66h
- lgdt [cs:si]
-
- ;
- ; Transition to 16 bit protected mode
- ;
- mov eax, cr0 ; Get control register 0
- or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1)
- mov cr0, eax ; Activate protected mode
-
- mov eax, cr4 ; Get control register 4
- or eax, 00000600h ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
- mov cr4, eax
-
- ;
- ; Now we're in 16 bit protected mode
- ; Set up the selectors for 32 bit protected mode entry
- ;
- mov ax, SYS_DATA_SEL
- mov ds, ax
- mov es, ax
- mov fs, ax
- mov gs, ax
- mov ss, ax
-
- ;
- ; Transition to Flat 32 bit protected mode
- ; The jump to a far pointer causes the transition to 32 bit mode
- ;
- mov esi, ProtectedModeEntryLinearAddress
- jmp dword far [cs:si]
-
-;----------------------------------------------------------------------------
-;
-; Procedure: ProtectedModeEntryPoint
-;
-; Input: None
-;
-; Output: None
-;
-; Destroys: Assume all registers
-;
-; Description:
-;
-; This function handles:
-; Call two basic APIs from FSP binary
-; Initializes stack with some early data (BIST, PEI entry, etc)
-;
-; Return: None
-;
-;----------------------------------------------------------------------------
-
-BITS 32
-align 4
-ProtectedModeEntryPoint:
- ;
- ; Early board hooks
- ;
- mov esp, BoardBeforeTempRamInitRet
- jmp ASM_PFX(BoardBeforeTempRamInit)
-
-BoardBeforeTempRamInitRet:
-
- ; Find the fsp info header
- mov edi, [ASM_PFX(PcdGet32 (PcdFsptBaseAddress))]
-
- mov eax, dword [edi + FVH_SIGINATURE_OFFSET]
- cmp eax, FVH_SIGINATURE_VALID_VALUE
- jnz FspHeaderNotFound
-
- xor eax, eax
- mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET]
- cmp ax, 0
- jnz FspFvExtHeaderExist
-
- xor eax, eax
- mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header
- add edi, eax
- jmp FspCheckFfsHeader
-
-FspFvExtHeaderExist:
- add edi, eax
- mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Header
- add edi, eax
-
- ; Round up to 8 byte alignment
- mov eax, edi
- and al, 07h
- jz FspCheckFfsHeader
-
- and edi, 0FFFFFFF8h
- add edi, 08h
-
-FspCheckFfsHeader:
- ; Check the ffs guid
- mov eax, dword [edi]
- cmp eax, FSP_HEADER_GUID_DWORD1
- jnz FspHeaderNotFound
-
- mov eax, dword [edi + 4]
- cmp eax, FSP_HEADER_GUID_DWORD2
- jnz FspHeaderNotFound
-
- mov eax, dword [edi + 8]
- cmp eax, FSP_HEADER_GUID_DWORD3
- jnz FspHeaderNotFound
-
- mov eax, dword [edi + 0Ch]
- cmp eax, FSP_HEADER_GUID_DWORD4
- jnz FspHeaderNotFound
-
- add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header
-
- ; Check the section type as raw section
- mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET]
- cmp al, 019h
- jnz FspHeaderNotFound
-
- add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header
- jmp FspHeaderFound
-
-FspHeaderNotFound:
- jmp $
-
-FspHeaderFound:
- ; Get the fsp TempRamInit Api address
- mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]
- add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
-
- ; Setup the hardcode stack
- mov esp, TempRamInitStack
-
- ; Call the fsp TempRamInit Api
- jmp eax
-
-TempRamInitDone:
- cmp eax, 8000000Eh ;Check if EFI_NOT_FOUND returned. Error code for Microcode Update not found.
- je CallSecFspInit ;If microcode not found, don't hang, but continue.
-
- cmp eax, 0 ;Check if EFI_SUCCESS retuned.
- jnz FspApiFailed
-
- ; ECX: start of range
- ; EDX: end of range
-CallSecFspInit:
- sub edx, [ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))] ; TemporaryRam for FSP
- xor eax, eax
- mov esp, edx
-
- ; Align the stack at DWORD
- add esp, 3
- and esp, 0FFFFFFFCh
-
- push edx
- push ecx
- push eax ; zero - no hob list yet
- call ASM_PFX(CallPeiCoreEntryPoint)
-
-FspApiFailed:
- jmp $
-
-align 10h
-TempRamInitStack:
- DD TempRamInitDone
- DD ASM_PFX(FsptUpdDataPtr); TempRamInitParams
-
-;
-; ROM-based Global-Descriptor Table for the Tiano PEI Phase
-;
-align 16
-global ASM_PFX(BootGdtTable)
-
-;
-; GDT[0]: 0x00: Null entry, never used.
-;
-NULL_SEL EQU $ - GDT_BASE ; Selector [0]
-GDT_BASE:
-ASM_PFX(BootGdtTable):
- DD 0
- DD 0
-;
-; Linear data segment descriptor
-;
-LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8]
- DW 0FFFFh ; limit 0xFFFFF
- DW 0 ; base 0
- DB 0
- DB 092h ; present, ring 0, data, expand-up, writable
- DB 0CFh ; page-granular, 32-bit
- DB 0
-;
-; Linear code segment descriptor
-;
-LINEAR_CODE_SEL EQU $ - GDT_BASE ; Selector [0x10]
- DW 0FFFFh ; limit 0xFFFFF
- DW 0 ; base 0
- DB 0
- DB 09Bh ; present, ring 0, data, expand-up, not-writable
- DB 0CFh ; page-granular, 32-bit
- DB 0
-;
-; System data segment descriptor
-;
-SYS_DATA_SEL EQU $ - GDT_BASE ; Selector [0x18]
- DW 0FFFFh ; limit 0xFFFFF
- DW 0 ; base 0
- DB 0
- DB 093h ; present, ring 0, data, expand-up, not-writable
- DB 0CFh ; page-granular, 32-bit
- DB 0
-
-;
-; System code segment descriptor
-;
-SYS_CODE_SEL EQU $ - GDT_BASE ; Selector [0x20]
- DW 0FFFFh ; limit 0xFFFFF
- DW 0 ; base 0
- DB 0
- DB 09Ah ; present, ring 0, data, expand-up, writable
- DB 0CFh ; page-granular, 32-bit
- DB 0
-;
-; Spare segment descriptor
-;
-SYS16_CODE_SEL EQU $ - GDT_BASE ; Selector [0x28]
- DW 0FFFFh ; limit 0xFFFFF
- DW 0 ; base 0
- DB 0Eh ; Changed from F000 to E000.
- DB 09Bh ; present, ring 0, code, expand-up, writable
- DB 00h ; byte-granular, 16-bit
- DB 0
-;
-; Spare segment descriptor
-;
-SYS16_DATA_SEL EQU $ - GDT_BASE ; Selector [0x30]
- DW 0FFFFh ; limit 0xFFFF
- DW 0 ; base 0
- DB 0
- DB 093h ; present, ring 0, data, expand-up, not-writable
- DB 00h ; byte-granular, 16-bit
- DB 0
-
-;
-; Spare segment descriptor
-;
-SPARE5_SEL EQU $ - GDT_BASE ; Selector [0x38]
- DW 0 ; limit 0
- DW 0 ; base 0
- DB 0
- DB 0 ; present, ring 0, data, expand-up, writable
- DB 0 ; page-granular, 32-bit
- DB 0
-GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes
-
-;
-; GDT Descriptor
-;
-GdtDesc: ; GDT descriptor
- DW GDT_SIZE - 1 ; GDT limit
- DD GDT_BASE ; GDT base address
-
-
-ProtectedModeEntryLinearAddress:
-ProtectedModeEntryLinear:
- DD ProtectedModeEntryPoint ; Offset of our 32 bit code
- DW LINEAR_CODE_SEL
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
deleted file mode 100644
index 47db32d64c..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
+++ /dev/null
@@ -1,72 +0,0 @@
-;------------------------------------------------------------------------------
-;
-; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
-; SPDX-License-Identifier: BSD-2-Clause-Patent
-; Abstract:
-;
-; Switch the stack from temporary memory to permanent memory.
-;
-;------------------------------------------------------------------------------
-
- SECTION .text
-
-;------------------------------------------------------------------------------
-; VOID
-; EFIAPI
-; SecSwitchStack (
-; UINT32 TemporaryMemoryBase,
-; UINT32 PermanentMemoryBase
-; );
-;------------------------------------------------------------------------------
-global ASM_PFX(SecSwitchStack)
-ASM_PFX(SecSwitchStack):
- ;
- ; Save three register: eax, ebx, ecx
- ;
- push eax
- push ebx
- push ecx
- push edx
-
- ;
- ; !!CAUTION!! this function address's is pushed into stack after
- ; migration of whole temporary memory, so need save it to permanent
- ; memory at first!
- ;
-
- mov ebx, [esp + 20] ; Save the first parameter
- mov ecx, [esp + 24] ; Save the second parameter
-
- ;
- ; Save this function's return address into permanent memory at first.
- ; Then, Fixup the esp point to permanent memory
- ;
- mov eax, esp
- sub eax, ebx
- add eax, ecx
- mov edx, dword [esp] ; copy pushed register's value to permanent memory
- mov dword [eax], edx
- mov edx, dword [esp + 4]
- mov dword [eax + 4], edx
- mov edx, dword [esp + 8]
- mov dword [eax + 8], edx
- mov edx, dword [esp + 12]
- mov dword [eax + 12], edx
- mov edx, dword [esp + 16] ; Update this function's return address into permanent memory
- mov dword [eax + 16], edx
- mov esp, eax ; From now, esp is pointed to permanent memory
-
- ;
- ; Fixup the ebp point to permanent memory
- ;
- mov eax, ebp
- sub eax, ebx
- add eax, ecx
- mov ebp, eax ; From now, ebp is pointed to permanent memory
-
- pop edx
- pop ecx
- pop ebx
- pop eax
- ret
-
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c
deleted file mode 100644
index ef89e3f310..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/** @file
- Provide platform init function.
-
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-
-#include <PiPei.h>
-#include <Library/DebugLib.h>
-#include <Library/SerialPortLib.h>
-#include <Library/SecBoardInitLib.h>
-#include <Library/TestPointCheckLib.h>
-
-/**
- Platform initialization.
-
- @param[in] FspHobList HobList produced by FSP.
- @param[in] StartOfRange Start of temporary RAM.
- @param[in] EndOfRange End of temporary RAM.
-**/
-VOID
-EFIAPI
-PlatformInit (
- IN VOID *FspHobList,
- IN VOID *StartOfRange,
- IN VOID *EndOfRange
- )
-{
- //
- // Platform initialization
- // Enable Serial port here
- //
- if (PcdGetBool(PcdSecSerialPortDebugEnable)) {
- SerialPortInitialize ();
- }
-
- DEBUG ((DEBUG_INFO, "PrintPeiCoreEntryPointParam in PlatformInit\n"));
- DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList));
- DEBUG ((DEBUG_INFO, "StartOfRange - 0x%x\n", StartOfRange));
- DEBUG ((DEBUG_INFO, "EndOfRange - 0x%x\n", EndOfRange));
-
- BoardAfterTempRamInit ();
-
- TestPointTempMemoryFunction (StartOfRange, EndOfRange);
-}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
deleted file mode 100644
index c99dd5ecdd..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+++ /dev/null
@@ -1,97 +0,0 @@
-## @file
-# Provide FSP wrapper platform sec related function.
-#
-# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-#
-##
-
-################################################################################
-#
-# Defines Section - statements that will be processed to create a Makefile.
-#
-################################################################################
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = SecFspWrapperPlatformSecLib
- FILE_GUID = 4E1C4F95-90EA-47de-9ACC-B8920189A1F5
- MODULE_TYPE = SEC
- VERSION_STRING = 1.0
- LIBRARY_CLASS = PlatformSecLib
-
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IA32 X64
-#
-
-################################################################################
-#
-# Sources Section - list of files that are required for the build to succeed.
-#
-################################################################################
-
-[Sources]
- FspWrapperPlatformSecLib.c
- SecRamInitData.c
- SecPlatformInformation.c
- SecGetPerformance.c
- SecTempRamDone.c
- PlatformInit.c
-
-[Sources.IA32]
- Ia32/SecEntry.nasm
- Ia32/PeiCoreEntry.nasm
- Ia32/Stack.nasm
- Ia32/Fsp.h
-
-################################################################################
-#
-# Package Dependency Section - list of Package files that are required for
-# this module.
-#
-################################################################################
-
-[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- UefiCpuPkg/UefiCpuPkg.dec
- IntelFsp2Pkg/IntelFsp2Pkg.dec
- IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
- MinPlatformPkg/MinPlatformPkg.dec
- KabylakeSiliconPkg/SiPkg.dec
-
-[LibraryClasses]
- LocalApicLib
- SerialPortLib
- FspWrapperPlatformLib
- FspWrapperApiLib
- BoardInitLib
- SecBoardInitLib
- TestPointCheckLib
- PeiServicesTablePointerLib
-
-[Ppis]
- gEfiSecPlatformInformationPpiGuid ## CONSUMES
- gPeiSecPerformancePpiGuid ## CONSUMES
- gTopOfTemporaryRamPpiGuid ## PRODUCES
- gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES
- gFspTempRamExitPpiGuid ## CONSUMES
-
-[Pcd]
- gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress ## CONSUMES
- gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES
- gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ## CONSUMES
-
-[FixedPcd]
- gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c
deleted file mode 100644
index c4eeb2b188..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/** @file
- Sample to provide SecGetPerformance function.
-
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <PiPei.h>
-
-#include <Ppi/SecPerformance.h>
-#include <Ppi/TopOfTemporaryRam.h>
-
-#include <Library/BaseMemoryLib.h>
-#include <Library/TimerLib.h>
-#include <Library/DebugLib.h>
-
-/**
- This interface conveys performance information out of the Security (SEC) phase into PEI.
-
- This service is published by the SEC phase. The SEC phase handoff has an optional
- EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the
- PEI Foundation. As such, if the platform supports collecting performance data in SEC,
- this information is encapsulated into the data structure abstracted by this service.
- This information is collected for the boot-strap processor (BSP) on IA-32.
-
- @param[in] PeiServices The pointer to the PEI Services Table.
- @param[in] This The pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.
- @param[out] Performance The pointer to performance data collected in SEC phase.
-
- @retval EFI_SUCCESS The data was successfully returned.
-
-**/
-EFI_STATUS
-EFIAPI
-SecGetPerformance (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN PEI_SEC_PERFORMANCE_PPI *This,
- OUT FIRMWARE_SEC_PERFORMANCE *Performance
- )
-{
- UINT32 Size;
- UINT32 Count;
- UINT32 TopOfTemporaryRam;
- UINT64 Ticker;
- VOID *TopOfTemporaryRamPpi;
- EFI_STATUS Status;
-
- DEBUG ((DEBUG_INFO, "SecGetPerformance\n"));
-
- Status = (*PeiServices)->LocatePpi (
- PeiServices,
- &gTopOfTemporaryRamPpiGuid,
- 0,
- NULL,
- (VOID **) &TopOfTemporaryRamPpi
- );
- if (EFI_ERROR (Status)) {
- return EFI_NOT_FOUND;
- }
- //
- // |--------------| <- TopOfTemporaryRam - BL
- // | List Ptr |
- // |--------------|
- // | BL RAM Start |
- // |--------------|
- // | BL RAM End |
- // |--------------|
- // |Number of BSPs|
- // |--------------|
- // | BIST |
- // |--------------|
- // | .... |
- // |--------------|
- // | TSC[63:32] |
- // |--------------|
- // | TSC[31:00] |
- // |--------------|
- //
- TopOfTemporaryRam = (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof(UINT32);
- TopOfTemporaryRam -= sizeof(UINT32) * 2;
- Count = *(UINT32 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32));
- Size = Count * sizeof (UINT32);
-
- Ticker = *(UINT64 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32) - Size - sizeof (UINT32) * 2);
- Performance->ResetEnd = GetTimeInNanoSecond (Ticker);
-
- return EFI_SUCCESS;
-}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c
deleted file mode 100644
index 5b94ed2bef..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/** @file
- Provide SecPlatformInformation function.
-
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <PiPei.h>
-
-#include <Ppi/SecPlatformInformation.h>
-#include <Ppi/TopOfTemporaryRam.h>
-
-#include <Library/BaseMemoryLib.h>
-#include <Library/DebugLib.h>
-
-/**
- This interface conveys state information out of the Security (SEC) phase into PEI.
-
- @param[in] PeiServices Pointer to the PEI Services Table.
- @param[in,out] StructureSize Pointer to the variable describing size of the input buffer.
- @param[out] PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
-
- @retval EFI_SUCCESS The data was successfully returned.
- @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
-
-**/
-EFI_STATUS
-EFIAPI
-SecPlatformInformation (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN OUT UINT64 *StructureSize,
- OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
- )
-{
- UINT32 *Bist;
- UINT32 Size;
- UINT32 Count;
- UINT32 TopOfTemporaryRam;
- VOID *TopOfTemporaryRamPpi;
- EFI_STATUS Status;
-
- DEBUG ((DEBUG_INFO, "SecPlatformInformation\n"));
-
- Status = (*PeiServices)->LocatePpi (
- PeiServices,
- &gTopOfTemporaryRamPpiGuid,
- 0,
- NULL,
- (VOID **) &TopOfTemporaryRamPpi
- );
- if (EFI_ERROR (Status)) {
- return EFI_NOT_FOUND;
- }
-
- //
- // The entries of BIST information, together with the number of them,
- // reside in the bottom of stack, left untouched by normal stack operation.
- // This routine copies the BIST information to the buffer pointed by
- // PlatformInformationRecord for output.
- //
- TopOfTemporaryRam = (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof (UINT32);
- TopOfTemporaryRam -= sizeof(UINT32) * 2;
- Count = *((UINT32 *)(UINTN) (TopOfTemporaryRam - sizeof (UINT32)));
- Size = Count * sizeof (IA32_HANDOFF_STATUS);
-
- if ((*StructureSize) < (UINT64) Size) {
- *StructureSize = Size;
- return EFI_BUFFER_TOO_SMALL;
- }
-
- *StructureSize = Size;
- Bist = (UINT32 *) (TopOfTemporaryRam - sizeof (UINT32) - Size);
-
- CopyMem (PlatformInformationRecord, Bist, Size);
-
- return EFI_SUCCESS;
-}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
deleted file mode 100644
index b356327b4c..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/** @file
- Provide TempRamInitParams data.
-
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <Library/PcdLib.h>
-#include <FspEas.h>
-#include "FsptCoreUpd.h"
-
-typedef struct {
- FSP_UPD_HEADER FspUpdHeader;
- FSPT_CORE_UPD FsptCoreUpd;
-} FSPT_UPD_CORE_DATA;
-
-GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA FsptUpdDataPtr = {
- {
- 0x4450555F54505346,
- 0x00,
- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
- }
- },
- {
- ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + FixedPcdGet32 (PcdFlashMicrocodeOffset)),
- ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet32 (PcdFlashMicrocodeOffset)),
- 0, // Set CodeRegionBase as 0, so that caching will be 4GB-(CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used.
- FixedPcdGet32 (PcdFlashCodeCacheSize),
- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
- }
- }
-};
-
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c
deleted file mode 100644
index 922e4ec204..0000000000
--- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/** @file
- Provide SecTemporaryRamDone function.
-
-Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <PiPei.h>
-
-#include <Ppi/TemporaryRamDone.h>
-#include <Ppi/TempRamExitPpi.h>
-
-#include <Library/BaseMemoryLib.h>
-#include <Library/DebugLib.h>
-#include <Library/PcdLib.h>
-#include <Library/DebugAgentLib.h>
-#include <Library/FspWrapperPlatformLib.h>
-#include <Library/FspWrapperApiLib.h>
-#include <Library/BoardInitLib.h>
-#include <Library/PeiServicesTablePointerLib.h>
-
-/**
-This interface disables temporary memory in SEC Phase.
-**/
-VOID
-EFIAPI
-SecPlatformDisableTemporaryMemory (
- VOID
- )
-{
- EFI_STATUS Status;
- VOID *TempRamExitParam;
- CONST EFI_PEI_SERVICES **PeiServices;
- FSP_TEMP_RAM_EXIT_PPI *TempRamExitPpi;
-
- DEBUG ((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n"));
-
- Status = BoardInitBeforeTempRamExit ();
- ASSERT_EFI_ERROR (Status);
-
- if (PcdGet8 (PcdFspModeSelection) == 1) {
- //
- // FSP API mode
- //
- TempRamExitParam = UpdateTempRamExitParam ();
- Status = CallTempRamExit (TempRamExitParam);
- DEBUG ((DEBUG_INFO, "TempRamExit status: 0x%x\n", Status));
- ASSERT_EFI_ERROR (Status);
- } else {
- //
- // FSP Dispatch mode
- //
- PeiServices = GetPeiServicesTablePointer ();
- Status = (*PeiServices)->LocatePpi (
- PeiServices,
- &gFspTempRamExitPpiGuid,
- 0,
- NULL,
- (VOID **) &TempRamExitPpi
- );
- ASSERT_EFI_ERROR (Status);
- if (EFI_ERROR (Status)) {
- return;
- }
- TempRamExitPpi->TempRamExit (NULL);
- }
-
- Status = BoardInitAfterTempRamExit ();
- ASSERT_EFI_ERROR (Status);
-
- return ;
-}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
index 2bc2b4126b..acdc31e708 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
@@ -126,7 +126,7 @@
#######################################
GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.inf
I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAccessLib.inf
- PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+ PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
# Thunderbolt
!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
index 77e4a6a610..4b07c0a684 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
@@ -166,7 +166,7 @@
EcLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseEcLib/BaseEcLib.inf
GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.inf
I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAccessLib.inf
- PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+ PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
# Thunderbolt
!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
--
2.23.0.windows.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [edk2-platforms] [PATCH V1 13/13] MinPlatformPkg: Remove BoardInitLib dependency from PlatformSecLib
2019-11-14 6:06 [edk2-platforms] [PATCH V1 00/13] SecFspWrapperPlatformSecLib Cleanup Nate DeSimone
` (11 preceding siblings ...)
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 12/13] KabylakeOpenBoardPkg: Remove SecFspWrapperPlatformSecLib override Nate DeSimone
@ 2019-11-14 6:06 ` Nate DeSimone
2019-11-14 15:18 ` Chiu, Chasel
2019-11-16 2:56 ` Kubacki, Michael A
12 siblings, 2 replies; 44+ messages in thread
From: Nate DeSimone @ 2019-11-14 6:06 UTC (permalink / raw)
To: devel; +Cc: Michael Kubacki, Chasel Chiu, Liming Gao
SecFspWrapperPlatformSecLib contains the implementation of
SecPlatformDisableTemporaryMemory(), which SecMain in UefiCpuPkg will
call as part of its implementation of EFI_PEI_TEMPORARY_RAM_DONE_PPI.
For platforms that use FSP, the implementation of
SecPlatformDisableTemporaryMemory() can be made generic since the chipset
specifics will be contained in FspTempRamExit().
The Minimum Platform Specification provides the BoardPkg two
interface hook points, BoardInitBeforeTempRamExit() and
BoardInitAfterTempRamExit() which must be called during
SecPlatformDisableTemporaryMemory(). Due to EFI_PEI_TEMPORARY_RAM_DONE_PPI
being a special case of a PPI that is implemented in SEC, these two
functions are the only ones in BoardInitLib that need to be called
by SEC.
Linking BoardInitLib with SEC places many restrictions on the
implementation of that library. The features available to SEC phase
code are very minimal. Since this code runs during PEI phase, these
restrictions are not actually required.
Instead of directly linking with BoardInitLib,
SecPlatformDisableTemporaryMemory() shall call BoardInitLib indirectly
through a PPI (PLATFORM_INIT_TEMP_RAM_EXIT_PPI.) This PPI is produced
by PlatformInitPreMem, which implements the other BoardInitLib calls
already, so this change should also slightly reduce the size of the
final binary image since less PE/COFF images will need to link with
BoardInitLib.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
.../SecFspWrapperPlatformSecLib.inf | 1 +
.../SecTempRamDone.c | 36 +++++++--
.../Include/Ppi/PlatformInitTempRamExitPpi.h | 55 ++++++++++++++
.../Intel/MinPlatformPkg/MinPlatformPkg.dec | 2 +
.../PlatformInitPei/PlatformInitPreMem.c | 76 ++++++++++++++++++-
.../PlatformInitPei/PlatformInitPreMem.inf | 1 +
6 files changed, 159 insertions(+), 12 deletions(-)
create mode 100644 Platform/Intel/MinPlatformPkg/Include/Ppi/PlatformInitTempRamExitPpi.h
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
index 02c720c73d..3465f50126 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
@@ -80,6 +80,7 @@
gTopOfTemporaryRamPpiGuid ## PRODUCES
gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES
gFspTempRamExitPpiGuid ## CONSUMES
+ gPlatformInitTempRamExitPpiGuid ## CONSUMES
[Pcd]
gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize ## CONSUMES
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c
index 922e4ec204..b22cf57d6c 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c
@@ -10,6 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Ppi/TemporaryRamDone.h>
#include <Ppi/TempRamExitPpi.h>
+#include <Ppi/PlatformInitTempRamExitPpi.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
@@ -17,7 +18,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/DebugAgentLib.h>
#include <Library/FspWrapperPlatformLib.h>
#include <Library/FspWrapperApiLib.h>
-#include <Library/BoardInitLib.h>
#include <Library/PeiServicesTablePointerLib.h>
/**
@@ -29,14 +29,35 @@ SecPlatformDisableTemporaryMemory (
VOID
)
{
- EFI_STATUS Status;
- VOID *TempRamExitParam;
- CONST EFI_PEI_SERVICES **PeiServices;
- FSP_TEMP_RAM_EXIT_PPI *TempRamExitPpi;
+ EFI_STATUS Status;
+ VOID *TempRamExitParam;
+ CONST EFI_PEI_SERVICES **PeiServices;
+ FSP_TEMP_RAM_EXIT_PPI *TempRamExitPpi;
+ PLATFORM_INIT_TEMP_RAM_EXIT_PPI *PlatformInitTempRamExitPpi;
DEBUG ((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n"));
+ PeiServices = GetPeiServicesTablePointer ();
+ ASSERT (PeiServices != NULL);
+ if (PeiServices == NULL) {
+ return;
+ }
+ ASSERT ((*PeiServices) != NULL);
+ if ((*PeiServices) == NULL) {
+ return;
+ }
+ Status = (*PeiServices)->LocatePpi (
+ PeiServices,
+ &gPlatformInitTempRamExitPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &PlatformInitTempRamExitPpi
+ );
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
- Status = BoardInitBeforeTempRamExit ();
+ Status = PlatformInitTempRamExitPpi->PlatformInitBeforeTempRamExit ();
ASSERT_EFI_ERROR (Status);
if (PcdGet8 (PcdFspModeSelection) == 1) {
@@ -51,7 +72,6 @@ SecPlatformDisableTemporaryMemory (
//
// FSP Dispatch mode
//
- PeiServices = GetPeiServicesTablePointer ();
Status = (*PeiServices)->LocatePpi (
PeiServices,
&gFspTempRamExitPpiGuid,
@@ -66,7 +86,7 @@ SecPlatformDisableTemporaryMemory (
TempRamExitPpi->TempRamExit (NULL);
}
- Status = BoardInitAfterTempRamExit ();
+ Status = PlatformInitTempRamExitPpi->PlatformInitAfterTempRamExit ();
ASSERT_EFI_ERROR (Status);
return ;
diff --git a/Platform/Intel/MinPlatformPkg/Include/Ppi/PlatformInitTempRamExitPpi.h b/Platform/Intel/MinPlatformPkg/Include/Ppi/PlatformInitTempRamExitPpi.h
new file mode 100644
index 0000000000..590647738c
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Include/Ppi/PlatformInitTempRamExitPpi.h
@@ -0,0 +1,55 @@
+/** @file
+ This file defines the PPI for notifying PlatformInitPreMem
+ of temporary memory being disabled.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PLATFORM_INIT_TEMP_RAM_EXIT_PPI_H_
+#define _PLATFORM_INIT_TEMP_RAM_EXIT_PPI_H_
+
+#include <PiPei.h>
+
+//
+// Forward declaration for the PLATFORM_INIT_TEMP_RAM_EXIT_PPI.
+//
+typedef struct _PLATFORM_INIT_TEMP_RAM_EXIT_PPI PLATFORM_INIT_TEMP_RAM_EXIT_PPI;
+
+/**
+ A hook for platform-specific initialization prior to disabling temporary RAM.
+
+ @retval EFI_SUCCESS The platform initialization was successful.
+ @retval EFI_NOT_READY The platform has not been detected yet.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PLATFORM_INIT_BEFORE_TEMP_RAM_EXIT) (
+ VOID
+ );
+
+/**
+ A hook for platform-specific initialization after disabling temporary RAM.
+
+ @retval EFI_SUCCESS The platform initialization was successful.
+ @retval EFI_NOT_READY The platform has not been detected yet.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PLATFORM_INIT_AFTER_TEMP_RAM_EXIT) (
+ VOID
+ );
+
+///
+/// This PPI provides functions for notifying PlatformInitPreMem
+/// of temporary memory being disabled.
+///
+struct _PLATFORM_INIT_TEMP_RAM_EXIT_PPI {
+ PLATFORM_INIT_BEFORE_TEMP_RAM_EXIT PlatformInitBeforeTempRamExit;
+ PLATFORM_INIT_AFTER_TEMP_RAM_EXIT PlatformInitAfterTempRamExit;
+};
+
+extern EFI_GUID gPlatformInitTempRamExitPpiGuid;
+
+#endif // _PLATFORM_INIT_TEMP_RAM_EXIT_PPI_H_
diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
index c6b5881646..5dfa4d420e 100644
--- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
+++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
@@ -28,6 +28,8 @@
gPeiBaseMemoryTestPpiGuid = {0xb6ec423c, 0x21d2, 0x490d, {0x85, 0xc6, 0xdd, 0x58, 0x64, 0xea, 0xa6, 0x74}}
gPeiPlatformMemorySizePpiGuid = {0x9a7ef41e, 0xc140, 0x4bd1, {0xb8, 0x84, 0x1e, 0x11, 0x24, 0x0b, 0x4c, 0xe6}}
+ gPlatformInitTempRamExitPpiGuid = {0xbae23646, 0xbd60, 0x4f8b, {0xb3, 0xf9, 0xf3, 0x91, 0xee, 0x7e, 0xe6, 0xc8}}
+
[Guids]
gMinPlatformPkgTokenSpaceGuid = {0x69d13bf0, 0xaf91, 0x4d96, {0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}}
diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c
index c579ff008e..efdeb6a91c 100644
--- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c
+++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c
@@ -29,6 +29,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Guid/MemoryTypeInformation.h>
#include <Ppi/PlatformMemorySize.h>
#include <Ppi/BaseMemoryTest.h>
+#include <Ppi/PlatformInitTempRamExitPpi.h>
EFI_STATUS
EFIAPI
@@ -72,7 +73,31 @@ BaseMemoryTest (
OUT EFI_PHYSICAL_ADDRESS *ErrorAddress
);
-static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList = {
+/**
+ A hook for platform-specific initialization prior to disabling temporary RAM.
+
+ @retval EFI_SUCCESS The platform initialization was successful.
+ @retval EFI_NOT_READY The platform has not been detected yet.
+**/
+EFI_STATUS
+EFIAPI
+PlatformInitBeforeTempRamExit (
+ VOID
+ );
+
+/**
+ A hook for platform-specific initialization after disabling temporary RAM.
+
+ @retval EFI_SUCCESS The platform initialization was successful.
+ @retval EFI_NOT_READY The platform has not been detected yet.
+**/
+EFI_STATUS
+EFIAPI
+PlatformInitAfterTempRamExit (
+ VOID
+ );
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList = {
(EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEfiPeiMemoryDiscoveredPpiGuid,
(EFI_PEIM_NOTIFY_ENTRY_POINT) MemoryDiscoveredPpiNotifyCallback
@@ -90,11 +115,11 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mPpiBootMode = {
NULL
};
-static PEI_BASE_MEMORY_TEST_PPI mPeiBaseMemoryTestPpi = { BaseMemoryTest };
+GLOBAL_REMOVE_IF_UNREFERENCED PEI_BASE_MEMORY_TEST_PPI mPeiBaseMemoryTestPpi = { BaseMemoryTest };
-static PEI_PLATFORM_MEMORY_SIZE_PPI mMemoryMemorySizePpi = { GetPlatformMemorySize };
+GLOBAL_REMOVE_IF_UNREFERENCED PEI_PLATFORM_MEMORY_SIZE_PPI mMemoryMemorySizePpi = { GetPlatformMemorySize };
-static EFI_PEI_PPI_DESCRIPTOR mMemPpiList[] = {
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mMemPpiList[] = {
{
EFI_PEI_PPI_DESCRIPTOR_PPI,
&gPeiBaseMemoryTestPpiGuid,
@@ -107,6 +132,17 @@ static EFI_PEI_PPI_DESCRIPTOR mMemPpiList[] = {
},
};
+GLOBAL_REMOVE_IF_UNREFERENCED PLATFORM_INIT_TEMP_RAM_EXIT_PPI mPlatformInitTempRamExitPpi = {
+ PlatformInitBeforeTempRamExit,
+ PlatformInitAfterTempRamExit
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mPlatformInitTempRamExitPpiDesc = {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gPlatformInitTempRamExitPpiGuid,
+ &mPlatformInitTempRamExitPpi
+};
+
///
/// Memory Reserved should be between 125% to 150% of the Current required memory
/// otherwise BdsMisc.c would do a reset to make it 125% to avoid s4 resume issues.
@@ -391,6 +427,35 @@ MemoryDiscoveredPpiNotifyCallback (
return Status;
}
+/**
+ A hook for platform-specific initialization prior to disabling temporary RAM.
+
+ @retval EFI_SUCCESS The platform initialization was successful.
+ @retval EFI_NOT_READY The platform has not been detected yet.
+**/
+EFI_STATUS
+EFIAPI
+PlatformInitBeforeTempRamExit (
+ VOID
+ )
+{
+ return BoardInitBeforeTempRamExit ();
+}
+
+/**
+ A hook for platform-specific initialization after disabling temporary RAM.
+
+ @retval EFI_SUCCESS The platform initialization was successful.
+ @retval EFI_NOT_READY The platform has not been detected yet.
+**/
+EFI_STATUS
+EFIAPI
+PlatformInitAfterTempRamExit (
+ VOID
+ )
+{
+ return BoardInitAfterTempRamExit ();
+}
/**
This function handles PlatformInit task after PeiReadOnlyVariable2 PPI produced
@@ -446,6 +511,9 @@ PlatformInitPreMem (
Status = BoardInitBeforeMemoryInit ();
ASSERT_EFI_ERROR (Status);
+ Status = PeiServicesInstallPpi (&mPlatformInitTempRamExitPpiDesc);
+ ASSERT_EFI_ERROR (Status);
+
return Status;
}
diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
index af5dbe8772..7ee18eb6d5 100644
--- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
+++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
@@ -53,6 +53,7 @@
gEfiPeiMemoryDiscoveredPpiGuid
gEfiPeiMasterBootModePpiGuid ## PRODUCES
gEfiPeiBootInRecoveryModePpiGuid ## PRODUCES
+ gPlatformInitTempRamExitPpiGuid ## PRODUCES
gEfiPeiReadOnlyVariable2PpiGuid
gPeiBaseMemoryTestPpiGuid
gPeiPlatformMemorySizePpiGuid
--
2.23.0.windows.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 01/13] KabylakeSiliconPkg: Change MODULE_TYPE of SiliconInitLib to PEIM
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 01/13] KabylakeSiliconPkg: Change MODULE_TYPE of SiliconInitLib to PEIM Nate DeSimone
@ 2019-11-14 15:15 ` Chiu, Chasel
2019-11-15 8:59 ` Chaganty, Rangasai V
2019-11-16 2:53 ` Kubacki, Michael A
2 siblings, 0 replies; 44+ messages in thread
From: Chiu, Chasel @ 2019-11-14 15:15 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io
Cc: Kubacki, Michael A, Chaganty, Rangasai V
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Thursday, November 14, 2019 2:07 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>; Chaganty, Rangasai V
> <rangasai.v.chaganty@intel.com>
> Subject: [edk2-platforms] [PATCH V1 01/13] KabylakeSiliconPkg: Change
> MODULE_TYPE of SiliconInitLib to PEIM
>
> This library contains PEI phase only code. For example,
> ClearIchSmiAndWake() calls PeiServicesGetBootMode().
> Accordingly, this library should have never been marked as a BASE library.
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../PeiSiliconInitLib.inf} | 3 ++-
> .../{SiliconInitLib => PeiSiliconInitLib}/SiliconInit.c | 0
> .../{SiliconInitLib => PeiSiliconInitLib}/SiliconInitPreMem.c | 0
> 3 files changed, 2 insertions(+), 1 deletion(-) rename
> Silicon/Intel/KabylakeSiliconPkg/Library/{SiliconInitLib/SiliconInitLib.inf =>
> PeiSiliconInitLib/PeiSiliconInitLib.inf} (91%) rename
> Silicon/Intel/KabylakeSiliconPkg/Library/{SiliconInitLib =>
> PeiSiliconInitLib}/SiliconInit.c (100%) rename
> Silicon/Intel/KabylakeSiliconPkg/Library/{SiliconInitLib =>
> PeiSiliconInitLib}/SiliconInitPreMem.c (100%)
>
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf
> b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.i
> nf
> similarity index 91%
> rename from
> Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf
> rename to
> Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
> index 132080e876..ff83bf2835 100644
> --- a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSili
> +++ conInitLib.inf
> @@ -11,8 +11,9 @@
> BASE_NAME = SiliconInitLib FILE_GUID
> = 72CD3A7B-FEA5-4F5E-9165-4DD12187BB13 VERSION_STRING
> = 1.0- MODULE_TYPE = BASE+ MODULE_TYPE
> = PEIM LIBRARY_CLASS = SiliconInitLib+ # # The
> following information is for reference only and not required by the build
> tools. #diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInit.c
> b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c
> similarity index 100%
> rename from
> Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInit.c
> rename to
> Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitPreMem.c
> b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMe
> m.c
> similarity index 100%
> rename from
> Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitPreMem.c
> rename to
> Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMem.c
> --
> 2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 02/13] KabylakeOpenBoardPkg: Update location of SiliconInitLib
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 02/13] KabylakeOpenBoardPkg: Update location of SiliconInitLib Nate DeSimone
@ 2019-11-14 15:15 ` Chiu, Chasel
2019-11-16 2:53 ` Kubacki, Michael A
1 sibling, 0 replies; 44+ messages in thread
From: Chiu, Chasel @ 2019-11-14 15:15 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io
Cc: Kubacki, Michael A, Jeremy Soller
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Thursday, November 14, 2019 2:07 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>; Jeremy Soller <jeremy@system76.com>
> Subject: [edk2-platforms] [PATCH V1 02/13] KabylakeOpenBoardPkg: Update
> location of SiliconInitLib
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Jeremy Soller <jeremy@system76.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc | 2
> +-
> .../Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 2
> +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> index e43c944201..2bc2b4126b 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> @@ -105,7 +105,7 @@
> # Silicon Initialization Package
>
> #######################################
>
>
> ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLi
> b.inf
>
> -
> SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/SiliconInitLib/SiliconInitLib.i
> nf
>
> +
> SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSiliconIn
> itLib.inf
>
>
> SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLib
> Fsp/PeiSiliconPolicyInitLibFsp.inf
>
>
>
> #####################################
>
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> index 1ce473432a..77e4a6a610 100644
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> +++
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> @@ -133,7 +133,7 @@
> # Silicon Initialization Package
>
> #######################################
>
>
> ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLi
> b.inf
>
> -
> SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/SiliconInitLib/SiliconInitLib.i
> nf
>
> +
> SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSiliconIn
> itLib.inf
>
>
>
> !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
>
> #
>
> --
> 2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 03/13] KabylakeSiliconPkg: Cleanup old comments
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 03/13] KabylakeSiliconPkg: Cleanup old comments Nate DeSimone
@ 2019-11-14 15:16 ` Chiu, Chasel
2019-11-16 2:53 ` Kubacki, Michael A
2019-11-18 9:15 ` Chaganty, Rangasai V
2 siblings, 0 replies; 44+ messages in thread
From: Chiu, Chasel @ 2019-11-14 15:16 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io
Cc: Kubacki, Michael A, Chaganty, Rangasai V
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Thursday, November 14, 2019 2:07 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>; Chaganty, Rangasai V
> <rangasai.v.chaganty@intel.com>
> Subject: [edk2-platforms] [PATCH V1 03/13] KabylakeSiliconPkg: Cleanup old
> comments
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../Library/PeiSiliconInitLib/SiliconInitPreMem.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMe
> m.c
> b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMe
> m.c
> index 65a67a6795..384877fba3 100644
> ---
> a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMe
> m.c
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/Silicon
> +++ InitPreMem.c
> @@ -31,9 +31,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include
> <Library/PeiServicesTablePointerLib.h> #include <Library/PchSerialIoLib.h>
> -//@todo it should be moved to Si Pkg. /**- Early Platform PCH
> initialization+ Early PCH initialization **/ VOID EarlySiliconInit (@@ -233,4
> +232,3 @@ SiliconInit (
> } }---
> 2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 04/13] CoffeeLakeSiliconPkg: Move TcoWdtHob.h
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 04/13] CoffeeLakeSiliconPkg: Move TcoWdtHob.h Nate DeSimone
@ 2019-11-14 15:16 ` Chiu, Chasel
2019-11-16 2:53 ` Kubacki, Michael A
2019-11-18 9:41 ` Chaganty, Rangasai V
2 siblings, 0 replies; 44+ messages in thread
From: Chiu, Chasel @ 2019-11-14 15:16 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io
Cc: Kubacki, Michael A, Chaganty, Rangasai V
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Thursday, November 14, 2019 2:07 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>; Chaganty, Rangasai V
> <rangasai.v.chaganty@intel.com>
> Subject: [edk2-platforms] [PATCH V1 04/13] CoffeeLakeSiliconPkg: Move
> TcoWdtHob.h
>
> Moves TcoWdtHob.h from WhiskeylakeOpenBoardPkg to
> CoffeelakeSiliconPkg.
> Oddly, gTcoWdtHobGuid was defined in CoffeelakeSiliconPkg/SiPkg.dec while
> the HOB definition itself was in WhiskeylakeOpenBoardPkg, this change
> cleans up the disparity.
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../Intel/CoffeelakeSiliconPkg}/Include/Guid/TcoWdtHob.h | 0
> 1 file changed, 0 insertions(+), 0 deletions(-) rename
> {Platform/Intel/WhiskeylakeOpenBoardPkg =>
> Silicon/Intel/CoffeelakeSiliconPkg}/Include/Guid/TcoWdtHob.h (100%)
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Guid/TcoWdtHob.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Guid/TcoWdtHob.h
> similarity index 100%
> rename from
> Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Guid/TcoWdtHob.h
> rename to Silicon/Intel/CoffeelakeSiliconPkg/Include/Guid/TcoWdtHob.h
> --
> 2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 05/13] CoffeelakeSiliconPkg: Add SiliconInitLib
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 05/13] CoffeelakeSiliconPkg: Add SiliconInitLib Nate DeSimone
@ 2019-11-14 15:16 ` Chiu, Chasel
2019-11-16 2:53 ` Kubacki, Michael A
2019-11-18 19:14 ` Chaganty, Rangasai V
2 siblings, 0 replies; 44+ messages in thread
From: Chiu, Chasel @ 2019-11-14 15:16 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io
Cc: Kubacki, Michael A, Chaganty, Rangasai V
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Thursday, November 14, 2019 2:07 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>; Chaganty, Rangasai V
> <rangasai.v.chaganty@intel.com>
> Subject: [edk2-platforms] [PATCH V1 05/13] CoffeelakeSiliconPkg: Add
> SiliconInitLib
>
> SiliconInitLib contains Silicon Init APIs that can be reused by BoardInitLib. It
> is expected that several implementations of BoardInitLib exist for a given
> SOC, these APIs allow the various BoardInitLib implementations to reuse
> common silicon initialization code. This matches the implementation already
> found in KabylakeSiliconPkg. This change also adds halting the TCO watch
> dog timer to PEI, which was previously done in SEC.
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../Include/Library/SiliconInitLib.h | 28 +++++
> .../PeiSiliconInitLib/PeiSiliconInitLib.inf | 46 ++++++++
> .../Library/PeiSiliconInitLib/SiliconInit.c | 19 +++
> .../PeiSiliconInitLib/SiliconInitPreMem.c | 109 ++++++++++++++++++
> 4 files changed, 202 insertions(+)
> create mode 100644
> Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.h
> create mode 100644
> Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.in
> f
> create mode 100644
> Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c
> create mode 100644
> Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMem
> .c
>
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.h
> new file mode 100644
> index 0000000000..a3411126a7
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.
> +++ h
> @@ -0,0 +1,28 @@
> +/** @file++Copyright (c) 2019, Intel Corporation. All rights
> +reserved.<BR>+SPDX-License-Identifier:
> +BSD-2-Clause-Patent++**/++#ifndef _SILICON_INIT_LIB_H_+#define
> +_SILICON_INIT_LIB_H_++#include <PiPei.h>++VOID+EarlySiliconInit (+
> +VOID+ );++VOID+SiliconInit (+ VOID+ );++VOID+LateSiliconInit (+
> +VOID+ );++#endif
> \ No newline at end of file
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib
> .inf
> b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib
> .inf
> new file mode 100644
> index 0000000000..47da5f608b
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSi
> +++ liconInitLib.inf
> @@ -0,0 +1,46 @@
> +### @file+#+# Copyright (c) 2019, Intel Corporation. All rights
> reserved.<BR>+#+# SPDX-License-Identifier:
> BSD-2-Clause-Patent+#+###++[Defines]+ INF_VERSION
> = 0x00010017+ BASE_NAME = SiliconInitLib+
> FILE_GUID =
> 82F2ACF0-2EBE-48C8-AC58-9D0F8BC1E16E+ VERSION_STRING
> = 1.0+ MODULE_TYPE = PEIM+ LIBRARY_CLASS
> = SiliconInitLib+#+# The following information is for reference only and not
> required by the build tools.+#+# VALID_ARCHITECTURES = IA32 X64 IPF
> EBC+#++[LibraryClasses]+ BaseLib+ BaseMemoryLib+ DebugLib+
> HobLib+ IoLib+ PcdLib+ PeiServicesLib+ PchCycleDecodingLib+
> PmcLib++[Packages]+ MdePkg/MdePkg.dec+
> CoffeelakeSiliconPkg/SiPkg.dec++[Sources]+ SiliconInit.c+
> SiliconInitPreMem.c++[Guids]+ gTcoWdtHobGuid
> ## CONSUMES++[Pcd]+ gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress
> ## CONSUMES+ gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ##
> CONSUMESdiff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c
> b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c
> new file mode 100644
> index 0000000000..122c02a3e5
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/Silic
> +++ onInit.c
> @@ -0,0 +1,19 @@
> +/** @file+ Silicon Init APIs for MinPlatform BoardInitLib
> +implementations.++Copyright (c) 2019, Intel Corporation. All rights
> +reserved.<BR>+SPDX-License-Identifier:
> +BSD-2-Clause-Patent++**/++#include <PiPei.h>++/**+ Late PCH
> +Init+**/+VOID+LateSiliconInit (+ VOID+ )+{+}diff --git
> +a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconI
> +nitPreMem.c
> +b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconI
> +nitPreMem.c
> new file mode 100644
> index 0000000000..23e4a3d4a0
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/Silic
> +++ onInitPreMem.c
> @@ -0,0 +1,109 @@
> +/** @file+ Silicon Init APIs for MinPlatform BoardInitLib
> implementations.++Copyright (c) 2019, Intel Corporation. All rights
> reserved.<BR>+SPDX-License-Identifier: BSD-2-Clause-Patent++**/++#include
> <PiPei.h>+#include <Guid/TcoWdtHob.h>+#include
> <Library/IoLib.h>+#include <Library/DebugLib.h>+#include
> <Library/HobLib.h>+#include <Library/PcdLib.h>+#include
> <Library/PeiServicesLib.h>+#include
> <Library/PchCycleDecodingLib.h>+#include <Library/PmcLib.h>+#include
> <Register/PchRegsLpc.h>+#include <Register/PchRegsPmc.h>++/**+ Early
> PCH initialization+**/+VOID+EarlySiliconInit (+ VOID+ )+{+ UINT16
> Data16;+ UINT8 Data8;+ UINT8 TcoRebootHappened;+
> TCO_WDT_HOB *TcoWdtHobPtr;+ EFI_STATUS Status;++ ///+ ///
> LPC I/O Configuration+ ///+ PchLpcIoDecodeRangesSet (+
> (V_LPC_CFG_IOD_LPT_378 << N_LPC_CFG_IOD_LPT) |+
> (V_LPC_CFG_IOD_COMB_3E8 << N_LPC_CFG_IOD_COMB) |+
> (V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA)+ );++
> PchLpcIoEnableDecodingSet (+ B_LPC_CFG_IOE_ME2 |+
> B_LPC_CFG_IOE_SE |+ B_LPC_CFG_IOE_ME1 |+
> B_LPC_CFG_IOE_KE |+ B_LPC_CFG_IOE_HGE |+
> B_LPC_CFG_IOE_LGE |+ B_LPC_CFG_IOE_FDE |+
> B_LPC_CFG_IOE_PPE |+ B_LPC_CFG_IOE_CBE |+
> B_LPC_CFG_IOE_CAE+ );++ ///+ /// Halt the TCO timer+ ///+
> Data16 = IoRead16 (PcdGet16 (PcdTcoBaseAddress) +
> R_TCO_IO_TCO1_CNT);+ Data16 |= B_TCO_IO_TCO1_CNT_TMR_HLT;+
> IoWrite16 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT,
> Data16);++ ///+ /// Read the Second TO status bit+ ///+ Data8 =
> IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS);+ if
> ((Data8 & B_TCO_IO_TCO2_STS_SECOND_TO) ==
> B_TCO_IO_TCO2_STS_SECOND_TO) {+ TcoRebootHappened = 1;+
> DEBUG ((DEBUG_INFO, "PlatformInitPreMem - TCO Second TO status bit is
> set. This might be a TCO reboot\n"));+ }+ else {+ TcoRebootHappened
> = 0;+ }++ ///+ /// Create HOB+ ///+ Status = PeiServicesCreateHob
> (EFI_HOB_TYPE_GUID_EXTENSION, sizeof(TCO_WDT_HOB), (VOID
> **)&TcoWdtHobPtr);+ if (!EFI_ERROR (Status)) {+
> TcoWdtHobPtr->Header.Name = gTcoWdtHobGuid;+
> TcoWdtHobPtr->TcoRebootHappened = TcoRebootHappened;+ }++ ///+
> /// Clear the Second TO status bit+ ///+ IoWrite8 (PcdGet16
> (PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS,
> B_TCO_IO_TCO2_STS_SECOND_TO);+}++/**+ Initialize the GPIO IO selection,
> GPIO USE selection, and GPIO signal inversion
> registers++**/+VOID+SiliconInit (+ VOID+ )+{+ UINT16 ABase;++
> ABase = PmcGetAcpiBase ();++ ///+ /// Clear all pending SMI. On S3 clear
> power button enable so it will not generate an SMI.+ ///+ IoWrite16
> (ABase + R_ACPI_IO_PM1_EN, 0);+ IoWrite32 (ABase +
> R_ACPI_IO_GPE0_EN_127_96, 0);+}--
> 2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 06/13] WhiskeylakeOpenBoardPkg: Add SiliconInitLib APIs to BoardInitLib
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 06/13] WhiskeylakeOpenBoardPkg: Add SiliconInitLib APIs to BoardInitLib Nate DeSimone
@ 2019-11-14 15:16 ` Chiu, Chasel
2019-11-16 2:53 ` Kubacki, Michael A
1 sibling, 0 replies; 44+ messages in thread
From: Chiu, Chasel @ 2019-11-14 15:16 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io; +Cc: Kubacki, Michael A
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Thursday, November 14, 2019 2:07 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>
> Subject: [edk2-platforms] [PATCH V1 06/13] WhiskeylakeOpenBoardPkg: Add
> SiliconInitLib APIs to BoardInitLib
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../BoardInitLib/PeiBoardInitPostMemLib.inf | 1 +
> .../BoardInitLib/PeiBoardInitPreMemLib.inf | 1 +
> .../PeiMultiBoardInitPostMemLib.inf | 1 +
> .../PeiMultiBoardInitPreMemLib.inf | 2 +-
> .../PeiWhiskeylakeURvpInitPostMemLib.c | 6 +-
> .../PeiWhiskeylakeURvpInitPreMemLib.c | 89 ++-----------------
> .../BoardInitLib/WhiskeylakeURvpInit.h | 1 +
> .../WhiskeylakeURvp/OpenBoardPkg.dsc | 5 ++
> 8 files changed, 24 insertions(+), 82 deletions(-)
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiBoardInitPostMemLib.inf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiBoardInitPostMemLib.inf
> index 9bf4d127c5..affc5c56ad 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiBoardInitPostMemLib.inf
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiBoardInitPostMemLib.inf
> @@ -26,6 +26,7 @@
> HdaVerbTableLib
>
> MemoryAllocationLib
>
> PcdLib
>
> + SiliconInitLib
>
>
>
> [Packages]
>
> MinPlatformPkg/MinPlatformPkg.dec
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiBoardInitPreMemLib.inf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiBoardInitPreMemLib.inf
> index 4ab80f9eb3..40e20285e0 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiBoardInitPreMemLib.inf
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiBoardInitPreMemLib.inf
> @@ -23,6 +23,7 @@
> BaseMemoryLib
>
> MemoryAllocationLib
>
> PcdLib
>
> + SiliconInitLib
>
>
>
> [Packages]
>
> MinPlatformPkg/MinPlatformPkg.dec
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiMultiBoardInitPostMemLib.inf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiMultiBoardInitPostMemLib.inf
> index c043e32638..21dc2f70c0 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiMultiBoardInitPostMemLib.inf
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiMultiBoardInitPostMemLib.inf
> @@ -30,6 +30,7 @@
> PeiPlatformHookLib
>
> PeiPolicyInitLib
>
> PchInfoLib
>
> + SiliconInitLib
>
>
>
> [Packages]
>
> MinPlatformPkg/MinPlatformPkg.dec
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiMultiBoardInitPreMemLib.inf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiMultiBoardInitPreMemLib.inf
> index cd0315377a..7389f1dfcd 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiMultiBoardInitPreMemLib.inf
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiMultiBoardInitPreMemLib.inf
> @@ -31,6 +31,7 @@
> PeiPlatformHookLib
>
> PeiPolicyInitLib
>
> PlatformHookLib
>
> + SiliconInitLib
>
> StallPpiLib
>
>
>
> [Packages]
>
> @@ -57,7 +58,6 @@
>
>
> [Guids]
>
> gPchGeneralPreMemConfigGuid ## CONSUMES
>
> - gTcoWdtHobGuid ## CONSUMES
>
>
>
> [Pcd]
>
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
> index 9413620a4a..248a6657d5 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
> @@ -430,6 +430,10 @@ WhiskeylakeURvpBoardInitBeforeSiliconInit (
> //
>
> Status = UpdateChipsetInitPtr();
>
>
>
> + ///
>
> + /// Do Late PCH init
>
> + ///
>
> + LateSiliconInit ();
>
> +
>
> return EFI_SUCCESS;
>
> }
>
> -
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
> index 0124888244..055d731651 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
> @@ -45,7 +45,6 @@
> #include <Library/PciSegmentLib.h>
>
> #include <PeiPlatformHookLib.h>
>
> #include <FirwmareConfigurations.h>
>
> -#include <Guid/TcoWdtHob.h>
>
> #include <Library/OcWdtLib.h>
>
>
>
> ///
>
> @@ -232,50 +231,8 @@ BoardMiscInitPreMem(
> return EFI_SUCCESS;
>
> }
>
>
>
> -//@todo it should be moved to Si Pkg.
>
> -/**
>
> -Early Platform PCH initialization
>
> -**/
>
> -VOID
>
> -EarlyPlatformPchInit(
>
> - VOID
>
> -)
>
> -{
>
> - UINT8 Data8;
>
> - UINT8 TcoRebootHappened;
>
> - TCO_WDT_HOB *TcoWdtHobPtr;
>
> - EFI_STATUS Status;
>
> -
>
> - ///
>
> - /// Read the Second TO status bit
>
> - ///
>
> - Data8 = IoRead8(PcdGet16(PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS);
>
> - if ((Data8 & B_TCO_IO_TCO2_STS_SECOND_TO) ==
> B_TCO_IO_TCO2_STS_SECOND_TO) {
>
> - TcoRebootHappened = 1;
>
> - DEBUG((DEBUG_INFO, "PlatformInitPreMem - TCO Second TO status bit
> is set. This might be a TCO reboot\n"));
>
> - }
>
> - else {
>
> - TcoRebootHappened = 0;
>
> - }
>
> -
>
> - ///
>
> - /// Create HOB
>
> - ///
>
> - Status = PeiServicesCreateHob(EFI_HOB_TYPE_GUID_EXTENSION,
> sizeof(TCO_WDT_HOB), (VOID **)&TcoWdtHobPtr);
>
> - if (!EFI_ERROR(Status)) {
>
> - TcoWdtHobPtr->Header.Name = gTcoWdtHobGuid;
>
> - TcoWdtHobPtr->TcoRebootHappened = TcoRebootHappened;
>
> - }
>
> -
>
> - ///
>
> - /// Clear the Second TO status bit
>
> - ///
>
> - IoWrite8(PcdGet16(PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS,
> B_TCO_IO_TCO2_STS_SECOND_TO);
>
> -}
>
> -
>
> /**
>
> Board configuration initialization in the pre-memory boot phase.
>
> -
>
> **/
>
> VOID
>
> BoardConfigInitPreMem (
>
> @@ -341,7 +298,6 @@ PlatformInitPreMemCallBack(
> )
>
> {
>
> EFI_STATUS Status;
>
> - UINT16 ABase;
>
> UINT8 FwConfig;
>
>
>
> //
>
> @@ -378,16 +334,8 @@ PlatformInitPreMemCallBack(
> ///
>
> /// Configure GPIO and SIO
>
> ///
>
> - Status = BoardInitPreMem();
>
> - ASSERT_EFI_ERROR(Status);
>
> -
>
> - ABase = PmcGetAcpiBase();
>
> -
>
> - ///
>
> - /// Clear all pending SMI. On S3 clear power button enable so it will not
> generate an SMI.
>
> - ///
>
> - IoWrite16(ABase + R_ACPI_IO_PM1_EN, 0);
>
> - IoWrite32(ABase + R_ACPI_IO_GPE0_EN_127_96, 0);
>
> + Status = BoardInitPreMem ();
>
> + ASSERT_EFI_ERROR (Status);
>
>
>
> ///
>
> /// Install Pre Memory PPIs
>
> @@ -550,12 +498,6 @@ WhiskeylakeURvpInitPreMem (
> Status = InstallStallPpi();
>
> ASSERT_EFI_ERROR(Status);
>
>
>
> - ///@todo it should be moved to Si Pkg.
>
> - ///
>
> - /// Do Early PCH init
>
> - ///
>
> - EarlyPlatformPchInit();
>
> -
>
> //
>
> // Install PCH RESET PPI and EFI RESET2 PeiService
>
> //
>
> @@ -588,6 +530,11 @@ WhiskeylakeURvpBoardInitBeforeMemoryInit (
> VOID
>
> )
>
> {
>
> + ///
>
> + /// Do basic PCH init
>
> + ///
>
> + SiliconInit ();
>
> +
>
> WhiskeylakeURvpInitPreMem ();
>
>
>
> return EFI_SUCCESS;
>
> @@ -600,27 +547,9 @@ WhiskeylakeURvpBoardDebugInit (
> )
>
> {
>
> ///
>
> - /// LPC I/O Configuration
>
> + /// Do Early PCH init
>
> ///
>
> - PchLpcIoDecodeRangesSet (
>
> - (V_LPC_CFG_IOD_LPT_378 << N_LPC_CFG_IOD_LPT) |
>
> - (V_LPC_CFG_IOD_COMB_3E8 << N_LPC_CFG_IOD_COMB) |
>
> - (V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA)
>
> - );
>
> -
>
> - PchLpcIoEnableDecodingSet (
>
> - B_LPC_CFG_IOE_ME2 |
>
> - B_LPC_CFG_IOE_SE |
>
> - B_LPC_CFG_IOE_ME1 |
>
> - B_LPC_CFG_IOE_KE |
>
> - B_LPC_CFG_IOE_HGE |
>
> - B_LPC_CFG_IOE_LGE |
>
> - B_LPC_CFG_IOE_FDE |
>
> - B_LPC_CFG_IOE_PPE |
>
> - B_LPC_CFG_IOE_CBE |
>
> - B_LPC_CFG_IOE_CAE
>
> - );
>
> -
>
> + EarlySiliconInit ();
>
> return EFI_SUCCESS;
>
> }
>
>
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/WhiskeylakeURvpInit.h
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/WhiskeylakeURvpInit.h
> index 325bcb41df..d3a709b2a9 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/WhiskeylakeURvpInit.h
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/WhiskeylakeURvpInit.h
> @@ -15,6 +15,7 @@
> #include <Library/MemoryAllocationLib.h>
>
> #include <Library/DebugLib.h>
>
> #include <Library/GpioLib.h>
>
> +#include <Library/SiliconInitLib.h>
>
> #include <Ppi/SiPolicy.h>
>
> #include <PchHsioPtssTables.h>
>
>
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardP
> kg.dsc
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardP
> kg.dsc
> index cdaf47b6f7..3cd0478021 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardP
> kg.dsc
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardP
> kg.dsc
> @@ -154,6 +154,11 @@
>
> TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTim
> erLib.inf
>
>
>
> [LibraryClasses.common.PEIM]
>
> + #######################################
>
> + # Silicon Initialization Package
>
> + #######################################
>
> +
> SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSiliconIn
> itLib.inf
>
> +
>
> #######################################
>
> # Platform Package
>
> #######################################
>
> --
> 2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 07/13] WhiskeylakeOpenBoardPkg: Whitespace cleanup in BoardInitLib
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 07/13] WhiskeylakeOpenBoardPkg: Whitespace cleanup in BoardInitLib Nate DeSimone
@ 2019-11-14 15:17 ` Chiu, Chasel
2019-11-16 2:53 ` Kubacki, Michael A
1 sibling, 0 replies; 44+ messages in thread
From: Chiu, Chasel @ 2019-11-14 15:17 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io; +Cc: Kubacki, Michael A
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Thursday, November 14, 2019 2:07 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>
> Subject: [edk2-platforms] [PATCH V1 07/13] WhiskeylakeOpenBoardPkg:
> Whitespace cleanup in BoardInitLib
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../PeiWhiskeylakeURvpInitPostMemLib.c | 185 ++++++-------
> .../PeiWhiskeylakeURvpInitPreMemLib.c | 257 +++++++++---------
> 2 files changed, 216 insertions(+), 226 deletions(-)
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
> index 248a6657d5..827af6bb57 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
> @@ -33,16 +33,16 @@
> #include "WhiskeylakeURvpInit.h"
>
>
>
> EFI_STATUS
>
> -BoardFunctionInit(
>
> +BoardFunctionInit (
>
> IN UINT16 BoardId
>
> -);
>
> + );
>
>
>
> /**
>
> -GPIO init function for PEI post memory phase.
>
> + GPIO init function for PEI post memory phase.
>
>
>
> -@param[in] BoardId An unsigned integrer represent the board id.
>
> + @param[in] BoardId An unsigned integrer represent the board
> id.
>
>
>
> -@retval EFI_SUCCESS The function completed successfully.
>
> + @retval EFI_SUCCESS The function completed successfully.
>
> **/
>
> EFI_STATUS
>
> BoardGpioInit(
>
> @@ -72,48 +72,48 @@ BoardGpioInit(
> }
>
>
>
> /**
>
> -Touch panel GPIO init function for PEI post memory phase.
>
> + Touch panel GPIO init function for PEI post memory phase.
>
>
>
> -@param[in] BoardId An unsigned integrer represent the board id.
>
> + @param[in] BoardId An unsigned integrer represent the board
> id.
>
>
>
> -@retval EFI_SUCCESS The function completed successfully.
>
> + @retval EFI_SUCCESS The function completed successfully.
>
> **/
>
> EFI_STATUS
>
> -TouchPanelGpioInit(
>
> +TouchPanelGpioInit (
>
> IN UINT16 BoardId
>
> -)
>
> + )
>
> {
>
> switch (BoardId) {
>
> default:
>
> - PcdSet32S(PcdBoardGpioTableTouchPanel, 0);
>
> + PcdSet32S (PcdBoardGpioTableTouchPanel, 0);
>
> break;
>
> }
>
> return EFI_SUCCESS;
>
> }
>
>
>
> /**
>
> -Misc. init function for PEI post memory phase.
>
> + Misc. init function for PEI post memory phase.
>
>
>
> -@param[in] BoardId An unsigned integrer represent the board id.
>
> + @param[in] BoardId An unsigned integrer represent the board
> id.
>
>
>
> -@retval EFI_SUCCESS The function completed successfully.
>
> + @retval EFI_SUCCESS The function completed successfully.
>
> **/
>
> EFI_STATUS
>
> -BoardMiscInit(
>
> +BoardMiscInit (
>
> IN UINT16 BoardId
>
> -)
>
> + )
>
> {
>
> - PcdSetBoolS(PcdDebugUsbUartEnable, FALSE);
>
> + PcdSetBoolS (PcdDebugUsbUartEnable, FALSE);
>
>
>
> switch (BoardId) {
>
>
>
> case BoardIdWhiskeyLakeRvp:
>
>
>
> - PcdSetBoolS(PcdMipiCamGpioEnable, TRUE);
>
> + PcdSetBoolS (PcdMipiCamGpioEnable, TRUE);
>
> break;
>
>
>
> default:
>
> - PcdSetBoolS(PcdMipiCamGpioEnable, FALSE);
>
> + PcdSetBoolS (PcdMipiCamGpioEnable, FALSE);
>
> break;
>
> }
>
>
>
> @@ -121,25 +121,22 @@ BoardMiscInit(
> }
>
>
>
> /**
>
> -Security GPIO init function for PEI post memory phase.
>
> + Security GPIO init function for PEI post memory phase.
>
>
>
> -@param[in] BoardId An unsigned integrer represent the board id.
>
> + @param[in] BoardId An unsigned integrer represent the board
> id.
>
>
>
> -@retval EFI_SUCCESS The function completed successfully.
>
> + @retval EFI_SUCCESS The function completed successfully.
>
> **/
>
> EFI_STATUS
>
> BoardSecurityInit (
>
> IN UINT16 BoardId
>
> -)
>
> + )
>
> {
>
> switch (BoardId) {
>
> -
>
> case BoardIdWhiskeyLakeRvp:
>
> -
>
> // TPM interrupt connects to GPIO_CNL_H_GPP_A_7
>
> PcdSet32S (PcdTpm2CurrentIrqNum, 0x1F);
>
> break;
>
> -
>
> }
>
>
>
> return EFI_SUCCESS;
>
> @@ -147,7 +144,6 @@ BoardSecurityInit (
>
>
> /**
>
> Board configuration initialization in the post-memory boot phase.
>
> -
>
> **/
>
> VOID
>
> BoardConfigInit (
>
> @@ -178,27 +174,26 @@ BoardConfigInit (
> ASSERT_EFI_ERROR (Status);
>
> }
>
>
>
> -//@todo Review this functionality and if it is required for WHL SDS
>
> /**
>
> -Create the HOB for hotkey status for 'Attempt USB First' feature
>
> + Create the HOB for hotkey status for 'Attempt USB First' feature
>
>
>
> -@retval EFI_SUCCESS HOB Creating successful.
>
> -@retval Others HOB Creating failed.
>
> + @retval EFI_SUCCESS HOB Creating successful.
>
> + @retval Others HOB Creating failed.
>
> **/
>
> EFI_STATUS
>
> -CreateAttemptUsbFirstHotkeyInfoHob(
>
> +CreateAttemptUsbFirstHotkeyInfoHob (
>
> VOID
>
> -)
>
> + )
>
> {
>
> EFI_STATUS Status;
>
> ATTEMPT_USB_FIRST_HOTKEY_INFO AttemptUsbFirstHotkeyInfo;
>
>
>
> Status = EFI_SUCCESS;
>
>
>
> - ZeroMem(
>
> + ZeroMem (
>
> &AttemptUsbFirstHotkeyInfo,
>
> - sizeof(AttemptUsbFirstHotkeyInfo)
>
> - );
>
> + sizeof (AttemptUsbFirstHotkeyInfo)
>
> + );
>
>
>
> AttemptUsbFirstHotkeyInfo.RevisonId = 0;
>
> AttemptUsbFirstHotkeyInfo.HotkeyTriggered = FALSE;
>
> @@ -206,29 +201,29 @@ CreateAttemptUsbFirstHotkeyInfoHob(
> ///
>
> /// Build HOB for Attempt USB First feature
>
> ///
>
> - BuildGuidDataHob(
>
> + BuildGuidDataHob (
>
> &gAttemptUsbFirstHotkeyInfoHobGuid,
>
> &(AttemptUsbFirstHotkeyInfo),
>
> - sizeof(ATTEMPT_USB_FIRST_HOTKEY_INFO)
>
> - );
>
> + sizeof (ATTEMPT_USB_FIRST_HOTKEY_INFO)
>
> + );
>
>
>
> return Status;
>
> }
>
>
>
> /**
>
> -Search and identify the physical address of a
>
> -file module inside the FW_BINARIES_FV_SIGNED FV
>
> + Search and identify the physical address of a
>
> + file module inside the FW_BINARIES_FV_SIGNED FV
>
>
>
> -@retval EFI_SUCCESS If address has been found
>
> -@retval Others If address has not been found
>
> + @retval EFI_SUCCESS If address has been found
>
> + @retval Others If address has not been found
>
> **/
>
> EFI_STATUS
>
> -FindModuleInFlash2(
>
> +FindModuleInFlash2 (
>
> IN EFI_FIRMWARE_VOLUME_HEADER *FvHeader,
>
> IN EFI_GUID *GuidPtr,
>
> IN OUT UINT32 *ModulePtr,
>
> IN OUT UINT32 *ModuleSize
>
> -)
>
> + )
>
> {
>
> EFI_FFS_FILE_HEADER *FfsHeader;
>
> EFI_FV_FILE_INFO FileInfo;
>
> @@ -246,57 +241,57 @@ FindModuleInFlash2(
> //
>
> // Locate FV_IMAGE file type in the FW_BINARIES_FV_SIGNED firmware
> volume
>
> //
>
> - Status =
> PeiServicesFfsFindNextFile(EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE,
> FvHeader, &FileHandle);
>
> - if (EFI_ERROR(Status)) {
>
> + Status = PeiServicesFfsFindNextFile
> (EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE, FvHeader, &FileHandle);
>
> + if (EFI_ERROR (Status)) {
>
> // unable to find FV_IMAGE file in this FV
>
> break;
>
> }
>
>
>
> FfsHeader = (EFI_FFS_FILE_HEADER*)FileHandle;
>
> - DEBUG((DEBUG_INFO, "FfsHeader 0x%X:\n", FfsHeader));
>
> - DEBUG((DEBUG_INFO, " Name = 0x%g\n", &FfsHeader->Name));
>
> - DEBUG((DEBUG_INFO, " Type = 0x%X\n", FfsHeader->Type));
>
> - if (IS_FFS_FILE2(FfsHeader)) {
>
> - DEBUG((DEBUG_INFO, " Size = 0x%X\n", FFS_FILE2_SIZE(FfsHeader)));
>
> + DEBUG ((DEBUG_INFO, "FfsHeader 0x%X:\n", FfsHeader));
>
> + DEBUG ((DEBUG_INFO, " Name = 0x%g\n", &FfsHeader->Name));
>
> + DEBUG ((DEBUG_INFO, " Type = 0x%X\n", FfsHeader->Type));
>
> + if (IS_FFS_FILE2 (FfsHeader)) {
>
> + DEBUG ((DEBUG_INFO, " Size = 0x%X\n",
> FFS_FILE2_SIZE(FfsHeader)));
>
> }
>
> else {
>
> - DEBUG((DEBUG_INFO, " Size = 0x%X\n", FFS_FILE_SIZE(FfsHeader)));
>
> + DEBUG ((DEBUG_INFO, " Size = 0x%X\n", FFS_FILE_SIZE(FfsHeader)));
>
> }
>
>
>
> //
>
> // Locate FW_BINARIES_FV FV_IMAGE Section
>
> //
>
> - Status =
> PeiServicesFfsFindSectionData(EFI_SECTION_FIRMWARE_VOLUME_IMAGE,
> FileHandle, &FileBuffer);
>
> - if (EFI_ERROR(Status)) {
>
> + Status = PeiServicesFfsFindSectionData
> (EFI_SECTION_FIRMWARE_VOLUME_IMAGE, FileHandle, &FileBuffer);
>
> + if (EFI_ERROR (Status)) {
>
> // continue to search for the next FV_IMAGE file
>
> - DEBUG((DEBUG_INFO, "FW_BINARIES_FV section not found. Status =
> %r\n", Status));
>
> + DEBUG ((DEBUG_INFO, "FW_BINARIES_FV section not found. Status
> = %r\n", Status));
>
> continue;
>
> }
>
>
>
> SectionHeader = (EFI_COMMON_SECTION_HEADER *)FileBuffer;
>
> - DEBUG((DEBUG_INFO, "GUIDED SectionHeader 0x%X:\n",
>
> + DEBUG ((DEBUG_INFO, "GUIDED SectionHeader 0x%X:\n",
>
> (UINT32)(UINT8 *)SectionHeader));
>
> if (IS_SECTION2(SectionHeader)) {
>
> - DEBUG((DEBUG_INFO, " Guid = 0x%g\n",
>
> + DEBUG ((DEBUG_INFO, " Guid = 0x%g\n",
>
> &((EFI_GUID_DEFINED_SECTION2
> *)SectionHeader)->SectionDefinitionGuid));
>
> - DEBUG((DEBUG_INFO, " DataOfset = 0x%X\n",
>
> + DEBUG ((DEBUG_INFO, " DataOfset = 0x%X\n",
>
> ((EFI_GUID_DEFINED_SECTION2 *)SectionHeader)->DataOffset));
>
> }
>
> else {
>
> - DEBUG((DEBUG_INFO, " Guid = 0x%g\n",
>
> + DEBUG ((DEBUG_INFO, " Guid = 0x%g\n",
>
> &((EFI_GUID_DEFINED_SECTION
> *)SectionHeader)->SectionDefinitionGuid));
>
> - DEBUG((DEBUG_INFO, " DataOfset = 0x%X\n",
>
> + DEBUG ((DEBUG_INFO, " DataOfset = 0x%X\n",
>
> ((EFI_GUID_DEFINED_SECTION *)SectionHeader)->DataOffset));
>
> }
>
> - DEBUG((DEBUG_INFO, " Type = 0x%X\n", SectionHeader->Type));
>
> + DEBUG ((DEBUG_INFO, " Type = 0x%X\n",
> SectionHeader->Type));
>
>
>
> //
>
> // Locate Firmware File System file within Firmware Volume
>
> //
>
> - Status = PeiServicesFfsFindFileByName(GuidPtr, FileBuffer, (VOID
> **)&FfsHeader);
>
> - if (EFI_ERROR(Status)) {
>
> + Status = PeiServicesFfsFindFileByName (GuidPtr, FileBuffer, (VOID
> **)&FfsHeader);
>
> + if (EFI_ERROR (Status)) {
>
> // continue to search for the next FV_IMAGE file
>
> - DEBUG((DEBUG_INFO, "Module not found. Status = %r\n", Status));
>
> + DEBUG ((DEBUG_INFO, "Module not found. Status = %r\n", Status));
>
> continue;
>
> }
>
>
>
> @@ -305,10 +300,10 @@ FindModuleInFlash2(
> //
>
> // Get File Information
>
> //
>
> - Status = PeiServicesFfsGetFileInfo(FfsHeader, &FileInfo);
>
> - if (!EFI_ERROR(Status)) {
>
> + Status = PeiServicesFfsGetFileInfo (FfsHeader, &FileInfo);
>
> + if (!EFI_ERROR (Status)) {
>
> *ModuleSize = (UINT32)FileInfo.BufferSize;
>
> - DEBUG((DEBUG_INFO, "Module {0x%g} found at = 0x%X, Size =
> 0x%X\n",
>
> + DEBUG ((DEBUG_INFO, "Module {0x%g} found at = 0x%X, Size =
> 0x%X\n",
>
> &FfsHeader->Name, *ModulePtr, *ModuleSize));
>
> return Status;
>
> }
>
> @@ -318,15 +313,15 @@ FindModuleInFlash2(
> }
>
>
>
> /**
>
> -Get the ChipsetInit Binary pointer.
>
> + Get the ChipsetInit Binary pointer.
>
>
>
> -@retval EFI_SUCCESS - ChipsetInit Binary found.
>
> -@retval EFI_NOT_FOUND - ChipsetInit Binary not found.
>
> + @retval EFI_SUCCESS - ChipsetInit Binary found.
>
> + @retval EFI_NOT_FOUND - ChipsetInit Binary not found.
>
> **/
>
> EFI_STATUS
>
> -UpdateChipsetInitPtr(
>
> +UpdateChipsetInitPtr (
>
> VOID
>
> -)
>
> + )
>
> {
>
> EFI_STATUS Status;
>
> PCH_STEPPING PchStep;
>
> @@ -339,18 +334,18 @@ UpdateChipsetInitPtr(
>
>
> ModuleAddr = 0;
>
> ModuleSize = 0;
>
> - PchStep = PchStepping();
>
> + PchStep = PchStepping ();
>
>
>
> - Status = PeiServicesLocatePpi(
>
> + Status = PeiServicesLocatePpi (
>
> &gSiPolicyPpiGuid,
>
> 0,
>
> NULL,
>
> (VOID **)&SiPolicyPpi
>
> - );
>
> - ASSERT_EFI_ERROR(Status);
>
> + );
>
> + ASSERT_EFI_ERROR (Status);
>
>
>
> - Status = GetConfigBlock((VOID *)SiPolicyPpi, &gHsioConfigGuid, (VOID
> *)&HsioConfig);
>
> - ASSERT_EFI_ERROR(Status);
>
> + Status = GetConfigBlock ((VOID *)SiPolicyPpi, &gHsioConfigGuid, (VOID
> *)&HsioConfig);
>
> + ASSERT_EFI_ERROR (Status);
>
>
>
> ChipsetInitBinaryGuidPtr = NULL;
>
> if (IsPchLp()) {
>
> @@ -358,22 +353,20 @@ UpdateChipsetInitPtr(
> case PCH_D0:
>
> case PCH_D1:
>
> ChipsetInitBinaryGuidPtr = &gCnlPchLpChipsetInitTableDxGuid;
>
> - DEBUG((DEBUG_INFO, "Using CnlPchLpChipsetInitTable_Dx table
> \n"));
>
> + DEBUG ((DEBUG_INFO, "Using CnlPchLpChipsetInitTable_Dx table
> \n"));
>
> break;
>
> default:
>
> return EFI_NOT_FOUND;
>
> }
>
> - }
>
> - else {
>
> + } else {
>
> return EFI_NOT_FOUND;
>
> }
>
>
>
> //
>
> // Locate Firmware Volume header
>
> //
>
> - // FvHeader = (EFI_FIRMWARE_VOLUME_HEADER
> *)(UINTN)GetFvBinaryBase();
>
> - FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *)
> FixedPcdGet32(PcdFlashFvPostMemoryBase);
>
> - Status = FindModuleInFlash2(FvHeader, ChipsetInitBinaryGuidPtr,
> &ModuleAddr, &ModuleSize);
>
> + FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *) FixedPcdGet32
> (PcdFlashFvPostMemoryBase);
>
> + Status = FindModuleInFlash2 (FvHeader, ChipsetInitBinaryGuidPtr,
> &ModuleAddr, &ModuleSize);
>
> //
>
> // Get ChipsetInit Binary Pointer
>
> //
>
> @@ -384,8 +377,8 @@ UpdateChipsetInitPtr(
> //
>
> HsioConfig->ChipsetInitBinLen = ModuleSize;
>
>
>
> - DEBUG((DEBUG_INFO, "ChipsetInit Binary Location: %x\n",
> HsioConfig->ChipsetInitBinPtr));
>
> - DEBUG((DEBUG_INFO, "ChipsetInit Binary Size: %x\n",
> HsioConfig->ChipsetInitBinLen));
>
> + DEBUG ((DEBUG_INFO, "ChipsetInit Binary Location: %x\n",
> HsioConfig->ChipsetInitBinPtr));
>
> + DEBUG ((DEBUG_INFO, "ChipsetInit Binary Size: %x\n",
> HsioConfig->ChipsetInitBinLen));
>
>
>
> return Status;
>
> }
>
> @@ -401,34 +394,34 @@ WhiskeylakeURvpBoardInitBeforeSiliconInit (
> VOID
>
> )
>
> {
>
> - EFI_STATUS Status;
>
> - UINT8 FwConfig;
>
> + EFI_STATUS Status;
>
> + UINT8 FwConfig;
>
>
>
> - BoardConfigInit();
>
> + BoardConfigInit ();
>
> //
>
> // Configure GPIO and SIO
>
> //
>
> - Status = BoardInit();
>
> - ASSERT_EFI_ERROR(Status);
>
> + Status = BoardInit ();
>
> + ASSERT_EFI_ERROR (Status);
>
>
>
> FwConfig = FwConfigProduction;
>
> - PeiPolicyInit(FwConfig);
>
> + PeiPolicyInit (FwConfig);
>
>
>
> //
>
> // Create USB Boot First hotkey information HOB
>
> //
>
> - CreateAttemptUsbFirstHotkeyInfoHob();
>
> + CreateAttemptUsbFirstHotkeyInfoHob ();
>
>
>
> //
>
> // Initializing Platform Specific Programming
>
> //
>
> - Status = PlatformSpecificInit();
>
> + Status = PlatformSpecificInit ();
>
> ASSERT_EFI_ERROR(Status);
>
>
>
> //
>
> // Update ChipsetInitPtr
>
> //
>
> - Status = UpdateChipsetInitPtr();
>
> + Status = UpdateChipsetInitPtr ();
>
>
>
> ///
>
> /// Do Late PCH init
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
> index 055d731651..75813ff351 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boar
> dInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
> @@ -68,84 +68,84 @@ GLOBAL_REMOVE_IF_UNREFERENCED const UINT16
> RcompResistorSklRvp1[SA_MRC_MAX_RCOMP
> GLOBAL_REMOVE_IF_UNREFERENCED const UINT16
> RcompTargetSklRvp1[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 40, 23,
> 40 };
>
>
>
> GLOBAL_REMOVE_IF_UNREFERENCED MEMORY_MAP MmioMap[] = {
>
> - { FixedPcdGet64(PcdApicLocalAddress),
> FixedPcdGet32(PcdApicLocalMmioSize) },
>
> - { FixedPcdGet64(PcdMchBaseAddress),
> FixedPcdGet32(PcdMchMmioSize) },
>
> - { FixedPcdGet64(PcdDmiBaseAddress), FixedPcdGet32(PcdDmiMmioSize) },
>
> - { FixedPcdGet64(PcdEpBaseAddress), FixedPcdGet32(PcdEpMmioSize) },
>
> - { FixedPcdGet64(PcdGdxcBaseAddress),
> FixedPcdGet32(PcdGdxcMmioSize) }
>
> + { FixedPcdGet64 (PcdApicLocalAddress), FixedPcdGet32
> (PcdApicLocalMmioSize) },
>
> + { FixedPcdGet64 (PcdMchBaseAddress), FixedPcdGet32
> (PcdMchMmioSize) },
>
> + { FixedPcdGet64 (PcdDmiBaseAddress), FixedPcdGet32
> (PcdDmiMmioSize) },
>
> + { FixedPcdGet64 (PcdEpBaseAddress), FixedPcdGet32
> (PcdEpMmioSize) },
>
> + { FixedPcdGet64 (PcdGdxcBaseAddress), FixedPcdGet32
> (PcdGdxcMmioSize) }
>
> };
>
>
>
> EFI_STATUS
>
> -MrcConfigInit(
>
> +MrcConfigInit (
>
> IN UINT16 BoardId
>
> -);
>
> + );
>
>
>
> EFI_STATUS
>
> -SaGpioConfigInit(
>
> +SaGpioConfigInit (
>
> IN UINT16 BoardId
>
> -);
>
> + );
>
>
>
> EFI_STATUS
>
> - SaMiscConfigInit(
>
> -IN UINT16 BoardId
>
> -);
>
> +SaMiscConfigInit (
>
> + IN UINT16 BoardId
>
> + );
>
>
>
> EFI_STATUS
>
> - RootPortClkInfoInit(
>
> -IN UINT16 BoardId
>
> -);
>
> +RootPortClkInfoInit (
>
> + IN UINT16 BoardId
>
> + );
>
>
>
> EFI_STATUS
>
> - UsbConfigInit(
>
> -IN UINT16 BoardId
>
> -);
>
> +UsbConfigInit (
>
> + IN UINT16 BoardId
>
> + );
>
>
>
> EFI_STATUS
>
> -GpioGroupTierInit(
>
> +GpioGroupTierInit (
>
> IN UINT16 BoardId
>
> -);
>
> + );
>
>
>
> EFI_STATUS
>
> -GpioTablePreMemInit(
>
> +GpioTablePreMemInit (
>
> IN UINT16 BoardId
>
> -);
>
> + );
>
>
>
> EFI_STATUS
>
> -PchPmConfigInit(
>
> +PchPmConfigInit (
>
> IN UINT16 BoardId
>
> -);
>
> + );
>
>
>
> EFI_STATUS
>
> -SaDisplayConfigInit(
>
> +SaDisplayConfigInit (
>
> IN UINT16 BoardId
>
> -);
>
> + );
>
>
>
> EFI_STATUS
>
> -BoardFunctionInitPreMem(
>
> +BoardFunctionInitPreMem (
>
> IN UINT16 BoardId
>
> -);
>
> + );
>
>
>
> EFI_STATUS
>
> EFIAPI
>
> -PlatformInitPreMemCallBack(
>
> +PlatformInitPreMemCallBack (
>
> IN CONST EFI_PEI_SERVICES **PeiServices,
>
> IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
>
> IN VOID *Ppi
>
> -);
>
> + );
>
>
>
> EFI_STATUS
>
> EFIAPI
>
> -MemoryDiscoveredPpiNotify(
>
> +MemoryDiscoveredPpiNotify (
>
> IN CONST EFI_PEI_SERVICES **PeiServices,
>
> IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
>
> IN VOID *Ppi
>
> -);
>
> + );
>
>
>
> EFI_STATUS
>
> EFIAPI
>
> -PchReset(
>
> +PchReset (
>
> IN CONST EFI_PEI_SERVICES **PeiServices
>
> -);
>
> + );
>
>
>
> static EFI_PEI_RESET_PPI mResetPpi = {
>
> PchReset
>
> @@ -172,16 +172,16 @@ static EFI_PEI_NOTIFY_DESCRIPTOR
> mMemDiscoveredNotifyList = {
> };
>
>
>
> /**
>
> -Board misc init function for PEI pre-memory phase.
>
> + Board misc init function for PEI pre-memory phase.
>
>
>
> -@param[in] BoardId An unsigned integer represent the board id.
>
> + @param[in] BoardId An unsigned integer represent the board
> id.
>
>
>
> -@retval EFI_SUCCESS The function completed successfully.
>
> + @retval EFI_SUCCESS The function completed successfully.
>
> **/
>
> EFI_STATUS
>
> -BoardMiscInitPreMem(
>
> +BoardMiscInitPreMem (
>
> IN UINT16 BoardId
>
> -)
>
> + )
>
> {
>
> PCD64_BLOB PcdData;
>
>
>
> @@ -211,22 +211,22 @@ BoardMiscInitPreMem(
> // power. An alternative way to contol modem power is to toggle
> FCP_OFF via GPP_D13
>
> // but board rework is required.
>
> //
>
> - PcdSet32S(PcdWwanFullCardPowerOffGpio, GPIO_CNL_LP_GPP_D16);
>
> - PcdSet32S(PcdWwanBbrstGpio, GPIO_CNL_LP_GPP_F1);
>
> - PcdSet32S(PcdWwanPerstGpio, GPIO_CNL_LP_GPP_E15);
>
> - PcdSet8S(PcdWwanPerstGpioPolarity, 1);
>
> + PcdSet32S (PcdWwanFullCardPowerOffGpio,
> GPIO_CNL_LP_GPP_D16);
>
> + PcdSet32S (PcdWwanBbrstGpio, GPIO_CNL_LP_GPP_F1);
>
> + PcdSet32S (PcdWwanPerstGpio, GPIO_CNL_LP_GPP_E15);
>
> + PcdSet8S (PcdWwanPerstGpioPolarity, 1);
>
> break;
>
>
>
> default:
>
> break;
>
> }
>
>
>
> - PcdSet64S(PcdRecoveryModeGpio, PcdData.Blob);
>
> + PcdSet64S (PcdRecoveryModeGpio, PcdData.Blob);
>
>
>
> //
>
> // Pc8374SioKbc Present
>
> //
>
> - PcdSetBoolS(PcdPc8374SioKbcPresent, FALSE);
>
> + PcdSetBoolS (PcdPc8374SioKbcPresent, FALSE);
>
>
>
> return EFI_SUCCESS;
>
> }
>
> @@ -279,23 +279,23 @@ BoardConfigInitPreMem (
> }
>
>
>
> /**
>
> -This function handles PlatformInit task after PeiReadOnlyVariable2 PPI
> produced
>
> + This function handles PlatformInit task after PeiReadOnlyVariable2 PPI
> produced
>
>
>
> -@param[in] PeiServices Pointer to PEI Services Table.
>
> -@param[in] NotifyDesc Pointer to the descriptor for the Notification
> event that
>
> - caused this function to execute.
>
> -@param[in] Ppi Pointer to the PPI data associated with this
> function.
>
> + @param[in] PeiServices Pointer to PEI Services Table.
>
> + @param[in] NotifyDesc Pointer to the descriptor for the
> Notification event that
>
> + caused this function to execute.
>
> + @param[in] Ppi Pointer to the PPI data associated with this
> function.
>
>
>
> -@retval EFI_SUCCESS The function completes successfully
>
> -@retval others
>
> + @retval EFI_SUCCESS The function completes successfully
>
> + @retval others Failure
>
> **/
>
> EFI_STATUS
>
> EFIAPI
>
> -PlatformInitPreMemCallBack(
>
> +PlatformInitPreMemCallBack (
>
> IN CONST EFI_PEI_SERVICES **PeiServices,
>
> IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
>
> IN VOID *Ppi
>
> -)
>
> + )
>
> {
>
> EFI_STATUS Status;
>
> UINT8 FwConfig;
>
> @@ -303,33 +303,33 @@ PlatformInitPreMemCallBack(
> //
>
> // Init Board Config Pcd.
>
> //
>
> - BoardConfigInitPreMem();
>
> + BoardConfigInitPreMem ();
>
>
>
> - DEBUG((DEBUG_ERROR, "Fail to get System Configuration and set the
> configuration to production mode!\n"));
>
> + DEBUG ((DEBUG_ERROR, "Fail to get System Configuration and set the
> configuration to production mode!\n"));
>
> FwConfig = FwConfigProduction;
>
> - PcdSetBoolS(PcdPcieWwanEnable, FALSE);
>
> - PcdSetBoolS(PcdWwanResetWorkaround, FALSE);
>
> + PcdSetBoolS (PcdPcieWwanEnable, FALSE);
>
> + PcdSetBoolS (PcdWwanResetWorkaround, FALSE);
>
>
>
> //
>
> // Early Board Configuration before memory is ready.
>
> //
>
> - Status = BoardInitEarlyPreMem();
>
> - ASSERT_EFI_ERROR(Status);
>
> + Status = BoardInitEarlyPreMem ();
>
> + ASSERT_EFI_ERROR (Status);
>
>
>
> ///
>
> /// If there was unexpected reset but no WDT expiration and no resume
> from S3/S4,
>
> /// clear unexpected reset status and enforce expiration. This is to inform
> Firmware
>
> /// which has no access to unexpected reset status bit, that something
> went wrong.
>
> ///
>
> - OcWdtResetCheck();
>
> + OcWdtResetCheck ();
>
>
>
> - Status = OcWdtInit();
>
> - ASSERT_EFI_ERROR(Status);
>
> + Status = OcWdtInit ();
>
> + ASSERT_EFI_ERROR (Status);
>
>
>
> //
>
> // Initialize Intel PEI Platform Policy
>
> //
>
> - PeiPolicyInitPreMem(FwConfig);
>
> + PeiPolicyInitPreMem (FwConfig);
>
>
>
> ///
>
> /// Configure GPIO and SIO
>
> @@ -340,56 +340,55 @@ PlatformInitPreMemCallBack(
> ///
>
> /// Install Pre Memory PPIs
>
> ///
>
> - Status = PeiServicesInstallPpi(&mPreMemPpiList[0]);
>
> - ASSERT_EFI_ERROR(Status);
>
> + Status = PeiServicesInstallPpi (&mPreMemPpiList[0]);
>
> + ASSERT_EFI_ERROR (Status);
>
>
>
> return Status;
>
> }
>
>
>
> /**
>
> -Provide hard reset PPI service.
>
> -To generate full hard reset, write 0x0E to PCH RESET_GENERATOR_PORT
> (0xCF9).
>
> + Provide hard reset PPI service.
>
> + To generate full hard reset, write 0x0E to PCH RESET_GENERATOR_PORT
> (0xCF9).
>
>
>
> -@param[in] PeiServices General purpose services available to
> every PEIM.
>
> + @param[in] PeiServices General purpose services available to
> every PEIM.
>
>
>
> -@retval Not return System reset occured.
>
> -@retval EFI_DEVICE_ERROR Device error, could not reset the system.
>
> + @retval Not return System reset occured.
>
> + @retval EFI_DEVICE_ERROR Device error, could not reset the
> system.
>
> **/
>
> EFI_STATUS
>
> EFIAPI
>
> -PchReset(
>
> +PchReset (
>
> IN CONST EFI_PEI_SERVICES **PeiServices
>
> -)
>
> + )
>
> {
>
> - DEBUG((DEBUG_INFO, "Perform Cold Reset\n"));
>
> - IoWrite8(RESET_GENERATOR_PORT, 0x0E);
>
> + DEBUG ((DEBUG_INFO, "Perform Cold Reset\n"));
>
> + IoWrite8 (RESET_GENERATOR_PORT, 0x0E);
>
>
>
> - CpuDeadLoop();
>
> + CpuDeadLoop ();
>
>
>
> ///
>
> /// System reset occured, should never reach at this line.
>
> ///
>
> - ASSERT_EFI_ERROR(EFI_DEVICE_ERROR);
>
> -
>
> + ASSERT_EFI_ERROR (EFI_DEVICE_ERROR);
>
> return EFI_DEVICE_ERROR;
>
> }
>
>
>
> /**
>
> -Install Firmware Volume Hob's once there is main memory
>
> + Install Firmware Volume Hob's once there is main memory
>
>
>
> -@param[in] PeiServices General purpose services available to
> every PEIM.
>
> -@param[in] NotifyDescriptor Notify that this module published.
>
> -@param[in] Ppi PPI that was installed.
>
> + @param[in] PeiServices General purpose services available to
> every PEIM.
>
> + @param[in] NotifyDescriptor Notify that this module published.
>
> + @param[in] Ppi PPI that was installed.
>
>
>
> -@retval EFI_SUCCESS The function completed successfully.
>
> + @retval EFI_SUCCESS The function completed successfully.
>
> **/
>
> EFI_STATUS
>
> EFIAPI
>
> -MemoryDiscoveredPpiNotify(
>
> +MemoryDiscoveredPpiNotify (
>
> IN CONST EFI_PEI_SERVICES **PeiServices,
>
> IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
>
> IN VOID *Ppi
>
> -)
>
> + )
>
> {
>
> EFI_STATUS Status;
>
> EFI_BOOT_MODE BootMode;
>
> @@ -400,12 +399,12 @@ MemoryDiscoveredPpiNotify(
>
>
> Index = 0;
>
>
>
> - Status = PeiServicesGetBootMode(&BootMode);
>
> - ASSERT_EFI_ERROR(Status);
>
> + Status = PeiServicesGetBootMode (&BootMode);
>
> + ASSERT_EFI_ERROR (Status);
>
>
>
> - AsmCpuid(0x80000000, &RegEax, NULL, NULL, NULL);
>
> + AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
>
> if (RegEax >= 0x80000008) {
>
> - AsmCpuid(0x80000008, &RegEax, NULL, NULL, NULL);
>
> + AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
>
> PhysicalAddressBits = (UINT8)RegEax;
>
> }
>
> else {
>
> @@ -415,69 +414,69 @@ MemoryDiscoveredPpiNotify(
> ///
>
> /// Create a CPU hand-off information
>
> ///
>
> - BuildCpuHob(PhysicalAddressBits, 16);
>
> + BuildCpuHob (PhysicalAddressBits, 16);
>
>
>
> ///
>
> /// Build Memory Mapped IO Resource which is used to build E820 Table
> in LegacyBios.
>
> ///
>
> - PcieMmioMap.BaseAddress = FixedPcdGet64(PcdPciExpressBaseAddress);
>
> - PcieMmioMap.Length = PcdGet32(PcdPciExpressRegionLength);
>
> + PcieMmioMap.BaseAddress = FixedPcdGet64
> (PcdPciExpressBaseAddress);
>
> + PcieMmioMap.Length = PcdGet32 (PcdPciExpressRegionLength);
>
>
>
> - BuildResourceDescriptorHob(
>
> + BuildResourceDescriptorHob (
>
> EFI_RESOURCE_MEMORY_MAPPED_IO,
>
> - (EFI_RESOURCE_ATTRIBUTE_PRESENT |
>
> - EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
>
> - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
>
> + (EFI_RESOURCE_ATTRIBUTE_PRESENT |
>
> + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
>
> + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
>
> PcieMmioMap.BaseAddress,
>
> PcieMmioMap.Length
>
> - );
>
> - BuildMemoryAllocationHob(
>
> + );
>
> + BuildMemoryAllocationHob (
>
> PcieMmioMap.BaseAddress,
>
> PcieMmioMap.Length,
>
> EfiMemoryMappedIO
>
> - );
>
> + );
>
> for (Index = 0; Index < sizeof(MmioMap) / (sizeof(MEMORY_MAP));
> Index++) {
>
> - BuildResourceDescriptorHob(
>
> + BuildResourceDescriptorHob (
>
> EFI_RESOURCE_MEMORY_MAPPED_IO,
>
> - (EFI_RESOURCE_ATTRIBUTE_PRESENT |
>
> - EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
>
> - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
>
> + (EFI_RESOURCE_ATTRIBUTE_PRESENT |
>
> + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
>
> + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
>
> MmioMap[Index].BaseAddress,
>
> MmioMap[Index].Length
>
> - );
>
> - BuildMemoryAllocationHob(
>
> + );
>
> + BuildMemoryAllocationHob (
>
> MmioMap[Index].BaseAddress,
>
> MmioMap[Index].Length,
>
> EfiMemoryMappedIO
>
> - );
>
> + );
>
> }
>
>
>
> //
>
> // Report resource HOB for flash FV
>
> //
>
> - BuildResourceDescriptorHob(
>
> + BuildResourceDescriptorHob (
>
> EFI_RESOURCE_MEMORY_MAPPED_IO,
>
> - (EFI_RESOURCE_ATTRIBUTE_PRESENT |
>
> - EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
>
> - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
>
> - (UINTN)FixedPcdGet32(PcdFlashAreaBaseAddress),
>
> - (UINTN)FixedPcdGet32(PcdFlashAreaSize)
>
> - );
>
> - BuildMemoryAllocationHob(
>
> - (UINTN)FixedPcdGet32(PcdFlashAreaBaseAddress),
>
> - (UINTN)FixedPcdGet32(PcdFlashAreaSize),
>
> + (EFI_RESOURCE_ATTRIBUTE_PRESENT |
>
> + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
>
> + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
>
> + (UINTN) FixedPcdGet32 (PcdFlashAreaBaseAddress),
>
> + (UINTN) FixedPcdGet32 (PcdFlashAreaSize)
>
> + );
>
> +
>
> + BuildMemoryAllocationHob (
>
> + (UINTN) FixedPcdGet32 (PcdFlashAreaBaseAddress),
>
> + (UINTN) FixedPcdGet32 (PcdFlashAreaSize),
>
> EfiMemoryMappedIO
>
> - );
>
> + );
>
>
>
> - BuildFvHob(
>
> - (UINTN)FixedPcdGet32(PcdFlashAreaBaseAddress),
>
> - (UINTN)FixedPcdGet32(PcdFlashAreaSize)
>
> - );
>
> + BuildFvHob (
>
> + (UINTN)FixedPcdGet32 (PcdFlashAreaBaseAddress),
>
> + (UINTN)FixedPcdGet32 (PcdFlashAreaSize)
>
> + );
>
>
>
> return Status;
>
> }
>
>
>
> -
>
> /**
>
> Board configuration init function for PEI pre-memory phase.
>
>
>
> @@ -495,26 +494,26 @@ WhiskeylakeURvpInitPreMem (
> ///
>
> /// Install Stall PPI
>
> ///
>
> - Status = InstallStallPpi();
>
> - ASSERT_EFI_ERROR(Status);
>
> + Status = InstallStallPpi ();
>
> + ASSERT_EFI_ERROR (Status);
>
>
>
> //
>
> // Install PCH RESET PPI and EFI RESET2 PeiService
>
> //
>
> - Status = PchInitializeReset();
>
> - ASSERT_EFI_ERROR(Status);
>
> + Status = PchInitializeReset ();
>
> + ASSERT_EFI_ERROR (Status);
>
>
>
> ///
>
> /// Performing PlatformInitPreMemCallBack after PeiReadOnlyVariable2
> PPI produced
>
> ///
>
> - Status = PeiServicesNotifyPpi(&mPreMemNotifyList);
>
> + Status = PeiServicesNotifyPpi (&mPreMemNotifyList);
>
>
>
> ///
>
> /// After code reorangized, memorycallback will run because the PPI is
> already
>
> /// installed when code run to here, it is supposed that the
> InstallEfiMemory is
>
> /// done before.
>
> ///
>
> - Status = PeiServicesNotifyPpi(&mMemDiscoveredNotifyList);
>
> + Status = PeiServicesNotifyPpi (&mMemDiscoveredNotifyList);
>
>
>
> return EFI_SUCCESS;
>
> }
>
> @@ -561,5 +560,3 @@ WhiskeylakeURvpBoardBootModeDetect (
> {
>
> return BOOT_WITH_FULL_CONFIGURATION;
>
> }
>
> -
>
> -
>
> --
> 2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 08/13] WhiskeylakeOpenBoardPkg: Remove SecFspWrapperPlatformSecLib override
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 08/13] WhiskeylakeOpenBoardPkg: Remove SecFspWrapperPlatformSecLib override Nate DeSimone
@ 2019-11-14 15:17 ` Chiu, Chasel
2019-11-16 2:53 ` Kubacki, Michael A
1 sibling, 0 replies; 44+ messages in thread
From: Chiu, Chasel @ 2019-11-14 15:17 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io; +Cc: Kubacki, Michael A
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Thursday, November 14, 2019 2:07 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>
> Subject: [edk2-platforms] [PATCH V1 08/13] WhiskeylakeOpenBoardPkg:
> Remove SecFspWrapperPlatformSecLib override
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../FspWrapperPlatformSecLib.c | 163 --------
> .../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 40 --
> .../SecFspWrapperPlatformSecLib/Ia32/Fsp.h | 43 ---
> .../Ia32/PeiCoreEntry.nasm | 130 -------
> .../Ia32/SecEntry.nasm | 361 ------------------
> .../Ia32/Stack.nasm | 72 ----
> .../PlatformInit.c | 54 ---
> .../SecFspWrapperPlatformSecLib.inf | 97 -----
> .../SecGetPerformance.c | 90 -----
> .../SecPlatformInformation.c | 79 ----
> .../SecRamInitData.c | 37 --
> .../SecTempRamDone.c | 48 ---
> .../WhiskeylakeURvp/OpenBoardPkg.dsc | 2 +-
> 13 files changed, 1 insertion(+), 1215 deletions(-) delete mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/FspWrapperPlatformSecLib.c
> delete mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/FsptCoreUpd.h
> delete mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/Ia32/Fsp.h
> delete mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/Ia32/PeiCoreEntry.nasm
> delete mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/Ia32/SecEntry.nasm
> delete mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/Ia32/Stack.nasm
> delete mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/PlatformInit.c
> delete mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> delete mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/SecGetPerformance.c
> delete mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/SecPlatformInformation.c
> delete mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/SecRamInitData.c
> delete mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/SecTempRamDone.c
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/FspWrapperPlatformSecLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/FspWrapperPlatformSecLib.c
> deleted file mode 100644
> index a767289bc5..0000000000
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/FspWrapperPlatformSecLib.c
> +++ /dev/null
> @@ -1,163 +0,0 @@
> -/** @file- Provide FSP wrapper platform sec related function.---
> Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>-
> SPDX-License-Identifier: BSD-2-Clause-Patent-**/--#include
> <PiPei.h>--#include <Ppi/SecPlatformInformation.h>-#include
> <Ppi/SecPerformance.h>-#include <Ppi/FirmwareVolumeInfo.h>-#include
> <Ppi/TopOfTemporaryRam.h>-#include
> <Guid/FirmwareFileSystem2.h>--#include <Library/LocalApicLib.h>-#include
> <Library/BaseMemoryLib.h>-#include <Library/DebugLib.h>-#include
> <Library/IoLib.h>--/**- This interface conveys state information out of the
> Security (SEC) phase into PEI.-- @param[in] PeiServices
> Pointer to the PEI Services Table.- @param[in,out] StructureSize
> Pointer to the variable describing size of the input buffer.- @param[out]
> PlatformInformationRecord Pointer to the
> EFI_SEC_PLATFORM_INFORMATION_RECORD.-- @retval EFI_SUCCESS
> The data was successfully returned.- @retval EFI_BUFFER_TOO_SMALL
> The buffer was too small.--**/-EFI_STATUS-EFIAPI-SecPlatformInformation (-
> IN CONST EFI_PEI_SERVICES **PeiServices,- IN OUT
> UINT64 *StructureSize,- OUT
> EFI_SEC_PLATFORM_INFORMATION_RECORD
> *PlatformInformationRecord- );--/**- This interface conveys performance
> information out of the Security (SEC) phase into PEI.-- This service is
> published by the SEC phase. The SEC phase handoff has an optional-
> EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed
> from SEC into the- PEI Foundation. As such, if the platform supports
> collecting performance data in SEC,- this information is encapsulated into
> the data structure abstracted by this service.- This information is collected
> for the boot-strap processor (BSP) on IA-32.-- @param[in] PeiServices
> The pointer to the PEI Services Table.- @param[in] This The
> pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.- @param[out]
> Performance The pointer to performance data collected in SEC phase.--
> @retval EFI_SUCCESS The data was successfully
> returned.--**/-EFI_STATUS-EFIAPI-SecGetPerformance (- IN CONST
> EFI_PEI_SERVICES **PeiServices,- IN
> PEI_SEC_PERFORMANCE_PPI *This,- OUT
> FIRMWARE_SEC_PERFORMANCE
> *Performance- );--PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi = {-
> SecGetPerformance-};--EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] = {-
> {- EFI_PEI_PPI_DESCRIPTOR_PPI,- &gTopOfTemporaryRamPpiGuid,-
> NULL // To be patched later.- },- {- EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,-
> &gPeiSecPerformancePpiGuid,- &mSecPerformancePpi- },-};--#define
> LEGACY_8259_MASK_REGISTER_MASTER 0x21-#define
> LEGACY_8259_MASK_REGISTER_SLAVE 0xA1-#define
> LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER 0x4D0-#define
> LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE 0x4D1--/**-
> Write to mask and edge/level triggered registers of master and slave 8259
> PICs.-- @param[in] Mask low byte for master PIC mask register,-
> high byte for slave PIC mask register.- @param[in] EdgeLevel low byte
> for master PIC edge/level triggered register,-
> high byte for slave PIC edge/level triggered
> register.--**/-VOID-Interrupt8259WriteMask (- IN UINT16 Mask,- IN
> UINT16 EdgeLevel- )-{- IoWrite8
> (LEGACY_8259_MASK_REGISTER_MASTER, (UINT8) Mask);- IoWrite8
> (LEGACY_8259_MASK_REGISTER_SLAVE, (UINT8) (Mask >> 8));- IoWrite8
> (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER, (UINT8)
> EdgeLevel);- IoWrite8
> (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE, (UINT8)
> (EdgeLevel >> 8));-}--/**- A developer supplied function to perform
> platform specific operations.-- It's a developer supplied function to
> perform any operations appropriate to a- given platform. It's invoked just
> before passing control to PEI core by SEC- core. Platform developer may
> modify the SecCoreData passed to PEI Core.- It returns a platform specific
> PPI list that platform wishes to pass to PEI core.- The Generic SEC core
> module will merge this list to join the final list passed to- PEI core.--
> @param[in,out] SecCoreData The same parameter as passing to
> PEI core. It- could be
> overridden by this function.-- @return The platform specific PPI list to be
> passed to PEI core or- NULL if there is no need of such platform
> specific PPI list.--**/-EFI_PEI_PPI_DESCRIPTOR *-EFIAPI-SecPlatformMain (-
> IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData- )-{-
> EFI_PEI_PPI_DESCRIPTOR *PpiList;-- DEBUG ((DEBUG_INFO, "FSP
> Wrapper BootFirmwareVolumeBase - 0x%x\n",
> SecCoreData->BootFirmwareVolumeBase));- DEBUG ((DEBUG_INFO, "FSP
> Wrapper BootFirmwareVolumeSize - 0x%x\n",
> SecCoreData->BootFirmwareVolumeSize));- DEBUG ((DEBUG_INFO, "FSP
> Wrapper TemporaryRamBase - 0x%x\n",
> SecCoreData->TemporaryRamBase));- DEBUG ((DEBUG_INFO, "FSP Wrapper
> TemporaryRamSize - 0x%x\n", SecCoreData->TemporaryRamSize));-
> DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamBase - 0x%x\n",
> SecCoreData->PeiTemporaryRamBase));- DEBUG ((DEBUG_INFO, "FSP
> Wrapper PeiTemporaryRamSize - 0x%x\n",
> SecCoreData->PeiTemporaryRamSize));- DEBUG ((DEBUG_INFO, "FSP
> Wrapper StackBase - 0x%x\n", SecCoreData->StackBase));-
> DEBUG ((DEBUG_INFO, "FSP Wrapper StackSize - 0x%x\n",
> SecCoreData->StackSize));-- InitializeApicTimer (0, (UINT32) -1, TRUE, 5);--
> //- // Set all 8259 interrupts to edge triggered and disabled- //-
> Interrupt8259WriteMask (0xFFFF, 0x0000);-- //- // Use middle of Heap as
> temp buffer, it will be copied by caller.- // Do not use Stack, because it will
> cause wrong calculation on stack by PeiCore- //- PpiList = (VOID
> *)((UINTN)SecCoreData->PeiTemporaryRamBase +
> (UINTN)SecCoreData->PeiTemporaryRamSize/2);- CopyMem (PpiList,
> mPeiSecPlatformPpi, sizeof(mPeiSecPlatformPpi));-- //- // Patch
> TopOfTemporaryRamPpi- //- PpiList[0].Ppi = (VOID
> *)((UINTN)SecCoreData->TemporaryRamBase +
> SecCoreData->TemporaryRamSize);-- return PpiList;-}-diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/FsptCoreUpd.h
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/FsptCoreUpd.h
> deleted file mode 100644
> index e7b5ed952b..0000000000
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/FsptCoreUpd.h
> +++ /dev/null
> @@ -1,40 +0,0 @@
> -/** @file-- Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>-
> SPDX-License-Identifier: BSD-2-Clause-Patent-**/--#ifndef
> __FSPT_CORE_UPD_H__-#define __FSPT_CORE_UPD_H__--#pragma
> pack(1)--/** Fsp T Core UPD-**/-typedef struct {--/** Offset 0x0020-**/-
> UINT32 MicrocodeRegionBase;--/** Offset
> 0x0024-**/- UINT32 MicrocodeRegionSize;--/**
> Offset 0x0028-**/- UINT32 CodeRegionBase;--/**
> Offset 0x002C-**/- UINT32 CodeRegionSize;--/**
> Offset 0x0030-**/- UINT8 Reserved[16];-}
> FSPT_CORE_UPD;--#pragma pack()--#endif-diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/Ia32/Fsp.h
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/Ia32/Fsp.h
> deleted file mode 100644
> index 1c88285a1d..0000000000
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/Ia32/Fsp.h
> +++ /dev/null
> @@ -1,43 +0,0 @@
> -/** @file- Fsp related definitions--- Copyright (c) 2019, Intel Corporation.
> All rights reserved.<BR>- SPDX-License-Identifier:
> BSD-2-Clause-Patent-**/--#ifndef __FSP_H__-#define __FSP_H__--//-// Fv
> Header-//-#define FVH_SIGINATURE_OFFSET 0x28-#define
> FVH_SIGINATURE_VALID_VALUE 0x4856465F // valid
> signature:_FVH-#define FVH_HEADER_LENGTH_OFFSET 0x30-#define
> FVH_EXTHEADER_OFFSET_OFFSET 0x34-#define
> FVH_EXTHEADER_SIZE_OFFSET 0x10--//-// Ffs Header-//-#define
> FSP_HEADER_GUID_DWORD1 0x912740BE-#define
> FSP_HEADER_GUID_DWORD2 0x47342284-#define
> FSP_HEADER_GUID_DWORD3 0xB08471B9-#define
> FSP_HEADER_GUID_DWORD4 0x0C3F3527-#define
> FFS_HEADER_SIZE_VALUE 0x18--//-// Section Header-//-#define
> SECTION_HEADER_TYPE_OFFSET 0x03-#define
> RAW_SECTION_HEADER_SIZE_VALUE 0x04--//-// Fsp Header-//-#define
> FSP_HEADER_IMAGEBASE_OFFSET 0x1C-#define
> FSP_HEADER_TEMPRAMINIT_OFFSET 0x30--#endif-diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/Ia32/PeiCoreEntry.nasm
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/Ia32/PeiCoreEntry.nasm
> deleted file mode 100644
> index 5c5b788085..0000000000
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/Ia32/PeiCoreEntry.nasm
> +++ /dev/null
> @@ -1,130 +0,0 @@
> -;-------------------------------------------------------------------------------;-; Copyright (c)
> 2019, Intel Corporation. All rights reserved.<BR>-; SPDX-License-Identifier:
> BSD-2-Clause-Patent-;-; Module Name:-;-; PeiCoreEntry.nasm-;-; Abstract:-;-;
> Find and call
> SecStartup-;-;--------------------------------------------------------------------------------SECTI
> ON .text--extern ASM_PFX(SecStartup)-extern ASM_PFX(PlatformInit)--global
> ASM_PFX(CallPeiCoreEntryPoint)-ASM_PFX(CallPeiCoreEntryPoint):- ;- ;
> Obtain the hob list pointer- ;- mov eax, [esp+4]- ;- ; Obtain the
> stack information- ; ECX: start of range- ; EDX: end of range- ;-
> mov ecx, [esp+8]- mov edx, [esp+0xC]-- ;- ; Platform init- ;-
> pushad- push edx- push ecx- push eax- call ASM_PFX(PlatformInit)-
> pop eax- pop eax- pop eax- popad-- ;- ; Set stack top
> pointer- ;- mov esp, edx-- ;- ; Push the hob list pointer- ;-
> push eax-- ;- ; Save the value- ; ECX: start of range- ; EDX:
> end of range- ;- mov ebp, esp- push ecx- push
> edx-- ;- ; Push processor count to stack first, then BIST status (AP then
> BSP)- ;- mov eax, 1- cpuid- shr ebx, 16- and ebx,
> 0xFF- cmp bl, 1- jae PushProcessorCount-- ;- ; Some
> processors report 0 logical processors. Effectively 0 = 1.- ; So we fix up
> the processor count- ;- inc ebx--PushProcessorCount:- push
> ebx-- ;- ; We need to implement a long-term solution for BIST capture.
> For now, we just copy BSP BIST- ; for all processor threads- ;- xor
> ecx, ecx- mov cl, bl-PushBist:- movd eax, mm0- push eax-
> loop PushBist-- ; Save Time-Stamp Counter- movd eax, mm5- push
> eax-- movd eax, mm6- push eax-- ;- ; Pass entry point of the PEI
> core- ;- mov edi, 0xFFFFFFE0- push DWORD [edi]-- ;- ; Pass
> BFV into the PEI Core- ;- mov edi, 0xFFFFFFFC- push DWORD
> [edi]-- ;- ; Pass stack size into the PEI Core- ;- mov ecx, [ebp - 4]-
> mov edx, [ebp - 8]- push ecx ; RamBase-- sub edx,
> ecx- push edx ; RamSize-- ;- ; Pass Control into the PEI
> Core- ;- call ASM_PFX(SecStartup)-diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/Ia32/SecEntry.nasm
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/Ia32/SecEntry.nasm
> deleted file mode 100644
> index 7f6d771e41..0000000000
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/Ia32/SecEntry.nasm
> +++ /dev/null
> @@ -1,361 +0,0 @@
> -;-------------------------------------------------------------------------------;-; Copyright (c)
> 2019, Intel Corporation. All rights reserved.<BR>-; SPDX-License-Identifier:
> BSD-2-Clause-Patent-; Module Name:-;-; SecEntry.nasm-;-; Abstract:-;-;
> This is the code that goes from real-mode to protected mode.-; It
> consumes the reset vector, calls TempRamInit API from FSP
> binary.-;-;--------------------------------------------------------------------------------#include
> "Fsp.h"--SECTION .text--extern ASM_PFX(CallPeiCoreEntryPoint)-extern
> ASM_PFX(FsptUpdDataPtr)-extern ASM_PFX(BoardBeforeTempRamInit)-;
> Pcds-extern ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))-extern
> ASM_PFX(PcdGet32
> (PcdFsptBaseAddress))--;------------------------------------------------------------------------
> -----;-; Procedure: _ModuleEntryPoint-;-; Input: None-;-; Output:
> None-;-; Destroys: Assume all registers-;-; Description:-;-; Transition
> to non-paged flat-model protected mode from a-; hard-coded GDT that
> provides exactly two descriptors.-; This is a bare bones transition to
> protected mode only-; used for a while in PEI and possibly DXE.-;-;
> After enabling protected mode, a far jump is executed to-; transfer to PEI
> using the newly loaded GDT.-;-; Return: None-;-; MMX Usage:-;
> MM0 = BIST State-; MM5 = Save time-stamp counter value
> high32bit-; MM6 = Save time-stamp counter value
> low32bit.-;-;------------------------------------------------------------------------------BITS
> 16-align 4-global
> ASM_PFX(_ModuleEntryPoint)-ASM_PFX(_ModuleEntryPoint):-
> fninit ; clear any pending Floating
> point exceptions- ;- ; Store the BIST value in mm0- ;- movd mm0,
> eax- cli-- ;- ; Check INIT# is asserted by port 0xCF9- ;- mov dx, 0CF9h-
> in al, dx- cmp al, 04h- jnz NotWarmStart--- ;- ; @note Issue warm
> reset, since if CPU only reset is issued not all MSRs are restored to their
> defaults- ;- mov dx, 0CF9h- mov al, 06h- out dx,
> al--NotWarmStart:- ;- ; Save time-stamp counter value- ; rdtsc load 64bit
> time-stamp counter to EDX:EAX- ;- rdtsc- movd mm5, edx- movd
> mm6, eax-- ;- ; Load the GDT table in GdtDesc- ;- mov esi,
> GdtDesc- DB 66h- lgdt [cs:si]-- ;- ; Transition to 16 bit
> protected mode- ;- mov eax, cr0 ; Get control
> register 0- or eax, 00000003h ; Set PE bit (bit #0) &
> MP bit (bit #1)- mov cr0, eax ; Activate
> protected mode-- mov eax, cr4 ; Get control
> register 4- or eax, 00000600h ; Set OSFXSR bit (bit #9)
> & OSXMMEXCPT bit (bit #10)- mov cr4, eax-- ;- ; Now we're in 16
> bit protected mode- ; Set up the selectors for 32 bit protected mode
> entry- ;- mov ax, SYS_DATA_SEL- mov ds, ax- mov es,
> ax- mov fs, ax- mov gs, ax- mov ss, ax-- ;- ; Transition
> to Flat 32 bit protected mode- ; The jump to a far pointer causes the
> transition to 32 bit mode- ;- mov esi, ProtectedModeEntryLinearAddress-
> jmp dword far
> [cs:si]--;-----------------------------------------------------------------------------;-; Procedure:
> ProtectedModeEntryPoint-;-; Input: None-;-; Output: None-;-;
> Destroys: Assume all registers-;-; Description:-;-; This function handles:-;
> Call two basic APIs from FSP binary-; Initializes stack with some early data
> (BIST, PEI entry, etc)-;-; Return:
> None-;-;------------------------------------------------------------------------------BITS 32-align
> 4-ProtectedModeEntryPoint:- ;- ; Early board hooks- ;- mov esp,
> BoardBeforeTempRamInitRet- jmp
> ASM_PFX(BoardBeforeTempRamInit)--BoardBeforeTempRamInitRet:-- ;
> Find the fsp info header- mov edi, [ASM_PFX(PcdGet32
> (PcdFsptBaseAddress))]-- mov eax, dword [edi +
> FVH_SIGINATURE_OFFSET]- cmp eax, FVH_SIGINATURE_VALID_VALUE-
> jnz FspHeaderNotFound-- xor eax, eax- mov ax, word [edi +
> FVH_EXTHEADER_OFFSET_OFFSET]- cmp ax, 0- jnz
> FspFvExtHeaderExist-- xor eax, eax- mov ax, word [edi +
> FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header- add edi, eax-
> jmp FspCheckFfsHeader--FspFvExtHeaderExist:- add edi, eax- mov
> eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Header-
> add edi, eax-- ; Round up to 8 byte alignment- mov eax, edi- and
> al, 07h- jz FspCheckFfsHeader-- and edi, 0FFFFFFF8h- add edi,
> 08h--FspCheckFfsHeader:- ; Check the ffs guid- mov eax, dword [edi]-
> cmp eax, FSP_HEADER_GUID_DWORD1- jnz FspHeaderNotFound--
> mov eax, dword [edi + 4]- cmp eax, FSP_HEADER_GUID_DWORD2- jnz
> FspHeaderNotFound-- mov eax, dword [edi + 8]- cmp eax,
> FSP_HEADER_GUID_DWORD3- jnz FspHeaderNotFound-- mov eax,
> dword [edi + 0Ch]- cmp eax, FSP_HEADER_GUID_DWORD4- jnz
> FspHeaderNotFound-- add edi, FFS_HEADER_SIZE_VALUE ; Bypass
> the ffs header-- ; Check the section type as raw section- mov al, byte
> [edi + SECTION_HEADER_TYPE_OFFSET]- cmp al, 019h- jnz
> FspHeaderNotFound-- add edi, RAW_SECTION_HEADER_SIZE_VALUE ;
> Bypass the section header- jmp FspHeaderFound--FspHeaderNotFound:-
> jmp $--FspHeaderFound:- ; Get the fsp TempRamInit Api address- mov
> eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]- add eax, dword [edi
> + FSP_HEADER_TEMPRAMINIT_OFFSET]-- ; Setup the hardcode stack- mov
> esp, TempRamInitStack-- ; Call the fsp TempRamInit Api- jmp
> eax--TempRamInitDone:- cmp eax, 8000000Eh ;Check if
> EFI_NOT_FOUND returned. Error code for Microcode Update not found.- je
> CallSecFspInit ;If microcode not found, don't hang, but continue.--
> cmp eax, 0 ;Check if EFI_SUCCESS retuned.- jnz
> FspApiFailed-- ; ECX: start of range- ; EDX: end of
> range-CallSecFspInit:- sub edx, [ASM_PFX(PcdGet32
> (PcdFspTemporaryRamSize))] ; TemporaryRam for FSP- xor eax, eax-
> mov esp, edx-- ; Align the stack at DWORD- add esp, 3- and
> esp, 0FFFFFFFCh-- push edx- push ecx- push eax ; zero - no
> hob list yet- call ASM_PFX(CallPeiCoreEntryPoint)--FspApiFailed:- jmp
> $--align 10h-TempRamInitStack:- DD TempRamInitDone- DD
> ASM_PFX(FsptUpdDataPtr); TempRamInitParams--;-; ROM-based
> Global-Descriptor Table for the Tiano PEI Phase-;-align 16-global
> ASM_PFX(BootGdtTable)--;-; GDT[0]: 0x00: Null entry, never used.-;-NULL_SEL
> EQU $ - GDT_BASE ; Selector [0]-GDT_BASE:-ASM_PFX(BootGdtTable):-
> DD 0- DD 0-;-; Linear data segment
> descriptor-;-LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8]-
> DW 0FFFFh ; limit 0xFFFFF- DW
> 0 ; base 0- DB 0- DB
> 092h ; present, ring 0, data, expand-up,
> writable- DB 0CFh ; page-granular,
> 32-bit- DB 0-;-; Linear code segment descriptor-;-LINEAR_CODE_SEL
> EQU $ - GDT_BASE ; Selector [0x10]- DW
> 0FFFFh ; limit 0xFFFFF- DW
> 0 ; base 0- DB 0- DB
> 09Bh ; present, ring 0, data, expand-up,
> not-writable- DB 0CFh ; page-granular,
> 32-bit- DB 0-;-; System data segment descriptor-;-SYS_DATA_SEL
> EQU $ - GDT_BASE ; Selector [0x18]- DW
> 0FFFFh ; limit 0xFFFFF- DW
> 0 ; base 0- DB 0- DB
> 093h ; present, ring 0, data, expand-up,
> not-writable- DB 0CFh ; page-granular,
> 32-bit- DB 0--;-; System code segment descriptor-;-SYS_CODE_SEL
> EQU $ - GDT_BASE ; Selector [0x20]- DW
> 0FFFFh ; limit 0xFFFFF- DW
> 0 ; base 0- DB 0- DB
> 09Ah ; present, ring 0, data, expand-up,
> writable- DB 0CFh ; page-granular,
> 32-bit- DB 0-;-; Spare segment descriptor-;-SYS16_CODE_SEL EQU
> $ - GDT_BASE ; Selector [0x28]- DW
> 0FFFFh ; limit 0xFFFFF- DW
> 0 ; base 0- DB
> 0Eh ; Changed from F000 to E000.- DB
> 09Bh ; present, ring 0, code, expand-up,
> writable- DB 00h ; byte-granular,
> 16-bit- DB 0-;-; Spare segment descriptor-;-SYS16_DATA_SEL EQU
> $ - GDT_BASE ; Selector [0x30]- DW
> 0FFFFh ; limit 0xFFFF- DW
> 0 ; base 0- DB 0- DB
> 093h ; present, ring 0, data, expand-up,
> not-writable- DB 00h ; byte-granular,
> 16-bit- DB 0--;-; Spare segment descriptor-;-SPARE5_SEL
> EQU $ - GDT_BASE ; Selector [0x38]- DW
> 0 ; limit 0- DW
> 0 ; base 0- DB 0- DB
> 0 ; present, ring 0, data, expand-up,
> writable- DB 0 ; page-granular,
> 32-bit- DB 0-GDT_SIZE EQU $ - GDT_BASE ; Size, in
> bytes--;-; GDT Descriptor-;-GdtDesc: ;
> GDT descriptor- DW GDT_SIZE - 1 ; GDT limit-
> DD GDT_BASE ; GDT base
> address---ProtectedModeEntryLinearAddress:-ProtectedModeEntryLinear:-
> DD ProtectedModeEntryPoint ; Offset of our 32 bit code- DW
> LINEAR_CODE_SELdiff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/Ia32/Stack.nasm
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/Ia32/Stack.nasm
> deleted file mode 100644
> index 47db32d64c..0000000000
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/Ia32/Stack.nasm
> +++ /dev/null
> @@ -1,72 +0,0 @@
> -;-------------------------------------------------------------------------------;-; Copyright (c)
> 2019, Intel Corporation. All rights reserved.<BR>-; SPDX-License-Identifier:
> BSD-2-Clause-Patent-; Abstract:-;-; Switch the stack from temporary
> memory to permanent
> memory.-;-;--------------------------------------------------------------------------------
> SECTION .text--;-------------------------------------------------------------------------------;
> VOID-; EFIAPI-; SecSwitchStack (-; UINT32 TemporaryMemoryBase,-;
> UINT32
> PermanentMemoryBase-; );-;---------------------------------------------------------------
> ----------------global
> ASM_PFX(SecSwitchStack)-ASM_PFX(SecSwitchStack):- ;- ; Save three
> register: eax, ebx, ecx- ;- push eax- push ebx- push ecx-
> push edx-- ;- ; !!CAUTION!! this function address's is pushed into
> stack after- ; migration of whole temporary memory, so need save it to
> permanent- ; memory at first!- ;-- mov ebx, [esp +
> 20] ; Save the first parameter- mov ecx, [esp +
> 24] ; Save the second parameter-- ;- ; Save this function's
> return address into permanent memory at first.- ; Then, Fixup the esp
> point to permanent memory- ;- mov eax, esp- sub eax,
> ebx- add eax, ecx- mov edx, dword [esp] ; copy
> pushed register's value to permanent memory- mov dword [eax], edx-
> mov edx, dword [esp + 4]- mov dword [eax + 4], edx- mov
> edx, dword [esp + 8]- mov dword [eax + 8], edx- mov edx,
> dword [esp + 12]- mov dword [eax + 12], edx- mov edx, dword
> [esp + 16] ; Update this function's return address into permanent
> memory- mov dword [eax + 16], edx- mov esp,
> eax ; From now, esp is pointed to permanent
> memory-- ;- ; Fixup the ebp point to permanent memory- ;-
> mov eax, ebp- sub eax, ebx- add eax, ecx- mov ebp,
> eax ; From now, ebp is pointed to permanent memory--
> pop edx- pop ecx- pop ebx- pop eax- ret-diff
> --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/PlatformInit.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/PlatformInit.c
> deleted file mode 100644
> index 06ca63c19a..0000000000
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/PlatformInit.c
> +++ /dev/null
> @@ -1,54 +0,0 @@
> -/** @file- Provide platform init function.--- Copyright (c) 2019, Intel
> Corporation. All rights reserved.<BR>- SPDX-License-Identifier:
> BSD-2-Clause-Patent-**/--#include <PiPei.h>-#include
> <Library/DebugLib.h>-#include <Library/SerialPortLib.h>-#include
> <Library/SecBoardInitLib.h>-#include <Library/TestPointCheckLib.h>-#include
> <Register/PchRegsPmc.h>-#include <Library/IoLib.h>--/**- Platform
> initialization.-- @param[in] FspHobList HobList produced by FSP.-
> @param[in] StartOfRange Start of temporary RAM.- @param[in]
> EndOfRange End of temporary RAM.-**/-VOID-EFIAPI-PlatformInit (- IN
> VOID *FspHobList,- IN VOID
> *StartOfRange,- IN VOID *EndOfRange- )-{- ///- ///
> Halt the TCO timer as early as possible- ///- IoWrite16 (PcdGet16
> (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT,
> B_TCO_IO_TCO1_CNT_TMR_HLT);-- //- // Platform initialization- //
> Enable Serial port here- //- if (PcdGetBool(PcdSecSerialPortDebugEnable))
> {- SerialPortInitialize ();- }-- DEBUG ((DEBUG_INFO,
> "PrintPeiCoreEntryPointParam in PlatformInit\n"));- DEBUG ((DEBUG_INFO,
> "FspHobList - 0x%x\n", FspHobList));- DEBUG ((DEBUG_INFO, "StartOfRange
> - 0x%x\n", StartOfRange));- DEBUG ((DEBUG_INFO, "EndOfRange - 0x%x\n",
> EndOfRange));-- BoardAfterTempRamInit ();--
> TestPointTempMemoryFunction (StartOfRange, EndOfRange);-}-diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> deleted file mode 100644
> index 06489a6336..0000000000
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> +++ /dev/null
> @@ -1,97 +0,0 @@
> -## @file-# Provide FSP wrapper platform sec related function.-#-#-#
> Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>-#-#
> SPDX-License-Identifier:
> BSD-2-Clause-Patent-#-#-##--########################################
> ########################################-#-# Defines Section -
> statements that will be processed to create a
> Makefile.-#-######################################################
> ##########################-[Defines]- INF_VERSION
> = 0x00010005- BASE_NAME =
> SecFspWrapperPlatformSecLib- FILE_GUID =
> 4E1C4F95-90EA-47de-9ACC-B8920189A1F5- MODULE_TYPE
> = SEC- VERSION_STRING = 1.0- LIBRARY_CLASS
> = PlatformSecLib---#-# The following information is for reference only and
> not required by the build tools.-#-# VALID_ARCHITECTURES =
> IA32
> X64-#--##########################################################
> ######################-#-# Sources Section - list of files that are required
> for the build to
> succeed.-#-######################################################
> ##########################--[Sources]- FspWrapperPlatformSecLib.c-
> SecRamInitData.c- SecPlatformInformation.c- SecGetPerformance.c-
> SecTempRamDone.c- PlatformInit.c--[Sources.IA32]- Ia32/SecEntry.nasm-
> Ia32/PeiCoreEntry.nasm- Ia32/Stack.nasm-
> Ia32/Fsp.h--######################################################
> ##########################-#-# Package Dependency Section - list of
> Package files that are required for-# this
> module.-#-#######################################################
> #########################--[Packages]- MdePkg/MdePkg.dec-
> MdeModulePkg/MdeModulePkg.dec- UefiCpuPkg/UefiCpuPkg.dec-
> IntelFsp2Pkg/IntelFsp2Pkg.dec-
> IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec-
> MinPlatformPkg/MinPlatformPkg.dec-
> CoffeelakeSiliconPkg/SiPkg.dec--[LibraryClasses]- LocalApicLib-
> SerialPortLib- FspWrapperPlatformLib- FspWrapperApiLib- BoardInitLib-
> SecBoardInitLib- TestPointCheckLib- IoLib--[Ppis]-
> gEfiSecPlatformInformationPpiGuid ## CONSUMES-
> gPeiSecPerformancePpiGuid ## CONSUMES-
> gTopOfTemporaryRamPpiGuid ## PRODUCES-
> gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES--[Pcd]-
> gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize
> ## CONSUMES- gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress
> ## CONSUMES- gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize
> ## CONSUMES-
> gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ##
> CONSUMES- gSiPkgTokenSpaceGuid.PcdTcoBaseAddress--[FixedPcd]-
> gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress
> ## CONSUMES-
> gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize
> ## CONSUMES-
> gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset
> ## CONSUMES-
> gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress
> ## CONSUMES- gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize
> ## CONSUMES-diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/SecGetPerformance.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/SecGetPerformance.c
> deleted file mode 100644
> index 67bdd232bb..0000000000
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/SecGetPerformance.c
> +++ /dev/null
> @@ -1,90 +0,0 @@
> -/** @file- Sample to provide SecGetPerformance function.--- Copyright
> (c) 2019, Intel Corporation. All rights reserved.<BR>- SPDX-License-Identifier:
> BSD-2-Clause-Patent-**/--#include <PiPei.h>--#include
> <Ppi/SecPerformance.h>-#include <Ppi/TopOfTemporaryRam.h>--#include
> <Library/BaseMemoryLib.h>-#include <Library/TimerLib.h>-#include
> <Library/DebugLib.h>--/**- This interface conveys performance information
> out of the Security (SEC) phase into PEI.-- This service is published by the
> SEC phase. The SEC phase handoff has an optional-
> EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed
> from SEC into the- PEI Foundation. As such, if the platform supports
> collecting performance data in SEC,- this information is encapsulated into
> the data structure abstracted by this service.- This information is collected
> for the boot-strap processor (BSP) on IA-32.-- @param[in] PeiServices
> The pointer to the PEI Services Table.- @param[in] This The
> pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.- @param[out]
> Performance The pointer to performance data collected in SEC phase.--
> @retval EFI_SUCCESS The data was successfully
> returned.--**/-EFI_STATUS-EFIAPI-SecGetPerformance (- IN CONST
> EFI_PEI_SERVICES **PeiServices,- IN
> PEI_SEC_PERFORMANCE_PPI *This,- OUT
> FIRMWARE_SEC_PERFORMANCE *Performance- )-{- UINT32 Size;-
> UINT32 Count;- UINT32 TopOfTemporaryRam;- UINT64
> Ticker;- VOID *TopOfTemporaryRamPpi;- EFI_STATUS Status;--
> DEBUG ((DEBUG_INFO, "SecGetPerformance\n"));-- Status =
> (*PeiServices)->LocatePpi (- PeiServices,-
> &gTopOfTemporaryRamPpiGuid,- 0,-
> NULL,- (VOID **)
> &TopOfTemporaryRamPpi- );- if
> (EFI_ERROR (Status)) {- return EFI_NOT_FOUND;- }- //- //
> |--------------| <- TopOfTemporaryRam - BL- // | List Ptr |- //
> |--------------|- // | BL RAM Start |- // |--------------|- // | BL RAM End
> |- // |--------------|- // |Number of BSPs|- // |--------------|- // |
> BIST |- // |--------------|- // | .... |- // |--------------|- // |
> TSC[63:32] |- // |--------------|- // | TSC[31:00] |- // |--------------|-
> //- TopOfTemporaryRam = (UINT32)(UINTN)TopOfTemporaryRamPpi -
> sizeof(UINT32);- TopOfTemporaryRam -= sizeof(UINT32) * 2;- Count
> = *(UINT32 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32));- Size
> = Count * sizeof (UINT32);-- Ticker = *(UINT64 *) (UINTN)
> (TopOfTemporaryRam - sizeof (UINT32) - Size - sizeof (UINT32) * 2);-
> Performance->ResetEnd = GetTimeInNanoSecond (Ticker);-- return
> EFI_SUCCESS;-}-diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/SecPlatformInformation.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/SecPlatformInformation.c
> deleted file mode 100644
> index e05daa8784..0000000000
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/SecPlatformInformation.c
> +++ /dev/null
> @@ -1,79 +0,0 @@
> -/** @file- Provide SecPlatformInformation function.--- Copyright (c) 2019,
> Intel Corporation. All rights reserved.<BR>- SPDX-License-Identifier:
> BSD-2-Clause-Patent-**/--#include <PiPei.h>--#include
> <Ppi/SecPlatformInformation.h>-#include
> <Ppi/TopOfTemporaryRam.h>--#include
> <Library/BaseMemoryLib.h>-#include <Library/DebugLib.h>--/**- This
> interface conveys state information out of the Security (SEC) phase into PEI.--
> @param[in] PeiServices Pointer to the PEI Services
> Table.- @param[in,out] StructureSize Pointer to the variable
> describing size of the input buffer.- @param[out]
> PlatformInformationRecord Pointer to the
> EFI_SEC_PLATFORM_INFORMATION_RECORD.-- @retval EFI_SUCCESS
> The data was successfully returned.- @retval EFI_BUFFER_TOO_SMALL
> The buffer was too small.--**/-EFI_STATUS-EFIAPI-SecPlatformInformation (-
> IN CONST EFI_PEI_SERVICES **PeiServices,- IN OUT
> UINT64 *StructureSize,- OUT
> EFI_SEC_PLATFORM_INFORMATION_RECORD
> *PlatformInformationRecord- )-{- UINT32 *Bist;- UINT32
> Size;- UINT32 Count;- UINT32 TopOfTemporaryRam;- VOID
> *TopOfTemporaryRamPpi;- EFI_STATUS Status;-- DEBUG ((DEBUG_INFO,
> "SecPlatformInformation\n"));-- Status = (*PeiServices)->LocatePpi (-
> PeiServices,-
> &gTopOfTemporaryRamPpiGuid,- 0,-
> NULL,- (VOID **)
> &TopOfTemporaryRamPpi- );- if
> (EFI_ERROR (Status)) {- return EFI_NOT_FOUND;- }-- //- // The
> entries of BIST information, together with the number of them,- // reside
> in the bottom of stack, left untouched by normal stack operation.- // This
> routine copies the BIST information to the buffer pointed by- //
> PlatformInformationRecord for output.- //- TopOfTemporaryRam =
> (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof (UINT32);-
> TopOfTemporaryRam -= sizeof(UINT32) * 2;- Count =
> *((UINT32 *)(UINTN) (TopOfTemporaryRam - sizeof (UINT32)));- Size
> = Count * sizeof (IA32_HANDOFF_STATUS);-- if ((*StructureSize) < (UINT64)
> Size) {- *StructureSize = Size;- return EFI_BUFFER_TOO_SMALL;- }--
> *StructureSize = Size;- Bist = (UINT32 *)
> (TopOfTemporaryRam - sizeof (UINT32) - Size);-- CopyMem
> (PlatformInformationRecord, Bist, Size);-- return EFI_SUCCESS;-}-diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/SecRamInitData.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/SecRamInitData.c
> deleted file mode 100644
> index 04f12a9438..0000000000
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/SecRamInitData.c
> +++ /dev/null
> @@ -1,37 +0,0 @@
> -/** @file- Provide TempRamInitParams data.--- Copyright (c) 2019, Intel
> Corporation. All rights reserved.<BR>- SPDX-License-Identifier:
> BSD-2-Clause-Patent-**/--#include <Library/PcdLib.h>-#include
> <FspEas.h>-#include "FsptCoreUpd.h"--typedef struct {- FSP_UPD_HEADER
> FspUpdHeader;- FSPT_CORE_UPD FsptCoreUpd;-}
> FSPT_UPD_CORE_DATA;--GLOBAL_REMOVE_IF_UNREFERENCED CONST
> FSPT_UPD_CORE_DATA FsptUpdDataPtr = {- {- 0x4450555F54505346,-
> 0x00,- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,-
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00- }- },- {-
> ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + FixedPcdGet32
> (PcdFlashMicrocodeOffset)),- ((UINT32)FixedPcdGet64
> (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet32
> (PcdFlashMicrocodeOffset)),- 0, // Set CodeRegionBase as 0,
> so that caching will be 4GB-(CodeRegionSize > LLCSize ? LLCSize :
> CodeRegionSize) will be used.- FixedPcdGet32 (PcdFlashCodeCacheSize),-
> { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,- 0x00,
> 0x00, 0x00, 0x00, 0x00, 0x00- }- }-};--diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/SecTempRamDone.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/SecTempRamDone.c
> deleted file mode 100644
> index 6d65d7d23f..0000000000
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/SecTempRamDone.c
> +++ /dev/null
> @@ -1,48 +0,0 @@
> -/** @file- Provide SecTemporaryRamDone function.--- Copyright (c) 2019,
> Intel Corporation. All rights reserved.<BR>- SPDX-License-Identifier:
> BSD-2-Clause-Patent-**/--#include <PiPei.h>--#include
> <Ppi/TemporaryRamDone.h>--#include <Library/BaseMemoryLib.h>-#include
> <Library/DebugLib.h>-#include <Library/PcdLib.h>-#include
> <Library/DebugAgentLib.h>-#include
> <Library/FspWrapperPlatformLib.h>-#include
> <Library/FspWrapperApiLib.h>-#include <Library/BoardInitLib.h>--/**-This
> interface disables temporary memory in SEC
> Phase.-**/-VOID-EFIAPI-SecPlatformDisableTemporaryMemory (-
> VOID- )-{- EFI_STATUS Status;- VOID
> *TempRamExitParam;-- DEBUG((DEBUG_INFO,
> "SecPlatformDisableTemporaryMemory enter\n"));-- Status =
> BoardInitBeforeTempRamExit ();- ASSERT_EFI_ERROR (Status);--
> TempRamExitParam = UpdateTempRamExitParam ();- Status =
> CallTempRamExit (TempRamExitParam);- DEBUG((DEBUG_INFO,
> "TempRamExit status: 0x%x\n", Status));- ASSERT_EFI_ERROR(Status);--
> Status = BoardInitAfterTempRamExit ();- ASSERT_EFI_ERROR (Status);--
> return ;-}-diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardP
> kg.dsc
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardP
> kg.dsc
> index 3cd0478021..127147c734 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardP
> kg.dsc
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardP
> k
> +++ g.dsc
> @@ -127,7 +127,7 @@
>
> GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpande
> rLib/BaseGpioExpanderLib.inf
> HdaVerbTableLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiHdaVerbTableLi
> b/PeiHdaVerbTableLib.inf
> I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cA
> ccessLib.inf-
> PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFsp
> WrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf+
> PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/SecFspWrapperPlatformSecLib.inf
> TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTim
> erLib.inf # Thunderbolt !if
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE--
> 2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 09/13] MinPlatformPkg: FSP Dispatch Mode Support for PlatformSecLib
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 09/13] MinPlatformPkg: FSP Dispatch Mode Support for PlatformSecLib Nate DeSimone
@ 2019-11-14 15:17 ` Chiu, Chasel
2019-11-16 2:54 ` Kubacki, Michael A
1 sibling, 0 replies; 44+ messages in thread
From: Chiu, Chasel @ 2019-11-14 15:17 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io
Cc: Kubacki, Michael A, Gao, Liming
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Thursday, November 14, 2019 2:07 PM
> To: devel@edk2.groups.io
> Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Chiu, Chasel
> <chasel.chiu@intel.com>; Gao, Liming <liming.gao@intel.com>
> Subject: [edk2-platforms] [PATCH V1 09/13] MinPlatformPkg: FSP Dispatch
> Mode Support for PlatformSecLib
>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../FspWrapperPlatformSecLib.c | 34 ++++++++++++---
> .../SecFspWrapperPlatformSecLib.inf | 7 +++-
> .../SecTempRamDone.c | 42
> +++++++++++++++----
> .../Intel/MinPlatformPkg/MinPlatformPkg.dec | 28 ++++++++++++-
> 4 files changed, 95 insertions(+), 16 deletions(-)
>
> diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/FspWrapperPlatformSecLib.c
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/FspWrapperPlatformSecLib.c
> index 303f3aac40..876c073fc4 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/FspWrapperPlatformSecLib.c
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/FspWrapperPlatformSecLib.c
> @@ -1,7 +1,7 @@
> /** @file Provide FSP wrapper platform sec related function. -Copyright
> (c) 2017, Intel Corporation. All rights reserved.<BR>+Copyright (c) 2017 - 2019,
> Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier:
> BSD-2-Clause-Patent **/@@ -12,6 +12,7 @@ SPDX-License-Identifier:
> BSD-2-Clause-Patent
> #include <Ppi/SecPerformance.h> #include <Ppi/FirmwareVolumeInfo.h>
> #include <Ppi/TopOfTemporaryRam.h>+#include <Ppi/PeiCoreFvLocation.h>
> #include <Guid/FirmwareFileSystem2.h> #include
> <Library/LocalApicLib.h>@@ -66,6 +67,18 @@ PEI_SEC_PERFORMANCE_PPI
> mSecPerformancePpi = {
> SecGetPerformance }; +EFI_PEI_CORE_FV_LOCATION_PPI
> mPeiCoreFvLocationPpi = {+ (VOID *) (UINTN) FixedPcdGet32
> (PcdFspmBaseAddress)+};++EFI_PEI_PPI_DESCRIPTOR
> mPeiCoreFvLocationPpiList[] = {+ {+ EFI_PEI_PPI_DESCRIPTOR_PPI,+
> &gEfiPeiCoreFvLocationPpiGuid,+ &mPeiCoreFvLocationPpi+ }+};+
> EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] =
> { { EFI_PEI_PPI_DESCRIPTOR_PPI,@@ -129,6 +142,8 @@
> SecPlatformMain (
> ) { EFI_PEI_PPI_DESCRIPTOR *PpiList;+ UINT8
> TopOfTemporaryRamPpiIndex;+ UINT8
> *CopyDestinationPointer; DEBUG ((DEBUG_INFO, "FSP Wrapper
> BootFirmwareVolumeBase - 0x%x\n",
> SecCoreData->BootFirmwareVolumeBase)); DEBUG ((DEBUG_INFO, "FSP
> Wrapper BootFirmwareVolumeSize - 0x%x\n",
> SecCoreData->BootFirmwareVolumeSize));@@ -150,13 +165,22 @@
> SecPlatformMain (
> // Use middle of Heap as temp buffer, it will be copied by caller. // Do
> not use Stack, because it will cause wrong calculation on stack by PeiCore
> //- PpiList = (VOID *)((UINTN)SecCoreData->PeiTemporaryRamBase +
> (UINTN)SecCoreData->PeiTemporaryRamSize/2);- CopyMem (PpiList,
> mPeiSecPlatformPpi, sizeof(mPeiSecPlatformPpi));-+ PpiList = (VOID
> *)((UINTN) SecCoreData->PeiTemporaryRamBase + (UINTN)
> SecCoreData->PeiTemporaryRamSize/2);+ CopyDestinationPointer = (UINT8
> *) PpiList;+ TopOfTemporaryRamPpiIndex = 0;+ if ((PcdGet8
> (PcdFspModeSelection) == 0) && PcdGetBool
> (PcdFspDispatchModeUseFspPeiMain)) {+ //+ // In Dispatch mode,
> wrapper should provide PeiCoreFvLocationPpi.+ //+ CopyMem
> (CopyDestinationPointer, mPeiCoreFvLocationPpiList, sizeof
> (mPeiCoreFvLocationPpiList));+ TopOfTemporaryRamPpiIndex = 1;+
> CopyDestinationPointer += sizeof (mPeiCoreFvLocationPpiList);+ }+
> CopyMem (CopyDestinationPointer, mPeiSecPlatformPpi,
> sizeof(mPeiSecPlatformPpi)); // // Patch TopOfTemporaryRamPpi //-
> PpiList[0].Ppi = (VOID *)((UINTN)SecCoreData->TemporaryRamBase +
> SecCoreData->TemporaryRamSize);+
> PpiList[TopOfTemporaryRamPpiIndex].Ppi = (VOID *)((UINTN)
> SecCoreData->TemporaryRamBase + SecCoreData->TemporaryRamSize);
> return PpiList; }diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecFspWrapperPlatformSecLib.inf
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecFspWrapperPlatformSecLib.inf
> index 3f5a63f273..02c720c73d 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecFspWrapperPlatformSecLib.inf
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/SecFspWrapperPlatformSecLib.inf
> @@ -72,18 +72,20 @@
> BoardInitLib SecBoardInitLib TestPointCheckLib+
> PeiServicesTablePointerLib [Ppis] gEfiSecPlatformInformationPpiGuid
> ## CONSUMES gPeiSecPerformancePpiGuid ##
> CONSUMES gTopOfTemporaryRamPpiGuid ## PRODUCES
> gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES+
> gFspTempRamExitPpiGuid ## CONSUMES [Pcd]
> gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize
> ## CONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress
> ## CONSUMES gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize
> ## CONSUMES-
> gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ##
> CONSUMES+
> gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable
> ## CONSUMES [FixedPcd]
> gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress
> ## CONSUMES@@ -91,3 +93,6 @@
> gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset
> ## CONSUMES
> gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress
> ## CONSUMES
> gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize
> ## CONSUMES+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress
> ## CONSUMES+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection
> ## CONSUMES+
> gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain
> ## CONSUMESdiff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecTempRamDone.c
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecTempRamDone.c
> index cde8a80a4e..922e4ec204 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecTempRamDone.c
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/SecTempRamDone.c
> @@ -1,7 +1,7 @@
> /** @file Provide SecTemporaryRamDone function. -Copyright (c) 2017,
> Intel Corporation. All rights reserved.<BR>+Copyright (c) 2017 - 2019, Intel
> Corporation. All rights reserved.<BR> SPDX-License-Identifier:
> BSD-2-Clause-Patent **/@@ -9,6 +9,7 @@ SPDX-License-Identifier:
> BSD-2-Clause-Patent
> #include <PiPei.h> #include <Ppi/TemporaryRamDone.h>+#include
> <Ppi/TempRamExitPpi.h> #include <Library/BaseMemoryLib.h> #include
> <Library/DebugLib.h>@@ -17,6 +18,7 @@ SPDX-License-Identifier:
> BSD-2-Clause-Patent #include <Library/FspWrapperPlatformLib.h> #include
> <Library/FspWrapperApiLib.h> #include <Library/BoardInitLib.h>+#include
> <Library/PeiServicesTablePointerLib.h> /** This interface disables
> temporary memory in SEC Phase.@@ -29,17 +31,41 @@
> SecPlatformDisableTemporaryMemory (
> { EFI_STATUS Status; VOID
> *TempRamExitParam;+ CONST EFI_PEI_SERVICES **PeiServices;+
> FSP_TEMP_RAM_EXIT_PPI *TempRamExitPpi;++ DEBUG
> ((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n")); -
> DEBUG((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n"));-
> Status = BoardInitBeforeTempRamExit (); ASSERT_EFI_ERROR (Status); -
> TempRamExitParam = UpdateTempRamExitParam ();- Status =
> CallTempRamExit (TempRamExitParam);- DEBUG((DEBUG_INFO,
> "TempRamExit status: 0x%x\n", Status));- ASSERT_EFI_ERROR(Status);- +
> if (PcdGet8 (PcdFspModeSelection) == 1) {+ //+ // FSP API mode+
> //+ TempRamExitParam = UpdateTempRamExitParam ();+ Status =
> CallTempRamExit (TempRamExitParam);+ DEBUG ((DEBUG_INFO,
> "TempRamExit status: 0x%x\n", Status));+ ASSERT_EFI_ERROR
> (Status);+ } else {+ //+ // FSP Dispatch mode+ //+
> PeiServices = GetPeiServicesTablePointer ();+ Status =
> (*PeiServices)->LocatePpi (+ PeiServices,+
> &gFspTempRamExitPpiGuid,+ 0,+
> NULL,+ (VOID **)
> &TempRamExitPpi+ );+
> ASSERT_EFI_ERROR (Status);+ if (EFI_ERROR (Status)) {+
> return;+ }+ TempRamExitPpi->TempRamExit (NULL);+ }+ Status =
> BoardInitAfterTempRamExit (); ASSERT_EFI_ERROR (Status); diff --git
> a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> index a851021c0b..856c17f737 100644
> --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> @@ -69,8 +69,6 @@ SetCacheMtrrLib|Include/Library/SetCacheMtrrLib.h
> [PcdsFixedAtBuild, PcdsPatchableInModule]
> -gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|FALSE|BOOLEA
> N|0x80000008-
> gMinPlatformPkgTokenSpaceGuid.PcdFspMaxUpdSize|0x00000000|UINT32|0
> x80000000
> gMinPlatformPkgTokenSpaceGuid.PcdFspReservedSizeOnStackTop|0x0000004
> 0|UINT32|0x80000001
> gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0x00000000|UINT32
> |0x80000002@@ -272,6 +270,32 @@
> gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UINT32|0x900000
> 19
> #
> gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4|UINT8|0xF00000A0 + ##
> FSP Boot Mode Selector+ # FALSE: The board is not a FSP wrapper (FSP
> binary not used)+ # TRUE: The board is a FSP wrapper (FSP binary is
> used)+ #+
> gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|FALSE|BOOLEA
> N|0x80000008++ ## FSP Dispatch Mode: Use the PEI Main Binary Included
> in FSP-M+ # FALSE: The PEI Main included in FvPreMemory is used to
> dispatch all PEIMs+ # (both inside FSP and outside FSP).+ #
> Pros:+ # * PEI Main is re-built from source and is always the
> latest version+ # * Platform code can link any desired
> LibraryClass to PEI Main+ # (Ex: Custom DebugLib instance,
> SerialPortLib, etc.)+ # Cons:+ # * The PEI Main being
> used to execute FSP PEIMs is not the PEI Main+ # that the
> FSP PEIMs were tested with, adding risk of breakage.+ # * Two
> copies of PEI Main will exist in the final binary,+ # #1 in
> FSP-M, #2 in FvPreMemory. The copy in FSP-M is never+ #
> executed, wasting space.+ #+ # <b>TRUE</b>: The PEI Main included in
> FSP is used to dispatch all PEIMs+ # (both inside FSP and outside
> FSP). PEI Main will not be included in+ # FvPreMemory. This is the
> default and is the recommended choice.+ #+
> gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE
> |BOOLEAN|0xF00000A8+ [PcdsFeatureFlag]
> gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit
> |FALSE|BOOLEAN|0xF00000A1--
> 2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 10/13] MinPlatformPkg: Coding style cleanups in MinPlatformPkg.dec
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 10/13] MinPlatformPkg: Coding style cleanups in MinPlatformPkg.dec Nate DeSimone
@ 2019-11-14 15:17 ` Chiu, Chasel
2019-11-16 2:54 ` Kubacki, Michael A
1 sibling, 0 replies; 44+ messages in thread
From: Chiu, Chasel @ 2019-11-14 15:17 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io
Cc: Kubacki, Michael A, Gao, Liming
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Thursday, November 14, 2019 2:07 PM
> To: devel@edk2.groups.io
> Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Chiu, Chasel
> <chasel.chiu@intel.com>; Gao, Liming <liming.gao@intel.com>
> Subject: [edk2-platforms] [PATCH V1 10/13] MinPlatformPkg: Coding style
> cleanups in MinPlatformPkg.dec
>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../Intel/MinPlatformPkg/MinPlatformPkg.dec | 281 +++++++++---------
> 1 file changed, 139 insertions(+), 142 deletions(-)
>
> diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> index 856c17f737..c6b5881646 100644
> --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> @@ -14,184 +14,182 @@
>
>
>
>
> [Defines]
>
> -DEC_SPECIFICATION = 0x00010017
>
> -PACKAGE_NAME = MinPlatformPkg
>
> -PACKAGE_VERSION = 0.1
>
> -PACKAGE_GUID = 463B3B00-0D18-4a5f-90C0-D5B851D2574B
>
> -
>
> + DEC_SPECIFICATION = 0x00010017
>
> + PACKAGE_NAME = MinPlatformPkg
>
> + PACKAGE_VERSION = 0.1
>
> + PACKAGE_GUID = 463B3B00-0D18-4a5f-90C0-D5B851D2574B
>
>
>
> [Includes]
>
> -Include
>
> + Include
>
>
>
> [Ppis]
>
> -gEdkiiSiliconInitializedPpiGuid = {0x82a72dc8, 0x61ec, 0x403e, {0xb1, 0x5a,
> 0x8d, 0x7a, 0x3a, 0x71, 0x84, 0x98}}
>
> + gEdkiiSiliconInitializedPpiGuid = {0x82a72dc8, 0x61ec, 0x403e, {0xb1,
> 0x5a, 0x8d, 0x7a, 0x3a, 0x71, 0x84, 0x98}}
>
>
>
> -gPeiBaseMemoryTestPpiGuid = { 0xb6ec423c, 0x21d2, 0x490d, { 0x85,
> 0xc6, 0xdd, 0x58, 0x64, 0xea, 0xa6, 0x74 } }
>
> -gPeiPlatformMemorySizePpiGuid = { 0x9a7ef41e, 0xc140, 0x4bd1, { 0xb8,
> 0x84, 0x1e, 0x11, 0x24, 0x0b, 0x4c, 0xe6 } }
>
> + gPeiBaseMemoryTestPpiGuid = {0xb6ec423c, 0x21d2, 0x490d,
> {0x85, 0xc6, 0xdd, 0x58, 0x64, 0xea, 0xa6, 0x74}}
>
> + gPeiPlatformMemorySizePpiGuid = {0x9a7ef41e, 0xc140, 0x4bd1,
> {0xb8, 0x84, 0x1e, 0x11, 0x24, 0x0b, 0x4c, 0xe6}}
>
>
>
> [Guids]
>
> -gMinPlatformPkgTokenSpaceGuid = {0x69d13bf0, 0xaf91, 0x4d96,
> {0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}}
>
> + gMinPlatformPkgTokenSpaceGuid = {0x69d13bf0, 0xaf91, 0x4d96,
> {0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}}
>
>
>
> -gAdapterInfoPlatformTestPointGuid = {0x5381e3ea, 0xb77, 0x4580, {0xad,
> 0xdf, 0xa9, 0x1c, 0x8, 0x3b, 0xf2, 0x97}}
>
> + gAdapterInfoPlatformTestPointGuid = {0x5381e3ea, 0x0b77, 0x4580,
> {0xad, 0xdf, 0xa9, 0x1c, 0x08, 0x3b, 0xf2, 0x97}}
>
>
>
> -gBoardDetectGuid = {0x1792429d, 0x9d94, 0x4e08, {0xa0, 0x99,
> 0x73, 0xa2, 0x86, 0xae, 0xb4, 0x35}}
>
> -gBoardPreMemInitGuid = {0x191dcfcf, 0xe16e, 0x43bb, {0x9b, 0xc3,
> 0x6e, 0xee, 0x6f, 0xab, 0x3a, 0x27}}
>
> -gBoardPostMemInitGuid = {0xa0e933ea, 0xa69, 0x47fb, {0xb2, 0xab,
> 0xa1, 0x6f, 0x71, 0x2d, 0x6f, 0x58}}
>
> -gBoardNotificationInitGuid = {0x78dbcabf, 0xc544, 0x4e6f, {0xaf, 0x3a, 0x71,
> 0x17, 0xd9, 0x42, 0x4e, 0xd1}}
>
> + gBoardDetectGuid = {0x1792429d, 0x9d94, 0x4e08,
> {0xa0, 0x99, 0x73, 0xa2, 0x86, 0xae, 0xb4, 0x35}}
>
> + gBoardPreMemInitGuid = {0x191dcfcf, 0xe16e, 0x43bb,
> {0x9b, 0xc3, 0x6e, 0xee, 0x6f, 0xab, 0x3a, 0x27}}
>
> + gBoardPostMemInitGuid = {0xa0e933ea, 0xa69, 0x47fb,
> {0xb2, 0xab, 0xa1, 0x6f, 0x71, 0x2d, 0x6f, 0x58}}
>
> + gBoardNotificationInitGuid = {0x78dbcabf, 0xc544, 0x4e6f, {0xaf,
> 0x3a, 0x71, 0x17, 0xd9, 0x42, 0x4e, 0xd1}}
>
>
>
> -gBoardAcpiTableGuid = {0xd70e9f57, 0x69f, 0x4bef, {0x96, 0xc0,
> 0x84, 0x74, 0xf4, 0xa2, 0x5f, 0x3a}}
>
> -gBoardAcpiEnableGuid = {0x9727b610, 0xf645, 0x4429, {0x89, 0x21,
> 0x2c, 0x2b, 0x58, 0xdc, 0xbb, 0xa}}
>
> + gBoardAcpiTableGuid = {0xd70e9f57, 0x69f, 0x4bef,
> {0x96, 0xc0, 0x84, 0x74, 0xf4, 0xa2, 0x5f, 0x3a}}
>
> + gBoardAcpiEnableGuid = {0x9727b610, 0xf645, 0x4429,
> {0x89, 0x21, 0x2c, 0x2b, 0x58, 0xdc, 0xbb, 0x0a}}
>
>
>
> -gDefaultDataFileGuid = { 0x1ae42876, 0x008f,
> 0x4161, { 0xb2, 0xb7, 0x1c, 0x0d, 0x15, 0xc5, 0xef, 0x43 }}
>
> -gDefaultDataOptSizeFileGuid = { 0x003e7b41, 0x98a2,
> 0x4be2, { 0xb2, 0x7a, 0x6c, 0x30, 0xc7, 0x65, 0x52, 0x25 }}
>
> + gDefaultDataFileGuid = {0x1ae42876, 0x008f, 0x4161,
> {0xb2, 0xb7, 0x1c, 0x0d, 0x15, 0xc5, 0xef, 0x43}}
>
> + gDefaultDataOptSizeFileGuid = {0x003e7b41, 0x98a2, 0x4be2,
> {0xb2, 0x7a, 0x6c, 0x30, 0xc7, 0x65, 0x52, 0x25}}
>
>
>
> [LibraryClasses]
>
>
>
> -PeiLib|Include/Library/PeiLib.h
>
> + PeiLib|Include/Library/PeiLib.h
>
>
>
> -AslUpdateLib|Include/Library/AslUpdateLib.h
>
> -BoardAcpiEnableLib|Include/Library/BoardAcpiEnableLib.h
>
> -BoardAcpiTableLib|Include/Library/BoardAcpiTableLib.h
>
> + AslUpdateLib|Include/Library/AslUpdateLib.h
>
> + BoardAcpiEnableLib|Include/Library/BoardAcpiEnableLib.h
>
> + BoardAcpiTableLib|Include/Library/BoardAcpiTableLib.h
>
>
>
> -SiliconPolicyInitLib|Include/Library/SiliconPolicyInitLib.h
>
> -SiliconPolicyUpdateLib|Include/Library/SiliconPolicyUpdateLib.h
>
> + SiliconPolicyInitLib|Include/Library/SiliconPolicyInitLib.h
>
> + SiliconPolicyUpdateLib|Include/Library/SiliconPolicyUpdateLib.h
>
>
>
> -SpiFlashCommonLib|Include/Library/SpiFlashCommonLib.h
>
> + SpiFlashCommonLib|Include/Library/SpiFlashCommonLib.h
>
>
>
> -BoardInitLib|Include/Library/BoardInitLib.h
>
> -MultiBoardInitSupportLib|Include/Library/MultiBoardInitSupportLib.h
>
> -SecBoardInitLib|Include/Library/SecBoardInitLib.h
>
> + BoardInitLib|Include/Library/BoardInitLib.h
>
> + MultiBoardInitSupportLib|Include/Library/MultiBoardInitSupportLib.h
>
> + SecBoardInitLib|Include/Library/SecBoardInitLib.h
>
>
>
> -TestPointLib|Include/Library/TestPointLib.h
>
> -TestPointCheckLib|Include/Library/TestPointCheckLib.h
>
> + TestPointLib|Include/Library/TestPointLib.h
>
> + TestPointCheckLib|Include/Library/TestPointCheckLib.h
>
>
>
> SetCacheMtrrLib|Include/Library/SetCacheMtrrLib.h
>
>
>
> [PcdsFixedAtBuild, PcdsPatchableInModule]
>
>
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFspMaxUpdSize|0x00000000|UINT32|
> 0x80000000
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFspReservedSizeOnStackTop|0x000000
> 40|UINT32|0x80000001
>
> -gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0x00000000|UINT32
> |0x80000002
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFspMaxUpdSize|0x00000000|UINT32|0
> x80000000
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFspReservedSizeOnStackTop|0x0000004
> 0|UINT32|0x80000001
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0x00000000|UINT32
> |0x80000002
>
>
>
> -gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000|UINT32
> |0x9000000B
>
> -gMinPlatformPkgTokenSpaceGuid.PcdLocalApicMmioSize|0x1000|UINT32|0x
> 9000000C
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000|UINT32
> |0x9000000B
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdLocalApicMmioSize|0x1000|UINT32|0x
> 9000000C
>
>
>
> -gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress|0xFEC00000|UINT32|0
> x9000000D
>
> -gMinPlatformPkgTokenSpaceGuid.PcdIoApicMmioSize|0x1000|UINT32|0x90
> 00000E
>
> -gMinPlatformPkgTokenSpaceGuid.PcdIoApicId|0x02|UINT8|0x90000014
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress|0xFEC00000|UINT32|0x
> 9000000D
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdIoApicMmioSize|0x1000|UINT32|0x900
> 0000E
>
> + gMinPlatformPkgTokenSpaceGuid.PcdIoApicId|0x02|UINT8|0x90000014
>
>
>
> -gMinPlatformPkgTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x9000
> 0012
>
> -gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x900
> 00013
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x9000
> 0012
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x9000
> 0013
>
>
>
> -gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|0|UINT8|0x90000015
>
> -gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase|0x09|UINT8|0x900000
> 16
>
> -gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000|UIN
> T32|0x90000017
>
> -gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicInterruptBase|24|UINT32|0x9
> 0000018
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|0|UINT8|0x90000015
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase|0x09|UINT8|0x900000
> 16
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000|UIN
> T32|0x90000017
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicInterruptBase|24|UINT32|0x90
> 000018
>
>
>
> -gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2|UINT32|0x900
> 00021
>
> -gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8|UINT32|0x90000
> 022
>
> -gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|4|UINT32|0x900
> 00023
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2|UINT32|0x900
> 00021
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8|UINT32|0x90000
> 022
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|4|UINT32|0x9000
> 0023
>
>
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x02|UINT8|0
> x90000025
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0001|UINT16|0x9
> 0000026
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000086A5|UINT32|0x900
> 00027
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x02|UINT8|0
> x90000025
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0001|UINT16|0x9
> 0000026
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000086A5|UINT32|0x9000
> 0027
>
>
>
> -gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0x
> 65|UINT32|0x20000500
>
> -gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0x30|
> UINT32|0x20000501
>
> -gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x40
> 2|UINT32|0x20000502
>
> -gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b|UI
> NT32|0x20000503
>
> -gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x25|U
> INT32|0x20000504
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0x
> 65|UINT32|0x20000500
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0x30|U
> INT32|0x20000501
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402
> |UINT32|0x20000502
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b|UI
> NT32|0x20000503
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x25|UI
> NT32|0x20000504
>
>
>
> -#
>
> -# The PCDs are used to control the Windows SMM Security Mitigations
> Table - Protection Flags
>
> -#
>
> -# BIT0: If set, expresses that for all synchronous SMM entries,SMM will
> validate that input and output buffers lie entirely within the expected fixed
> memory regions.
>
> -# BIT1: If set, expresses that for all synchronous SMM entries, SMM will
> validate that input and output pointers embedded within the fixed
> communication buffer only refer to address ranges \
>
> -# that lie entirely within the expected fixed memory regions.
>
> -# BIT2: Firmware setting this bit is an indication that it will not allow
> reconfiguration of system resources via non-architectural mechanisms.
>
> -# BIT3-31: Reserved
>
> -#
>
> -gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0|UINT32|0x100
> 01006
>
> + #
>
> + # The PCDs are used to control the Windows SMM Security Mitigations
> Table - Protection Flags
>
> + #
>
> + # BIT0: If set, expresses that for all synchronous SMM entries,SMM will
> validate that input and output buffers lie entirely within the expected fixed
> memory regions.
>
> + # BIT1: If set, expresses that for all synchronous SMM entries, SMM will
> validate that input and output pointers embedded within the fixed
> communication buffer only refer to address ranges \
>
> + # that lie entirely within the expected fixed memory regions.
>
> + # BIT2: Firmware setting this bit is an indication that it will not allow
> reconfiguration of system resources via non-architectural mechanisms.
>
> + # BIT3-31: Reserved
>
> + #
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0|UINT32|0x100
> 01006
>
>
>
> -gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable|TRUE|BOO
> LEAN|0x00100206
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable|TRUE|BOOL
> EAN|0x00100206
>
>
>
> -#
>
> -# See HstiIbvFeatureBit.h for the definition
>
> -#
>
> -# #define HSTI_BYTE<X>_<AAA> BIT<Y>
>
> -#
>
> -# It means BYTE<X> BIT<Y> is for feature <AAA>.
>
> -#
>
> -gMinPlatformPkgTokenSpaceGuid.PcdHstiIbvPlatformFeature|{0x00, 0x00,
> 0x00}|VOID*|0x00100301
>
> + #
>
> + # See HstiIbvFeatureBit.h for the definition
>
> + #
>
> + # #define HSTI_BYTE<X>_<AAA> BIT<Y>
>
> + #
>
> + # It means BYTE<X> BIT<Y> is for feature <AAA>.
>
> + #
>
> + gMinPlatformPkgTokenSpaceGuid.PcdHstiIbvPlatformFeature|{0x00, 0x00,
> 0x00}|VOID*|0x00100301
>
>
>
> -#
>
> -# See TestPointCheckLib.h for the definition
>
> -#
>
> -# #define TEST_POINT_BYTE<X>_<AAA> BIT<Y>
>
> -#
>
> -# It means BYTE<X> BIT<Y> is for feature <AAA>.
>
> -#
> BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 BYTE8
>
> -# Stage debug:
> {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00}
>
> -# Stage memory:
> {0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00}
>
> -# Stage UEFI boot:
> {0x03, 0x07, 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00}
>
> -# Stage OS boot:
> {0x03, 0x07, 0x03, 0x05, 0x3F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00}
>
> -# Stage Secure boot:
> {0x03, 0x0F, 0x03, 0x1D, 0x3F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00}
>
> -# Stage Advanced:
> {0x03, 0x0F, 0x03, 0x1D, 0x3F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00}
>
> -gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03,
> 0x0F, 0x03, 0x1D, 0x3F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00}|VOID*|0x00100302
>
> + #
>
> + # See TestPointCheckLib.h for the definition
>
> + #
>
> + # #define TEST_POINT_BYTE<X>_<AAA> BIT<Y>
>
> + #
>
> + # It means BYTE<X> BIT<Y> is for feature <AAA>.
>
> + #
> BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 BYTE8
>
> + # Stage debug:
> {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00}
>
> + # Stage memory:
> {0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00}
>
> + # Stage UEFI boot:
> {0x03, 0x07, 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00}
>
> + # Stage OS boot:
> {0x03, 0x07, 0x03, 0x05, 0x3F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00}
>
> + # Stage Secure boot:
> {0x03, 0x0F, 0x03, 0x1D, 0x3F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00}
>
> + # Stage Advanced:
> {0x03, 0x0F, 0x03, 0x1D, 0x3F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00}
>
> + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03,
> 0x0F, 0x03, 0x1D, 0x3F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00}|VOID*|0x00100302
>
>
>
> -[PcdsFixedAtBuild, PcdsPatchableInModule]
>
> -##
>
> -## The Flash relevant PCD are ineffective and will be patched basing on FDF
> definitions during build.
>
> -## Set all of them to 0 here to prevent from confusion.
>
> -##
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFF800000|UI
> NT32|0x10000001
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize|0x00800000|UINT32|0x
> 10000002
>
> -
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0xFFE60000|UI
> NT32|0x30000004
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x000A0000|UI
> NT32|0x30000005
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset|0x00660000|
> UINT32|0x30000006
>
> -
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|0x00000000|
> UINT32|0x20000004
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize|0x00000000|UI
> NT32|0x20000005
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|0x00000000
> |UINT32|0x20000006
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|0x00000000|
> UINT32|0x20000007
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize|0x00000000|
> UINT32|0x20000008
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|0x0000000
> 0|UINT32|0x20000009
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|0x00000000|UIN
> T32|0x2000000A
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize|0x00000000|UINT
> 32|0x2000000B
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|0x00000000|UI
> NT32|0x2000000C
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|0x00000000|UINT
> 32|0x2000000D
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize|0x00000000|UINT3
> 2|0x2000000E
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|0x00000000|UIN
> T32|0x2000000F
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|0x00000000|UINT
> 32|0x20000010
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize|0x00000000|UINT
> 32|0x20000011
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|0x00000000|UI
> NT32|0x20000012
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|0x00000000|UI
> NT32|0x20000013
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize|0x00000000|UIN
> T32|0x20000014
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|0x00000000|U
> INT32|0x20000015
>
> -
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageBase|0x00000000|UIN
> T32|0x20000016
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize|0x00000000|UINT
> 32|0x20000017
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset|0x00000000|UI
> NT32|0x20000018
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|0x00000
> 000|UINT32|0x20000019
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|0x0000
> 0000|UINT32|0x2000001A
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|0x0
> 0000000|UINT32|0x2000001B
>
> -
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|0x00000000|UINT32
> |0x20000021
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize|0x00000000|UINT32|
> 0x20000022
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|0x00000000|UINT3
> 2|0x20000023
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|0x00000000|UINT32
> |0x20000024
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize|0x00000000|UINT32|
> 0x20000025
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|0x00000000|UINT3
> 2|0x20000026
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|0x00000000|UINT32|
> 0x20000027
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize|0x00000000|UINT32|
> 0x20000028
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|0x00000000|UINT3
> 2|0x20000029
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUBase|0x00000000|UINT32
> |0x2000002A
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUSize|0x00000000|UINT32|
> 0x2000002B
>
> -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUOffset|0x00000000|UINT3
> 2|0x2000002C
>
> + ##
>
> + ## The Flash relevant PCD are ineffective and will be patched basing on
> FDF definitions during build.
>
> + ## Set all of them to 0 here to prevent from confusion.
>
> + ##
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFF800000|UI
> NT32|0x10000001
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize|0x00800000|UINT32|0x1
> 0000002
>
> +
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0xFFE60000|UI
> NT32|0x30000004
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x000A0000|UIN
> T32|0x30000005
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset|0x00660000|U
> INT32|0x30000006
>
> +
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|0x00000000|U
> INT32|0x20000004
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize|0x00000000|UI
> NT32|0x20000005
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|0x00000000|
> UINT32|0x20000006
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|0x00000000|
> UINT32|0x20000007
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize|0x00000000|U
> INT32|0x20000008
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|0x00000000
> |UINT32|0x20000009
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|0x00000000|UIN
> T32|0x2000000A
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize|0x00000000|UINT
> 32|0x2000000B
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|0x00000000|UI
> NT32|0x2000000C
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|0x00000000|UINT3
> 2|0x2000000D
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize|0x00000000|UINT3
> 2|0x2000000E
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|0x00000000|UINT
> 32|0x2000000F
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|0x00000000|UINT
> 32|0x20000010
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize|0x00000000|UINT3
> 2|0x20000011
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|0x00000000|UIN
> T32|0x20000012
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|0x00000000|UIN
> T32|0x20000013
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize|0x00000000|UIN
> T32|0x20000014
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|0x00000000|UI
> NT32|0x20000015
>
> +
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageBase|0x00000000|UINT
> 32|0x20000016
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize|0x00000000|UINT3
> 2|0x20000017
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset|0x00000000|UIN
> T32|0x20000018
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|0x00000
> 000|UINT32|0x20000019
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|0x0000
> 0000|UINT32|0x2000001A
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|0x00
> 000000|UINT32|0x2000001B
>
> +
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|0x00000000|UINT32|
> 0x20000021
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize|0x00000000|UINT32|0
> x20000022
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|0x00000000|UINT32
> |0x20000023
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|0x00000000|UINT32
> |0x20000024
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize|0x00000000|UINT32|
> 0x20000025
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|0x00000000|UINT3
> 2|0x20000026
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|0x00000000|UINT32|
> 0x20000027
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize|0x00000000|UINT32|0
> x20000028
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|0x00000000|UINT32
> |0x20000029
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUBase|0x00000000|UINT32|
> 0x2000002A
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUSize|0x00000000|UINT32|0
> x2000002B
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUOffset|0x00000000|UINT32
> |0x2000002C
>
>
>
> [PcdsDynamic, PcdsDynamicEx]
>
> -gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UINT32|0x900000
> 19
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UINT32|0x900000
> 19
>
>
>
> [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
>
>
>
> @@ -261,7 +259,7 @@
> gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UINT32|0x900000
> 19
>
>
> [PcdsFixedAtBuild]
>
>
>
> - #
>
> + ## MinPlatform Boot Stage Selector
>
> # Stage 1 - enable debug (system deadloop after debug init)
>
> # Stage 2 - mem init (system deadloop after mem init)
>
> # Stage 3 - boot to shell only
>
> @@ -305,4 +303,3 @@
> gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UINT32|0x900000
> 19
> gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable
> |FALSE|BOOLEAN|0xF00000A5
>
>
> gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE|BOOLE
> AN|0xF00000A6
>
> gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable
> |FALSE|BOOLEAN|0xF00000A7
>
> -
>
> --
> 2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 11/13] KabylakeOpenBoardPkg: Add support for PcdFspDispatchModeUseFspPeiMain
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 11/13] KabylakeOpenBoardPkg: Add support for PcdFspDispatchModeUseFspPeiMain Nate DeSimone
@ 2019-11-14 15:18 ` Chiu, Chasel
2019-11-16 2:54 ` Kubacki, Michael A
1 sibling, 0 replies; 44+ messages in thread
From: Chiu, Chasel @ 2019-11-14 15:18 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io; +Cc: Kubacki, Michael A
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Thursday, November 14, 2019 2:07 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>
> Subject: [edk2-platforms] [PATCH V1 11/13] KabylakeOpenBoardPkg: Add
> support for PcdFspDispatchModeUseFspPeiMain
>
> If PcdFspDispatchModeUseFspPeiMain is FALSE, then the BoardPkg should
> include PeiMain in FvPreMemory.
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../KabylakeRvp3/OpenBoardPkg.fdf | 5 +++--
> .../KabylakeRvp3/OpenBoardPkgPcd.dsc | 20
> +++++++++++++++++++
> 2 files changed, 23 insertions(+), 2 deletions(-)
>
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> index 98eb7dcb5a..3b3b153b68 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> +++
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> @@ -229,10 +229,11 @@ READ_LOCK_STATUS = TRUE
> FvNameGuid = FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D INF
> UefiCpuPkg/SecCore/SecCore.inf-!if
> (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) ||
> (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)+!if
> (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) ||
> (gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain ==
> FALSE) || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1) #
> # PeiMain is needed only for FSP API mode or EDK2 build,-# in FSP dispatch
> mode the one inside FSP Binary is launched.+# in FSP dispatch mode the one
> inside FSP Binary is launched+# unless requested otherwise
> (PcdFspDispatchModeUseFspPeiMain == FALSE). # INF
> MdeModulePkg/Core/Pei/PeiMain.inf !endifdiff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d
> sc
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d
> sc
> index 580504cbc1..5474edd01c 100644
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d
> sc
> +++
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d
> +++ sc
> @@ -39,6 +39,26 @@
> # gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE +
> #+ # FALSE: The PEI Main included in FvPreMemory is used to dispatch all
> PEIMs+ # (both inside FSP and outside FSP).+ # Pros:+
> # * PEI Main is re-built from source and is always the latest
> version+ # * Platform code can link any desired LibraryClass to
> PEI Main+ # (Ex: Custom DebugLib instance, SerialPortLib,
> etc.)+ # Cons:+ # * The PEI Main being used to
> execute FSP PEIMs is not the PEI Main+ # that the FSP PEIMs
> were tested with, adding risk of breakage.+ # * Two copies of
> PEI Main will exist in the final binary,+ # #1 in FSP-M, #2 in
> FvPreMemory. The copy in FSP-M is never+ # executed,
> wasting space.+ #+ # <b>TRUE</b>: The PEI Main included in FSP is
> used to dispatch all PEIMs+ # (both inside FSP and outside FSP).
> PEI Main will not be included in+ # FvPreMemory. This is the
> default and is the recommended choice.+ #+
> gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE
> + # # FSP Base address PCD will be updated in FDF basing on flash map.
> #--
> 2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 12/13] KabylakeOpenBoardPkg: Remove SecFspWrapperPlatformSecLib override
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 12/13] KabylakeOpenBoardPkg: Remove SecFspWrapperPlatformSecLib override Nate DeSimone
@ 2019-11-14 15:18 ` Chiu, Chasel
2019-11-16 2:54 ` Kubacki, Michael A
1 sibling, 0 replies; 44+ messages in thread
From: Chiu, Chasel @ 2019-11-14 15:18 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io
Cc: Kubacki, Michael A, Jeremy Soller
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Thursday, November 14, 2019 2:07 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>; Jeremy Soller <jeremy@system76.com>
> Subject: [edk2-platforms] [PATCH V1 12/13] KabylakeOpenBoardPkg: Remove
> SecFspWrapperPlatformSecLib override
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Jeremy Soller <jeremy@system76.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../FspWrapperPlatformSecLib.c | 186 ---------
> .../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 40 --
> .../SecFspWrapperPlatformSecLib/Ia32/Fsp.h | 42 --
> .../Ia32/PeiCoreEntry.nasm | 130 -------
> .../Ia32/SecEntry.nasm | 361 ------------------
> .../Ia32/Stack.nasm | 72 ----
> .../PlatformInit.c | 47 ---
> .../SecFspWrapperPlatformSecLib.inf | 97 -----
> .../SecGetPerformance.c | 89 -----
> .../SecPlatformInformation.c | 78 ----
> .../SecRamInitData.c | 36 --
> .../SecTempRamDone.c | 73 ----
> .../GalagoPro3/OpenBoardPkg.dsc | 2 +-
> .../KabylakeRvp3/OpenBoardPkg.dsc | 2 +-
> 14 files changed, 2 insertions(+), 1253 deletions(-) delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP
> latformSecLib/FspWrapperPlatformSecLib.c
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP
> latformSecLib/FsptCoreUpd.h
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP
> latformSecLib/Ia32/Fsp.h
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP
> latformSecLib/Ia32/PeiCoreEntry.nasm
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP
> latformSecLib/Ia32/SecEntry.nasm
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP
> latformSecLib/Ia32/Stack.nasm
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP
> latformSecLib/PlatformInit.c
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP
> latformSecLib/SecFspWrapperPlatformSecLib.inf
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP
> latformSecLib/SecGetPerformance.c
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP
> latformSecLib/SecPlatformInformation.c
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP
> latformSecLib/SecRamInitData.c
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP
> latformSecLib/SecTempRamDone.c
>
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/FspWrapperPlatformSecLib.c
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/FspWrapperPlatformSecLib.c
> deleted file mode 100644
> index d40eecae95..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/FspWrapperPlatformSecLib.c
> +++ /dev/null
> @@ -1,186 +0,0 @@
> -/** @file- Provide FSP wrapper platform sec related function.--Copyright (c)
> 2017 - 2019, Intel Corporation. All rights
> reserved.<BR>-SPDX-License-Identifier: BSD-2-Clause-Patent--**/--#include
> <PiPei.h>--#include <Ppi/SecPlatformInformation.h>-#include
> <Ppi/SecPerformance.h>-#include <Ppi/FirmwareVolumeInfo.h>-#include
> <Ppi/TopOfTemporaryRam.h>-#include <Ppi/PeiCoreFvLocation.h>-#include
> <Guid/FirmwareFileSystem2.h>--#include <Library/LocalApicLib.h>-#include
> <Library/BaseMemoryLib.h>-#include <Library/DebugLib.h>-#include
> <Library/IoLib.h>--/**- This interface conveys state information out of the
> Security (SEC) phase into PEI.-- @param[in] PeiServices
> Pointer to the PEI Services Table.- @param[in,out] StructureSize
> Pointer to the variable describing size of the input buffer.- @param[out]
> PlatformInformationRecord Pointer to the
> EFI_SEC_PLATFORM_INFORMATION_RECORD.-- @retval EFI_SUCCESS
> The data was successfully returned.- @retval EFI_BUFFER_TOO_SMALL
> The buffer was too small.--**/-EFI_STATUS-EFIAPI-SecPlatformInformation (-
> IN CONST EFI_PEI_SERVICES **PeiServices,- IN OUT
> UINT64 *StructureSize,- OUT
> EFI_SEC_PLATFORM_INFORMATION_RECORD
> *PlatformInformationRecord- );--/**- This interface conveys performance
> information out of the Security (SEC) phase into PEI.-- This service is
> published by the SEC phase. The SEC phase handoff has an optional-
> EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed
> from SEC into the- PEI Foundation. As such, if the platform supports
> collecting performance data in SEC,- this information is encapsulated into
> the data structure abstracted by this service.- This information is collected
> for the boot-strap processor (BSP) on IA-32.-- @param[in] PeiServices
> The pointer to the PEI Services Table.- @param[in] This The
> pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.- @param[out]
> Performance The pointer to performance data collected in SEC phase.--
> @retval EFI_SUCCESS The data was successfully
> returned.--**/-EFI_STATUS-EFIAPI-SecGetPerformance (- IN CONST
> EFI_PEI_SERVICES **PeiServices,- IN
> PEI_SEC_PERFORMANCE_PPI *This,- OUT
> FIRMWARE_SEC_PERFORMANCE
> *Performance- );--PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi = {-
> SecGetPerformance-};--EFI_PEI_CORE_FV_LOCATION_PPI
> mPeiCoreFvLocationPpi = {- (VOID *) (UINTN) FixedPcdGet32
> (PcdFspmBaseAddress)-};--EFI_PEI_PPI_DESCRIPTOR
> mPeiCoreFvLocationPpiList[] = {- {- EFI_PEI_PPI_DESCRIPTOR_PPI,-
> &gEfiPeiCoreFvLocationPpiGuid,-
> &mPeiCoreFvLocationPpi- }-};--EFI_PEI_PPI_DESCRIPTOR
> mPeiSecPlatformPpi[] = {- {- EFI_PEI_PPI_DESCRIPTOR_PPI,-
> &gTopOfTemporaryRamPpiGuid,- NULL // To be patched later.- },- {-
> EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,-
> &gPeiSecPerformancePpiGuid,- &mSecPerformancePpi- },-};--#define
> LEGACY_8259_MASK_REGISTER_MASTER 0x21-#define
> LEGACY_8259_MASK_REGISTER_SLAVE 0xA1-#define
> LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER 0x4D0-#define
> LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE 0x4D1--/**-
> Write to mask and edge/level triggered registers of master and slave 8259
> PICs.-- @param[in] Mask low byte for master PIC mask register,-
> high byte for slave PIC mask register.- @param[in] EdgeLevel low byte
> for master PIC edge/level triggered register,-
> high byte for slave PIC edge/level triggered
> register.--**/-VOID-Interrupt8259WriteMask (- IN UINT16 Mask,- IN
> UINT16 EdgeLevel- )-{- IoWrite8
> (LEGACY_8259_MASK_REGISTER_MASTER, (UINT8) Mask);- IoWrite8
> (LEGACY_8259_MASK_REGISTER_SLAVE, (UINT8) (Mask >> 8));- IoWrite8
> (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER, (UINT8)
> EdgeLevel);- IoWrite8
> (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE, (UINT8)
> (EdgeLevel >> 8));-}--/**- A developer supplied function to perform
> platform specific operations.-- It's a developer supplied function to
> perform any operations appropriate to a- given platform. It's invoked just
> before passing control to PEI core by SEC- core. Platform developer may
> modify the SecCoreData passed to PEI Core.- It returns a platform specific
> PPI list that platform wishes to pass to PEI core.- The Generic SEC core
> module will merge this list to join the final list passed to- PEI core.--
> @param[in,out] SecCoreData The same parameter as passing to
> PEI core. It- could be
> overridden by this function.-- @return The platform specific PPI list to be
> passed to PEI core or- NULL if there is no need of such platform
> specific PPI list.--**/-EFI_PEI_PPI_DESCRIPTOR *-EFIAPI-SecPlatformMain (-
> IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData- )-{-
> EFI_PEI_PPI_DESCRIPTOR *PpiList;- UINT8
> TopOfTemporaryRamPpiIndex;- UINT8
> *CopyDestinationPointer;-- DEBUG ((DEBUG_INFO, "FSP Wrapper
> BootFirmwareVolumeBase - 0x%x\n",
> SecCoreData->BootFirmwareVolumeBase));- DEBUG ((DEBUG_INFO, "FSP
> Wrapper BootFirmwareVolumeSize - 0x%x\n",
> SecCoreData->BootFirmwareVolumeSize));- DEBUG ((DEBUG_INFO, "FSP
> Wrapper TemporaryRamBase - 0x%x\n",
> SecCoreData->TemporaryRamBase));- DEBUG ((DEBUG_INFO, "FSP Wrapper
> TemporaryRamSize - 0x%x\n", SecCoreData->TemporaryRamSize));-
> DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamBase - 0x%x\n",
> SecCoreData->PeiTemporaryRamBase));- DEBUG ((DEBUG_INFO, "FSP
> Wrapper PeiTemporaryRamSize - 0x%x\n",
> SecCoreData->PeiTemporaryRamSize));- DEBUG ((DEBUG_INFO, "FSP
> Wrapper StackBase - 0x%x\n", SecCoreData->StackBase));-
> DEBUG ((DEBUG_INFO, "FSP Wrapper StackSize - 0x%x\n",
> SecCoreData->StackSize));-- InitializeApicTimer (0, (UINT32) -1, TRUE, 5);--
> //- // Set all 8259 interrupts to edge triggered and disabled- //-
> Interrupt8259WriteMask (0xFFFF, 0x0000);-- //- // Use middle of Heap as
> temp buffer, it will be copied by caller.- // Do not use Stack, because it will
> cause wrong calculation on stack by PeiCore- //- PpiList = (VOID *)((UINTN)
> SecCoreData->PeiTemporaryRamBase + (UINTN)
> SecCoreData->PeiTemporaryRamSize/2);- CopyDestinationPointer = (UINT8
> *) PpiList;- TopOfTemporaryRamPpiIndex = 0;- if (PcdGet8
> (PcdFspModeSelection) == 0) {- //- // In Dispatch mode, wrapper
> should provide PeiCoreFvLocationPpi.- //- CopyMem
> (CopyDestinationPointer, mPeiCoreFvLocationPpiList, sizeof
> (mPeiCoreFvLocationPpiList));- TopOfTemporaryRamPpiIndex = 1;-
> CopyDestinationPointer += sizeof (mPeiCoreFvLocationPpiList);- }-
> CopyMem (CopyDestinationPointer, mPeiSecPlatformPpi,
> sizeof(mPeiSecPlatformPpi));- //- // Patch TopOfTemporaryRamPpi- //-
> PpiList[TopOfTemporaryRamPpiIndex].Ppi = (VOID *)((UINTN)
> SecCoreData->TemporaryRamBase + SecCoreData->TemporaryRamSize);--
> return PpiList;-}diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/FsptCoreUpd.h
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/FsptCoreUpd.h
> deleted file mode 100644
> index 7c0f605b92..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/FsptCoreUpd.h
> +++ /dev/null
> @@ -1,40 +0,0 @@
> -/** @file--Copyright (c) 2017, Intel Corporation. All rights
> reserved.<BR>-SPDX-License-Identifier: BSD-2-Clause-Patent--**/--#ifndef
> __FSPT_CORE_UPD_H__-#define __FSPT_CORE_UPD_H__--#pragma
> pack(1)--/** Fsp T Core UPD-**/-typedef struct {--/** Offset 0x0020-**/-
> UINT32 MicrocodeRegionBase;--/** Offset
> 0x0024-**/- UINT32 MicrocodeRegionSize;--/**
> Offset 0x0028-**/- UINT32 CodeRegionBase;--/**
> Offset 0x002C-**/- UINT32 CodeRegionSize;--/**
> Offset 0x0030-**/- UINT8 Reserved[16];-}
> FSPT_CORE_UPD;--#pragma pack()--#endifdiff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/Ia32/Fsp.h
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/Ia32/Fsp.h
> deleted file mode 100644
> index 9f6cdcf476..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/Ia32/Fsp.h
> +++ /dev/null
> @@ -1,42 +0,0 @@
> -/** @file- Fsp related definitions--Copyright (c) 2017, Intel Corporation. All
> rights reserved.<BR>-SPDX-License-Identifier:
> BSD-2-Clause-Patent--**/--#ifndef __FSP_H__-#define __FSP_H__--//-// Fv
> Header-//-#define FVH_SIGINATURE_OFFSET 0x28-#define
> FVH_SIGINATURE_VALID_VALUE 0x4856465F // valid
> signature:_FVH-#define FVH_HEADER_LENGTH_OFFSET 0x30-#define
> FVH_EXTHEADER_OFFSET_OFFSET 0x34-#define
> FVH_EXTHEADER_SIZE_OFFSET 0x10--//-// Ffs Header-//-#define
> FSP_HEADER_GUID_DWORD1 0x912740BE-#define
> FSP_HEADER_GUID_DWORD2 0x47342284-#define
> FSP_HEADER_GUID_DWORD3 0xB08471B9-#define
> FSP_HEADER_GUID_DWORD4 0x0C3F3527-#define
> FFS_HEADER_SIZE_VALUE 0x18--//-// Section Header-//-#define
> SECTION_HEADER_TYPE_OFFSET 0x03-#define
> RAW_SECTION_HEADER_SIZE_VALUE 0x04--//-// Fsp Header-//-#define
> FSP_HEADER_IMAGEBASE_OFFSET 0x1C-#define
> FSP_HEADER_TEMPRAMINIT_OFFSET 0x30--#endifdiff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/Ia32/PeiCoreEntry.nasm
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/Ia32/PeiCoreEntry.nasm
> deleted file mode 100644
> index 5c5b788085..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/Ia32/PeiCoreEntry.nasm
> +++ /dev/null
> @@ -1,130 +0,0 @@
> -;-------------------------------------------------------------------------------;-; Copyright (c)
> 2019, Intel Corporation. All rights reserved.<BR>-; SPDX-License-Identifier:
> BSD-2-Clause-Patent-;-; Module Name:-;-; PeiCoreEntry.nasm-;-; Abstract:-;-;
> Find and call
> SecStartup-;-;--------------------------------------------------------------------------------SECTI
> ON .text--extern ASM_PFX(SecStartup)-extern ASM_PFX(PlatformInit)--global
> ASM_PFX(CallPeiCoreEntryPoint)-ASM_PFX(CallPeiCoreEntryPoint):- ;- ;
> Obtain the hob list pointer- ;- mov eax, [esp+4]- ;- ; Obtain the
> stack information- ; ECX: start of range- ; EDX: end of range- ;-
> mov ecx, [esp+8]- mov edx, [esp+0xC]-- ;- ; Platform init- ;-
> pushad- push edx- push ecx- push eax- call ASM_PFX(PlatformInit)-
> pop eax- pop eax- pop eax- popad-- ;- ; Set stack top
> pointer- ;- mov esp, edx-- ;- ; Push the hob list pointer- ;-
> push eax-- ;- ; Save the value- ; ECX: start of range- ; EDX:
> end of range- ;- mov ebp, esp- push ecx- push
> edx-- ;- ; Push processor count to stack first, then BIST status (AP then
> BSP)- ;- mov eax, 1- cpuid- shr ebx, 16- and ebx,
> 0xFF- cmp bl, 1- jae PushProcessorCount-- ;- ; Some
> processors report 0 logical processors. Effectively 0 = 1.- ; So we fix up
> the processor count- ;- inc ebx--PushProcessorCount:- push
> ebx-- ;- ; We need to implement a long-term solution for BIST capture.
> For now, we just copy BSP BIST- ; for all processor threads- ;- xor
> ecx, ecx- mov cl, bl-PushBist:- movd eax, mm0- push eax-
> loop PushBist-- ; Save Time-Stamp Counter- movd eax, mm5- push
> eax-- movd eax, mm6- push eax-- ;- ; Pass entry point of the PEI
> core- ;- mov edi, 0xFFFFFFE0- push DWORD [edi]-- ;- ; Pass
> BFV into the PEI Core- ;- mov edi, 0xFFFFFFFC- push DWORD
> [edi]-- ;- ; Pass stack size into the PEI Core- ;- mov ecx, [ebp - 4]-
> mov edx, [ebp - 8]- push ecx ; RamBase-- sub edx,
> ecx- push edx ; RamSize-- ;- ; Pass Control into the PEI
> Core- ;- call ASM_PFX(SecStartup)-diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/Ia32/SecEntry.nasm
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/Ia32/SecEntry.nasm
> deleted file mode 100644
> index 7f6d771e41..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/Ia32/SecEntry.nasm
> +++ /dev/null
> @@ -1,361 +0,0 @@
> -;-------------------------------------------------------------------------------;-; Copyright (c)
> 2019, Intel Corporation. All rights reserved.<BR>-; SPDX-License-Identifier:
> BSD-2-Clause-Patent-; Module Name:-;-; SecEntry.nasm-;-; Abstract:-;-;
> This is the code that goes from real-mode to protected mode.-; It
> consumes the reset vector, calls TempRamInit API from FSP
> binary.-;-;--------------------------------------------------------------------------------#include
> "Fsp.h"--SECTION .text--extern ASM_PFX(CallPeiCoreEntryPoint)-extern
> ASM_PFX(FsptUpdDataPtr)-extern ASM_PFX(BoardBeforeTempRamInit)-;
> Pcds-extern ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))-extern
> ASM_PFX(PcdGet32
> (PcdFsptBaseAddress))--;------------------------------------------------------------------------
> -----;-; Procedure: _ModuleEntryPoint-;-; Input: None-;-; Output:
> None-;-; Destroys: Assume all registers-;-; Description:-;-; Transition
> to non-paged flat-model protected mode from a-; hard-coded GDT that
> provides exactly two descriptors.-; This is a bare bones transition to
> protected mode only-; used for a while in PEI and possibly DXE.-;-;
> After enabling protected mode, a far jump is executed to-; transfer to PEI
> using the newly loaded GDT.-;-; Return: None-;-; MMX Usage:-;
> MM0 = BIST State-; MM5 = Save time-stamp counter value
> high32bit-; MM6 = Save time-stamp counter value
> low32bit.-;-;------------------------------------------------------------------------------BITS
> 16-align 4-global
> ASM_PFX(_ModuleEntryPoint)-ASM_PFX(_ModuleEntryPoint):-
> fninit ; clear any pending Floating
> point exceptions- ;- ; Store the BIST value in mm0- ;- movd mm0,
> eax- cli-- ;- ; Check INIT# is asserted by port 0xCF9- ;- mov dx, 0CF9h-
> in al, dx- cmp al, 04h- jnz NotWarmStart--- ;- ; @note Issue warm
> reset, since if CPU only reset is issued not all MSRs are restored to their
> defaults- ;- mov dx, 0CF9h- mov al, 06h- out dx,
> al--NotWarmStart:- ;- ; Save time-stamp counter value- ; rdtsc load 64bit
> time-stamp counter to EDX:EAX- ;- rdtsc- movd mm5, edx- movd
> mm6, eax-- ;- ; Load the GDT table in GdtDesc- ;- mov esi,
> GdtDesc- DB 66h- lgdt [cs:si]-- ;- ; Transition to 16 bit
> protected mode- ;- mov eax, cr0 ; Get control
> register 0- or eax, 00000003h ; Set PE bit (bit #0) &
> MP bit (bit #1)- mov cr0, eax ; Activate
> protected mode-- mov eax, cr4 ; Get control
> register 4- or eax, 00000600h ; Set OSFXSR bit (bit #9)
> & OSXMMEXCPT bit (bit #10)- mov cr4, eax-- ;- ; Now we're in 16
> bit protected mode- ; Set up the selectors for 32 bit protected mode
> entry- ;- mov ax, SYS_DATA_SEL- mov ds, ax- mov es,
> ax- mov fs, ax- mov gs, ax- mov ss, ax-- ;- ; Transition
> to Flat 32 bit protected mode- ; The jump to a far pointer causes the
> transition to 32 bit mode- ;- mov esi, ProtectedModeEntryLinearAddress-
> jmp dword far
> [cs:si]--;-----------------------------------------------------------------------------;-; Procedure:
> ProtectedModeEntryPoint-;-; Input: None-;-; Output: None-;-;
> Destroys: Assume all registers-;-; Description:-;-; This function handles:-;
> Call two basic APIs from FSP binary-; Initializes stack with some early data
> (BIST, PEI entry, etc)-;-; Return:
> None-;-;------------------------------------------------------------------------------BITS 32-align
> 4-ProtectedModeEntryPoint:- ;- ; Early board hooks- ;- mov esp,
> BoardBeforeTempRamInitRet- jmp
> ASM_PFX(BoardBeforeTempRamInit)--BoardBeforeTempRamInitRet:-- ;
> Find the fsp info header- mov edi, [ASM_PFX(PcdGet32
> (PcdFsptBaseAddress))]-- mov eax, dword [edi +
> FVH_SIGINATURE_OFFSET]- cmp eax, FVH_SIGINATURE_VALID_VALUE-
> jnz FspHeaderNotFound-- xor eax, eax- mov ax, word [edi +
> FVH_EXTHEADER_OFFSET_OFFSET]- cmp ax, 0- jnz
> FspFvExtHeaderExist-- xor eax, eax- mov ax, word [edi +
> FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header- add edi, eax-
> jmp FspCheckFfsHeader--FspFvExtHeaderExist:- add edi, eax- mov
> eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Header-
> add edi, eax-- ; Round up to 8 byte alignment- mov eax, edi- and
> al, 07h- jz FspCheckFfsHeader-- and edi, 0FFFFFFF8h- add edi,
> 08h--FspCheckFfsHeader:- ; Check the ffs guid- mov eax, dword [edi]-
> cmp eax, FSP_HEADER_GUID_DWORD1- jnz FspHeaderNotFound--
> mov eax, dword [edi + 4]- cmp eax, FSP_HEADER_GUID_DWORD2- jnz
> FspHeaderNotFound-- mov eax, dword [edi + 8]- cmp eax,
> FSP_HEADER_GUID_DWORD3- jnz FspHeaderNotFound-- mov eax,
> dword [edi + 0Ch]- cmp eax, FSP_HEADER_GUID_DWORD4- jnz
> FspHeaderNotFound-- add edi, FFS_HEADER_SIZE_VALUE ; Bypass
> the ffs header-- ; Check the section type as raw section- mov al, byte
> [edi + SECTION_HEADER_TYPE_OFFSET]- cmp al, 019h- jnz
> FspHeaderNotFound-- add edi, RAW_SECTION_HEADER_SIZE_VALUE ;
> Bypass the section header- jmp FspHeaderFound--FspHeaderNotFound:-
> jmp $--FspHeaderFound:- ; Get the fsp TempRamInit Api address- mov
> eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]- add eax, dword [edi
> + FSP_HEADER_TEMPRAMINIT_OFFSET]-- ; Setup the hardcode stack- mov
> esp, TempRamInitStack-- ; Call the fsp TempRamInit Api- jmp
> eax--TempRamInitDone:- cmp eax, 8000000Eh ;Check if
> EFI_NOT_FOUND returned. Error code for Microcode Update not found.- je
> CallSecFspInit ;If microcode not found, don't hang, but continue.--
> cmp eax, 0 ;Check if EFI_SUCCESS retuned.- jnz
> FspApiFailed-- ; ECX: start of range- ; EDX: end of
> range-CallSecFspInit:- sub edx, [ASM_PFX(PcdGet32
> (PcdFspTemporaryRamSize))] ; TemporaryRam for FSP- xor eax, eax-
> mov esp, edx-- ; Align the stack at DWORD- add esp, 3- and
> esp, 0FFFFFFFCh-- push edx- push ecx- push eax ; zero - no
> hob list yet- call ASM_PFX(CallPeiCoreEntryPoint)--FspApiFailed:- jmp
> $--align 10h-TempRamInitStack:- DD TempRamInitDone- DD
> ASM_PFX(FsptUpdDataPtr); TempRamInitParams--;-; ROM-based
> Global-Descriptor Table for the Tiano PEI Phase-;-align 16-global
> ASM_PFX(BootGdtTable)--;-; GDT[0]: 0x00: Null entry, never used.-;-NULL_SEL
> EQU $ - GDT_BASE ; Selector [0]-GDT_BASE:-ASM_PFX(BootGdtTable):-
> DD 0- DD 0-;-; Linear data segment
> descriptor-;-LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8]-
> DW 0FFFFh ; limit 0xFFFFF- DW
> 0 ; base 0- DB 0- DB
> 092h ; present, ring 0, data, expand-up,
> writable- DB 0CFh ; page-granular,
> 32-bit- DB 0-;-; Linear code segment descriptor-;-LINEAR_CODE_SEL
> EQU $ - GDT_BASE ; Selector [0x10]- DW
> 0FFFFh ; limit 0xFFFFF- DW
> 0 ; base 0- DB 0- DB
> 09Bh ; present, ring 0, data, expand-up,
> not-writable- DB 0CFh ; page-granular,
> 32-bit- DB 0-;-; System data segment descriptor-;-SYS_DATA_SEL
> EQU $ - GDT_BASE ; Selector [0x18]- DW
> 0FFFFh ; limit 0xFFFFF- DW
> 0 ; base 0- DB 0- DB
> 093h ; present, ring 0, data, expand-up,
> not-writable- DB 0CFh ; page-granular,
> 32-bit- DB 0--;-; System code segment descriptor-;-SYS_CODE_SEL
> EQU $ - GDT_BASE ; Selector [0x20]- DW
> 0FFFFh ; limit 0xFFFFF- DW
> 0 ; base 0- DB 0- DB
> 09Ah ; present, ring 0, data, expand-up,
> writable- DB 0CFh ; page-granular,
> 32-bit- DB 0-;-; Spare segment descriptor-;-SYS16_CODE_SEL EQU
> $ - GDT_BASE ; Selector [0x28]- DW
> 0FFFFh ; limit 0xFFFFF- DW
> 0 ; base 0- DB
> 0Eh ; Changed from F000 to E000.- DB
> 09Bh ; present, ring 0, code, expand-up,
> writable- DB 00h ; byte-granular,
> 16-bit- DB 0-;-; Spare segment descriptor-;-SYS16_DATA_SEL EQU
> $ - GDT_BASE ; Selector [0x30]- DW
> 0FFFFh ; limit 0xFFFF- DW
> 0 ; base 0- DB 0- DB
> 093h ; present, ring 0, data, expand-up,
> not-writable- DB 00h ; byte-granular,
> 16-bit- DB 0--;-; Spare segment descriptor-;-SPARE5_SEL
> EQU $ - GDT_BASE ; Selector [0x38]- DW
> 0 ; limit 0- DW
> 0 ; base 0- DB 0- DB
> 0 ; present, ring 0, data, expand-up,
> writable- DB 0 ; page-granular,
> 32-bit- DB 0-GDT_SIZE EQU $ - GDT_BASE ; Size, in
> bytes--;-; GDT Descriptor-;-GdtDesc: ;
> GDT descriptor- DW GDT_SIZE - 1 ; GDT limit-
> DD GDT_BASE ; GDT base
> address---ProtectedModeEntryLinearAddress:-ProtectedModeEntryLinear:-
> DD ProtectedModeEntryPoint ; Offset of our 32 bit code- DW
> LINEAR_CODE_SELdiff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/Ia32/Stack.nasm
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/Ia32/Stack.nasm
> deleted file mode 100644
> index 47db32d64c..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/Ia32/Stack.nasm
> +++ /dev/null
> @@ -1,72 +0,0 @@
> -;-------------------------------------------------------------------------------;-; Copyright (c)
> 2019, Intel Corporation. All rights reserved.<BR>-; SPDX-License-Identifier:
> BSD-2-Clause-Patent-; Abstract:-;-; Switch the stack from temporary
> memory to permanent
> memory.-;-;--------------------------------------------------------------------------------
> SECTION .text--;-------------------------------------------------------------------------------;
> VOID-; EFIAPI-; SecSwitchStack (-; UINT32 TemporaryMemoryBase,-;
> UINT32
> PermanentMemoryBase-; );-;---------------------------------------------------------------
> ----------------global
> ASM_PFX(SecSwitchStack)-ASM_PFX(SecSwitchStack):- ;- ; Save three
> register: eax, ebx, ecx- ;- push eax- push ebx- push ecx-
> push edx-- ;- ; !!CAUTION!! this function address's is pushed into
> stack after- ; migration of whole temporary memory, so need save it to
> permanent- ; memory at first!- ;-- mov ebx, [esp +
> 20] ; Save the first parameter- mov ecx, [esp +
> 24] ; Save the second parameter-- ;- ; Save this function's
> return address into permanent memory at first.- ; Then, Fixup the esp
> point to permanent memory- ;- mov eax, esp- sub eax,
> ebx- add eax, ecx- mov edx, dword [esp] ; copy
> pushed register's value to permanent memory- mov dword [eax], edx-
> mov edx, dword [esp + 4]- mov dword [eax + 4], edx- mov
> edx, dword [esp + 8]- mov dword [eax + 8], edx- mov edx,
> dword [esp + 12]- mov dword [eax + 12], edx- mov edx, dword
> [esp + 16] ; Update this function's return address into permanent
> memory- mov dword [eax + 16], edx- mov esp,
> eax ; From now, esp is pointed to permanent
> memory-- ;- ; Fixup the ebp point to permanent memory- ;-
> mov eax, ebp- sub eax, ebx- add eax, ecx- mov ebp,
> eax ; From now, ebp is pointed to permanent memory--
> pop edx- pop ecx- pop ebx- pop eax- ret-diff
> --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/PlatformInit.c
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/PlatformInit.c
> deleted file mode 100644
> index ef89e3f310..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/PlatformInit.c
> +++ /dev/null
> @@ -1,47 +0,0 @@
> -/** @file- Provide platform init function.--Copyright (c) 2017, Intel
> Corporation. All rights reserved.<BR>-SPDX-License-Identifier:
> BSD-2-Clause-Patent--**/---#include <PiPei.h>-#include
> <Library/DebugLib.h>-#include <Library/SerialPortLib.h>-#include
> <Library/SecBoardInitLib.h>-#include <Library/TestPointCheckLib.h>--/**-
> Platform initialization.-- @param[in] FspHobList HobList produced by
> FSP.- @param[in] StartOfRange Start of temporary RAM.- @param[in]
> EndOfRange End of temporary RAM.-**/-VOID-EFIAPI-PlatformInit (- IN
> VOID *FspHobList,- IN VOID
> *StartOfRange,- IN VOID *EndOfRange- )-{- //- //
> Platform initialization- // Enable Serial port here- //- if
> (PcdGetBool(PcdSecSerialPortDebugEnable)) {- SerialPortInitialize
> ();- }-- DEBUG ((DEBUG_INFO, "PrintPeiCoreEntryPointParam in
> PlatformInit\n"));- DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n",
> FspHobList));- DEBUG ((DEBUG_INFO, "StartOfRange - 0x%x\n",
> StartOfRange));- DEBUG ((DEBUG_INFO, "EndOfRange - 0x%x\n",
> EndOfRange));-- BoardAfterTempRamInit ();--
> TestPointTempMemoryFunction (StartOfRange, EndOfRange);-}diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> deleted file mode 100644
> index c99dd5ecdd..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> +++ /dev/null
> @@ -1,97 +0,0 @@
> -## @file-# Provide FSP wrapper platform sec related function.-#-#
> Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>-#-#
> SPDX-License-Identifier:
> BSD-2-Clause-Patent-#-#-##--########################################
> ########################################-#-# Defines Section -
> statements that will be processed to create a
> Makefile.-#-######################################################
> ##########################-[Defines]- INF_VERSION
> = 0x00010005- BASE_NAME =
> SecFspWrapperPlatformSecLib- FILE_GUID =
> 4E1C4F95-90EA-47de-9ACC-B8920189A1F5- MODULE_TYPE
> = SEC- VERSION_STRING = 1.0- LIBRARY_CLASS
> = PlatformSecLib---#-# The following information is for reference only and
> not required by the build tools.-#-# VALID_ARCHITECTURES =
> IA32
> X64-#--##########################################################
> ######################-#-# Sources Section - list of files that are required
> for the build to
> succeed.-#-######################################################
> ##########################--[Sources]- FspWrapperPlatformSecLib.c-
> SecRamInitData.c- SecPlatformInformation.c- SecGetPerformance.c-
> SecTempRamDone.c- PlatformInit.c--[Sources.IA32]- Ia32/SecEntry.nasm-
> Ia32/PeiCoreEntry.nasm- Ia32/Stack.nasm-
> Ia32/Fsp.h--######################################################
> ##########################-#-# Package Dependency Section - list of
> Package files that are required for-# this
> module.-#-#######################################################
> #########################--[Packages]- MdePkg/MdePkg.dec-
> MdeModulePkg/MdeModulePkg.dec- UefiCpuPkg/UefiCpuPkg.dec-
> IntelFsp2Pkg/IntelFsp2Pkg.dec-
> IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec-
> MinPlatformPkg/MinPlatformPkg.dec-
> KabylakeSiliconPkg/SiPkg.dec--[LibraryClasses]- LocalApicLib-
> SerialPortLib- FspWrapperPlatformLib- FspWrapperApiLib- BoardInitLib-
> SecBoardInitLib- TestPointCheckLib- PeiServicesTablePointerLib--[Ppis]-
> gEfiSecPlatformInformationPpiGuid ## CONSUMES-
> gPeiSecPerformancePpiGuid ## CONSUMES-
> gTopOfTemporaryRamPpiGuid ## PRODUCES-
> gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES-
> gFspTempRamExitPpiGuid ## CONSUMES--[Pcd]-
> gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize
> ## CONSUMES- gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress
> ## CONSUMES- gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize
> ## CONSUMES-
> gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable
> ## CONSUMES--[FixedPcd]-
> gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress
> ## CONSUMES-
> gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize
> ## CONSUMES-
> gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset
> ## CONSUMES-
> gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress
> ## CONSUMES- gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize
> ## CONSUMES- gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress
> ## CONSUMES- gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection
> ## CONSUMESdiff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecGetPerformance.c
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecGetPerformance.c
> deleted file mode 100644
> index c4eeb2b188..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecGetPerformance.c
> +++ /dev/null
> @@ -1,89 +0,0 @@
> -/** @file- Sample to provide SecGetPerformance function.--Copyright (c)
> 2017, Intel Corporation. All rights reserved.<BR>-SPDX-License-Identifier:
> BSD-2-Clause-Patent--**/--#include <PiPei.h>--#include
> <Ppi/SecPerformance.h>-#include <Ppi/TopOfTemporaryRam.h>--#include
> <Library/BaseMemoryLib.h>-#include <Library/TimerLib.h>-#include
> <Library/DebugLib.h>--/**- This interface conveys performance information
> out of the Security (SEC) phase into PEI.-- This service is published by the
> SEC phase. The SEC phase handoff has an optional-
> EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed
> from SEC into the- PEI Foundation. As such, if the platform supports
> collecting performance data in SEC,- this information is encapsulated into
> the data structure abstracted by this service.- This information is collected
> for the boot-strap processor (BSP) on IA-32.-- @param[in] PeiServices
> The pointer to the PEI Services Table.- @param[in] This The
> pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.- @param[out]
> Performance The pointer to performance data collected in SEC phase.--
> @retval EFI_SUCCESS The data was successfully
> returned.--**/-EFI_STATUS-EFIAPI-SecGetPerformance (- IN CONST
> EFI_PEI_SERVICES **PeiServices,- IN
> PEI_SEC_PERFORMANCE_PPI *This,- OUT
> FIRMWARE_SEC_PERFORMANCE *Performance- )-{- UINT32 Size;-
> UINT32 Count;- UINT32 TopOfTemporaryRam;- UINT64
> Ticker;- VOID *TopOfTemporaryRamPpi;- EFI_STATUS Status;--
> DEBUG ((DEBUG_INFO, "SecGetPerformance\n"));-- Status =
> (*PeiServices)->LocatePpi (- PeiServices,-
> &gTopOfTemporaryRamPpiGuid,- 0,-
> NULL,- (VOID **)
> &TopOfTemporaryRamPpi- );- if
> (EFI_ERROR (Status)) {- return EFI_NOT_FOUND;- }- //- //
> |--------------| <- TopOfTemporaryRam - BL- // | List Ptr |- //
> |--------------|- // | BL RAM Start |- // |--------------|- // | BL RAM End
> |- // |--------------|- // |Number of BSPs|- // |--------------|- // |
> BIST |- // |--------------|- // | .... |- // |--------------|- // |
> TSC[63:32] |- // |--------------|- // | TSC[31:00] |- // |--------------|-
> //- TopOfTemporaryRam = (UINT32)(UINTN)TopOfTemporaryRamPpi -
> sizeof(UINT32);- TopOfTemporaryRam -= sizeof(UINT32) * 2;- Count
> = *(UINT32 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32));- Size
> = Count * sizeof (UINT32);-- Ticker = *(UINT64 *) (UINTN)
> (TopOfTemporaryRam - sizeof (UINT32) - Size - sizeof (UINT32) * 2);-
> Performance->ResetEnd = GetTimeInNanoSecond (Ticker);-- return
> EFI_SUCCESS;-}diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecPlatformInformation.c
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecPlatformInformation.c
> deleted file mode 100644
> index 5b94ed2bef..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecPlatformInformation.c
> +++ /dev/null
> @@ -1,78 +0,0 @@
> -/** @file- Provide SecPlatformInformation function.--Copyright (c) 2017,
> Intel Corporation. All rights reserved.<BR>-SPDX-License-Identifier:
> BSD-2-Clause-Patent--**/--#include <PiPei.h>--#include
> <Ppi/SecPlatformInformation.h>-#include
> <Ppi/TopOfTemporaryRam.h>--#include
> <Library/BaseMemoryLib.h>-#include <Library/DebugLib.h>--/**- This
> interface conveys state information out of the Security (SEC) phase into PEI.--
> @param[in] PeiServices Pointer to the PEI Services
> Table.- @param[in,out] StructureSize Pointer to the variable
> describing size of the input buffer.- @param[out]
> PlatformInformationRecord Pointer to the
> EFI_SEC_PLATFORM_INFORMATION_RECORD.-- @retval EFI_SUCCESS
> The data was successfully returned.- @retval EFI_BUFFER_TOO_SMALL
> The buffer was too small.--**/-EFI_STATUS-EFIAPI-SecPlatformInformation (-
> IN CONST EFI_PEI_SERVICES **PeiServices,- IN OUT
> UINT64 *StructureSize,- OUT
> EFI_SEC_PLATFORM_INFORMATION_RECORD
> *PlatformInformationRecord- )-{- UINT32 *Bist;- UINT32
> Size;- UINT32 Count;- UINT32 TopOfTemporaryRam;- VOID
> *TopOfTemporaryRamPpi;- EFI_STATUS Status;-- DEBUG ((DEBUG_INFO,
> "SecPlatformInformation\n"));-- Status = (*PeiServices)->LocatePpi (-
> PeiServices,-
> &gTopOfTemporaryRamPpiGuid,- 0,-
> NULL,- (VOID **)
> &TopOfTemporaryRamPpi- );- if
> (EFI_ERROR (Status)) {- return EFI_NOT_FOUND;- }-- //- // The
> entries of BIST information, together with the number of them,- // reside
> in the bottom of stack, left untouched by normal stack operation.- // This
> routine copies the BIST information to the buffer pointed by- //
> PlatformInformationRecord for output.- //- TopOfTemporaryRam =
> (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof (UINT32);-
> TopOfTemporaryRam -= sizeof(UINT32) * 2;- Count =
> *((UINT32 *)(UINTN) (TopOfTemporaryRam - sizeof (UINT32)));- Size
> = Count * sizeof (IA32_HANDOFF_STATUS);-- if ((*StructureSize) < (UINT64)
> Size) {- *StructureSize = Size;- return EFI_BUFFER_TOO_SMALL;- }--
> *StructureSize = Size;- Bist = (UINT32 *)
> (TopOfTemporaryRam - sizeof (UINT32) - Size);-- CopyMem
> (PlatformInformationRecord, Bist, Size);-- return EFI_SUCCESS;-}diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecRamInitData.c
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecRamInitData.c
> deleted file mode 100644
> index b356327b4c..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecRamInitData.c
> +++ /dev/null
> @@ -1,36 +0,0 @@
> -/** @file- Provide TempRamInitParams data.--Copyright (c) 2017, Intel
> Corporation. All rights reserved.<BR>-SPDX-License-Identifier:
> BSD-2-Clause-Patent--**/--#include <Library/PcdLib.h>-#include
> <FspEas.h>-#include "FsptCoreUpd.h"--typedef struct {- FSP_UPD_HEADER
> FspUpdHeader;- FSPT_CORE_UPD FsptCoreUpd;-}
> FSPT_UPD_CORE_DATA;--GLOBAL_REMOVE_IF_UNREFERENCED CONST
> FSPT_UPD_CORE_DATA FsptUpdDataPtr = {- {- 0x4450555F54505346,-
> 0x00,- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,-
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00- }- },- {-
> ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + FixedPcdGet32
> (PcdFlashMicrocodeOffset)),- ((UINT32)FixedPcdGet64
> (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet32
> (PcdFlashMicrocodeOffset)),- 0, // Set CodeRegionBase as 0,
> so that caching will be 4GB-(CodeRegionSize > LLCSize ? LLCSize :
> CodeRegionSize) will be used.- FixedPcdGet32 (PcdFlashCodeCacheSize),-
> { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,- 0x00,
> 0x00, 0x00, 0x00, 0x00, 0x00- }- }-};-diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecTempRamDone.c
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecTempRamDone.c
> deleted file mode 100644
> index 922e4ec204..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrappe
> rPlatformSecLib/SecTempRamDone.c
> +++ /dev/null
> @@ -1,73 +0,0 @@
> -/** @file- Provide SecTemporaryRamDone function.--Copyright (c) 2017 -
> 2019, Intel Corporation. All rights reserved.<BR>-SPDX-License-Identifier:
> BSD-2-Clause-Patent--**/--#include <PiPei.h>--#include
> <Ppi/TemporaryRamDone.h>-#include <Ppi/TempRamExitPpi.h>--#include
> <Library/BaseMemoryLib.h>-#include <Library/DebugLib.h>-#include
> <Library/PcdLib.h>-#include <Library/DebugAgentLib.h>-#include
> <Library/FspWrapperPlatformLib.h>-#include
> <Library/FspWrapperApiLib.h>-#include <Library/BoardInitLib.h>-#include
> <Library/PeiServicesTablePointerLib.h>--/**-This interface disables temporary
> memory in SEC
> Phase.-**/-VOID-EFIAPI-SecPlatformDisableTemporaryMemory (-
> VOID- )-{- EFI_STATUS Status;- VOID
> *TempRamExitParam;- CONST EFI_PEI_SERVICES **PeiServices;-
> FSP_TEMP_RAM_EXIT_PPI *TempRamExitPpi;-- DEBUG ((DEBUG_INFO,
> "SecPlatformDisableTemporaryMemory enter\n"));-- Status =
> BoardInitBeforeTempRamExit ();- ASSERT_EFI_ERROR (Status);-- if
> (PcdGet8 (PcdFspModeSelection) == 1) {- //- // FSP API mode- //-
> TempRamExitParam = UpdateTempRamExitParam ();- Status =
> CallTempRamExit (TempRamExitParam);- DEBUG ((DEBUG_INFO,
> "TempRamExit status: 0x%x\n", Status));- ASSERT_EFI_ERROR (Status);- }
> else {- //- // FSP Dispatch mode- //- PeiServices =
> GetPeiServicesTablePointer ();- Status = (*PeiServices)->LocatePpi (-
> PeiServices,- &gFspTempRamExitPpiGuid,-
> 0,- NULL,-
> (VOID **) &TempRamExitPpi- );-
> ASSERT_EFI_ERROR (Status);- if (EFI_ERROR (Status)) {-
> return;- }- TempRamExitPpi->TempRamExit (NULL);- }-- Status =
> BoardInitAfterTempRamExit ();- ASSERT_EFI_ERROR (Status);--
> return ;-}diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> index 2bc2b4126b..acdc31e708 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> @@ -126,7 +126,7 @@
> #######################################
> GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpande
> rLib/BaseGpioExpanderLib.inf
> I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cA
> ccessLib.inf-
> PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFsp
> WrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf+
> PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/SecFspWrapperPlatformSecLib.inf # Thunderbolt !if
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUEdiff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> index 77e4a6a610..4b07c0a684 100644
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> +++
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> @@ -166,7 +166,7 @@
> EcLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseEcLib/BaseEcLib.inf
> GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpande
> rLib/BaseGpioExpanderLib.inf
> I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cA
> ccessLib.inf-
> PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFsp
> WrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf+
> PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/SecFspWrapperPlatformSecLib.inf # Thunderbolt !if
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE--
> 2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 13/13] MinPlatformPkg: Remove BoardInitLib dependency from PlatformSecLib
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 13/13] MinPlatformPkg: Remove BoardInitLib dependency from PlatformSecLib Nate DeSimone
@ 2019-11-14 15:18 ` Chiu, Chasel
2019-11-16 2:56 ` Kubacki, Michael A
1 sibling, 0 replies; 44+ messages in thread
From: Chiu, Chasel @ 2019-11-14 15:18 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io
Cc: Kubacki, Michael A, Gao, Liming
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Thursday, November 14, 2019 2:07 PM
> To: devel@edk2.groups.io
> Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Chiu, Chasel
> <chasel.chiu@intel.com>; Gao, Liming <liming.gao@intel.com>
> Subject: [edk2-platforms] [PATCH V1 13/13] MinPlatformPkg: Remove
> BoardInitLib dependency from PlatformSecLib
>
> SecFspWrapperPlatformSecLib contains the implementation of
> SecPlatformDisableTemporaryMemory(), which SecMain in UefiCpuPkg will
> call as part of its implementation of EFI_PEI_TEMPORARY_RAM_DONE_PPI.
> For platforms that use FSP, the implementation of
> SecPlatformDisableTemporaryMemory() can be made generic since the
> chipset specifics will be contained in FspTempRamExit().
>
> The Minimum Platform Specification provides the BoardPkg two interface
> hook points, BoardInitBeforeTempRamExit() and
> BoardInitAfterTempRamExit() which must be called during
> SecPlatformDisableTemporaryMemory(). Due to
> EFI_PEI_TEMPORARY_RAM_DONE_PPI being a special case of a PPI that is
> implemented in SEC, these two functions are the only ones in BoardInitLib
> that need to be called by SEC.
>
> Linking BoardInitLib with SEC places many restrictions on the
> implementation of that library. The features available to SEC phase code are
> very minimal. Since this code runs during PEI phase, these restrictions are
> not actually required.
>
> Instead of directly linking with BoardInitLib,
> SecPlatformDisableTemporaryMemory() shall call BoardInitLib indirectly
> through a PPI (PLATFORM_INIT_TEMP_RAM_EXIT_PPI.) This PPI is produced
> by PlatformInitPreMem, which implements the other BoardInitLib calls
> already, so this change should also slightly reduce the size of the final binary
> image since less PE/COFF images will need to link with BoardInitLib.
>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../SecFspWrapperPlatformSecLib.inf | 1 +
> .../SecTempRamDone.c | 36 +++++++--
> .../Include/Ppi/PlatformInitTempRamExitPpi.h | 55 ++++++++++++++
> .../Intel/MinPlatformPkg/MinPlatformPkg.dec | 2 +
> .../PlatformInitPei/PlatformInitPreMem.c | 76 ++++++++++++++++++-
> .../PlatformInitPei/PlatformInitPreMem.inf | 1 +
> 6 files changed, 159 insertions(+), 12 deletions(-) create mode 100644
> Platform/Intel/MinPlatformPkg/Include/Ppi/PlatformInitTempRamExitPpi.h
>
> diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecFspWrapperPlatformSecLib.inf
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecFspWrapperPlatformSecLib.inf
> index 02c720c73d..3465f50126 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecFspWrapperPlatformSecLib.inf
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/SecFspWrapperPlatformSecLib.inf
> @@ -80,6 +80,7 @@
> gTopOfTemporaryRamPpiGuid ## PRODUCES
> gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES
> gFspTempRamExitPpiGuid ## CONSUMES+
> gPlatformInitTempRamExitPpiGuid ## CONSUMES [Pcd]
> gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize
> ## CONSUMESdiff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecTempRamDone.c
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecTempRamDone.c
> index 922e4ec204..b22cf57d6c 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecTempRamDone.c
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/SecTempRamDone.c
> @@ -10,6 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> #include <Ppi/TemporaryRamDone.h> #include
> <Ppi/TempRamExitPpi.h>+#include <Ppi/PlatformInitTempRamExitPpi.h>
> #include <Library/BaseMemoryLib.h> #include <Library/DebugLib.h>@@
> -17,7 +18,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include
> <Library/DebugAgentLib.h> #include <Library/FspWrapperPlatformLib.h>
> #include <Library/FspWrapperApiLib.h>-#include <Library/BoardInitLib.h>
> #include <Library/PeiServicesTablePointerLib.h> /**@@ -29,14 +29,35 @@
> SecPlatformDisableTemporaryMemory (
> VOID ) {- EFI_STATUS Status;- VOID
> *TempRamExitParam;- CONST EFI_PEI_SERVICES **PeiServices;-
> FSP_TEMP_RAM_EXIT_PPI *TempRamExitPpi;+ EFI_STATUS
> Status;+ VOID *TempRamExitParam;+
> CONST EFI_PEI_SERVICES **PeiServices;+
> FSP_TEMP_RAM_EXIT_PPI *TempRamExitPpi;+
> PLATFORM_INIT_TEMP_RAM_EXIT_PPI *PlatformInitTempRamExitPpi;
> DEBUG ((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n"));+
> PeiServices = GetPeiServicesTablePointer ();+ ASSERT (PeiServices != NULL);+
> if (PeiServices == NULL) {+ return;+ }+ ASSERT ((*PeiServices) !=
> NULL);+ if ((*PeiServices) == NULL) {+ return;+ }+ Status =
> (*PeiServices)->LocatePpi (+ PeiServices,+
> &gPlatformInitTempRamExitPpiGuid,+ 0,+
> NULL,+ (VOID **)
> &PlatformInitTempRamExitPpi+ );+
> ASSERT_EFI_ERROR (Status);+ if (EFI_ERROR (Status)) {+ return;+ } -
> Status = BoardInitBeforeTempRamExit ();+ Status =
> PlatformInitTempRamExitPpi->PlatformInitBeforeTempRamExit ();
> ASSERT_EFI_ERROR (Status); if (PcdGet8 (PcdFspModeSelection) == 1)
> {@@ -51,7 +72,6 @@ SecPlatformDisableTemporaryMemory (
> // // FSP Dispatch mode //- PeiServices =
> GetPeiServicesTablePointer (); Status = (*PeiServices)->LocatePpi
> ( PeiServices,
> &gFspTempRamExitPpiGuid,@@ -66,7 +86,7 @@
> SecPlatformDisableTemporaryMemory (
> TempRamExitPpi->TempRamExit (NULL); } - Status =
> BoardInitAfterTempRamExit ();+ Status =
> PlatformInitTempRamExitPpi->PlatformInitAfterTempRamExit ();
> ASSERT_EFI_ERROR (Status); return ;diff --git
> a/Platform/Intel/MinPlatformPkg/Include/Ppi/PlatformInitTempRamExitPpi.h
> b/Platform/Intel/MinPlatformPkg/Include/Ppi/PlatformInitTempRamExitPpi.h
> new file mode 100644
> index 0000000000..590647738c
> --- /dev/null
> +++
> b/Platform/Intel/MinPlatformPkg/Include/Ppi/PlatformInitTempRamExitP
> +++ pi.h
> @@ -0,0 +1,55 @@
> +/** @file+ This file defines the PPI for notifying PlatformInitPreMem+ of
> temporary memory being disabled.++Copyright (c) 2019, Intel Corporation.
> All rights reserved.<BR>+SPDX-License-Identifier:
> BSD-2-Clause-Patent++**/++#ifndef
> _PLATFORM_INIT_TEMP_RAM_EXIT_PPI_H_+#define
> _PLATFORM_INIT_TEMP_RAM_EXIT_PPI_H_++#include <PiPei.h>++//+//
> Forward declaration for the
> PLATFORM_INIT_TEMP_RAM_EXIT_PPI.+//+typedef struct
> _PLATFORM_INIT_TEMP_RAM_EXIT_PPI
> PLATFORM_INIT_TEMP_RAM_EXIT_PPI;++/**+ A hook for platform-specific
> initialization prior to disabling temporary RAM.++ @retval EFI_SUCCESS
> The platform initialization was successful.+ @retval EFI_NOT_READY The
> platform has not been detected yet.+**/+typedef+EFI_STATUS+(EFIAPI
> *PLATFORM_INIT_BEFORE_TEMP_RAM_EXIT) (+ VOID+ );++/**+ A hook
> for platform-specific initialization after disabling temporary RAM.++
> @retval EFI_SUCCESS The platform initialization was successful.+
> @retval EFI_NOT_READY The platform has not been detected
> yet.+**/+typedef+EFI_STATUS+(EFIAPI
> *PLATFORM_INIT_AFTER_TEMP_RAM_EXIT) (+ VOID+ );++///+/// This PPI
> provides functions for notifying PlatformInitPreMem+/// of temporary
> memory being disabled.+///+struct _PLATFORM_INIT_TEMP_RAM_EXIT_PPI
> {+ PLATFORM_INIT_BEFORE_TEMP_RAM_EXIT
> PlatformInitBeforeTempRamExit;+
> PLATFORM_INIT_AFTER_TEMP_RAM_EXIT
> PlatformInitAfterTempRamExit;+};++extern EFI_GUID
> gPlatformInitTempRamExitPpiGuid;++#endif //
> _PLATFORM_INIT_TEMP_RAM_EXIT_PPI_H_diff --git
> a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> index c6b5881646..5dfa4d420e 100644
> --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> @@ -28,6 +28,8 @@
> gPeiBaseMemoryTestPpiGuid = {0xb6ec423c, 0x21d2, 0x490d,
> {0x85, 0xc6, 0xdd, 0x58, 0x64, 0xea, 0xa6, 0x74}}
> gPeiPlatformMemorySizePpiGuid = {0x9a7ef41e, 0xc140, 0x4bd1, {0xb8,
> 0x84, 0x1e, 0x11, 0x24, 0x0b, 0x4c, 0xe6}} +
> gPlatformInitTempRamExitPpiGuid = {0xbae23646, 0xbd60, 0x4f8b, {0xb3,
> 0xf9, 0xf3, 0x91, 0xee, 0x7e, 0xe6, 0xc8}}+ [Guids]
> gMinPlatformPkgTokenSpaceGuid = {0x69d13bf0, 0xaf91, 0x4d96, {0xaa,
> 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}} diff --git
> a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPr
> eMem.c
> b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPr
> eMem.c
> index c579ff008e..efdeb6a91c 100644
> ---
> a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPr
> eMem.c
> +++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/Platfor
> +++ mInitPreMem.c
> @@ -29,6 +29,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include
> <Guid/MemoryTypeInformation.h> #include <Ppi/PlatformMemorySize.h>
> #include <Ppi/BaseMemoryTest.h>+#include
> <Ppi/PlatformInitTempRamExitPpi.h> EFI_STATUS EFIAPI@@ -72,7 +73,31
> @@ BaseMemoryTest (
> OUT EFI_PHYSICAL_ADDRESS *ErrorAddress ); -static
> EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList = {+/**+ A hook
> for platform-specific initialization prior to disabling temporary RAM.++
> @retval EFI_SUCCESS The platform initialization was successful.+
> @retval EFI_NOT_READY The platform has not been detected
> yet.+**/+EFI_STATUS+EFIAPI+PlatformInitBeforeTempRamExit (+
> VOID+ );++/**+ A hook for platform-specific initialization after disabling
> temporary RAM.++ @retval EFI_SUCCESS The platform initialization was
> successful.+ @retval EFI_NOT_READY The platform has not been detected
> yet.+**/+EFI_STATUS+EFIAPI+PlatformInitAfterTempRamExit (+
> VOID+ );++GLOBAL_REMOVE_IF_UNREFERENCED
> EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList =
> { (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
> &gEfiPeiMemoryDiscoveredPpiGuid, (EFI_PEIM_NOTIFY_ENTRY_POINT)
> MemoryDiscoveredPpiNotifyCallback@@ -90,11 +115,11 @@
> GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR
> mPpiBootMode = {
> NULL }; -static PEI_BASE_MEMORY_TEST_PPI
> mPeiBaseMemoryTestPpi =
> { BaseMemoryTest };+GLOBAL_REMOVE_IF_UNREFERENCED
> PEI_BASE_MEMORY_TEST_PPI mPeiBaseMemoryTestPpi =
> { BaseMemoryTest }; -static PEI_PLATFORM_MEMORY_SIZE_PPI
> mMemoryMemorySizePpi =
> { GetPlatformMemorySize };+GLOBAL_REMOVE_IF_UNREFERENCED
> PEI_PLATFORM_MEMORY_SIZE_PPI mMemoryMemorySizePpi =
> { GetPlatformMemorySize }; -static EFI_PEI_PPI_DESCRIPTOR
> mMemPpiList[] = {+GLOBAL_REMOVE_IF_UNREFERENCED
> EFI_PEI_PPI_DESCRIPTOR mMemPpiList[] =
> { { EFI_PEI_PPI_DESCRIPTOR_PPI,
> &gPeiBaseMemoryTestPpiGuid,@@ -107,6 +132,17 @@ static
> EFI_PEI_PPI_DESCRIPTOR mMemPpiList[] = {
> }, }; +GLOBAL_REMOVE_IF_UNREFERENCED
> PLATFORM_INIT_TEMP_RAM_EXIT_PPI mPlatformInitTempRamExitPpi = {+
> PlatformInitBeforeTempRamExit,+
> PlatformInitAfterTempRamExit+};++GLOBAL_REMOVE_IF_UNREFERENCED
> EFI_PEI_PPI_DESCRIPTOR mPlatformInitTempRamExitPpiDesc = {+
> (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),+
> &gPlatformInitTempRamExitPpiGuid,+ &mPlatformInitTempRamExitPpi+};+
> /// /// Memory Reserved should be between 125% to 150% of the Current
> required memory /// otherwise BdsMisc.c would do a reset to make it 125%
> to avoid s4 resume issues.@@ -391,6 +427,35 @@
> MemoryDiscoveredPpiNotifyCallback (
> return Status; } +/**+ A hook for platform-specific initialization prior to
> disabling temporary RAM.++ @retval EFI_SUCCESS The platform
> initialization was successful.+ @retval EFI_NOT_READY The platform has
> not been detected
> yet.+**/+EFI_STATUS+EFIAPI+PlatformInitBeforeTempRamExit (+
> VOID+ )+{+ return BoardInitBeforeTempRamExit ();+}++/**+ A hook for
> platform-specific initialization after disabling temporary RAM.++ @retval
> EFI_SUCCESS The platform initialization was successful.+ @retval
> EFI_NOT_READY The platform has not been detected
> yet.+**/+EFI_STATUS+EFIAPI+PlatformInitAfterTempRamExit (+ VOID+ )+{+
> return BoardInitAfterTempRamExit ();+} /** This function handles
> PlatformInit task after PeiReadOnlyVariable2 PPI produced@@ -446,6 +511,9
> @@ PlatformInitPreMem (
> Status = BoardInitBeforeMemoryInit (); ASSERT_EFI_ERROR (Status); +
> Status = PeiServicesInstallPpi (&mPlatformInitTempRamExitPpiDesc);+
> ASSERT_EFI_ERROR (Status);+ return Status; } diff --git
> a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPr
> eMem.inf
> b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPr
> eMem.inf
> index af5dbe8772..7ee18eb6d5 100644
> ---
> a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPr
> eMem.inf
> +++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/Platfor
> +++ mInitPreMem.inf
> @@ -53,6 +53,7 @@
> gEfiPeiMemoryDiscoveredPpiGuid gEfiPeiMasterBootModePpiGuid
> ## PRODUCES gEfiPeiBootInRecoveryModePpiGuid ##
> PRODUCES+ gPlatformInitTempRamExitPpiGuid ##
> PRODUCES gEfiPeiReadOnlyVariable2PpiGuid
> gPeiBaseMemoryTestPpiGuid gPeiPlatformMemorySizePpiGuid--
> 2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 01/13] KabylakeSiliconPkg: Change MODULE_TYPE of SiliconInitLib to PEIM
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 01/13] KabylakeSiliconPkg: Change MODULE_TYPE of SiliconInitLib to PEIM Nate DeSimone
2019-11-14 15:15 ` Chiu, Chasel
@ 2019-11-15 8:59 ` Chaganty, Rangasai V
2019-11-16 2:53 ` Kubacki, Michael A
2 siblings, 0 replies; 44+ messages in thread
From: Chaganty, Rangasai V @ 2019-11-15 8:59 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io
Cc: Chiu, Chasel, Kubacki, Michael A
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Desimone, Nathaniel L
Sent: Wednesday, November 13, 2019 10:07 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A <michael.a.kubacki@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>
Subject: [edk2-platforms] [PATCH V1 01/13] KabylakeSiliconPkg: Change MODULE_TYPE of SiliconInitLib to PEIM
This library contains PEI phase only code. For example,
ClearIchSmiAndWake() calls PeiServicesGetBootMode().
Accordingly, this library should have never been marked as a BASE library.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
.../PeiSiliconInitLib.inf} | 3 ++-
.../{SiliconInitLib => PeiSiliconInitLib}/SiliconInit.c | 0
.../{SiliconInitLib => PeiSiliconInitLib}/SiliconInitPreMem.c | 0
3 files changed, 2 insertions(+), 1 deletion(-) rename Silicon/Intel/KabylakeSiliconPkg/Library/{SiliconInitLib/SiliconInitLib.inf => PeiSiliconInitLib/PeiSiliconInitLib.inf} (91%) rename Silicon/Intel/KabylakeSiliconPkg/Library/{SiliconInitLib => PeiSiliconInitLib}/SiliconInit.c (100%) rename Silicon/Intel/KabylakeSiliconPkg/Library/{SiliconInitLib => PeiSiliconInitLib}/SiliconInitPreMem.c (100%)
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
similarity index 91%
rename from Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf
rename to Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
index 132080e876..ff83bf2835 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf
+++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSili
+++ conInitLib.inf
@@ -11,8 +11,9 @@
BASE_NAME = SiliconInitLib FILE_GUID = 72CD3A7B-FEA5-4F5E-9165-4DD12187BB13 VERSION_STRING = 1.0- MODULE_TYPE = BASE+ MODULE_TYPE = PEIM LIBRARY_CLASS = SiliconInitLib+ # # The following information is for reference only and not required by the build tools. #diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInit.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c
similarity index 100%
rename from Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInit.c
rename to Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitPreMem.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMem.c
similarity index 100%
rename from Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitPreMem.c
rename to Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMem.c
--
2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 01/13] KabylakeSiliconPkg: Change MODULE_TYPE of SiliconInitLib to PEIM
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 01/13] KabylakeSiliconPkg: Change MODULE_TYPE of SiliconInitLib to PEIM Nate DeSimone
2019-11-14 15:15 ` Chiu, Chasel
2019-11-15 8:59 ` Chaganty, Rangasai V
@ 2019-11-16 2:53 ` Kubacki, Michael A
2 siblings, 0 replies; 44+ messages in thread
From: Kubacki, Michael A @ 2019-11-16 2:53 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io
Cc: Chiu, Chasel, Chaganty, Rangasai V
Reviewed-by: Michael Kubacki <michael.a.kubacki@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Wednesday, November 13, 2019 10:07 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>; Chaganty, Rangasai V
> <rangasai.v.chaganty@intel.com>
> Subject: [edk2-platforms] [PATCH V1 01/13] KabylakeSiliconPkg: Change
> MODULE_TYPE of SiliconInitLib to PEIM
>
> This library contains PEI phase only code. For example,
> ClearIchSmiAndWake() calls PeiServicesGetBootMode().
> Accordingly, this library should have never been marked as a BASE library.
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../PeiSiliconInitLib.inf} | 3 ++-
> .../{SiliconInitLib => PeiSiliconInitLib}/SiliconInit.c | 0
> .../{SiliconInitLib => PeiSiliconInitLib}/SiliconInitPreMem.c | 0
> 3 files changed, 2 insertions(+), 1 deletion(-) rename
> Silicon/Intel/KabylakeSiliconPkg/Library/{SiliconInitLib/SiliconInitLib.inf =>
> PeiSiliconInitLib/PeiSiliconInitLib.inf} (91%) rename
> Silicon/Intel/KabylakeSiliconPkg/Library/{SiliconInitLib =>
> PeiSiliconInitLib}/SiliconInit.c (100%) rename
> Silicon/Intel/KabylakeSiliconPkg/Library/{SiliconInitLib =>
> PeiSiliconInitLib}/SiliconInitPreMem.c (100%)
>
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf
> b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.in
> f
> similarity index 91%
> rename from
> Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf
> rename to
> Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
> index 132080e876..ff83bf2835 100644
> --- a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSili
> +++ conInitLib.inf
> @@ -11,8 +11,9 @@
> BASE_NAME = SiliconInitLib FILE_GUID = 72CD3A7B-
> FEA5-4F5E-9165-4DD12187BB13 VERSION_STRING = 1.0-
> MODULE_TYPE = BASE+ MODULE_TYPE = PEIM
> LIBRARY_CLASS = SiliconInitLib+ # # The following information is for
> reference only and not required by the build tools. #diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInit.c
> b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c
> similarity index 100%
> rename from
> Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInit.c
> rename to
> Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitPreMem.c
> b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMe
> m.c
> similarity index 100%
> rename from
> Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitPreMem.c
> rename to
> Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMem.c
> --
> 2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 02/13] KabylakeOpenBoardPkg: Update location of SiliconInitLib
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 02/13] KabylakeOpenBoardPkg: Update location of SiliconInitLib Nate DeSimone
2019-11-14 15:15 ` Chiu, Chasel
@ 2019-11-16 2:53 ` Kubacki, Michael A
1 sibling, 0 replies; 44+ messages in thread
From: Kubacki, Michael A @ 2019-11-16 2:53 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io; +Cc: Chiu, Chasel, Jeremy Soller
Reviewed-by: Michael Kubacki <michael.a.kubacki@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Wednesday, November 13, 2019 10:07 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>; Jeremy Soller <jeremy@system76.com>
> Subject: [edk2-platforms] [PATCH V1 02/13] KabylakeOpenBoardPkg: Update
> location of SiliconInitLib
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Jeremy Soller <jeremy@system76.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc | 2
> +-
> .../Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> index e43c944201..2bc2b4126b 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> +++
> b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> @@ -105,7 +105,7 @@
> # Silicon Initialization Package
>
> #######################################
>
>
> ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLi
> b.inf
>
> -
> SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/SiliconInitLib/SiliconInitLib.i
> nf
>
> +
> SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSiliconI
> nitLib.inf
>
>
> SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLib
> Fsp/PeiSiliconPolicyInitLibFsp.inf
>
>
>
> #####################################
>
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> index 1ce473432a..77e4a6a610 100644
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> +++
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> @@ -133,7 +133,7 @@
> # Silicon Initialization Package
>
> #######################################
>
>
> ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLi
> b.inf
>
> -
> SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/SiliconInitLib/SiliconInitLib.i
> nf
>
> +
> SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSiliconI
> nitLib.inf
>
>
>
> !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
>
> #
>
> --
> 2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 03/13] KabylakeSiliconPkg: Cleanup old comments
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 03/13] KabylakeSiliconPkg: Cleanup old comments Nate DeSimone
2019-11-14 15:16 ` Chiu, Chasel
@ 2019-11-16 2:53 ` Kubacki, Michael A
2019-11-18 9:15 ` Chaganty, Rangasai V
2 siblings, 0 replies; 44+ messages in thread
From: Kubacki, Michael A @ 2019-11-16 2:53 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io
Cc: Chiu, Chasel, Chaganty, Rangasai V
Reviewed-by: Michael Kubacki <michael.a.kubacki@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Wednesday, November 13, 2019 10:07 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>; Chaganty, Rangasai V
> <rangasai.v.chaganty@intel.com>
> Subject: [edk2-platforms] [PATCH V1 03/13] KabylakeSiliconPkg: Cleanup old
> comments
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../Library/PeiSiliconInitLib/SiliconInitPreMem.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMe
> m.c
> b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMe
> m.c
> index 65a67a6795..384877fba3 100644
> ---
> a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMe
> m.c
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/Silicon
> +++ InitPreMem.c
> @@ -31,9 +31,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include
> <Library/PeiServicesTablePointerLib.h> #include <Library/PchSerialIoLib.h> -
> //@todo it should be moved to Si Pkg. /**- Early Platform PCH initialization+
> Early PCH initialization **/ VOID EarlySiliconInit (@@ -233,4 +232,3 @@
> SiliconInit (
> } }---
> 2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 04/13] CoffeeLakeSiliconPkg: Move TcoWdtHob.h
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 04/13] CoffeeLakeSiliconPkg: Move TcoWdtHob.h Nate DeSimone
2019-11-14 15:16 ` Chiu, Chasel
@ 2019-11-16 2:53 ` Kubacki, Michael A
2019-11-18 9:41 ` Chaganty, Rangasai V
2 siblings, 0 replies; 44+ messages in thread
From: Kubacki, Michael A @ 2019-11-16 2:53 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io
Cc: Chiu, Chasel, Chaganty, Rangasai V
Reviewed-by: Michael Kubacki <michael.a.kubacki@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Wednesday, November 13, 2019 10:07 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>; Chaganty, Rangasai V
> <rangasai.v.chaganty@intel.com>
> Subject: [edk2-platforms] [PATCH V1 04/13] CoffeeLakeSiliconPkg: Move
> TcoWdtHob.h
>
> Moves TcoWdtHob.h from WhiskeylakeOpenBoardPkg to
> CoffeelakeSiliconPkg.
> Oddly, gTcoWdtHobGuid was defined in CoffeelakeSiliconPkg/SiPkg.dec
> while the HOB definition itself was in WhiskeylakeOpenBoardPkg, this
> change cleans up the disparity.
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../Intel/CoffeelakeSiliconPkg}/Include/Guid/TcoWdtHob.h | 0
> 1 file changed, 0 insertions(+), 0 deletions(-) rename
> {Platform/Intel/WhiskeylakeOpenBoardPkg =>
> Silicon/Intel/CoffeelakeSiliconPkg}/Include/Guid/TcoWdtHob.h (100%)
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Guid/TcoWdtHob.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Guid/TcoWdtHob.h
> similarity index 100%
> rename from
> Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Guid/TcoWdtHob.h
> rename to Silicon/Intel/CoffeelakeSiliconPkg/Include/Guid/TcoWdtHob.h
> --
> 2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 05/13] CoffeelakeSiliconPkg: Add SiliconInitLib
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 05/13] CoffeelakeSiliconPkg: Add SiliconInitLib Nate DeSimone
2019-11-14 15:16 ` Chiu, Chasel
@ 2019-11-16 2:53 ` Kubacki, Michael A
2019-11-18 19:14 ` Chaganty, Rangasai V
2 siblings, 0 replies; 44+ messages in thread
From: Kubacki, Michael A @ 2019-11-16 2:53 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io
Cc: Chiu, Chasel, Chaganty, Rangasai V
Reviewed-by: Michael Kubacki <michael.a.kubacki@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Wednesday, November 13, 2019 10:07 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>; Chaganty, Rangasai V
> <rangasai.v.chaganty@intel.com>
> Subject: [edk2-platforms] [PATCH V1 05/13] CoffeelakeSiliconPkg: Add
> SiliconInitLib
>
> SiliconInitLib contains Silicon Init APIs that can be reused by BoardInitLib. It is
> expected that several implementations of BoardInitLib exist for a given SOC,
> these APIs allow the various BoardInitLib implementations to reuse common
> silicon initialization code. This matches the implementation already found in
> KabylakeSiliconPkg. This change also adds halting the TCO watch dog timer to
> PEI, which was previously done in SEC.
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../Include/Library/SiliconInitLib.h | 28 +++++
> .../PeiSiliconInitLib/PeiSiliconInitLib.inf | 46 ++++++++
> .../Library/PeiSiliconInitLib/SiliconInit.c | 19 +++
> .../PeiSiliconInitLib/SiliconInitPreMem.c | 109 ++++++++++++++++++
> 4 files changed, 202 insertions(+)
> create mode 100644
> Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.h
> create mode 100644
> Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.in
> f
> create mode 100644
> Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c
> create mode 100644
> Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMem
> .c
>
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.h
> new file mode 100644
> index 0000000000..a3411126a7
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.
> +++ h
> @@ -0,0 +1,28 @@
> +/** @file++Copyright (c) 2019, Intel Corporation. All rights
> +reserved.<BR>+SPDX-License-Identifier:
> +BSD-2-Clause-Patent++**/++#ifndef _SILICON_INIT_LIB_H_+#define
> +_SILICON_INIT_LIB_H_++#include <PiPei.h>++VOID+EarlySiliconInit (+
> +VOID+ );++VOID+SiliconInit (+ VOID+ );++VOID+LateSiliconInit (+
> +VOID+ );++#endif
> \ No newline at end of file
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.
> inf
> b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.
> inf
> new file mode 100644
> index 0000000000..47da5f608b
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSi
> +++ liconInitLib.inf
> @@ -0,0 +1,46 @@
> +### @file+#+# Copyright (c) 2019, Intel Corporation. All rights
> reserved.<BR>+#+# SPDX-License-Identifier: BSD-2-Clause-
> Patent+#+###++[Defines]+ INF_VERSION = 0x00010017+
> BASE_NAME = SiliconInitLib+ FILE_GUID = 82F2ACF0-
> 2EBE-48C8-AC58-9D0F8BC1E16E+ VERSION_STRING = 1.0+
> MODULE_TYPE = PEIM+ LIBRARY_CLASS =
> SiliconInitLib+#+# The following information is for reference only and not
> required by the build tools.+#+# VALID_ARCHITECTURES = IA32 X64 IPF
> EBC+#++[LibraryClasses]+ BaseLib+ BaseMemoryLib+ DebugLib+ HobLib+
> IoLib+ PcdLib+ PeiServicesLib+ PchCycleDecodingLib+
> PmcLib++[Packages]+ MdePkg/MdePkg.dec+
> CoffeelakeSiliconPkg/SiPkg.dec++[Sources]+ SiliconInit.c+
> SiliconInitPreMem.c++[Guids]+ gTcoWdtHobGuid ##
> CONSUMES++[Pcd]+ gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ##
> CONSUMES+ gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ##
> CONSUMESdiff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c
> b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c
> new file mode 100644
> index 0000000000..122c02a3e5
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/Silic
> +++ onInit.c
> @@ -0,0 +1,19 @@
> +/** @file+ Silicon Init APIs for MinPlatform BoardInitLib
> +implementations.++Copyright (c) 2019, Intel Corporation. All rights
> +reserved.<BR>+SPDX-License-Identifier:
> +BSD-2-Clause-Patent++**/++#include <PiPei.h>++/**+ Late PCH
> +Init+**/+VOID+LateSiliconInit (+ VOID+ )+{+}diff --git
> +a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconI
> +nitPreMem.c
> +b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconI
> +nitPreMem.c
> new file mode 100644
> index 0000000000..23e4a3d4a0
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/Silic
> +++ onInitPreMem.c
> @@ -0,0 +1,109 @@
> +/** @file+ Silicon Init APIs for MinPlatform BoardInitLib
> implementations.++Copyright (c) 2019, Intel Corporation. All rights
> reserved.<BR>+SPDX-License-Identifier: BSD-2-Clause-
> Patent++**/++#include <PiPei.h>+#include <Guid/TcoWdtHob.h>+#include
> <Library/IoLib.h>+#include <Library/DebugLib.h>+#include
> <Library/HobLib.h>+#include <Library/PcdLib.h>+#include
> <Library/PeiServicesLib.h>+#include
> <Library/PchCycleDecodingLib.h>+#include <Library/PmcLib.h>+#include
> <Register/PchRegsLpc.h>+#include <Register/PchRegsPmc.h>++/**+ Early
> PCH initialization+**/+VOID+EarlySiliconInit (+ VOID+ )+{+ UINT16
> Data16;+ UINT8 Data8;+ UINT8 TcoRebootHappened;+
> TCO_WDT_HOB *TcoWdtHobPtr;+ EFI_STATUS Status;++ ///+ /// LPC I/O
> Configuration+ ///+ PchLpcIoDecodeRangesSet (+
> (V_LPC_CFG_IOD_LPT_378 << N_LPC_CFG_IOD_LPT) |+
> (V_LPC_CFG_IOD_COMB_3E8 << N_LPC_CFG_IOD_COMB) |+
> (V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA)+ );++
> PchLpcIoEnableDecodingSet (+ B_LPC_CFG_IOE_ME2 |+
> B_LPC_CFG_IOE_SE |+ B_LPC_CFG_IOE_ME1 |+ B_LPC_CFG_IOE_KE |+
> B_LPC_CFG_IOE_HGE |+ B_LPC_CFG_IOE_LGE |+ B_LPC_CFG_IOE_FDE
> |+ B_LPC_CFG_IOE_PPE |+ B_LPC_CFG_IOE_CBE |+
> B_LPC_CFG_IOE_CAE+ );++ ///+ /// Halt the TCO timer+ ///+ Data16 =
> IoRead16 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT);+
> Data16 |= B_TCO_IO_TCO1_CNT_TMR_HLT;+ IoWrite16 (PcdGet16
> (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT, Data16);++ ///+ /// Read the
> Second TO status bit+ ///+ Data8 = IoRead8 (PcdGet16
> (PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS);+ if ((Data8 &
> B_TCO_IO_TCO2_STS_SECOND_TO) == B_TCO_IO_TCO2_STS_SECOND_TO)
> {+ TcoRebootHappened = 1;+ DEBUG ((DEBUG_INFO,
> "PlatformInitPreMem - TCO Second TO status bit is set. This might be a TCO
> reboot\n"));+ }+ else {+ TcoRebootHappened = 0;+ }++ ///+ /// Create
> HOB+ ///+ Status = PeiServicesCreateHob
> (EFI_HOB_TYPE_GUID_EXTENSION, sizeof(TCO_WDT_HOB), (VOID
> **)&TcoWdtHobPtr);+ if (!EFI_ERROR (Status)) {+ TcoWdtHobPtr-
> >Header.Name = gTcoWdtHobGuid;+ TcoWdtHobPtr-
> >TcoRebootHappened = TcoRebootHappened;+ }++ ///+ /// Clear the
> Second TO status bit+ ///+ IoWrite8 (PcdGet16 (PcdTcoBaseAddress) +
> R_TCO_IO_TCO2_STS, B_TCO_IO_TCO2_STS_SECOND_TO);+}++/**+
> Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal inversion
> registers++**/+VOID+SiliconInit (+ VOID+ )+{+ UINT16 ABase;++ ABase
> = PmcGetAcpiBase ();++ ///+ /// Clear all pending SMI. On S3 clear power
> button enable so it will not generate an SMI.+ ///+ IoWrite16 (ABase +
> R_ACPI_IO_PM1_EN, 0);+ IoWrite32 (ABase +
> R_ACPI_IO_GPE0_EN_127_96, 0);+}--
> 2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 06/13] WhiskeylakeOpenBoardPkg: Add SiliconInitLib APIs to BoardInitLib
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 06/13] WhiskeylakeOpenBoardPkg: Add SiliconInitLib APIs to BoardInitLib Nate DeSimone
2019-11-14 15:16 ` Chiu, Chasel
@ 2019-11-16 2:53 ` Kubacki, Michael A
1 sibling, 0 replies; 44+ messages in thread
From: Kubacki, Michael A @ 2019-11-16 2:53 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io; +Cc: Chiu, Chasel
Reviewed-by: Michael Kubacki <michael.a.kubacki@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Wednesday, November 13, 2019 10:07 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>
> Subject: [edk2-platforms] [PATCH V1 06/13] WhiskeylakeOpenBoardPkg:
> Add SiliconInitLib APIs to BoardInitLib
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../BoardInitLib/PeiBoardInitPostMemLib.inf | 1 +
> .../BoardInitLib/PeiBoardInitPreMemLib.inf | 1 +
> .../PeiMultiBoardInitPostMemLib.inf | 1 +
> .../PeiMultiBoardInitPreMemLib.inf | 2 +-
> .../PeiWhiskeylakeURvpInitPostMemLib.c | 6 +-
> .../PeiWhiskeylakeURvpInitPreMemLib.c | 89 ++-----------------
> .../BoardInitLib/WhiskeylakeURvpInit.h | 1 +
> .../WhiskeylakeURvp/OpenBoardPkg.dsc | 5 ++
> 8 files changed, 24 insertions(+), 82 deletions(-)
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiBoardInitPostMemLib.inf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiBoardInitPostMemLib.inf
> index 9bf4d127c5..affc5c56ad 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiBoardInitPostMemLib.inf
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiBoardInitPostMemLib.inf
> @@ -26,6 +26,7 @@
> HdaVerbTableLib
>
> MemoryAllocationLib
>
> PcdLib
>
> + SiliconInitLib
>
>
>
> [Packages]
>
> MinPlatformPkg/MinPlatformPkg.dec
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiBoardInitPreMemLib.inf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiBoardInitPreMemLib.inf
> index 4ab80f9eb3..40e20285e0 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiBoardInitPreMemLib.inf
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiBoardInitPreMemLib.inf
> @@ -23,6 +23,7 @@
> BaseMemoryLib
>
> MemoryAllocationLib
>
> PcdLib
>
> + SiliconInitLib
>
>
>
> [Packages]
>
> MinPlatformPkg/MinPlatformPkg.dec
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiMultiBoardInitPostMemLib.inf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiMultiBoardInitPostMemLib.inf
> index c043e32638..21dc2f70c0 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiMultiBoardInitPostMemLib.inf
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiMultiBoardInitPostMemLib.inf
> @@ -30,6 +30,7 @@
> PeiPlatformHookLib
>
> PeiPolicyInitLib
>
> PchInfoLib
>
> + SiliconInitLib
>
>
>
> [Packages]
>
> MinPlatformPkg/MinPlatformPkg.dec
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiMultiBoardInitPreMemLib.inf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiMultiBoardInitPreMemLib.inf
> index cd0315377a..7389f1dfcd 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiMultiBoardInitPreMemLib.inf
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiMultiBoardInitPreMemLib.inf
> @@ -31,6 +31,7 @@
> PeiPlatformHookLib
>
> PeiPolicyInitLib
>
> PlatformHookLib
>
> + SiliconInitLib
>
> StallPpiLib
>
>
>
> [Packages]
>
> @@ -57,7 +58,6 @@
>
>
> [Guids]
>
> gPchGeneralPreMemConfigGuid ## CONSUMES
>
> - gTcoWdtHobGuid ## CONSUMES
>
>
>
> [Pcd]
>
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
> index 9413620a4a..248a6657d5 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
> @@ -430,6 +430,10 @@ WhiskeylakeURvpBoardInitBeforeSiliconInit (
> //
>
> Status = UpdateChipsetInitPtr();
>
>
>
> + ///
>
> + /// Do Late PCH init
>
> + ///
>
> + LateSiliconInit ();
>
> +
>
> return EFI_SUCCESS;
>
> }
>
> -
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
> index 0124888244..055d731651 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
> @@ -45,7 +45,6 @@
> #include <Library/PciSegmentLib.h>
>
> #include <PeiPlatformHookLib.h>
>
> #include <FirwmareConfigurations.h>
>
> -#include <Guid/TcoWdtHob.h>
>
> #include <Library/OcWdtLib.h>
>
>
>
> ///
>
> @@ -232,50 +231,8 @@ BoardMiscInitPreMem(
> return EFI_SUCCESS;
>
> }
>
>
>
> -//@todo it should be moved to Si Pkg.
>
> -/**
>
> -Early Platform PCH initialization
>
> -**/
>
> -VOID
>
> -EarlyPlatformPchInit(
>
> - VOID
>
> -)
>
> -{
>
> - UINT8 Data8;
>
> - UINT8 TcoRebootHappened;
>
> - TCO_WDT_HOB *TcoWdtHobPtr;
>
> - EFI_STATUS Status;
>
> -
>
> - ///
>
> - /// Read the Second TO status bit
>
> - ///
>
> - Data8 = IoRead8(PcdGet16(PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS);
>
> - if ((Data8 & B_TCO_IO_TCO2_STS_SECOND_TO) ==
> B_TCO_IO_TCO2_STS_SECOND_TO) {
>
> - TcoRebootHappened = 1;
>
> - DEBUG((DEBUG_INFO, "PlatformInitPreMem - TCO Second TO status bit is
> set. This might be a TCO reboot\n"));
>
> - }
>
> - else {
>
> - TcoRebootHappened = 0;
>
> - }
>
> -
>
> - ///
>
> - /// Create HOB
>
> - ///
>
> - Status = PeiServicesCreateHob(EFI_HOB_TYPE_GUID_EXTENSION,
> sizeof(TCO_WDT_HOB), (VOID **)&TcoWdtHobPtr);
>
> - if (!EFI_ERROR(Status)) {
>
> - TcoWdtHobPtr->Header.Name = gTcoWdtHobGuid;
>
> - TcoWdtHobPtr->TcoRebootHappened = TcoRebootHappened;
>
> - }
>
> -
>
> - ///
>
> - /// Clear the Second TO status bit
>
> - ///
>
> - IoWrite8(PcdGet16(PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS,
> B_TCO_IO_TCO2_STS_SECOND_TO);
>
> -}
>
> -
>
> /**
>
> Board configuration initialization in the pre-memory boot phase.
>
> -
>
> **/
>
> VOID
>
> BoardConfigInitPreMem (
>
> @@ -341,7 +298,6 @@ PlatformInitPreMemCallBack(
> )
>
> {
>
> EFI_STATUS Status;
>
> - UINT16 ABase;
>
> UINT8 FwConfig;
>
>
>
> //
>
> @@ -378,16 +334,8 @@ PlatformInitPreMemCallBack(
> ///
>
> /// Configure GPIO and SIO
>
> ///
>
> - Status = BoardInitPreMem();
>
> - ASSERT_EFI_ERROR(Status);
>
> -
>
> - ABase = PmcGetAcpiBase();
>
> -
>
> - ///
>
> - /// Clear all pending SMI. On S3 clear power button enable so it will not
> generate an SMI.
>
> - ///
>
> - IoWrite16(ABase + R_ACPI_IO_PM1_EN, 0);
>
> - IoWrite32(ABase + R_ACPI_IO_GPE0_EN_127_96, 0);
>
> + Status = BoardInitPreMem ();
>
> + ASSERT_EFI_ERROR (Status);
>
>
>
> ///
>
> /// Install Pre Memory PPIs
>
> @@ -550,12 +498,6 @@ WhiskeylakeURvpInitPreMem (
> Status = InstallStallPpi();
>
> ASSERT_EFI_ERROR(Status);
>
>
>
> - ///@todo it should be moved to Si Pkg.
>
> - ///
>
> - /// Do Early PCH init
>
> - ///
>
> - EarlyPlatformPchInit();
>
> -
>
> //
>
> // Install PCH RESET PPI and EFI RESET2 PeiService
>
> //
>
> @@ -588,6 +530,11 @@ WhiskeylakeURvpBoardInitBeforeMemoryInit (
> VOID
>
> )
>
> {
>
> + ///
>
> + /// Do basic PCH init
>
> + ///
>
> + SiliconInit ();
>
> +
>
> WhiskeylakeURvpInitPreMem ();
>
>
>
> return EFI_SUCCESS;
>
> @@ -600,27 +547,9 @@ WhiskeylakeURvpBoardDebugInit (
> )
>
> {
>
> ///
>
> - /// LPC I/O Configuration
>
> + /// Do Early PCH init
>
> ///
>
> - PchLpcIoDecodeRangesSet (
>
> - (V_LPC_CFG_IOD_LPT_378 << N_LPC_CFG_IOD_LPT) |
>
> - (V_LPC_CFG_IOD_COMB_3E8 << N_LPC_CFG_IOD_COMB) |
>
> - (V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA)
>
> - );
>
> -
>
> - PchLpcIoEnableDecodingSet (
>
> - B_LPC_CFG_IOE_ME2 |
>
> - B_LPC_CFG_IOE_SE |
>
> - B_LPC_CFG_IOE_ME1 |
>
> - B_LPC_CFG_IOE_KE |
>
> - B_LPC_CFG_IOE_HGE |
>
> - B_LPC_CFG_IOE_LGE |
>
> - B_LPC_CFG_IOE_FDE |
>
> - B_LPC_CFG_IOE_PPE |
>
> - B_LPC_CFG_IOE_CBE |
>
> - B_LPC_CFG_IOE_CAE
>
> - );
>
> -
>
> + EarlySiliconInit ();
>
> return EFI_SUCCESS;
>
> }
>
>
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/WhiskeylakeURvpInit.h
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/WhiskeylakeURvpInit.h
> index 325bcb41df..d3a709b2a9 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/WhiskeylakeURvpInit.h
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/WhiskeylakeURvpInit.h
> @@ -15,6 +15,7 @@
> #include <Library/MemoryAllocationLib.h>
>
> #include <Library/DebugLib.h>
>
> #include <Library/GpioLib.h>
>
> +#include <Library/SiliconInitLib.h>
>
> #include <Ppi/SiPolicy.h>
>
> #include <PchHsioPtssTables.h>
>
>
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoard
> Pkg.dsc
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoard
> Pkg.dsc
> index cdaf47b6f7..3cd0478021 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoard
> Pkg.dsc
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoard
> Pkg.dsc
> @@ -154,6 +154,11 @@
>
> TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTi
> merLib.inf
>
>
>
> [LibraryClasses.common.PEIM]
>
> + #######################################
>
> + # Silicon Initialization Package
>
> + #######################################
>
> +
> SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSiliconI
> nitLib.inf
>
> +
>
> #######################################
>
> # Platform Package
>
> #######################################
>
> --
> 2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 07/13] WhiskeylakeOpenBoardPkg: Whitespace cleanup in BoardInitLib
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 07/13] WhiskeylakeOpenBoardPkg: Whitespace cleanup in BoardInitLib Nate DeSimone
2019-11-14 15:17 ` Chiu, Chasel
@ 2019-11-16 2:53 ` Kubacki, Michael A
1 sibling, 0 replies; 44+ messages in thread
From: Kubacki, Michael A @ 2019-11-16 2:53 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io; +Cc: Chiu, Chasel
Reviewed-by: Michael Kubacki <michael.a.kubacki@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Wednesday, November 13, 2019 10:07 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>
> Subject: [edk2-platforms] [PATCH V1 07/13] WhiskeylakeOpenBoardPkg:
> Whitespace cleanup in BoardInitLib
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../PeiWhiskeylakeURvpInitPostMemLib.c | 185 ++++++-------
> .../PeiWhiskeylakeURvpInitPreMemLib.c | 257 +++++++++---------
> 2 files changed, 216 insertions(+), 226 deletions(-)
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
> index 248a6657d5..827af6bb57 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
> @@ -33,16 +33,16 @@
> #include "WhiskeylakeURvpInit.h"
>
>
>
> EFI_STATUS
>
> -BoardFunctionInit(
>
> +BoardFunctionInit (
>
> IN UINT16 BoardId
>
> -);
>
> + );
>
>
>
> /**
>
> -GPIO init function for PEI post memory phase.
>
> + GPIO init function for PEI post memory phase.
>
>
>
> -@param[in] BoardId An unsigned integrer represent the board id.
>
> + @param[in] BoardId An unsigned integrer represent the board id.
>
>
>
> -@retval EFI_SUCCESS The function completed successfully.
>
> + @retval EFI_SUCCESS The function completed successfully.
>
> **/
>
> EFI_STATUS
>
> BoardGpioInit(
>
> @@ -72,48 +72,48 @@ BoardGpioInit(
> }
>
>
>
> /**
>
> -Touch panel GPIO init function for PEI post memory phase.
>
> + Touch panel GPIO init function for PEI post memory phase.
>
>
>
> -@param[in] BoardId An unsigned integrer represent the board id.
>
> + @param[in] BoardId An unsigned integrer represent the board id.
>
>
>
> -@retval EFI_SUCCESS The function completed successfully.
>
> + @retval EFI_SUCCESS The function completed successfully.
>
> **/
>
> EFI_STATUS
>
> -TouchPanelGpioInit(
>
> +TouchPanelGpioInit (
>
> IN UINT16 BoardId
>
> -)
>
> + )
>
> {
>
> switch (BoardId) {
>
> default:
>
> - PcdSet32S(PcdBoardGpioTableTouchPanel, 0);
>
> + PcdSet32S (PcdBoardGpioTableTouchPanel, 0);
>
> break;
>
> }
>
> return EFI_SUCCESS;
>
> }
>
>
>
> /**
>
> -Misc. init function for PEI post memory phase.
>
> + Misc. init function for PEI post memory phase.
>
>
>
> -@param[in] BoardId An unsigned integrer represent the board id.
>
> + @param[in] BoardId An unsigned integrer represent the board id.
>
>
>
> -@retval EFI_SUCCESS The function completed successfully.
>
> + @retval EFI_SUCCESS The function completed successfully.
>
> **/
>
> EFI_STATUS
>
> -BoardMiscInit(
>
> +BoardMiscInit (
>
> IN UINT16 BoardId
>
> -)
>
> + )
>
> {
>
> - PcdSetBoolS(PcdDebugUsbUartEnable, FALSE);
>
> + PcdSetBoolS (PcdDebugUsbUartEnable, FALSE);
>
>
>
> switch (BoardId) {
>
>
>
> case BoardIdWhiskeyLakeRvp:
>
>
>
> - PcdSetBoolS(PcdMipiCamGpioEnable, TRUE);
>
> + PcdSetBoolS (PcdMipiCamGpioEnable, TRUE);
>
> break;
>
>
>
> default:
>
> - PcdSetBoolS(PcdMipiCamGpioEnable, FALSE);
>
> + PcdSetBoolS (PcdMipiCamGpioEnable, FALSE);
>
> break;
>
> }
>
>
>
> @@ -121,25 +121,22 @@ BoardMiscInit(
> }
>
>
>
> /**
>
> -Security GPIO init function for PEI post memory phase.
>
> + Security GPIO init function for PEI post memory phase.
>
>
>
> -@param[in] BoardId An unsigned integrer represent the board id.
>
> + @param[in] BoardId An unsigned integrer represent the board id.
>
>
>
> -@retval EFI_SUCCESS The function completed successfully.
>
> + @retval EFI_SUCCESS The function completed successfully.
>
> **/
>
> EFI_STATUS
>
> BoardSecurityInit (
>
> IN UINT16 BoardId
>
> -)
>
> + )
>
> {
>
> switch (BoardId) {
>
> -
>
> case BoardIdWhiskeyLakeRvp:
>
> -
>
> // TPM interrupt connects to GPIO_CNL_H_GPP_A_7
>
> PcdSet32S (PcdTpm2CurrentIrqNum, 0x1F);
>
> break;
>
> -
>
> }
>
>
>
> return EFI_SUCCESS;
>
> @@ -147,7 +144,6 @@ BoardSecurityInit (
>
>
> /**
>
> Board configuration initialization in the post-memory boot phase.
>
> -
>
> **/
>
> VOID
>
> BoardConfigInit (
>
> @@ -178,27 +174,26 @@ BoardConfigInit (
> ASSERT_EFI_ERROR (Status);
>
> }
>
>
>
> -//@todo Review this functionality and if it is required for WHL SDS
>
> /**
>
> -Create the HOB for hotkey status for 'Attempt USB First' feature
>
> + Create the HOB for hotkey status for 'Attempt USB First' feature
>
>
>
> -@retval EFI_SUCCESS HOB Creating successful.
>
> -@retval Others HOB Creating failed.
>
> + @retval EFI_SUCCESS HOB Creating successful.
>
> + @retval Others HOB Creating failed.
>
> **/
>
> EFI_STATUS
>
> -CreateAttemptUsbFirstHotkeyInfoHob(
>
> +CreateAttemptUsbFirstHotkeyInfoHob (
>
> VOID
>
> -)
>
> + )
>
> {
>
> EFI_STATUS Status;
>
> ATTEMPT_USB_FIRST_HOTKEY_INFO AttemptUsbFirstHotkeyInfo;
>
>
>
> Status = EFI_SUCCESS;
>
>
>
> - ZeroMem(
>
> + ZeroMem (
>
> &AttemptUsbFirstHotkeyInfo,
>
> - sizeof(AttemptUsbFirstHotkeyInfo)
>
> - );
>
> + sizeof (AttemptUsbFirstHotkeyInfo)
>
> + );
>
>
>
> AttemptUsbFirstHotkeyInfo.RevisonId = 0;
>
> AttemptUsbFirstHotkeyInfo.HotkeyTriggered = FALSE;
>
> @@ -206,29 +201,29 @@ CreateAttemptUsbFirstHotkeyInfoHob(
> ///
>
> /// Build HOB for Attempt USB First feature
>
> ///
>
> - BuildGuidDataHob(
>
> + BuildGuidDataHob (
>
> &gAttemptUsbFirstHotkeyInfoHobGuid,
>
> &(AttemptUsbFirstHotkeyInfo),
>
> - sizeof(ATTEMPT_USB_FIRST_HOTKEY_INFO)
>
> - );
>
> + sizeof (ATTEMPT_USB_FIRST_HOTKEY_INFO)
>
> + );
>
>
>
> return Status;
>
> }
>
>
>
> /**
>
> -Search and identify the physical address of a
>
> -file module inside the FW_BINARIES_FV_SIGNED FV
>
> + Search and identify the physical address of a
>
> + file module inside the FW_BINARIES_FV_SIGNED FV
>
>
>
> -@retval EFI_SUCCESS If address has been found
>
> -@retval Others If address has not been found
>
> + @retval EFI_SUCCESS If address has been found
>
> + @retval Others If address has not been found
>
> **/
>
> EFI_STATUS
>
> -FindModuleInFlash2(
>
> +FindModuleInFlash2 (
>
> IN EFI_FIRMWARE_VOLUME_HEADER *FvHeader,
>
> IN EFI_GUID *GuidPtr,
>
> IN OUT UINT32 *ModulePtr,
>
> IN OUT UINT32 *ModuleSize
>
> -)
>
> + )
>
> {
>
> EFI_FFS_FILE_HEADER *FfsHeader;
>
> EFI_FV_FILE_INFO FileInfo;
>
> @@ -246,57 +241,57 @@ FindModuleInFlash2(
> //
>
> // Locate FV_IMAGE file type in the FW_BINARIES_FV_SIGNED firmware
> volume
>
> //
>
> - Status =
> PeiServicesFfsFindNextFile(EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE,
> FvHeader, &FileHandle);
>
> - if (EFI_ERROR(Status)) {
>
> + Status = PeiServicesFfsFindNextFile
> (EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE, FvHeader, &FileHandle);
>
> + if (EFI_ERROR (Status)) {
>
> // unable to find FV_IMAGE file in this FV
>
> break;
>
> }
>
>
>
> FfsHeader = (EFI_FFS_FILE_HEADER*)FileHandle;
>
> - DEBUG((DEBUG_INFO, "FfsHeader 0x%X:\n", FfsHeader));
>
> - DEBUG((DEBUG_INFO, " Name = 0x%g\n", &FfsHeader->Name));
>
> - DEBUG((DEBUG_INFO, " Type = 0x%X\n", FfsHeader->Type));
>
> - if (IS_FFS_FILE2(FfsHeader)) {
>
> - DEBUG((DEBUG_INFO, " Size = 0x%X\n", FFS_FILE2_SIZE(FfsHeader)));
>
> + DEBUG ((DEBUG_INFO, "FfsHeader 0x%X:\n", FfsHeader));
>
> + DEBUG ((DEBUG_INFO, " Name = 0x%g\n", &FfsHeader->Name));
>
> + DEBUG ((DEBUG_INFO, " Type = 0x%X\n", FfsHeader->Type));
>
> + if (IS_FFS_FILE2 (FfsHeader)) {
>
> + DEBUG ((DEBUG_INFO, " Size = 0x%X\n", FFS_FILE2_SIZE(FfsHeader)));
>
> }
>
> else {
>
> - DEBUG((DEBUG_INFO, " Size = 0x%X\n", FFS_FILE_SIZE(FfsHeader)));
>
> + DEBUG ((DEBUG_INFO, " Size = 0x%X\n", FFS_FILE_SIZE(FfsHeader)));
>
> }
>
>
>
> //
>
> // Locate FW_BINARIES_FV FV_IMAGE Section
>
> //
>
> - Status =
> PeiServicesFfsFindSectionData(EFI_SECTION_FIRMWARE_VOLUME_IMAGE,
> FileHandle, &FileBuffer);
>
> - if (EFI_ERROR(Status)) {
>
> + Status = PeiServicesFfsFindSectionData
> (EFI_SECTION_FIRMWARE_VOLUME_IMAGE, FileHandle, &FileBuffer);
>
> + if (EFI_ERROR (Status)) {
>
> // continue to search for the next FV_IMAGE file
>
> - DEBUG((DEBUG_INFO, "FW_BINARIES_FV section not found. Status =
> %r\n", Status));
>
> + DEBUG ((DEBUG_INFO, "FW_BINARIES_FV section not found. Status =
> %r\n", Status));
>
> continue;
>
> }
>
>
>
> SectionHeader = (EFI_COMMON_SECTION_HEADER *)FileBuffer;
>
> - DEBUG((DEBUG_INFO, "GUIDED SectionHeader 0x%X:\n",
>
> + DEBUG ((DEBUG_INFO, "GUIDED SectionHeader 0x%X:\n",
>
> (UINT32)(UINT8 *)SectionHeader));
>
> if (IS_SECTION2(SectionHeader)) {
>
> - DEBUG((DEBUG_INFO, " Guid = 0x%g\n",
>
> + DEBUG ((DEBUG_INFO, " Guid = 0x%g\n",
>
> &((EFI_GUID_DEFINED_SECTION2 *)SectionHeader)-
> >SectionDefinitionGuid));
>
> - DEBUG((DEBUG_INFO, " DataOfset = 0x%X\n",
>
> + DEBUG ((DEBUG_INFO, " DataOfset = 0x%X\n",
>
> ((EFI_GUID_DEFINED_SECTION2 *)SectionHeader)->DataOffset));
>
> }
>
> else {
>
> - DEBUG((DEBUG_INFO, " Guid = 0x%g\n",
>
> + DEBUG ((DEBUG_INFO, " Guid = 0x%g\n",
>
> &((EFI_GUID_DEFINED_SECTION *)SectionHeader)-
> >SectionDefinitionGuid));
>
> - DEBUG((DEBUG_INFO, " DataOfset = 0x%X\n",
>
> + DEBUG ((DEBUG_INFO, " DataOfset = 0x%X\n",
>
> ((EFI_GUID_DEFINED_SECTION *)SectionHeader)->DataOffset));
>
> }
>
> - DEBUG((DEBUG_INFO, " Type = 0x%X\n", SectionHeader->Type));
>
> + DEBUG ((DEBUG_INFO, " Type = 0x%X\n", SectionHeader->Type));
>
>
>
> //
>
> // Locate Firmware File System file within Firmware Volume
>
> //
>
> - Status = PeiServicesFfsFindFileByName(GuidPtr, FileBuffer, (VOID
> **)&FfsHeader);
>
> - if (EFI_ERROR(Status)) {
>
> + Status = PeiServicesFfsFindFileByName (GuidPtr, FileBuffer, (VOID
> **)&FfsHeader);
>
> + if (EFI_ERROR (Status)) {
>
> // continue to search for the next FV_IMAGE file
>
> - DEBUG((DEBUG_INFO, "Module not found. Status = %r\n", Status));
>
> + DEBUG ((DEBUG_INFO, "Module not found. Status = %r\n", Status));
>
> continue;
>
> }
>
>
>
> @@ -305,10 +300,10 @@ FindModuleInFlash2(
> //
>
> // Get File Information
>
> //
>
> - Status = PeiServicesFfsGetFileInfo(FfsHeader, &FileInfo);
>
> - if (!EFI_ERROR(Status)) {
>
> + Status = PeiServicesFfsGetFileInfo (FfsHeader, &FileInfo);
>
> + if (!EFI_ERROR (Status)) {
>
> *ModuleSize = (UINT32)FileInfo.BufferSize;
>
> - DEBUG((DEBUG_INFO, "Module {0x%g} found at = 0x%X, Size = 0x%X\n",
>
> + DEBUG ((DEBUG_INFO, "Module {0x%g} found at = 0x%X, Size =
> 0x%X\n",
>
> &FfsHeader->Name, *ModulePtr, *ModuleSize));
>
> return Status;
>
> }
>
> @@ -318,15 +313,15 @@ FindModuleInFlash2(
> }
>
>
>
> /**
>
> -Get the ChipsetInit Binary pointer.
>
> + Get the ChipsetInit Binary pointer.
>
>
>
> -@retval EFI_SUCCESS - ChipsetInit Binary found.
>
> -@retval EFI_NOT_FOUND - ChipsetInit Binary not found.
>
> + @retval EFI_SUCCESS - ChipsetInit Binary found.
>
> + @retval EFI_NOT_FOUND - ChipsetInit Binary not found.
>
> **/
>
> EFI_STATUS
>
> -UpdateChipsetInitPtr(
>
> +UpdateChipsetInitPtr (
>
> VOID
>
> -)
>
> + )
>
> {
>
> EFI_STATUS Status;
>
> PCH_STEPPING PchStep;
>
> @@ -339,18 +334,18 @@ UpdateChipsetInitPtr(
>
>
> ModuleAddr = 0;
>
> ModuleSize = 0;
>
> - PchStep = PchStepping();
>
> + PchStep = PchStepping ();
>
>
>
> - Status = PeiServicesLocatePpi(
>
> + Status = PeiServicesLocatePpi (
>
> &gSiPolicyPpiGuid,
>
> 0,
>
> NULL,
>
> (VOID **)&SiPolicyPpi
>
> - );
>
> - ASSERT_EFI_ERROR(Status);
>
> + );
>
> + ASSERT_EFI_ERROR (Status);
>
>
>
> - Status = GetConfigBlock((VOID *)SiPolicyPpi, &gHsioConfigGuid, (VOID
> *)&HsioConfig);
>
> - ASSERT_EFI_ERROR(Status);
>
> + Status = GetConfigBlock ((VOID *)SiPolicyPpi, &gHsioConfigGuid, (VOID
> *)&HsioConfig);
>
> + ASSERT_EFI_ERROR (Status);
>
>
>
> ChipsetInitBinaryGuidPtr = NULL;
>
> if (IsPchLp()) {
>
> @@ -358,22 +353,20 @@ UpdateChipsetInitPtr(
> case PCH_D0:
>
> case PCH_D1:
>
> ChipsetInitBinaryGuidPtr = &gCnlPchLpChipsetInitTableDxGuid;
>
> - DEBUG((DEBUG_INFO, "Using CnlPchLpChipsetInitTable_Dx table \n"));
>
> + DEBUG ((DEBUG_INFO, "Using CnlPchLpChipsetInitTable_Dx table
> \n"));
>
> break;
>
> default:
>
> return EFI_NOT_FOUND;
>
> }
>
> - }
>
> - else {
>
> + } else {
>
> return EFI_NOT_FOUND;
>
> }
>
>
>
> //
>
> // Locate Firmware Volume header
>
> //
>
> - // FvHeader = (EFI_FIRMWARE_VOLUME_HEADER
> *)(UINTN)GetFvBinaryBase();
>
> - FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *)
> FixedPcdGet32(PcdFlashFvPostMemoryBase);
>
> - Status = FindModuleInFlash2(FvHeader, ChipsetInitBinaryGuidPtr,
> &ModuleAddr, &ModuleSize);
>
> + FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *) FixedPcdGet32
> (PcdFlashFvPostMemoryBase);
>
> + Status = FindModuleInFlash2 (FvHeader, ChipsetInitBinaryGuidPtr,
> &ModuleAddr, &ModuleSize);
>
> //
>
> // Get ChipsetInit Binary Pointer
>
> //
>
> @@ -384,8 +377,8 @@ UpdateChipsetInitPtr(
> //
>
> HsioConfig->ChipsetInitBinLen = ModuleSize;
>
>
>
> - DEBUG((DEBUG_INFO, "ChipsetInit Binary Location: %x\n", HsioConfig-
> >ChipsetInitBinPtr));
>
> - DEBUG((DEBUG_INFO, "ChipsetInit Binary Size: %x\n", HsioConfig-
> >ChipsetInitBinLen));
>
> + DEBUG ((DEBUG_INFO, "ChipsetInit Binary Location: %x\n", HsioConfig-
> >ChipsetInitBinPtr));
>
> + DEBUG ((DEBUG_INFO, "ChipsetInit Binary Size: %x\n", HsioConfig-
> >ChipsetInitBinLen));
>
>
>
> return Status;
>
> }
>
> @@ -401,34 +394,34 @@ WhiskeylakeURvpBoardInitBeforeSiliconInit (
> VOID
>
> )
>
> {
>
> - EFI_STATUS Status;
>
> - UINT8 FwConfig;
>
> + EFI_STATUS Status;
>
> + UINT8 FwConfig;
>
>
>
> - BoardConfigInit();
>
> + BoardConfigInit ();
>
> //
>
> // Configure GPIO and SIO
>
> //
>
> - Status = BoardInit();
>
> - ASSERT_EFI_ERROR(Status);
>
> + Status = BoardInit ();
>
> + ASSERT_EFI_ERROR (Status);
>
>
>
> FwConfig = FwConfigProduction;
>
> - PeiPolicyInit(FwConfig);
>
> + PeiPolicyInit (FwConfig);
>
>
>
> //
>
> // Create USB Boot First hotkey information HOB
>
> //
>
> - CreateAttemptUsbFirstHotkeyInfoHob();
>
> + CreateAttemptUsbFirstHotkeyInfoHob ();
>
>
>
> //
>
> // Initializing Platform Specific Programming
>
> //
>
> - Status = PlatformSpecificInit();
>
> + Status = PlatformSpecificInit ();
>
> ASSERT_EFI_ERROR(Status);
>
>
>
> //
>
> // Update ChipsetInitPtr
>
> //
>
> - Status = UpdateChipsetInitPtr();
>
> + Status = UpdateChipsetInitPtr ();
>
>
>
> ///
>
> /// Do Late PCH init
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
> index 055d731651..75813ff351 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Boa
> rdInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
> @@ -68,84 +68,84 @@ GLOBAL_REMOVE_IF_UNREFERENCED const UINT16
> RcompResistorSklRvp1[SA_MRC_MAX_RCOMP
> GLOBAL_REMOVE_IF_UNREFERENCED const UINT16
> RcompTargetSklRvp1[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 40, 23,
> 40 };
>
>
>
> GLOBAL_REMOVE_IF_UNREFERENCED MEMORY_MAP MmioMap[] = {
>
> - { FixedPcdGet64(PcdApicLocalAddress),
> FixedPcdGet32(PcdApicLocalMmioSize) },
>
> - { FixedPcdGet64(PcdMchBaseAddress), FixedPcdGet32(PcdMchMmioSize)
> },
>
> - { FixedPcdGet64(PcdDmiBaseAddress), FixedPcdGet32(PcdDmiMmioSize)
> },
>
> - { FixedPcdGet64(PcdEpBaseAddress), FixedPcdGet32(PcdEpMmioSize) },
>
> - { FixedPcdGet64(PcdGdxcBaseAddress),
> FixedPcdGet32(PcdGdxcMmioSize) }
>
> + { FixedPcdGet64 (PcdApicLocalAddress), FixedPcdGet32
> (PcdApicLocalMmioSize) },
>
> + { FixedPcdGet64 (PcdMchBaseAddress), FixedPcdGet32
> (PcdMchMmioSize) },
>
> + { FixedPcdGet64 (PcdDmiBaseAddress), FixedPcdGet32
> (PcdDmiMmioSize) },
>
> + { FixedPcdGet64 (PcdEpBaseAddress), FixedPcdGet32 (PcdEpMmioSize)
> },
>
> + { FixedPcdGet64 (PcdGdxcBaseAddress), FixedPcdGet32
> (PcdGdxcMmioSize) }
>
> };
>
>
>
> EFI_STATUS
>
> -MrcConfigInit(
>
> +MrcConfigInit (
>
> IN UINT16 BoardId
>
> -);
>
> + );
>
>
>
> EFI_STATUS
>
> -SaGpioConfigInit(
>
> +SaGpioConfigInit (
>
> IN UINT16 BoardId
>
> -);
>
> + );
>
>
>
> EFI_STATUS
>
> - SaMiscConfigInit(
>
> -IN UINT16 BoardId
>
> -);
>
> +SaMiscConfigInit (
>
> + IN UINT16 BoardId
>
> + );
>
>
>
> EFI_STATUS
>
> - RootPortClkInfoInit(
>
> -IN UINT16 BoardId
>
> -);
>
> +RootPortClkInfoInit (
>
> + IN UINT16 BoardId
>
> + );
>
>
>
> EFI_STATUS
>
> - UsbConfigInit(
>
> -IN UINT16 BoardId
>
> -);
>
> +UsbConfigInit (
>
> + IN UINT16 BoardId
>
> + );
>
>
>
> EFI_STATUS
>
> -GpioGroupTierInit(
>
> +GpioGroupTierInit (
>
> IN UINT16 BoardId
>
> -);
>
> + );
>
>
>
> EFI_STATUS
>
> -GpioTablePreMemInit(
>
> +GpioTablePreMemInit (
>
> IN UINT16 BoardId
>
> -);
>
> + );
>
>
>
> EFI_STATUS
>
> -PchPmConfigInit(
>
> +PchPmConfigInit (
>
> IN UINT16 BoardId
>
> -);
>
> + );
>
>
>
> EFI_STATUS
>
> -SaDisplayConfigInit(
>
> +SaDisplayConfigInit (
>
> IN UINT16 BoardId
>
> -);
>
> + );
>
>
>
> EFI_STATUS
>
> -BoardFunctionInitPreMem(
>
> +BoardFunctionInitPreMem (
>
> IN UINT16 BoardId
>
> -);
>
> + );
>
>
>
> EFI_STATUS
>
> EFIAPI
>
> -PlatformInitPreMemCallBack(
>
> +PlatformInitPreMemCallBack (
>
> IN CONST EFI_PEI_SERVICES **PeiServices,
>
> IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
>
> IN VOID *Ppi
>
> -);
>
> + );
>
>
>
> EFI_STATUS
>
> EFIAPI
>
> -MemoryDiscoveredPpiNotify(
>
> +MemoryDiscoveredPpiNotify (
>
> IN CONST EFI_PEI_SERVICES **PeiServices,
>
> IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
>
> IN VOID *Ppi
>
> -);
>
> + );
>
>
>
> EFI_STATUS
>
> EFIAPI
>
> -PchReset(
>
> +PchReset (
>
> IN CONST EFI_PEI_SERVICES **PeiServices
>
> -);
>
> + );
>
>
>
> static EFI_PEI_RESET_PPI mResetPpi = {
>
> PchReset
>
> @@ -172,16 +172,16 @@ static EFI_PEI_NOTIFY_DESCRIPTOR
> mMemDiscoveredNotifyList = {
> };
>
>
>
> /**
>
> -Board misc init function for PEI pre-memory phase.
>
> + Board misc init function for PEI pre-memory phase.
>
>
>
> -@param[in] BoardId An unsigned integer represent the board id.
>
> + @param[in] BoardId An unsigned integer represent the board id.
>
>
>
> -@retval EFI_SUCCESS The function completed successfully.
>
> + @retval EFI_SUCCESS The function completed successfully.
>
> **/
>
> EFI_STATUS
>
> -BoardMiscInitPreMem(
>
> +BoardMiscInitPreMem (
>
> IN UINT16 BoardId
>
> -)
>
> + )
>
> {
>
> PCD64_BLOB PcdData;
>
>
>
> @@ -211,22 +211,22 @@ BoardMiscInitPreMem(
> // power. An alternative way to contol modem power is to toggle
> FCP_OFF via GPP_D13
>
> // but board rework is required.
>
> //
>
> - PcdSet32S(PcdWwanFullCardPowerOffGpio, GPIO_CNL_LP_GPP_D16);
>
> - PcdSet32S(PcdWwanBbrstGpio, GPIO_CNL_LP_GPP_F1);
>
> - PcdSet32S(PcdWwanPerstGpio, GPIO_CNL_LP_GPP_E15);
>
> - PcdSet8S(PcdWwanPerstGpioPolarity, 1);
>
> + PcdSet32S (PcdWwanFullCardPowerOffGpio, GPIO_CNL_LP_GPP_D16);
>
> + PcdSet32S (PcdWwanBbrstGpio, GPIO_CNL_LP_GPP_F1);
>
> + PcdSet32S (PcdWwanPerstGpio, GPIO_CNL_LP_GPP_E15);
>
> + PcdSet8S (PcdWwanPerstGpioPolarity, 1);
>
> break;
>
>
>
> default:
>
> break;
>
> }
>
>
>
> - PcdSet64S(PcdRecoveryModeGpio, PcdData.Blob);
>
> + PcdSet64S (PcdRecoveryModeGpio, PcdData.Blob);
>
>
>
> //
>
> // Pc8374SioKbc Present
>
> //
>
> - PcdSetBoolS(PcdPc8374SioKbcPresent, FALSE);
>
> + PcdSetBoolS (PcdPc8374SioKbcPresent, FALSE);
>
>
>
> return EFI_SUCCESS;
>
> }
>
> @@ -279,23 +279,23 @@ BoardConfigInitPreMem (
> }
>
>
>
> /**
>
> -This function handles PlatformInit task after PeiReadOnlyVariable2 PPI
> produced
>
> + This function handles PlatformInit task after PeiReadOnlyVariable2 PPI
> produced
>
>
>
> -@param[in] PeiServices Pointer to PEI Services Table.
>
> -@param[in] NotifyDesc Pointer to the descriptor for the Notification
> event that
>
> - caused this function to execute.
>
> -@param[in] Ppi Pointer to the PPI data associated with this function.
>
> + @param[in] PeiServices Pointer to PEI Services Table.
>
> + @param[in] NotifyDesc Pointer to the descriptor for the Notification
> event that
>
> + caused this function to execute.
>
> + @param[in] Ppi Pointer to the PPI data associated with this function.
>
>
>
> -@retval EFI_SUCCESS The function completes successfully
>
> -@retval others
>
> + @retval EFI_SUCCESS The function completes successfully
>
> + @retval others Failure
>
> **/
>
> EFI_STATUS
>
> EFIAPI
>
> -PlatformInitPreMemCallBack(
>
> +PlatformInitPreMemCallBack (
>
> IN CONST EFI_PEI_SERVICES **PeiServices,
>
> IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
>
> IN VOID *Ppi
>
> -)
>
> + )
>
> {
>
> EFI_STATUS Status;
>
> UINT8 FwConfig;
>
> @@ -303,33 +303,33 @@ PlatformInitPreMemCallBack(
> //
>
> // Init Board Config Pcd.
>
> //
>
> - BoardConfigInitPreMem();
>
> + BoardConfigInitPreMem ();
>
>
>
> - DEBUG((DEBUG_ERROR, "Fail to get System Configuration and set the
> configuration to production mode!\n"));
>
> + DEBUG ((DEBUG_ERROR, "Fail to get System Configuration and set the
> configuration to production mode!\n"));
>
> FwConfig = FwConfigProduction;
>
> - PcdSetBoolS(PcdPcieWwanEnable, FALSE);
>
> - PcdSetBoolS(PcdWwanResetWorkaround, FALSE);
>
> + PcdSetBoolS (PcdPcieWwanEnable, FALSE);
>
> + PcdSetBoolS (PcdWwanResetWorkaround, FALSE);
>
>
>
> //
>
> // Early Board Configuration before memory is ready.
>
> //
>
> - Status = BoardInitEarlyPreMem();
>
> - ASSERT_EFI_ERROR(Status);
>
> + Status = BoardInitEarlyPreMem ();
>
> + ASSERT_EFI_ERROR (Status);
>
>
>
> ///
>
> /// If there was unexpected reset but no WDT expiration and no resume
> from S3/S4,
>
> /// clear unexpected reset status and enforce expiration. This is to inform
> Firmware
>
> /// which has no access to unexpected reset status bit, that something
> went wrong.
>
> ///
>
> - OcWdtResetCheck();
>
> + OcWdtResetCheck ();
>
>
>
> - Status = OcWdtInit();
>
> - ASSERT_EFI_ERROR(Status);
>
> + Status = OcWdtInit ();
>
> + ASSERT_EFI_ERROR (Status);
>
>
>
> //
>
> // Initialize Intel PEI Platform Policy
>
> //
>
> - PeiPolicyInitPreMem(FwConfig);
>
> + PeiPolicyInitPreMem (FwConfig);
>
>
>
> ///
>
> /// Configure GPIO and SIO
>
> @@ -340,56 +340,55 @@ PlatformInitPreMemCallBack(
> ///
>
> /// Install Pre Memory PPIs
>
> ///
>
> - Status = PeiServicesInstallPpi(&mPreMemPpiList[0]);
>
> - ASSERT_EFI_ERROR(Status);
>
> + Status = PeiServicesInstallPpi (&mPreMemPpiList[0]);
>
> + ASSERT_EFI_ERROR (Status);
>
>
>
> return Status;
>
> }
>
>
>
> /**
>
> -Provide hard reset PPI service.
>
> -To generate full hard reset, write 0x0E to PCH RESET_GENERATOR_PORT
> (0xCF9).
>
> + Provide hard reset PPI service.
>
> + To generate full hard reset, write 0x0E to PCH RESET_GENERATOR_PORT
> (0xCF9).
>
>
>
> -@param[in] PeiServices General purpose services available to every
> PEIM.
>
> + @param[in] PeiServices General purpose services available to every
> PEIM.
>
>
>
> -@retval Not return System reset occured.
>
> -@retval EFI_DEVICE_ERROR Device error, could not reset the system.
>
> + @retval Not return System reset occured.
>
> + @retval EFI_DEVICE_ERROR Device error, could not reset the system.
>
> **/
>
> EFI_STATUS
>
> EFIAPI
>
> -PchReset(
>
> +PchReset (
>
> IN CONST EFI_PEI_SERVICES **PeiServices
>
> -)
>
> + )
>
> {
>
> - DEBUG((DEBUG_INFO, "Perform Cold Reset\n"));
>
> - IoWrite8(RESET_GENERATOR_PORT, 0x0E);
>
> + DEBUG ((DEBUG_INFO, "Perform Cold Reset\n"));
>
> + IoWrite8 (RESET_GENERATOR_PORT, 0x0E);
>
>
>
> - CpuDeadLoop();
>
> + CpuDeadLoop ();
>
>
>
> ///
>
> /// System reset occured, should never reach at this line.
>
> ///
>
> - ASSERT_EFI_ERROR(EFI_DEVICE_ERROR);
>
> -
>
> + ASSERT_EFI_ERROR (EFI_DEVICE_ERROR);
>
> return EFI_DEVICE_ERROR;
>
> }
>
>
>
> /**
>
> -Install Firmware Volume Hob's once there is main memory
>
> + Install Firmware Volume Hob's once there is main memory
>
>
>
> -@param[in] PeiServices General purpose services available to every
> PEIM.
>
> -@param[in] NotifyDescriptor Notify that this module published.
>
> -@param[in] Ppi PPI that was installed.
>
> + @param[in] PeiServices General purpose services available to every
> PEIM.
>
> + @param[in] NotifyDescriptor Notify that this module published.
>
> + @param[in] Ppi PPI that was installed.
>
>
>
> -@retval EFI_SUCCESS The function completed successfully.
>
> + @retval EFI_SUCCESS The function completed successfully.
>
> **/
>
> EFI_STATUS
>
> EFIAPI
>
> -MemoryDiscoveredPpiNotify(
>
> +MemoryDiscoveredPpiNotify (
>
> IN CONST EFI_PEI_SERVICES **PeiServices,
>
> IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
>
> IN VOID *Ppi
>
> -)
>
> + )
>
> {
>
> EFI_STATUS Status;
>
> EFI_BOOT_MODE BootMode;
>
> @@ -400,12 +399,12 @@ MemoryDiscoveredPpiNotify(
>
>
> Index = 0;
>
>
>
> - Status = PeiServicesGetBootMode(&BootMode);
>
> - ASSERT_EFI_ERROR(Status);
>
> + Status = PeiServicesGetBootMode (&BootMode);
>
> + ASSERT_EFI_ERROR (Status);
>
>
>
> - AsmCpuid(0x80000000, &RegEax, NULL, NULL, NULL);
>
> + AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
>
> if (RegEax >= 0x80000008) {
>
> - AsmCpuid(0x80000008, &RegEax, NULL, NULL, NULL);
>
> + AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
>
> PhysicalAddressBits = (UINT8)RegEax;
>
> }
>
> else {
>
> @@ -415,69 +414,69 @@ MemoryDiscoveredPpiNotify(
> ///
>
> /// Create a CPU hand-off information
>
> ///
>
> - BuildCpuHob(PhysicalAddressBits, 16);
>
> + BuildCpuHob (PhysicalAddressBits, 16);
>
>
>
> ///
>
> /// Build Memory Mapped IO Resource which is used to build E820 Table in
> LegacyBios.
>
> ///
>
> - PcieMmioMap.BaseAddress = FixedPcdGet64(PcdPciExpressBaseAddress);
>
> - PcieMmioMap.Length = PcdGet32(PcdPciExpressRegionLength);
>
> + PcieMmioMap.BaseAddress = FixedPcdGet64
> (PcdPciExpressBaseAddress);
>
> + PcieMmioMap.Length = PcdGet32 (PcdPciExpressRegionLength);
>
>
>
> - BuildResourceDescriptorHob(
>
> + BuildResourceDescriptorHob (
>
> EFI_RESOURCE_MEMORY_MAPPED_IO,
>
> - (EFI_RESOURCE_ATTRIBUTE_PRESENT |
>
> - EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
>
> - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
>
> + (EFI_RESOURCE_ATTRIBUTE_PRESENT |
>
> + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
>
> + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
>
> PcieMmioMap.BaseAddress,
>
> PcieMmioMap.Length
>
> - );
>
> - BuildMemoryAllocationHob(
>
> + );
>
> + BuildMemoryAllocationHob (
>
> PcieMmioMap.BaseAddress,
>
> PcieMmioMap.Length,
>
> EfiMemoryMappedIO
>
> - );
>
> + );
>
> for (Index = 0; Index < sizeof(MmioMap) / (sizeof(MEMORY_MAP));
> Index++) {
>
> - BuildResourceDescriptorHob(
>
> + BuildResourceDescriptorHob (
>
> EFI_RESOURCE_MEMORY_MAPPED_IO,
>
> - (EFI_RESOURCE_ATTRIBUTE_PRESENT |
>
> - EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
>
> - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
>
> + (EFI_RESOURCE_ATTRIBUTE_PRESENT |
>
> + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
>
> + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
>
> MmioMap[Index].BaseAddress,
>
> MmioMap[Index].Length
>
> - );
>
> - BuildMemoryAllocationHob(
>
> + );
>
> + BuildMemoryAllocationHob (
>
> MmioMap[Index].BaseAddress,
>
> MmioMap[Index].Length,
>
> EfiMemoryMappedIO
>
> - );
>
> + );
>
> }
>
>
>
> //
>
> // Report resource HOB for flash FV
>
> //
>
> - BuildResourceDescriptorHob(
>
> + BuildResourceDescriptorHob (
>
> EFI_RESOURCE_MEMORY_MAPPED_IO,
>
> - (EFI_RESOURCE_ATTRIBUTE_PRESENT |
>
> - EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
>
> - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
>
> - (UINTN)FixedPcdGet32(PcdFlashAreaBaseAddress),
>
> - (UINTN)FixedPcdGet32(PcdFlashAreaSize)
>
> - );
>
> - BuildMemoryAllocationHob(
>
> - (UINTN)FixedPcdGet32(PcdFlashAreaBaseAddress),
>
> - (UINTN)FixedPcdGet32(PcdFlashAreaSize),
>
> + (EFI_RESOURCE_ATTRIBUTE_PRESENT |
>
> + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
>
> + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
>
> + (UINTN) FixedPcdGet32 (PcdFlashAreaBaseAddress),
>
> + (UINTN) FixedPcdGet32 (PcdFlashAreaSize)
>
> + );
>
> +
>
> + BuildMemoryAllocationHob (
>
> + (UINTN) FixedPcdGet32 (PcdFlashAreaBaseAddress),
>
> + (UINTN) FixedPcdGet32 (PcdFlashAreaSize),
>
> EfiMemoryMappedIO
>
> - );
>
> + );
>
>
>
> - BuildFvHob(
>
> - (UINTN)FixedPcdGet32(PcdFlashAreaBaseAddress),
>
> - (UINTN)FixedPcdGet32(PcdFlashAreaSize)
>
> - );
>
> + BuildFvHob (
>
> + (UINTN)FixedPcdGet32 (PcdFlashAreaBaseAddress),
>
> + (UINTN)FixedPcdGet32 (PcdFlashAreaSize)
>
> + );
>
>
>
> return Status;
>
> }
>
>
>
> -
>
> /**
>
> Board configuration init function for PEI pre-memory phase.
>
>
>
> @@ -495,26 +494,26 @@ WhiskeylakeURvpInitPreMem (
> ///
>
> /// Install Stall PPI
>
> ///
>
> - Status = InstallStallPpi();
>
> - ASSERT_EFI_ERROR(Status);
>
> + Status = InstallStallPpi ();
>
> + ASSERT_EFI_ERROR (Status);
>
>
>
> //
>
> // Install PCH RESET PPI and EFI RESET2 PeiService
>
> //
>
> - Status = PchInitializeReset();
>
> - ASSERT_EFI_ERROR(Status);
>
> + Status = PchInitializeReset ();
>
> + ASSERT_EFI_ERROR (Status);
>
>
>
> ///
>
> /// Performing PlatformInitPreMemCallBack after PeiReadOnlyVariable2
> PPI produced
>
> ///
>
> - Status = PeiServicesNotifyPpi(&mPreMemNotifyList);
>
> + Status = PeiServicesNotifyPpi (&mPreMemNotifyList);
>
>
>
> ///
>
> /// After code reorangized, memorycallback will run because the PPI is
> already
>
> /// installed when code run to here, it is supposed that the
> InstallEfiMemory is
>
> /// done before.
>
> ///
>
> - Status = PeiServicesNotifyPpi(&mMemDiscoveredNotifyList);
>
> + Status = PeiServicesNotifyPpi (&mMemDiscoveredNotifyList);
>
>
>
> return EFI_SUCCESS;
>
> }
>
> @@ -561,5 +560,3 @@ WhiskeylakeURvpBoardBootModeDetect (
> {
>
> return BOOT_WITH_FULL_CONFIGURATION;
>
> }
>
> -
>
> -
>
> --
> 2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 08/13] WhiskeylakeOpenBoardPkg: Remove SecFspWrapperPlatformSecLib override
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 08/13] WhiskeylakeOpenBoardPkg: Remove SecFspWrapperPlatformSecLib override Nate DeSimone
2019-11-14 15:17 ` Chiu, Chasel
@ 2019-11-16 2:53 ` Kubacki, Michael A
1 sibling, 0 replies; 44+ messages in thread
From: Kubacki, Michael A @ 2019-11-16 2:53 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io; +Cc: Chiu, Chasel
Reviewed-by: Michael Kubacki <michael.a.kubacki@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Wednesday, November 13, 2019 10:07 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>
> Subject: [edk2-platforms] [PATCH V1 08/13] WhiskeylakeOpenBoardPkg:
> Remove SecFspWrapperPlatformSecLib override
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../FspWrapperPlatformSecLib.c | 163 --------
> .../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 40 --
> .../SecFspWrapperPlatformSecLib/Ia32/Fsp.h | 43 ---
> .../Ia32/PeiCoreEntry.nasm | 130 -------
> .../Ia32/SecEntry.nasm | 361 ------------------
> .../Ia32/Stack.nasm | 72 ----
> .../PlatformInit.c | 54 ---
> .../SecFspWrapperPlatformSecLib.inf | 97 -----
> .../SecGetPerformance.c | 90 -----
> .../SecPlatformInformation.c | 79 ----
> .../SecRamInitData.c | 37 --
> .../SecTempRamDone.c | 48 ---
> .../WhiskeylakeURvp/OpenBoardPkg.dsc | 2 +-
> 13 files changed, 1 insertion(+), 1215 deletions(-) delete mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/FspWrapperPlatformSecLib.c
> delete mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/FsptCoreUpd.h
> delete mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/Ia32/Fsp.h
> delete mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/Ia32/PeiCoreEntry.nasm
> delete mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/Ia32/SecEntry.nasm
> delete mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/Ia32/Stack.nasm
> delete mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/PlatformInit.c
> delete mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> delete mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/SecGetPerformance.c
> delete mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/SecPlatformInformation.c
> delete mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/SecRamInitData.c
> delete mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra
> pperPlatformSecLib/SecTempRamDone.c
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/FspWrapperPlatformSecLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/FspWrapperPlatformSecLib.c
> deleted file mode 100644
> index a767289bc5..0000000000
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/FspWrapperPlatformSecLib.c
> +++ /dev/null
> @@ -1,163 +0,0 @@
> -/** @file- Provide FSP wrapper platform sec related function.--- Copyright
> (c) 2019, Intel Corporation. All rights reserved.<BR>- SPDX-License-Identifier:
> BSD-2-Clause-Patent-**/--#include <PiPei.h>--#include
> <Ppi/SecPlatformInformation.h>-#include <Ppi/SecPerformance.h>-
> #include <Ppi/FirmwareVolumeInfo.h>-#include
> <Ppi/TopOfTemporaryRam.h>-#include <Guid/FirmwareFileSystem2.h>--
> #include <Library/LocalApicLib.h>-#include <Library/BaseMemoryLib.h>-
> #include <Library/DebugLib.h>-#include <Library/IoLib.h>--/**- This
> interface conveys state information out of the Security (SEC) phase into PEI.-
> - @param[in] PeiServices Pointer to the PEI Services Table.-
> @param[in,out] StructureSize Pointer to the variable describing size of
> the input buffer.- @param[out] PlatformInformationRecord Pointer to the
> EFI_SEC_PLATFORM_INFORMATION_RECORD.-- @retval EFI_SUCCESS
> The data was successfully returned.- @retval EFI_BUFFER_TOO_SMALL The
> buffer was too small.--**/-EFI_STATUS-EFIAPI-SecPlatformInformation (- IN
> CONST EFI_PEI_SERVICES **PeiServices,- IN OUT UINT64
> *StructureSize,- OUT EFI_SEC_PLATFORM_INFORMATION_RECORD
> *PlatformInformationRecord- );--/**- This interface conveys performance
> information out of the Security (SEC) phase into PEI.-- This service is
> published by the SEC phase. The SEC phase handoff has an optional-
> EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed
> from SEC into the- PEI Foundation. As such, if the platform supports
> collecting performance data in SEC,- this information is encapsulated into the
> data structure abstracted by this service.- This information is collected for
> the boot-strap processor (BSP) on IA-32.-- @param[in] PeiServices The
> pointer to the PEI Services Table.- @param[in] This The pointer to this
> instance of the PEI_SEC_PERFORMANCE_PPI.- @param[out] Performance
> The pointer to performance data collected in SEC phase.-- @retval
> EFI_SUCCESS The data was successfully returned.--**/-EFI_STATUS-EFIAPI-
> SecGetPerformance (- IN CONST EFI_PEI_SERVICES **PeiServices,- IN
> PEI_SEC_PERFORMANCE_PPI *This,- OUT
> FIRMWARE_SEC_PERFORMANCE *Performance- );--
> PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi = {-
> SecGetPerformance-};--EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] = {-
> {- EFI_PEI_PPI_DESCRIPTOR_PPI,- &gTopOfTemporaryRamPpiGuid,-
> NULL // To be patched later.- },- {- EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,-
> &gPeiSecPerformancePpiGuid,- &mSecPerformancePpi- },-};--#define
> LEGACY_8259_MASK_REGISTER_MASTER 0x21-#define
> LEGACY_8259_MASK_REGISTER_SLAVE 0xA1-#define
> LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER 0x4D0-#define
> LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE 0x4D1--/**-
> Write to mask and edge/level triggered registers of master and slave 8259
> PICs.-- @param[in] Mask low byte for master PIC mask register,-
> high byte for slave PIC mask register.- @param[in] EdgeLevel low byte for
> master PIC edge/level triggered register,- high byte for slave PIC
> edge/level triggered register.--**/-VOID-Interrupt8259WriteMask (- IN
> UINT16 Mask,- IN UINT16 EdgeLevel- )-{- IoWrite8
> (LEGACY_8259_MASK_REGISTER_MASTER, (UINT8) Mask);- IoWrite8
> (LEGACY_8259_MASK_REGISTER_SLAVE, (UINT8) (Mask >> 8));- IoWrite8
> (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER, (UINT8)
> EdgeLevel);- IoWrite8
> (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE, (UINT8)
> (EdgeLevel >> 8));-}--/**- A developer supplied function to perform
> platform specific operations.-- It's a developer supplied function to perform
> any operations appropriate to a- given platform. It's invoked just before
> passing control to PEI core by SEC- core. Platform developer may modify the
> SecCoreData passed to PEI Core.- It returns a platform specific PPI list that
> platform wishes to pass to PEI core.- The Generic SEC core module will
> merge this list to join the final list passed to- PEI core.-- @param[in,out]
> SecCoreData The same parameter as passing to PEI core. It-
> could be overridden by this function.-- @return The platform specific PPI list
> to be passed to PEI core or- NULL if there is no need of such platform
> specific PPI list.--**/-EFI_PEI_PPI_DESCRIPTOR *-EFIAPI-SecPlatformMain (-
> IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData- )-{-
> EFI_PEI_PPI_DESCRIPTOR *PpiList;-- DEBUG ((DEBUG_INFO, "FSP
> Wrapper BootFirmwareVolumeBase - 0x%x\n", SecCoreData-
> >BootFirmwareVolumeBase));- DEBUG ((DEBUG_INFO, "FSP Wrapper
> BootFirmwareVolumeSize - 0x%x\n", SecCoreData-
> >BootFirmwareVolumeSize));- DEBUG ((DEBUG_INFO, "FSP Wrapper
> TemporaryRamBase - 0x%x\n", SecCoreData->TemporaryRamBase));-
> DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamSize - 0x%x\n",
> SecCoreData->TemporaryRamSize));- DEBUG ((DEBUG_INFO, "FSP Wrapper
> PeiTemporaryRamBase - 0x%x\n", SecCoreData-
> >PeiTemporaryRamBase));- DEBUG ((DEBUG_INFO, "FSP Wrapper
> PeiTemporaryRamSize - 0x%x\n", SecCoreData->PeiTemporaryRamSize));-
> DEBUG ((DEBUG_INFO, "FSP Wrapper StackBase - 0x%x\n",
> SecCoreData->StackBase));- DEBUG ((DEBUG_INFO, "FSP Wrapper StackSize
> - 0x%x\n", SecCoreData->StackSize));-- InitializeApicTimer (0, (UINT32) -1,
> TRUE, 5);-- //- // Set all 8259 interrupts to edge triggered and disabled- //-
> Interrupt8259WriteMask (0xFFFF, 0x0000);-- //- // Use middle of Heap as
> temp buffer, it will be copied by caller.- // Do not use Stack, because it will
> cause wrong calculation on stack by PeiCore- //- PpiList = (VOID
> *)((UINTN)SecCoreData->PeiTemporaryRamBase + (UINTN)SecCoreData-
> >PeiTemporaryRamSize/2);- CopyMem (PpiList, mPeiSecPlatformPpi,
> sizeof(mPeiSecPlatformPpi));-- //- // Patch TopOfTemporaryRamPpi- //-
> PpiList[0].Ppi = (VOID *)((UINTN)SecCoreData->TemporaryRamBase +
> SecCoreData->TemporaryRamSize);-- return PpiList;-}-diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/FsptCoreUpd.h
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/FsptCoreUpd.h
> deleted file mode 100644
> index e7b5ed952b..0000000000
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/FsptCoreUpd.h
> +++ /dev/null
> @@ -1,40 +0,0 @@
> -/** @file-- Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>-
> SPDX-License-Identifier: BSD-2-Clause-Patent-**/--#ifndef
> __FSPT_CORE_UPD_H__-#define __FSPT_CORE_UPD_H__--#pragma
> pack(1)--/** Fsp T Core UPD-**/-typedef struct {--/** Offset 0x0020-**/-
> UINT32 MicrocodeRegionBase;--/** Offset 0x0024-**/- UINT32
> MicrocodeRegionSize;--/** Offset 0x0028-**/- UINT32
> CodeRegionBase;--/** Offset 0x002C-**/- UINT32
> CodeRegionSize;--/** Offset 0x0030-**/- UINT8 Reserved[16];-}
> FSPT_CORE_UPD;--#pragma pack()--#endif-diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/Ia32/Fsp.h
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/Ia32/Fsp.h
> deleted file mode 100644
> index 1c88285a1d..0000000000
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/Ia32/Fsp.h
> +++ /dev/null
> @@ -1,43 +0,0 @@
> -/** @file- Fsp related definitions--- Copyright (c) 2019, Intel Corporation.
> All rights reserved.<BR>- SPDX-License-Identifier: BSD-2-Clause-Patent-**/-
> -#ifndef __FSP_H__-#define __FSP_H__--//-// Fv Header-//-#define
> FVH_SIGINATURE_OFFSET 0x28-#define
> FVH_SIGINATURE_VALID_VALUE 0x4856465F // valid signature:_FVH-
> #define FVH_HEADER_LENGTH_OFFSET 0x30-#define
> FVH_EXTHEADER_OFFSET_OFFSET 0x34-#define
> FVH_EXTHEADER_SIZE_OFFSET 0x10--//-// Ffs Header-//-#define
> FSP_HEADER_GUID_DWORD1 0x912740BE-#define
> FSP_HEADER_GUID_DWORD2 0x47342284-#define
> FSP_HEADER_GUID_DWORD3 0xB08471B9-#define
> FSP_HEADER_GUID_DWORD4 0x0C3F3527-#define
> FFS_HEADER_SIZE_VALUE 0x18--//-// Section Header-//-#define
> SECTION_HEADER_TYPE_OFFSET 0x03-#define
> RAW_SECTION_HEADER_SIZE_VALUE 0x04--//-// Fsp Header-//-#define
> FSP_HEADER_IMAGEBASE_OFFSET 0x1C-#define
> FSP_HEADER_TEMPRAMINIT_OFFSET 0x30--#endif-diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/Ia32/PeiCoreEntry.nasm
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/Ia32/PeiCoreEntry.nasm
> deleted file mode 100644
> index 5c5b788085..0000000000
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/Ia32/PeiCoreEntry.nasm
> +++ /dev/null
> @@ -1,130 +0,0 @@
> -;-------------------------------------------------------------------------------;-;
> Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>-; SPDX-
> License-Identifier: BSD-2-Clause-Patent-;-; Module Name:-;-;
> PeiCoreEntry.nasm-;-; Abstract:-;-; Find and call SecStartup-;-;-----------------
> ---------------------------------------------------------------SECTION .text--extern
> ASM_PFX(SecStartup)-extern ASM_PFX(PlatformInit)--global
> ASM_PFX(CallPeiCoreEntryPoint)-ASM_PFX(CallPeiCoreEntryPoint):- ;- ;
> Obtain the hob list pointer- ;- mov eax, [esp+4]- ;- ; Obtain the stack
> information- ; ECX: start of range- ; EDX: end of range- ;- mov ecx,
> [esp+8]- mov edx, [esp+0xC]-- ;- ; Platform init- ;- pushad- push edx-
> push ecx- push eax- call ASM_PFX(PlatformInit)- pop eax- pop eax- pop
> eax- popad-- ;- ; Set stack top pointer- ;- mov esp, edx-- ;- ; Push the
> hob list pointer- ;- push eax-- ;- ; Save the value- ; ECX: start of range- ;
> EDX: end of range- ;- mov ebp, esp- push ecx- push edx-- ;- ; Push
> processor count to stack first, then BIST status (AP then BSP)- ;- mov eax,
> 1- cpuid- shr ebx, 16- and ebx, 0xFF- cmp bl, 1- jae
> PushProcessorCount-- ;- ; Some processors report 0 logical processors.
> Effectively 0 = 1.- ; So we fix up the processor count- ;- inc ebx--
> PushProcessorCount:- push ebx-- ;- ; We need to implement a long-term
> solution for BIST capture. For now, we just copy BSP BIST- ; for all processor
> threads- ;- xor ecx, ecx- mov cl, bl-PushBist:- movd eax, mm0- push
> eax- loop PushBist-- ; Save Time-Stamp Counter- movd eax, mm5- push
> eax-- movd eax, mm6- push eax-- ;- ; Pass entry point of the PEI core- ;-
> mov edi, 0xFFFFFFE0- push DWORD [edi]-- ;- ; Pass BFV into the PEI
> Core- ;- mov edi, 0xFFFFFFFC- push DWORD [edi]-- ;- ; Pass stack size
> into the PEI Core- ;- mov ecx, [ebp - 4]- mov edx, [ebp - 8]- push ecx
> ; RamBase-- sub edx, ecx- push edx ; RamSize-- ;- ; Pass Control into
> the PEI Core- ;- call ASM_PFX(SecStartup)-diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/Ia32/SecEntry.nasm
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/Ia32/SecEntry.nasm
> deleted file mode 100644
> index 7f6d771e41..0000000000
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/Ia32/SecEntry.nasm
> +++ /dev/null
> @@ -1,361 +0,0 @@
> -;-------------------------------------------------------------------------------;-;
> Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>-; SPDX-
> License-Identifier: BSD-2-Clause-Patent-; Module Name:-;-; SecEntry.nasm-
> ;-; Abstract:-;-; This is the code that goes from real-mode to protected
> mode.-; It consumes the reset vector, calls TempRamInit API from FSP
> binary.-;-;--------------------------------------------------------------------------------
> #include "Fsp.h"--SECTION .text--extern ASM_PFX(CallPeiCoreEntryPoint)-
> extern ASM_PFX(FsptUpdDataPtr)-extern
> ASM_PFX(BoardBeforeTempRamInit)-; Pcds-extern ASM_PFX(PcdGet32
> (PcdFspTemporaryRamSize))-extern ASM_PFX(PcdGet32
> (PcdFsptBaseAddress))--;--------------------------------------------------------------
> ---------------;-; Procedure: _ModuleEntryPoint-;-; Input: None-;-;
> Output: None-;-; Destroys: Assume all registers-;-; Description:-;-;
> Transition to non-paged flat-model protected mode from a-; hard-coded
> GDT that provides exactly two descriptors.-; This is a bare bones transition
> to protected mode only-; used for a while in PEI and possibly DXE.-;-; After
> enabling protected mode, a far jump is executed to-; transfer to PEI using
> the newly loaded GDT.-;-; Return: None-;-; MMX Usage:-; MM0 =
> BIST State-; MM5 = Save time-stamp counter value high32bit-;
> MM6 = Save time-stamp counter value low32bit.-;-;-------------------------------
> -----------------------------------------------BITS 16-align 4-global
> ASM_PFX(_ModuleEntryPoint)-ASM_PFX(_ModuleEntryPoint):- fninit
> ; clear any pending Floating point exceptions- ;- ; Store the BIST value in
> mm0- ;- movd mm0, eax- cli-- ;- ; Check INIT# is asserted by port 0xCF9-
> ;- mov dx, 0CF9h- in al, dx- cmp al, 04h- jnz NotWarmStart--- ;- ; @note
> Issue warm reset, since if CPU only reset is issued not all MSRs are restored
> to their defaults- ;- mov dx, 0CF9h- mov al, 06h- out dx, al--NotWarmStart:-
> ;- ; Save time-stamp counter value- ; rdtsc load 64bit time-stamp counter to
> EDX:EAX- ;- rdtsc- movd mm5, edx- movd mm6, eax-- ;- ; Load the GDT
> table in GdtDesc- ;- mov esi, GdtDesc- DB 66h- lgdt [cs:si]-- ;- ;
> Transition to 16 bit protected mode- ;- mov eax, cr0 ; Get control
> register 0- or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1)-
> mov cr0, eax ; Activate protected mode-- mov eax, cr4
> ; Get control register 4- or eax, 00000600h ; Set OSFXSR bit (bit #9) &
> OSXMMEXCPT bit (bit #10)- mov cr4, eax-- ;- ; Now we're in 16 bit
> protected mode- ; Set up the selectors for 32 bit protected mode entry- ;-
> mov ax, SYS_DATA_SEL- mov ds, ax- mov es, ax- mov fs, ax- mov
> gs, ax- mov ss, ax-- ;- ; Transition to Flat 32 bit protected mode- ; The
> jump to a far pointer causes the transition to 32 bit mode- ;- mov esi,
> ProtectedModeEntryLinearAddress- jmp dword far [cs:si]--;------------------
> -----------------------------------------------------------;-; Procedure:
> ProtectedModeEntryPoint-;-; Input: None-;-; Output: None-;-;
> Destroys: Assume all registers-;-; Description:-;-; This function handles:-;
> Call two basic APIs from FSP binary-; Initializes stack with some early data
> (BIST, PEI entry, etc)-;-; Return: None-;-;-----------------------------------------
> -------------------------------------BITS 32-align 4-ProtectedModeEntryPoint:- ;-
> ; Early board hooks- ;- mov esp, BoardBeforeTempRamInitRet- jmp
> ASM_PFX(BoardBeforeTempRamInit)--BoardBeforeTempRamInitRet:-- ;
> Find the fsp info header- mov edi, [ASM_PFX(PcdGet32
> (PcdFsptBaseAddress))]-- mov eax, dword [edi +
> FVH_SIGINATURE_OFFSET]- cmp eax, FVH_SIGINATURE_VALID_VALUE-
> jnz FspHeaderNotFound-- xor eax, eax- mov ax, word [edi +
> FVH_EXTHEADER_OFFSET_OFFSET]- cmp ax, 0- jnz FspFvExtHeaderExist--
> xor eax, eax- mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass
> Fv Header- add edi, eax- jmp FspCheckFfsHeader--FspFvExtHeaderExist:-
> add edi, eax- mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ;
> Bypass Ext Fv Header- add edi, eax-- ; Round up to 8 byte alignment- mov
> eax, edi- and al, 07h- jz FspCheckFfsHeader-- and edi, 0FFFFFFF8h- add
> edi, 08h--FspCheckFfsHeader:- ; Check the ffs guid- mov eax, dword [edi]-
> cmp eax, FSP_HEADER_GUID_DWORD1- jnz FspHeaderNotFound-- mov
> eax, dword [edi + 4]- cmp eax, FSP_HEADER_GUID_DWORD2- jnz
> FspHeaderNotFound-- mov eax, dword [edi + 8]- cmp eax,
> FSP_HEADER_GUID_DWORD3- jnz FspHeaderNotFound-- mov eax, dword
> [edi + 0Ch]- cmp eax, FSP_HEADER_GUID_DWORD4- jnz
> FspHeaderNotFound-- add edi, FFS_HEADER_SIZE_VALUE ; Bypass the
> ffs header-- ; Check the section type as raw section- mov al, byte [edi +
> SECTION_HEADER_TYPE_OFFSET]- cmp al, 019h- jnz FspHeaderNotFound--
> add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header-
> jmp FspHeaderFound--FspHeaderNotFound:- jmp $--FspHeaderFound:- ;
> Get the fsp TempRamInit Api address- mov eax, dword [edi +
> FSP_HEADER_IMAGEBASE_OFFSET]- add eax, dword [edi +
> FSP_HEADER_TEMPRAMINIT_OFFSET]-- ; Setup the hardcode stack- mov
> esp, TempRamInitStack-- ; Call the fsp TempRamInit Api- jmp eax--
> TempRamInitDone:- cmp eax, 8000000Eh ;Check if EFI_NOT_FOUND
> returned. Error code for Microcode Update not found.- je CallSecFspInit
> ;If microcode not found, don't hang, but continue.-- cmp eax, 0 ;Check
> if EFI_SUCCESS retuned.- jnz FspApiFailed-- ; ECX: start of range- ; EDX:
> end of range-CallSecFspInit:- sub edx, [ASM_PFX(PcdGet32
> (PcdFspTemporaryRamSize))] ; TemporaryRam for FSP- xor eax, eax- mov
> esp, edx-- ; Align the stack at DWORD- add esp, 3- and esp, 0FFFFFFFCh--
> push edx- push ecx- push eax ; zero - no hob list yet- call
> ASM_PFX(CallPeiCoreEntryPoint)--FspApiFailed:- jmp $--align 10h-
> TempRamInitStack:- DD TempRamInitDone- DD
> ASM_PFX(FsptUpdDataPtr); TempRamInitParams--;-; ROM-based Global-
> Descriptor Table for the Tiano PEI Phase-;-align 16-global
> ASM_PFX(BootGdtTable)--;-; GDT[0]: 0x00: Null entry, never used.-;-
> NULL_SEL EQU $ - GDT_BASE ; Selector [0]-GDT_BASE:-
> ASM_PFX(BootGdtTable):- DD 0- DD 0-;-; Linear data
> segment descriptor-;-LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8]-
> DW 0FFFFh ; limit 0xFFFFF- DW 0 ; base 0- DB
> 0- DB 092h ; present, ring 0, data, expand-up, writable- DB
> 0CFh ; page-granular, 32-bit- DB 0-;-; Linear code segment
> descriptor-;-LINEAR_CODE_SEL EQU $ - GDT_BASE ; Selector [0x10]- DW
> 0FFFFh ; limit 0xFFFFF- DW 0 ; base 0- DB 0-
> DB 09Bh ; present, ring 0, data, expand-up, not-writable- DB
> 0CFh ; page-granular, 32-bit- DB 0-;-; System data segment
> descriptor-;-SYS_DATA_SEL EQU $ - GDT_BASE ; Selector [0x18]- DW
> 0FFFFh ; limit 0xFFFFF- DW 0 ; base 0- DB 0-
> DB 093h ; present, ring 0, data, expand-up, not-writable- DB
> 0CFh ; page-granular, 32-bit- DB 0--;-; System code segment
> descriptor-;-SYS_CODE_SEL EQU $ - GDT_BASE ; Selector [0x20]- DW
> 0FFFFh ; limit 0xFFFFF- DW 0 ; base 0- DB 0-
> DB 09Ah ; present, ring 0, data, expand-up, writable- DB 0CFh
> ; page-granular, 32-bit- DB 0-;-; Spare segment descriptor-;-
> SYS16_CODE_SEL EQU $ - GDT_BASE ; Selector [0x28]- DW 0FFFFh
> ; limit 0xFFFFF- DW 0 ; base 0- DB 0Eh ;
> Changed from F000 to E000.- DB 09Bh ; present, ring 0, code,
> expand-up, writable- DB 00h ; byte-granular, 16-bit- DB 0-;-;
> Spare segment descriptor-;-SYS16_DATA_SEL EQU $ - GDT_BASE ;
> Selector [0x30]- DW 0FFFFh ; limit 0xFFFF- DW 0
> ; base 0- DB 0- DB 093h ; present, ring 0, data, expand-up,
> not-writable- DB 00h ; byte-granular, 16-bit- DB 0--;-; Spare
> segment descriptor-;-SPARE5_SEL EQU $ - GDT_BASE ; Selector [0x38]-
> DW 0 ; limit 0- DW 0 ; base 0- DB 0- DB 0
> ; present, ring 0, data, expand-up, writable- DB 0 ; page-
> granular, 32-bit- DB 0-GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes--;-
> ; GDT Descriptor-;-GdtDesc: ; GDT descriptor- DW GDT_SIZE
> - 1 ; GDT limit- DD GDT_BASE ; GDT base address---
> ProtectedModeEntryLinearAddress:-ProtectedModeEntryLinear:- DD
> ProtectedModeEntryPoint ; Offset of our 32 bit code- DW
> LINEAR_CODE_SELdiff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/Ia32/Stack.nasm
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/Ia32/Stack.nasm
> deleted file mode 100644
> index 47db32d64c..0000000000
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/Ia32/Stack.nasm
> +++ /dev/null
> @@ -1,72 +0,0 @@
> -;-------------------------------------------------------------------------------;-;
> Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>-; SPDX-
> License-Identifier: BSD-2-Clause-Patent-; Abstract:-;-; Switch the stack from
> temporary memory to permanent memory.-;-;-------------------------------------
> ------------------------------------------- SECTION .text--;----------------------------
> ---------------------------------------------------; VOID-; EFIAPI-; SecSwitchStack (-;
> UINT32 TemporaryMemoryBase,-; UINT32 PermanentMemoryBase-; );-
> ;-------------------------------------------------------------------------------global
> ASM_PFX(SecSwitchStack)-ASM_PFX(SecSwitchStack):- ;- ; Save three
> register: eax, ebx, ecx- ;- push eax- push ebx- push ecx- push edx--
> ;- ; !!CAUTION!! this function address's is pushed into stack after- ;
> migration of whole temporary memory, so need save it to permanent- ;
> memory at first!- ;-- mov ebx, [esp + 20] ; Save the first parameter-
> mov ecx, [esp + 24] ; Save the second parameter-- ;- ; Save this
> function's return address into permanent memory at first.- ; Then, Fixup
> the esp point to permanent memory- ;- mov eax, esp- sub eax, ebx-
> add eax, ecx- mov edx, dword [esp] ; copy pushed register's value to
> permanent memory- mov dword [eax], edx- mov edx, dword [esp + 4]-
> mov dword [eax + 4], edx- mov edx, dword [esp + 8]- mov dword [eax
> + 8], edx- mov edx, dword [esp + 12]- mov dword [eax + 12], edx- mov
> edx, dword [esp + 16] ; Update this function's return address into
> permanent memory- mov dword [eax + 16], edx- mov esp, eax
> ; From now, esp is pointed to permanent memory-- ;- ; Fixup the ebp
> point to permanent memory- ;- mov eax, ebp- sub eax, ebx- add
> eax, ecx- mov ebp, eax ; From now, ebp is pointed to permanent
> memory-- pop edx- pop ecx- pop ebx- pop eax- ret-diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/PlatformInit.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/PlatformInit.c
> deleted file mode 100644
> index 06ca63c19a..0000000000
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/PlatformInit.c
> +++ /dev/null
> @@ -1,54 +0,0 @@
> -/** @file- Provide platform init function.--- Copyright (c) 2019, Intel
> Corporation. All rights reserved.<BR>- SPDX-License-Identifier: BSD-2-
> Clause-Patent-**/--#include <PiPei.h>-#include <Library/DebugLib.h>-
> #include <Library/SerialPortLib.h>-#include <Library/SecBoardInitLib.h>-
> #include <Library/TestPointCheckLib.h>-#include <Register/PchRegsPmc.h>-
> #include <Library/IoLib.h>--/**- Platform initialization.-- @param[in]
> FspHobList HobList produced by FSP.- @param[in] StartOfRange Start of
> temporary RAM.- @param[in] EndOfRange End of temporary RAM.-**/-
> VOID-EFIAPI-PlatformInit (- IN VOID *FspHobList,- IN VOID
> *StartOfRange,- IN VOID *EndOfRange- )-{- ///- /// Halt the TCO
> timer as early as possible- ///- IoWrite16 (PcdGet16 (PcdTcoBaseAddress) +
> R_TCO_IO_TCO1_CNT, B_TCO_IO_TCO1_CNT_TMR_HLT);-- //- // Platform
> initialization- // Enable Serial port here- //- if
> (PcdGetBool(PcdSecSerialPortDebugEnable)) {- SerialPortInitialize ();- }--
> DEBUG ((DEBUG_INFO, "PrintPeiCoreEntryPointParam in PlatformInit\n"));-
> DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList));- DEBUG
> ((DEBUG_INFO, "StartOfRange - 0x%x\n", StartOfRange));- DEBUG
> ((DEBUG_INFO, "EndOfRange - 0x%x\n", EndOfRange));--
> BoardAfterTempRamInit ();-- TestPointTempMemoryFunction
> (StartOfRange, EndOfRange);-}-diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> deleted file mode 100644
> index 06489a6336..0000000000
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> +++ /dev/null
> @@ -1,97 +0,0 @@
> -## @file-# Provide FSP wrapper platform sec related function.-#-#-#
> Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>-#-# SPDX-
> License-Identifier: BSD-2-Clause-Patent-#-#-##--
> ##########################################################
> ######################-#-# Defines Section - statements that will be
> processed to create a Makefile.-#-
> ##########################################################
> ######################-[Defines]- INF_VERSION =
> 0x00010005- BASE_NAME = SecFspWrapperPlatformSecLib-
> FILE_GUID = 4E1C4F95-90EA-47de-9ACC-B8920189A1F5-
> MODULE_TYPE = SEC- VERSION_STRING = 1.0-
> LIBRARY_CLASS = PlatformSecLib---#-# The following information is
> for reference only and not required by the build tools.-#-#
> VALID_ARCHITECTURES = IA32 X64-#--
> ##########################################################
> ######################-#-# Sources Section - list of files that are
> required for the build to succeed.-#-
> ##########################################################
> ######################--[Sources]- FspWrapperPlatformSecLib.c-
> SecRamInitData.c- SecPlatformInformation.c- SecGetPerformance.c-
> SecTempRamDone.c- PlatformInit.c--[Sources.IA32]- Ia32/SecEntry.nasm-
> Ia32/PeiCoreEntry.nasm- Ia32/Stack.nasm- Ia32/Fsp.h--
> ##########################################################
> ######################-#-# Package Dependency Section - list of
> Package files that are required for-# this module.-#-
> ##########################################################
> ######################--[Packages]- MdePkg/MdePkg.dec-
> MdeModulePkg/MdeModulePkg.dec- UefiCpuPkg/UefiCpuPkg.dec-
> IntelFsp2Pkg/IntelFsp2Pkg.dec-
> IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec-
> MinPlatformPkg/MinPlatformPkg.dec- CoffeelakeSiliconPkg/SiPkg.dec--
> [LibraryClasses]- LocalApicLib- SerialPortLib- FspWrapperPlatformLib-
> FspWrapperApiLib- BoardInitLib- SecBoardInitLib- TestPointCheckLib- IoLib-
> -[Ppis]- gEfiSecPlatformInformationPpiGuid ## CONSUMES-
> gPeiSecPerformancePpiGuid ## CONSUMES-
> gTopOfTemporaryRamPpiGuid ## PRODUCES-
> gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES--[Pcd]-
> gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize ##
> CONSUMES- gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress
> ## CONSUMES- gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize
> ## CONSUMES-
> gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ##
> CONSUMES- gSiPkgTokenSpaceGuid.PcdTcoBaseAddress--[FixedPcd]-
> gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress ##
> CONSUMES-
> gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ##
> CONSUMES- gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset
> ## CONSUMES-
> gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ##
> CONSUMES- gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize
> ## CONSUMES-diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/SecGetPerformance.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/SecGetPerformance.c
> deleted file mode 100644
> index 67bdd232bb..0000000000
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/SecGetPerformance.c
> +++ /dev/null
> @@ -1,90 +0,0 @@
> -/** @file- Sample to provide SecGetPerformance function.--- Copyright (c)
> 2019, Intel Corporation. All rights reserved.<BR>- SPDX-License-Identifier:
> BSD-2-Clause-Patent-**/--#include <PiPei.h>--#include
> <Ppi/SecPerformance.h>-#include <Ppi/TopOfTemporaryRam.h>--#include
> <Library/BaseMemoryLib.h>-#include <Library/TimerLib.h>-#include
> <Library/DebugLib.h>--/**- This interface conveys performance information
> out of the Security (SEC) phase into PEI.-- This service is published by the SEC
> phase. The SEC phase handoff has an optional- EFI_PEI_PPI_DESCRIPTOR list
> as its final argument when control is passed from SEC into the- PEI
> Foundation. As such, if the platform supports collecting performance data in
> SEC,- this information is encapsulated into the data structure abstracted by
> this service.- This information is collected for the boot-strap processor (BSP)
> on IA-32.-- @param[in] PeiServices The pointer to the PEI Services Table.-
> @param[in] This The pointer to this instance of the
> PEI_SEC_PERFORMANCE_PPI.- @param[out] Performance The pointer to
> performance data collected in SEC phase.-- @retval EFI_SUCCESS The data
> was successfully returned.--**/-EFI_STATUS-EFIAPI-SecGetPerformance (-
> IN CONST EFI_PEI_SERVICES **PeiServices,- IN
> PEI_SEC_PERFORMANCE_PPI *This,- OUT
> FIRMWARE_SEC_PERFORMANCE *Performance- )-{- UINT32 Size;-
> UINT32 Count;- UINT32 TopOfTemporaryRam;- UINT64 Ticker;-
> VOID *TopOfTemporaryRamPpi;- EFI_STATUS Status;-- DEBUG
> ((DEBUG_INFO, "SecGetPerformance\n"));-- Status = (*PeiServices)-
> >LocatePpi (- PeiServices,-
> &gTopOfTemporaryRamPpiGuid,- 0,- NULL,-
> (VOID **) &TopOfTemporaryRamPpi- );- if (EFI_ERROR
> (Status)) {- return EFI_NOT_FOUND;- }- //- // |--------------| <-
> TopOfTemporaryRam - BL- // | List Ptr |- // |--------------|- // | BL RAM
> Start |- // |--------------|- // | BL RAM End |- // |--------------|- // |Number
> of BSPs|- // |--------------|- // | BIST |- // |--------------|- // | .... |-
> // |--------------|- // | TSC[63:32] |- // |--------------|- // | TSC[31:00] |- //
> |--------------|- //- TopOfTemporaryRam =
> (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof(UINT32);-
> TopOfTemporaryRam -= sizeof(UINT32) * 2;- Count = *(UINT32 *)
> (UINTN) (TopOfTemporaryRam - sizeof (UINT32));- Size = Count *
> sizeof (UINT32);-- Ticker = *(UINT64 *) (UINTN) (TopOfTemporaryRam -
> sizeof (UINT32) - Size - sizeof (UINT32) * 2);- Performance->ResetEnd =
> GetTimeInNanoSecond (Ticker);-- return EFI_SUCCESS;-}-diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/SecPlatformInformation.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/SecPlatformInformation.c
> deleted file mode 100644
> index e05daa8784..0000000000
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/SecPlatformInformation.c
> +++ /dev/null
> @@ -1,79 +0,0 @@
> -/** @file- Provide SecPlatformInformation function.--- Copyright (c) 2019,
> Intel Corporation. All rights reserved.<BR>- SPDX-License-Identifier: BSD-2-
> Clause-Patent-**/--#include <PiPei.h>--#include
> <Ppi/SecPlatformInformation.h>-#include <Ppi/TopOfTemporaryRam.h>--
> #include <Library/BaseMemoryLib.h>-#include <Library/DebugLib.h>--/**-
> This interface conveys state information out of the Security (SEC) phase into
> PEI.-- @param[in] PeiServices Pointer to the PEI Services Table.-
> @param[in,out] StructureSize Pointer to the variable describing size of
> the input buffer.- @param[out] PlatformInformationRecord Pointer to the
> EFI_SEC_PLATFORM_INFORMATION_RECORD.-- @retval EFI_SUCCESS
> The data was successfully returned.- @retval EFI_BUFFER_TOO_SMALL The
> buffer was too small.--**/-EFI_STATUS-EFIAPI-SecPlatformInformation (- IN
> CONST EFI_PEI_SERVICES **PeiServices,- IN OUT UINT64
> *StructureSize,- OUT EFI_SEC_PLATFORM_INFORMATION_RECORD
> *PlatformInformationRecord- )-{- UINT32 *Bist;- UINT32 Size;- UINT32
> Count;- UINT32 TopOfTemporaryRam;- VOID
> *TopOfTemporaryRamPpi;- EFI_STATUS Status;-- DEBUG ((DEBUG_INFO,
> "SecPlatformInformation\n"));-- Status = (*PeiServices)->LocatePpi (-
> PeiServices,- &gTopOfTemporaryRamPpiGuid,-
> 0,- NULL,- (VOID **) &TopOfTemporaryRamPpi-
> );- if (EFI_ERROR (Status)) {- return EFI_NOT_FOUND;- }-- //- // The
> entries of BIST information, together with the number of them,- // reside in
> the bottom of stack, left untouched by normal stack operation.- // This
> routine copies the BIST information to the buffer pointed by- //
> PlatformInformationRecord for output.- //- TopOfTemporaryRam =
> (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof (UINT32);-
> TopOfTemporaryRam -= sizeof(UINT32) * 2;- Count = *((UINT32
> *)(UINTN) (TopOfTemporaryRam - sizeof (UINT32)));- Size = Count *
> sizeof (IA32_HANDOFF_STATUS);-- if ((*StructureSize) < (UINT64) Size) {-
> *StructureSize = Size;- return EFI_BUFFER_TOO_SMALL;- }--
> *StructureSize = Size;- Bist = (UINT32 *) (TopOfTemporaryRam - sizeof
> (UINT32) - Size);-- CopyMem (PlatformInformationRecord, Bist, Size);--
> return EFI_SUCCESS;-}-diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/SecRamInitData.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/SecRamInitData.c
> deleted file mode 100644
> index 04f12a9438..0000000000
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/SecRamInitData.c
> +++ /dev/null
> @@ -1,37 +0,0 @@
> -/** @file- Provide TempRamInitParams data.--- Copyright (c) 2019, Intel
> Corporation. All rights reserved.<BR>- SPDX-License-Identifier: BSD-2-
> Clause-Patent-**/--#include <Library/PcdLib.h>-#include <FspEas.h>-
> #include "FsptCoreUpd.h"--typedef struct {- FSP_UPD_HEADER
> FspUpdHeader;- FSPT_CORE_UPD FsptCoreUpd;-}
> FSPT_UPD_CORE_DATA;--GLOBAL_REMOVE_IF_UNREFERENCED CONST
> FSPT_UPD_CORE_DATA FsptUpdDataPtr = {- {- 0x4450555F54505346,-
> 0x00,- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,- 0x00,
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00- }- },- {- ((UINT32)FixedPcdGet64
> (PcdCpuMicrocodePatchAddress) + FixedPcdGet32
> (PcdFlashMicrocodeOffset)),- ((UINT32)FixedPcdGet64
> (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet32
> (PcdFlashMicrocodeOffset)),- 0, // Set CodeRegionBase as 0, so that
> caching will be 4GB-(CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize)
> will be used.- FixedPcdGet32 (PcdFlashCodeCacheSize),- { 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,- 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00- }- }-};--diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/SecTempRamDone.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/SecTempRamDone.c
> deleted file mode 100644
> index 6d65d7d23f..0000000000
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr
> apperPlatformSecLib/SecTempRamDone.c
> +++ /dev/null
> @@ -1,48 +0,0 @@
> -/** @file- Provide SecTemporaryRamDone function.--- Copyright (c) 2019,
> Intel Corporation. All rights reserved.<BR>- SPDX-License-Identifier: BSD-2-
> Clause-Patent-**/--#include <PiPei.h>--#include
> <Ppi/TemporaryRamDone.h>--#include <Library/BaseMemoryLib.h>-
> #include <Library/DebugLib.h>-#include <Library/PcdLib.h>-#include
> <Library/DebugAgentLib.h>-#include <Library/FspWrapperPlatformLib.h>-
> #include <Library/FspWrapperApiLib.h>-#include <Library/BoardInitLib.h>--
> /**-This interface disables temporary memory in SEC Phase.-**/-VOID-
> EFIAPI-SecPlatformDisableTemporaryMemory (- VOID- )-{- EFI_STATUS
> Status;- VOID *TempRamExitParam;-- DEBUG((DEBUG_INFO,
> "SecPlatformDisableTemporaryMemory enter\n"));-- Status =
> BoardInitBeforeTempRamExit ();- ASSERT_EFI_ERROR (Status);--
> TempRamExitParam = UpdateTempRamExitParam ();- Status =
> CallTempRamExit (TempRamExitParam);- DEBUG((DEBUG_INFO,
> "TempRamExit status: 0x%x\n", Status));- ASSERT_EFI_ERROR(Status);--
> Status = BoardInitAfterTempRamExit ();- ASSERT_EFI_ERROR (Status);--
> return ;-}-diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoard
> Pkg.dsc
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoard
> Pkg.dsc
> index 3cd0478021..127147c734 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoard
> Pkg.dsc
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoard
> Pk
> +++ g.dsc
> @@ -127,7 +127,7 @@
>
> GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpan
> derLib/BaseGpioExpanderLib.inf
> HdaVerbTableLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiHdaVerbTabl
> eLib/PeiHdaVerbTableLib.inf
> I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2
> cAccessLib.inf-
> PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFs
> pWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf+
> PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTi
> merLib.inf # Thunderbolt !if
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE--
> 2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 09/13] MinPlatformPkg: FSP Dispatch Mode Support for PlatformSecLib
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 09/13] MinPlatformPkg: FSP Dispatch Mode Support for PlatformSecLib Nate DeSimone
2019-11-14 15:17 ` Chiu, Chasel
@ 2019-11-16 2:54 ` Kubacki, Michael A
1 sibling, 0 replies; 44+ messages in thread
From: Kubacki, Michael A @ 2019-11-16 2:54 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io; +Cc: Chiu, Chasel, Gao, Liming
FspWrapperPlatformSecLib.c:
* Line 179: Given the other whitespace fixes, there's one missing here after sizeof.
CopyMem (CopyDestinationPointer, mPeiSecPlatformPpi, sizeof(mPeiSecPlatformPpi));
It does not have to be fixed in this commit.
Reviewed-by: Michael Kubacki <michael.a.kubacki@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Wednesday, November 13, 2019 10:07 PM
> To: devel@edk2.groups.io
> Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Chiu, Chasel
> <chasel.chiu@intel.com>; Gao, Liming <liming.gao@intel.com>
> Subject: [edk2-platforms] [PATCH V1 09/13] MinPlatformPkg: FSP Dispatch
> Mode Support for PlatformSecLib
>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../FspWrapperPlatformSecLib.c | 34 ++++++++++++---
> .../SecFspWrapperPlatformSecLib.inf | 7 +++-
> .../SecTempRamDone.c | 42 +++++++++++++++----
> .../Intel/MinPlatformPkg/MinPlatformPkg.dec | 28 ++++++++++++-
> 4 files changed, 95 insertions(+), 16 deletions(-)
>
> diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatf
> ormSecLib/FspWrapperPlatformSecLib.c
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatf
> ormSecLib/FspWrapperPlatformSecLib.c
> index 303f3aac40..876c073fc4 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatf
> ormSecLib/FspWrapperPlatformSecLib.c
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/FspWrapperPlatformSecLib.c
> @@ -1,7 +1,7 @@
> /** @file Provide FSP wrapper platform sec related function. -Copyright (c)
> 2017, Intel Corporation. All rights reserved.<BR>+Copyright (c) 2017 - 2019,
> Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-
> Clause-Patent **/@@ -12,6 +12,7 @@ SPDX-License-Identifier: BSD-2-
> Clause-Patent
> #include <Ppi/SecPerformance.h> #include <Ppi/FirmwareVolumeInfo.h>
> #include <Ppi/TopOfTemporaryRam.h>+#include <Ppi/PeiCoreFvLocation.h>
> #include <Guid/FirmwareFileSystem2.h> #include
> <Library/LocalApicLib.h>@@ -66,6 +67,18 @@ PEI_SEC_PERFORMANCE_PPI
> mSecPerformancePpi = {
> SecGetPerformance }; +EFI_PEI_CORE_FV_LOCATION_PPI
> mPeiCoreFvLocationPpi = {+ (VOID *) (UINTN) FixedPcdGet32
> (PcdFspmBaseAddress)+};++EFI_PEI_PPI_DESCRIPTOR
> mPeiCoreFvLocationPpiList[] = {+ {+ EFI_PEI_PPI_DESCRIPTOR_PPI,+
> &gEfiPeiCoreFvLocationPpiGuid,+ &mPeiCoreFvLocationPpi+ }+};+
> EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] = { {
> EFI_PEI_PPI_DESCRIPTOR_PPI,@@ -129,6 +142,8 @@ SecPlatformMain (
> ) { EFI_PEI_PPI_DESCRIPTOR *PpiList;+ UINT8
> TopOfTemporaryRamPpiIndex;+ UINT8 *CopyDestinationPointer;
> DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeBase - 0x%x\n",
> SecCoreData->BootFirmwareVolumeBase)); DEBUG ((DEBUG_INFO, "FSP
> Wrapper BootFirmwareVolumeSize - 0x%x\n", SecCoreData-
> >BootFirmwareVolumeSize));@@ -150,13 +165,22 @@ SecPlatformMain (
> // Use middle of Heap as temp buffer, it will be copied by caller. // Do not
> use Stack, because it will cause wrong calculation on stack by PeiCore //-
> PpiList = (VOID *)((UINTN)SecCoreData->PeiTemporaryRamBase +
> (UINTN)SecCoreData->PeiTemporaryRamSize/2);- CopyMem (PpiList,
> mPeiSecPlatformPpi, sizeof(mPeiSecPlatformPpi));-+ PpiList = (VOID
> *)((UINTN) SecCoreData->PeiTemporaryRamBase + (UINTN) SecCoreData-
> >PeiTemporaryRamSize/2);+ CopyDestinationPointer = (UINT8 *) PpiList;+
> TopOfTemporaryRamPpiIndex = 0;+ if ((PcdGet8 (PcdFspModeSelection) ==
> 0) && PcdGetBool (PcdFspDispatchModeUseFspPeiMain)) {+ //+ // In
> Dispatch mode, wrapper should provide PeiCoreFvLocationPpi.+ //+
> CopyMem (CopyDestinationPointer, mPeiCoreFvLocationPpiList, sizeof
> (mPeiCoreFvLocationPpiList));+ TopOfTemporaryRamPpiIndex = 1;+
> CopyDestinationPointer += sizeof (mPeiCoreFvLocationPpiList);+ }+
> CopyMem (CopyDestinationPointer, mPeiSecPlatformPpi,
> sizeof(mPeiSecPlatformPpi)); // // Patch TopOfTemporaryRamPpi //-
> PpiList[0].Ppi = (VOID *)((UINTN)SecCoreData->TemporaryRamBase +
> SecCoreData->TemporaryRamSize);+
> PpiList[TopOfTemporaryRamPpiIndex].Ppi = (VOID *)((UINTN) SecCoreData-
> >TemporaryRamBase + SecCoreData->TemporaryRamSize); return PpiList;
> }diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatf
> ormSecLib/SecFspWrapperPlatformSecLib.inf
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatf
> ormSecLib/SecFspWrapperPlatformSecLib.inf
> index 3f5a63f273..02c720c73d 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatf
> ormSecLib/SecFspWrapperPlatformSecLib.inf
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/SecFspWrapperPlatformSecLib.inf
> @@ -72,18 +72,20 @@
> BoardInitLib SecBoardInitLib TestPointCheckLib+
> PeiServicesTablePointerLib [Ppis] gEfiSecPlatformInformationPpiGuid ##
> CONSUMES gPeiSecPerformancePpiGuid ## CONSUMES
> gTopOfTemporaryRamPpiGuid ## PRODUCES
> gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES+
> gFspTempRamExitPpiGuid ## CONSUMES [Pcd]
> gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize ##
> CONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress
> ## CONSUMES gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize
> ## CONSUMES-
> gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ##
> CONSUMES+
> gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ##
> CONSUMES [FixedPcd]
> gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress ##
> CONSUMES@@ -91,3 +93,6 @@
> gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset ##
> CONSUMES
> gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ##
> CONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize
> ## CONSUMES+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress
> ## CONSUMES+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection
> ## CONSUMES+
> gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain
> ## CONSUMESdiff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatf
> ormSecLib/SecTempRamDone.c
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatf
> ormSecLib/SecTempRamDone.c
> index cde8a80a4e..922e4ec204 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatf
> ormSecLib/SecTempRamDone.c
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/SecTempRamDone.c
> @@ -1,7 +1,7 @@
> /** @file Provide SecTemporaryRamDone function. -Copyright (c) 2017,
> Intel Corporation. All rights reserved.<BR>+Copyright (c) 2017 - 2019, Intel
> Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-
> Patent **/@@ -9,6 +9,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> #include <PiPei.h> #include <Ppi/TemporaryRamDone.h>+#include
> <Ppi/TempRamExitPpi.h> #include <Library/BaseMemoryLib.h> #include
> <Library/DebugLib.h>@@ -17,6 +18,7 @@ SPDX-License-Identifier: BSD-2-
> Clause-Patent #include <Library/FspWrapperPlatformLib.h> #include
> <Library/FspWrapperApiLib.h> #include <Library/BoardInitLib.h>+#include
> <Library/PeiServicesTablePointerLib.h> /** This interface disables
> temporary memory in SEC Phase.@@ -29,17 +31,41 @@
> SecPlatformDisableTemporaryMemory (
> { EFI_STATUS Status; VOID *TempRamExitParam;+
> CONST EFI_PEI_SERVICES **PeiServices;+ FSP_TEMP_RAM_EXIT_PPI
> *TempRamExitPpi;++ DEBUG ((DEBUG_INFO,
> "SecPlatformDisableTemporaryMemory enter\n")); - DEBUG((DEBUG_INFO,
> "SecPlatformDisableTemporaryMemory enter\n"));- Status =
> BoardInitBeforeTempRamExit (); ASSERT_EFI_ERROR (Status); -
> TempRamExitParam = UpdateTempRamExitParam ();- Status =
> CallTempRamExit (TempRamExitParam);- DEBUG((DEBUG_INFO,
> "TempRamExit status: 0x%x\n", Status));- ASSERT_EFI_ERROR(Status);- + if
> (PcdGet8 (PcdFspModeSelection) == 1) {+ //+ // FSP API mode+ //+
> TempRamExitParam = UpdateTempRamExitParam ();+ Status =
> CallTempRamExit (TempRamExitParam);+ DEBUG ((DEBUG_INFO,
> "TempRamExit status: 0x%x\n", Status));+ ASSERT_EFI_ERROR (Status);+ }
> else {+ //+ // FSP Dispatch mode+ //+ PeiServices =
> GetPeiServicesTablePointer ();+ Status = (*PeiServices)->LocatePpi (+
> PeiServices,+ &gFspTempRamExitPpiGuid,+ 0,+
> NULL,+ (VOID **) &TempRamExitPpi+ );+
> ASSERT_EFI_ERROR (Status);+ if (EFI_ERROR (Status)) {+ return;+ }+
> TempRamExitPpi->TempRamExit (NULL);+ }+ Status =
> BoardInitAfterTempRamExit (); ASSERT_EFI_ERROR (Status); diff --git
> a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> index a851021c0b..856c17f737 100644
> --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> @@ -69,8 +69,6 @@ SetCacheMtrrLib|Include/Library/SetCacheMtrrLib.h
> [PcdsFixedAtBuild, PcdsPatchableInModule] -
> gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|FALSE|BOOLE
> AN|0x80000008-
> gMinPlatformPkgTokenSpaceGuid.PcdFspMaxUpdSize|0x00000000|UINT32|
> 0x80000000
> gMinPlatformPkgTokenSpaceGuid.PcdFspReservedSizeOnStackTop|0x00000
> 040|UINT32|0x80000001
> gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0x00000000|UINT3
> 2|0x80000002@@ -272,6 +270,32 @@
> gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UINT32|0x90000
> 019
> # gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4|UINT8|0xF00000A0
> + ## FSP Boot Mode Selector+ # FALSE: The board is not a FSP wrapper (FSP
> binary not used)+ # TRUE: The board is a FSP wrapper (FSP binary is used)+
> #+
> gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|FALSE|BOOLE
> AN|0x80000008++ ## FSP Dispatch Mode: Use the PEI Main Binary Included
> in FSP-M+ # FALSE: The PEI Main included in FvPreMemory is used to
> dispatch all PEIMs+ # (both inside FSP and outside FSP).+ # Pros:+ #
> * PEI Main is re-built from source and is always the latest version+ # *
> Platform code can link any desired LibraryClass to PEI Main+ # (Ex:
> Custom DebugLib instance, SerialPortLib, etc.)+ # Cons:+ # * The PEI
> Main being used to execute FSP PEIMs is not the PEI Main+ # that the
> FSP PEIMs were tested with, adding risk of breakage.+ # * Two copies of
> PEI Main will exist in the final binary,+ # #1 in FSP-M, #2 in
> FvPreMemory. The copy in FSP-M is never+ # executed, wasting
> space.+ #+ # <b>TRUE</b>: The PEI Main included in FSP is used to dispatch
> all PEIMs+ # (both inside FSP and outside FSP). PEI Main will not be
> included in+ # FvPreMemory. This is the default and is the recommended
> choice.+ #+
> gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TR
> UE|BOOLEAN|0xF00000A8+ [PcdsFeatureFlag]
> gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit
> |FALSE|BOOLEAN|0xF00000A1--
> 2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 10/13] MinPlatformPkg: Coding style cleanups in MinPlatformPkg.dec
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 10/13] MinPlatformPkg: Coding style cleanups in MinPlatformPkg.dec Nate DeSimone
2019-11-14 15:17 ` Chiu, Chasel
@ 2019-11-16 2:54 ` Kubacki, Michael A
1 sibling, 0 replies; 44+ messages in thread
From: Kubacki, Michael A @ 2019-11-16 2:54 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io; +Cc: Chiu, Chasel, Gao, Liming
Reviewed-by: Michael Kubacki <michael.a.kubacki@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Wednesday, November 13, 2019 10:07 PM
> To: devel@edk2.groups.io
> Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Chiu, Chasel
> <chasel.chiu@intel.com>; Gao, Liming <liming.gao@intel.com>
> Subject: [edk2-platforms] [PATCH V1 10/13] MinPlatformPkg: Coding style
> cleanups in MinPlatformPkg.dec
>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../Intel/MinPlatformPkg/MinPlatformPkg.dec | 281 +++++++++---------
> 1 file changed, 139 insertions(+), 142 deletions(-)
>
> diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> index 856c17f737..c6b5881646 100644
> --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> @@ -14,184 +14,182 @@
>
>
>
>
> [Defines]
>
> -DEC_SPECIFICATION = 0x00010017
>
> -PACKAGE_NAME = MinPlatformPkg
>
> -PACKAGE_VERSION = 0.1
>
> -PACKAGE_GUID = 463B3B00-0D18-4a5f-90C0-D5B851D2574B
>
> -
>
> + DEC_SPECIFICATION = 0x00010017
>
> + PACKAGE_NAME = MinPlatformPkg
>
> + PACKAGE_VERSION = 0.1
>
> + PACKAGE_GUID = 463B3B00-0D18-4a5f-90C0-D5B851D2574B
>
>
>
> [Includes]
>
> -Include
>
> + Include
>
>
>
> [Ppis]
>
> -gEdkiiSiliconInitializedPpiGuid = {0x82a72dc8, 0x61ec, 0x403e, {0xb1, 0x5a,
> 0x8d, 0x7a, 0x3a, 0x71, 0x84, 0x98}}
>
> + gEdkiiSiliconInitializedPpiGuid = {0x82a72dc8, 0x61ec, 0x403e, {0xb1, 0x5a,
> 0x8d, 0x7a, 0x3a, 0x71, 0x84, 0x98}}
>
>
>
> -gPeiBaseMemoryTestPpiGuid = { 0xb6ec423c, 0x21d2, 0x490d, { 0x85,
> 0xc6, 0xdd, 0x58, 0x64, 0xea, 0xa6, 0x74 } }
>
> -gPeiPlatformMemorySizePpiGuid = { 0x9a7ef41e, 0xc140, 0x4bd1, { 0xb8,
> 0x84, 0x1e, 0x11, 0x24, 0x0b, 0x4c, 0xe6 } }
>
> + gPeiBaseMemoryTestPpiGuid = {0xb6ec423c, 0x21d2, 0x490d, {0x85,
> 0xc6, 0xdd, 0x58, 0x64, 0xea, 0xa6, 0x74}}
>
> + gPeiPlatformMemorySizePpiGuid = {0x9a7ef41e, 0xc140, 0x4bd1, {0xb8,
> 0x84, 0x1e, 0x11, 0x24, 0x0b, 0x4c, 0xe6}}
>
>
>
> [Guids]
>
> -gMinPlatformPkgTokenSpaceGuid = {0x69d13bf0, 0xaf91, 0x4d96,
> {0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}}
>
> + gMinPlatformPkgTokenSpaceGuid = {0x69d13bf0, 0xaf91, 0x4d96, {0xaa,
> 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}}
>
>
>
> -gAdapterInfoPlatformTestPointGuid = {0x5381e3ea, 0xb77, 0x4580, {0xad,
> 0xdf, 0xa9, 0x1c, 0x8, 0x3b, 0xf2, 0x97}}
>
> + gAdapterInfoPlatformTestPointGuid = {0x5381e3ea, 0x0b77, 0x4580,
> {0xad, 0xdf, 0xa9, 0x1c, 0x08, 0x3b, 0xf2, 0x97}}
>
>
>
> -gBoardDetectGuid = {0x1792429d, 0x9d94, 0x4e08, {0xa0, 0x99, 0x73,
> 0xa2, 0x86, 0xae, 0xb4, 0x35}}
>
> -gBoardPreMemInitGuid = {0x191dcfcf, 0xe16e, 0x43bb, {0x9b, 0xc3, 0x6e,
> 0xee, 0x6f, 0xab, 0x3a, 0x27}}
>
> -gBoardPostMemInitGuid = {0xa0e933ea, 0xa69, 0x47fb, {0xb2, 0xab,
> 0xa1, 0x6f, 0x71, 0x2d, 0x6f, 0x58}}
>
> -gBoardNotificationInitGuid = {0x78dbcabf, 0xc544, 0x4e6f, {0xaf, 0x3a, 0x71,
> 0x17, 0xd9, 0x42, 0x4e, 0xd1}}
>
> + gBoardDetectGuid = {0x1792429d, 0x9d94, 0x4e08, {0xa0, 0x99,
> 0x73, 0xa2, 0x86, 0xae, 0xb4, 0x35}}
>
> + gBoardPreMemInitGuid = {0x191dcfcf, 0xe16e, 0x43bb, {0x9b, 0xc3,
> 0x6e, 0xee, 0x6f, 0xab, 0x3a, 0x27}}
>
> + gBoardPostMemInitGuid = {0xa0e933ea, 0xa69, 0x47fb, {0xb2, 0xab,
> 0xa1, 0x6f, 0x71, 0x2d, 0x6f, 0x58}}
>
> + gBoardNotificationInitGuid = {0x78dbcabf, 0xc544, 0x4e6f, {0xaf, 0x3a,
> 0x71, 0x17, 0xd9, 0x42, 0x4e, 0xd1}}
>
>
>
> -gBoardAcpiTableGuid = {0xd70e9f57, 0x69f, 0x4bef, {0x96, 0xc0, 0x84,
> 0x74, 0xf4, 0xa2, 0x5f, 0x3a}}
>
> -gBoardAcpiEnableGuid = {0x9727b610, 0xf645, 0x4429, {0x89, 0x21, 0x2c,
> 0x2b, 0x58, 0xdc, 0xbb, 0xa}}
>
> + gBoardAcpiTableGuid = {0xd70e9f57, 0x69f, 0x4bef, {0x96, 0xc0,
> 0x84, 0x74, 0xf4, 0xa2, 0x5f, 0x3a}}
>
> + gBoardAcpiEnableGuid = {0x9727b610, 0xf645, 0x4429, {0x89, 0x21,
> 0x2c, 0x2b, 0x58, 0xdc, 0xbb, 0x0a}}
>
>
>
> -gDefaultDataFileGuid = { 0x1ae42876, 0x008f, 0x4161, { 0xb2,
> 0xb7, 0x1c, 0x0d, 0x15, 0xc5, 0xef, 0x43 }}
>
> -gDefaultDataOptSizeFileGuid = { 0x003e7b41, 0x98a2, 0x4be2, {
> 0xb2, 0x7a, 0x6c, 0x30, 0xc7, 0x65, 0x52, 0x25 }}
>
> + gDefaultDataFileGuid = {0x1ae42876, 0x008f, 0x4161, {0xb2, 0xb7,
> 0x1c, 0x0d, 0x15, 0xc5, 0xef, 0x43}}
>
> + gDefaultDataOptSizeFileGuid = {0x003e7b41, 0x98a2, 0x4be2, {0xb2,
> 0x7a, 0x6c, 0x30, 0xc7, 0x65, 0x52, 0x25}}
>
>
>
> [LibraryClasses]
>
>
>
> -PeiLib|Include/Library/PeiLib.h
>
> + PeiLib|Include/Library/PeiLib.h
>
>
>
> -AslUpdateLib|Include/Library/AslUpdateLib.h
>
> -BoardAcpiEnableLib|Include/Library/BoardAcpiEnableLib.h
>
> -BoardAcpiTableLib|Include/Library/BoardAcpiTableLib.h
>
> + AslUpdateLib|Include/Library/AslUpdateLib.h
>
> + BoardAcpiEnableLib|Include/Library/BoardAcpiEnableLib.h
>
> + BoardAcpiTableLib|Include/Library/BoardAcpiTableLib.h
>
>
>
> -SiliconPolicyInitLib|Include/Library/SiliconPolicyInitLib.h
>
> -SiliconPolicyUpdateLib|Include/Library/SiliconPolicyUpdateLib.h
>
> + SiliconPolicyInitLib|Include/Library/SiliconPolicyInitLib.h
>
> + SiliconPolicyUpdateLib|Include/Library/SiliconPolicyUpdateLib.h
>
>
>
> -SpiFlashCommonLib|Include/Library/SpiFlashCommonLib.h
>
> + SpiFlashCommonLib|Include/Library/SpiFlashCommonLib.h
>
>
>
> -BoardInitLib|Include/Library/BoardInitLib.h
>
> -MultiBoardInitSupportLib|Include/Library/MultiBoardInitSupportLib.h
>
> -SecBoardInitLib|Include/Library/SecBoardInitLib.h
>
> + BoardInitLib|Include/Library/BoardInitLib.h
>
> + MultiBoardInitSupportLib|Include/Library/MultiBoardInitSupportLib.h
>
> + SecBoardInitLib|Include/Library/SecBoardInitLib.h
>
>
>
> -TestPointLib|Include/Library/TestPointLib.h
>
> -TestPointCheckLib|Include/Library/TestPointCheckLib.h
>
> + TestPointLib|Include/Library/TestPointLib.h
>
> + TestPointCheckLib|Include/Library/TestPointCheckLib.h
>
>
>
> SetCacheMtrrLib|Include/Library/SetCacheMtrrLib.h
>
>
>
> [PcdsFixedAtBuild, PcdsPatchableInModule]
>
>
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFspMaxUpdSize|0x00000000|UINT32|
> 0x80000000
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFspReservedSizeOnStackTop|0x00000
> 040|UINT32|0x80000001
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0x00000000|UINT3
> 2|0x80000002
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFspMaxUpdSize|0x00000000|UINT32|
> 0x80000000
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFspReservedSizeOnStackTop|0x00000
> 040|UINT32|0x80000001
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0x00000000|UINT3
> 2|0x80000002
>
>
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000|UINT32
> |0x9000000B
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdLocalApicMmioSize|0x1000|UINT32|0
> x9000000C
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000|UINT32
> |0x9000000B
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdLocalApicMmioSize|0x1000|UINT32|0
> x9000000C
>
>
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress|0xFEC00000|UINT32|0
> x9000000D
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdIoApicMmioSize|0x1000|UINT32|0x90
> 00000E
>
> -gMinPlatformPkgTokenSpaceGuid.PcdIoApicId|0x02|UINT8|0x90000014
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress|0xFEC00000|UINT32|0
> x9000000D
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdIoApicMmioSize|0x1000|UINT32|0x90
> 00000E
>
> + gMinPlatformPkgTokenSpaceGuid.PcdIoApicId|0x02|UINT8|0x90000014
>
>
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x900
> 00012
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x900
> 00013
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x900
> 00012
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x900
> 00013
>
>
>
> -gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|0|UINT8|0x90000015
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase|0x09|UINT8|0x90000
> 016
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000|UI
> NT32|0x90000017
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicInterruptBase|24|UINT32|0x
> 90000018
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|0|UINT8|0x90000015
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase|0x09|UINT8|0x90000
> 016
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000|UI
> NT32|0x90000017
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicInterruptBase|24|UINT32|0x
> 90000018
>
>
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2|UINT32|0x90
> 000021
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8|UINT32|0x9000
> 0022
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|4|UINT32|0x90
> 000023
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2|UINT32|0x90
> 000021
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8|UINT32|0x9000
> 0022
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|4|UINT32|0x90
> 000023
>
>
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x02|UINT8|
> 0x90000025
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0001|UINT16|0x
> 90000026
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000086A5|UINT32|0x900
> 00027
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x02|UINT8|
> 0x90000025
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0001|UINT16|0x
> 90000026
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000086A5|UINT32|0x900
> 00027
>
>
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0
> x65|UINT32|0x20000500
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0x30
> |UINT32|0x20000501
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x4
> 02|UINT32|0x20000502
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b|
> UINT32|0x20000503
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x25|
> UINT32|0x20000504
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0
> x65|UINT32|0x20000500
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0x30
> |UINT32|0x20000501
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x4
> 02|UINT32|0x20000502
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b|
> UINT32|0x20000503
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x25|
> UINT32|0x20000504
>
>
>
> -#
>
> -# The PCDs are used to control the Windows SMM Security Mitigations Table
> - Protection Flags
>
> -#
>
> -# BIT0: If set, expresses that for all synchronous SMM entries,SMM will
> validate that input and output buffers lie entirely within the expected fixed
> memory regions.
>
> -# BIT1: If set, expresses that for all synchronous SMM entries, SMM will
> validate that input and output pointers embedded within the fixed
> communication buffer only refer to address ranges \
>
> -# that lie entirely within the expected fixed memory regions.
>
> -# BIT2: Firmware setting this bit is an indication that it will not allow
> reconfiguration of system resources via non-architectural mechanisms.
>
> -# BIT3-31: Reserved
>
> -#
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0|UINT32|0x10
> 001006
>
> + #
>
> + # The PCDs are used to control the Windows SMM Security Mitigations
> Table - Protection Flags
>
> + #
>
> + # BIT0: If set, expresses that for all synchronous SMM entries,SMM will
> validate that input and output buffers lie entirely within the expected fixed
> memory regions.
>
> + # BIT1: If set, expresses that for all synchronous SMM entries, SMM will
> validate that input and output pointers embedded within the fixed
> communication buffer only refer to address ranges \
>
> + # that lie entirely within the expected fixed memory regions.
>
> + # BIT2: Firmware setting this bit is an indication that it will not allow
> reconfiguration of system resources via non-architectural mechanisms.
>
> + # BIT3-31: Reserved
>
> + #
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0|UINT32|0x10
> 001006
>
>
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable|TRUE|BOO
> LEAN|0x00100206
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable|TRUE|BOO
> LEAN|0x00100206
>
>
>
> -#
>
> -# See HstiIbvFeatureBit.h for the definition
>
> -#
>
> -# #define HSTI_BYTE<X>_<AAA> BIT<Y>
>
> -#
>
> -# It means BYTE<X> BIT<Y> is for feature <AAA>.
>
> -#
>
> -gMinPlatformPkgTokenSpaceGuid.PcdHstiIbvPlatformFeature|{0x00, 0x00,
> 0x00}|VOID*|0x00100301
>
> + #
>
> + # See HstiIbvFeatureBit.h for the definition
>
> + #
>
> + # #define HSTI_BYTE<X>_<AAA> BIT<Y>
>
> + #
>
> + # It means BYTE<X> BIT<Y> is for feature <AAA>.
>
> + #
>
> + gMinPlatformPkgTokenSpaceGuid.PcdHstiIbvPlatformFeature|{0x00,
> 0x00, 0x00}|VOID*|0x00100301
>
>
>
> -#
>
> -# See TestPointCheckLib.h for the definition
>
> -#
>
> -# #define TEST_POINT_BYTE<X>_<AAA> BIT<Y>
>
> -#
>
> -# It means BYTE<X> BIT<Y> is for feature <AAA>.
>
> -# BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5
> BYTE6 BYTE7 BYTE8
>
> -# Stage debug: {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
>
> -# Stage memory: {0x03, 0x07, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
>
> -# Stage UEFI boot: {0x03, 0x07, 0x03, 0x05, 0x0F, 0x00,
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
>
> -# Stage OS boot: {0x03, 0x07, 0x03, 0x05, 0x3F, 0x00,
> 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
>
> -# Stage Secure boot: {0x03, 0x0F, 0x03, 0x1D, 0x3F,
> 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
>
> -# Stage Advanced: {0x03, 0x0F, 0x03, 0x1D, 0x3F,
> 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
>
> -gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03,
> 0x0F, 0x03, 0x1D, 0x3F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00}|VOID*|0x00100302
>
> + #
>
> + # See TestPointCheckLib.h for the definition
>
> + #
>
> + # #define TEST_POINT_BYTE<X>_<AAA> BIT<Y>
>
> + #
>
> + # It means BYTE<X> BIT<Y> is for feature <AAA>.
>
> + # BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5
> BYTE6 BYTE7 BYTE8
>
> + # Stage debug: {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
>
> + # Stage memory: {0x03, 0x07, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
>
> + # Stage UEFI boot: {0x03, 0x07, 0x03, 0x05, 0x0F,
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
>
> + # Stage OS boot: {0x03, 0x07, 0x03, 0x05, 0x3F,
> 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
>
> + # Stage Secure boot: {0x03, 0x0F, 0x03, 0x1D, 0x3F,
> 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
>
> + # Stage Advanced: {0x03, 0x0F, 0x03, 0x1D, 0x3F,
> 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03,
> 0x0F, 0x03, 0x1D, 0x3F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00}|VOID*|0x00100302
>
>
>
> -[PcdsFixedAtBuild, PcdsPatchableInModule]
>
> -##
>
> -## The Flash relevant PCD are ineffective and will be patched basing on FDF
> definitions during build.
>
> -## Set all of them to 0 here to prevent from confusion.
>
> -##
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFF800000|U
> INT32|0x10000001
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize|0x00800000|UINT32|0x
> 10000002
>
> -
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0xFFE60000|U
> INT32|0x30000004
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x000A0000|UI
> NT32|0x30000005
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset|0x00660000|
> UINT32|0x30000006
>
> -
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|0x00000000|
> UINT32|0x20000004
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize|0x00000000|
> UINT32|0x20000005
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|0x00000000
> |UINT32|0x20000006
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|0x00000000
> |UINT32|0x20000007
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize|0x00000000|
> UINT32|0x20000008
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|0x0000000
> 0|UINT32|0x20000009
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|0x00000000|UI
> NT32|0x2000000A
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize|0x00000000|UIN
> T32|0x2000000B
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|0x00000000|U
> INT32|0x2000000C
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|0x00000000|UINT
> 32|0x2000000D
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize|0x00000000|UINT
> 32|0x2000000E
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|0x00000000|UI
> NT32|0x2000000F
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|0x00000000|UIN
> T32|0x20000010
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize|0x00000000|UINT
> 32|0x20000011
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|0x00000000|UI
> NT32|0x20000012
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|0x00000000|UI
> NT32|0x20000013
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize|0x00000000|UI
> NT32|0x20000014
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|0x00000000|
> UINT32|0x20000015
>
> -
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageBase|0x00000000|UIN
> T32|0x20000016
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize|0x00000000|UINT
> 32|0x20000017
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset|0x00000000|UI
> NT32|0x20000018
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|0x0000
> 0000|UINT32|0x20000019
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|0x000
> 00000|UINT32|0x2000001A
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|0x
> 00000000|UINT32|0x2000001B
>
> -
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|0x00000000|UINT32
> |0x20000021
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize|0x00000000|UINT32|
> 0x20000022
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|0x00000000|UINT3
> 2|0x20000023
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|0x00000000|UINT3
> 2|0x20000024
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize|0x00000000|UINT32
> |0x20000025
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|0x00000000|UINT
> 32|0x20000026
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|0x00000000|UINT32
> |0x20000027
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize|0x00000000|UINT32|
> 0x20000028
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|0x00000000|UINT3
> 2|0x20000029
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUBase|0x00000000|UINT32
> |0x2000002A
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUSize|0x00000000|UINT32
> |0x2000002B
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUOffset|0x00000000|UINT
> 32|0x2000002C
>
> + ##
>
> + ## The Flash relevant PCD are ineffective and will be patched basing on
> FDF definitions during build.
>
> + ## Set all of them to 0 here to prevent from confusion.
>
> + ##
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFF800000|U
> INT32|0x10000001
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize|0x00800000|UINT32|0x
> 10000002
>
> +
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0xFFE60000|U
> INT32|0x30000004
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x000A0000|UI
> NT32|0x30000005
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset|0x00660000|
> UINT32|0x30000006
>
> +
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|0x00000000|
> UINT32|0x20000004
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize|0x00000000|
> UINT32|0x20000005
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|0x00000000
> |UINT32|0x20000006
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|0x00000000
> |UINT32|0x20000007
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize|0x00000000|
> UINT32|0x20000008
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|0x0000000
> 0|UINT32|0x20000009
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|0x00000000|UI
> NT32|0x2000000A
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize|0x00000000|UIN
> T32|0x2000000B
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|0x00000000|U
> INT32|0x2000000C
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|0x00000000|UINT
> 32|0x2000000D
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize|0x00000000|UINT
> 32|0x2000000E
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|0x00000000|UI
> NT32|0x2000000F
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|0x00000000|UIN
> T32|0x20000010
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize|0x00000000|UINT
> 32|0x20000011
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|0x00000000|UI
> NT32|0x20000012
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|0x00000000|UI
> NT32|0x20000013
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize|0x00000000|UI
> NT32|0x20000014
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|0x00000000|
> UINT32|0x20000015
>
> +
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageBase|0x00000000|UIN
> T32|0x20000016
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize|0x00000000|UINT
> 32|0x20000017
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset|0x00000000|UI
> NT32|0x20000018
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|0x0000
> 0000|UINT32|0x20000019
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|0x000
> 00000|UINT32|0x2000001A
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|0x
> 00000000|UINT32|0x2000001B
>
> +
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|0x00000000|UINT32
> |0x20000021
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize|0x00000000|UINT32|
> 0x20000022
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|0x00000000|UINT3
> 2|0x20000023
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|0x00000000|UINT3
> 2|0x20000024
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize|0x00000000|UINT32
> |0x20000025
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|0x00000000|UINT
> 32|0x20000026
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|0x00000000|UINT32
> |0x20000027
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize|0x00000000|UINT32|
> 0x20000028
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|0x00000000|UINT3
> 2|0x20000029
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUBase|0x00000000|UINT32
> |0x2000002A
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUSize|0x00000000|UINT32
> |0x2000002B
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUOffset|0x00000000|UINT
> 32|0x2000002C
>
>
>
> [PcdsDynamic, PcdsDynamicEx]
>
> -
> gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UINT32|0x90000
> 019
>
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UINT32|0x90000
> 019
>
>
>
> [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
>
>
>
> @@ -261,7 +259,7 @@
> gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UINT32|0x90000
> 019
>
>
> [PcdsFixedAtBuild]
>
>
>
> - #
>
> + ## MinPlatform Boot Stage Selector
>
> # Stage 1 - enable debug (system deadloop after debug init)
>
> # Stage 2 - mem init (system deadloop after mem init)
>
> # Stage 3 - boot to shell only
>
> @@ -305,4 +303,3 @@
> gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UINT32|0x90000
> 019
> gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable
> |FALSE|BOOLEAN|0xF00000A5
>
>
> gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE|BOOL
> EAN|0xF00000A6
>
> gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable
> |FALSE|BOOLEAN|0xF00000A7
>
> -
>
> --
> 2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 11/13] KabylakeOpenBoardPkg: Add support for PcdFspDispatchModeUseFspPeiMain
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 11/13] KabylakeOpenBoardPkg: Add support for PcdFspDispatchModeUseFspPeiMain Nate DeSimone
2019-11-14 15:18 ` Chiu, Chasel
@ 2019-11-16 2:54 ` Kubacki, Michael A
1 sibling, 0 replies; 44+ messages in thread
From: Kubacki, Michael A @ 2019-11-16 2:54 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io; +Cc: Chiu, Chasel
Reviewed-by: Michael Kubacki <michael.a.kubacki@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Wednesday, November 13, 2019 10:07 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>
> Subject: [edk2-platforms] [PATCH V1 11/13] KabylakeOpenBoardPkg: Add
> support for PcdFspDispatchModeUseFspPeiMain
>
> If PcdFspDispatchModeUseFspPeiMain is FALSE, then the BoardPkg should
> include PeiMain in FvPreMemory.
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../KabylakeRvp3/OpenBoardPkg.fdf | 5 +++--
> .../KabylakeRvp3/OpenBoardPkgPcd.dsc | 20 +++++++++++++++++++
> 2 files changed, 23 insertions(+), 2 deletions(-)
>
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> index 98eb7dcb5a..3b3b153b68 100644
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> +++
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> @@ -229,10 +229,11 @@ READ_LOCK_STATUS = TRUE
> FvNameGuid = FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D INF
> UefiCpuPkg/SecCore/SecCore.inf-!if
> (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) ||
> (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)+!if
> (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) ||
> (gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain ==
> FALSE) || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
> # # PeiMain is needed only for FSP API mode or EDK2 build,-# in FSP dispatch
> mode the one inside FSP Binary is launched.+# in FSP dispatch mode the one
> inside FSP Binary is launched+# unless requested otherwise
> (PcdFspDispatchModeUseFspPeiMain == FALSE). # INF
> MdeModulePkg/Core/Pei/PeiMain.inf !endifdiff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.
> dsc
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.
> dsc
> index 580504cbc1..5474edd01c 100644
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.
> dsc
> +++
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.
> d
> +++ sc
> @@ -39,6 +39,26 @@
> # gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE +
> #+ # FALSE: The PEI Main included in FvPreMemory is used to dispatch all
> PEIMs+ # (both inside FSP and outside FSP).+ # Pros:+ # * PEI
> Main is re-built from source and is always the latest version+ # *
> Platform code can link any desired LibraryClass to PEI Main+ # (Ex:
> Custom DebugLib instance, SerialPortLib, etc.)+ # Cons:+ # * The PEI
> Main being used to execute FSP PEIMs is not the PEI Main+ # that the
> FSP PEIMs were tested with, adding risk of breakage.+ # * Two copies of
> PEI Main will exist in the final binary,+ # #1 in FSP-M, #2 in
> FvPreMemory. The copy in FSP-M is never+ # executed, wasting
> space.+ #+ # <b>TRUE</b>: The PEI Main included in FSP is used to dispatch
> all PEIMs+ # (both inside FSP and outside FSP). PEI Main will not be
> included in+ # FvPreMemory. This is the default and is the recommended
> choice.+ #+
> gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TR
> UE+ # # FSP Base address PCD will be updated in FDF basing on flash map.
> #--
> 2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 12/13] KabylakeOpenBoardPkg: Remove SecFspWrapperPlatformSecLib override
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 12/13] KabylakeOpenBoardPkg: Remove SecFspWrapperPlatformSecLib override Nate DeSimone
2019-11-14 15:18 ` Chiu, Chasel
@ 2019-11-16 2:54 ` Kubacki, Michael A
1 sibling, 0 replies; 44+ messages in thread
From: Kubacki, Michael A @ 2019-11-16 2:54 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io; +Cc: Chiu, Chasel, Jeremy Soller
Reviewed-by: Michael Kubacki <michael.a.kubacki@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Wednesday, November 13, 2019 10:07 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>; Jeremy Soller <jeremy@system76.com>
> Subject: [edk2-platforms] [PATCH V1 12/13] KabylakeOpenBoardPkg:
> Remove SecFspWrapperPlatformSecLib override
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Jeremy Soller <jeremy@system76.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../FspWrapperPlatformSecLib.c | 186 ---------
> .../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 40 --
> .../SecFspWrapperPlatformSecLib/Ia32/Fsp.h | 42 --
> .../Ia32/PeiCoreEntry.nasm | 130 -------
> .../Ia32/SecEntry.nasm | 361 ------------------
> .../Ia32/Stack.nasm | 72 ----
> .../PlatformInit.c | 47 ---
> .../SecFspWrapperPlatformSecLib.inf | 97 -----
> .../SecGetPerformance.c | 89 -----
> .../SecPlatformInformation.c | 78 ----
> .../SecRamInitData.c | 36 --
> .../SecTempRamDone.c | 73 ----
> .../GalagoPro3/OpenBoardPkg.dsc | 2 +-
> .../KabylakeRvp3/OpenBoardPkg.dsc | 2 +-
> 14 files changed, 2 insertions(+), 1253 deletions(-) delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/FspWrapperPlatformSecLib.c
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/FsptCoreUpd.h
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/Ia32/Fsp.h
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/Ia32/PeiCoreEntry.nasm
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/Ia32/SecEntry.nasm
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/Ia32/Stack.nasm
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/PlatformInit.c
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/SecFspWrapperPlatformSecLib.inf
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/SecGetPerformance.c
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/SecPlatformInformation.c
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/SecRamInitData.c
> delete mode 100644
> Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper
> PlatformSecLib/SecTempRamDone.c
>
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/FspWrapperPlatformSecLib.c
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/FspWrapperPlatformSecLib.c
> deleted file mode 100644
> index d40eecae95..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/FspWrapperPlatformSecLib.c
> +++ /dev/null
> @@ -1,186 +0,0 @@
> -/** @file- Provide FSP wrapper platform sec related function.--Copyright
> (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>-SPDX-License-
> Identifier: BSD-2-Clause-Patent--**/--#include <PiPei.h>--#include
> <Ppi/SecPlatformInformation.h>-#include <Ppi/SecPerformance.h>-
> #include <Ppi/FirmwareVolumeInfo.h>-#include
> <Ppi/TopOfTemporaryRam.h>-#include <Ppi/PeiCoreFvLocation.h>-#include
> <Guid/FirmwareFileSystem2.h>--#include <Library/LocalApicLib.h>-#include
> <Library/BaseMemoryLib.h>-#include <Library/DebugLib.h>-#include
> <Library/IoLib.h>--/**- This interface conveys state information out of the
> Security (SEC) phase into PEI.-- @param[in] PeiServices Pointer to
> the PEI Services Table.- @param[in,out] StructureSize Pointer to the
> variable describing size of the input buffer.- @param[out]
> PlatformInformationRecord Pointer to the
> EFI_SEC_PLATFORM_INFORMATION_RECORD.-- @retval EFI_SUCCESS
> The data was successfully returned.- @retval EFI_BUFFER_TOO_SMALL The
> buffer was too small.--**/-EFI_STATUS-EFIAPI-SecPlatformInformation (- IN
> CONST EFI_PEI_SERVICES **PeiServices,- IN OUT UINT64
> *StructureSize,- OUT EFI_SEC_PLATFORM_INFORMATION_RECORD
> *PlatformInformationRecord- );--/**- This interface conveys performance
> information out of the Security (SEC) phase into PEI.-- This service is
> published by the SEC phase. The SEC phase handoff has an optional-
> EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed
> from SEC into the- PEI Foundation. As such, if the platform supports
> collecting performance data in SEC,- this information is encapsulated into the
> data structure abstracted by this service.- This information is collected for
> the boot-strap processor (BSP) on IA-32.-- @param[in] PeiServices The
> pointer to the PEI Services Table.- @param[in] This The pointer to this
> instance of the PEI_SEC_PERFORMANCE_PPI.- @param[out] Performance
> The pointer to performance data collected in SEC phase.-- @retval
> EFI_SUCCESS The data was successfully returned.--**/-EFI_STATUS-EFIAPI-
> SecGetPerformance (- IN CONST EFI_PEI_SERVICES **PeiServices,- IN
> PEI_SEC_PERFORMANCE_PPI *This,- OUT
> FIRMWARE_SEC_PERFORMANCE *Performance- );--
> PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi = {-
> SecGetPerformance-};--EFI_PEI_CORE_FV_LOCATION_PPI
> mPeiCoreFvLocationPpi = {- (VOID *) (UINTN) FixedPcdGet32
> (PcdFspmBaseAddress)-};--EFI_PEI_PPI_DESCRIPTOR
> mPeiCoreFvLocationPpiList[] = {- {- EFI_PEI_PPI_DESCRIPTOR_PPI,-
> &gEfiPeiCoreFvLocationPpiGuid,- &mPeiCoreFvLocationPpi- }-};--
> EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] = {- {-
> EFI_PEI_PPI_DESCRIPTOR_PPI,- &gTopOfTemporaryRamPpiGuid,- NULL
> // To be patched later.- },- {- EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,-
> &gPeiSecPerformancePpiGuid,- &mSecPerformancePpi- },-};--#define
> LEGACY_8259_MASK_REGISTER_MASTER 0x21-#define
> LEGACY_8259_MASK_REGISTER_SLAVE 0xA1-#define
> LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER 0x4D0-#define
> LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE 0x4D1--/**-
> Write to mask and edge/level triggered registers of master and slave 8259
> PICs.-- @param[in] Mask low byte for master PIC mask register,-
> high byte for slave PIC mask register.- @param[in] EdgeLevel low byte for
> master PIC edge/level triggered register,- high byte for slave PIC
> edge/level triggered register.--**/-VOID-Interrupt8259WriteMask (- IN
> UINT16 Mask,- IN UINT16 EdgeLevel- )-{- IoWrite8
> (LEGACY_8259_MASK_REGISTER_MASTER, (UINT8) Mask);- IoWrite8
> (LEGACY_8259_MASK_REGISTER_SLAVE, (UINT8) (Mask >> 8));- IoWrite8
> (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER, (UINT8)
> EdgeLevel);- IoWrite8
> (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE, (UINT8)
> (EdgeLevel >> 8));-}--/**- A developer supplied function to perform
> platform specific operations.-- It's a developer supplied function to perform
> any operations appropriate to a- given platform. It's invoked just before
> passing control to PEI core by SEC- core. Platform developer may modify the
> SecCoreData passed to PEI Core.- It returns a platform specific PPI list that
> platform wishes to pass to PEI core.- The Generic SEC core module will
> merge this list to join the final list passed to- PEI core.-- @param[in,out]
> SecCoreData The same parameter as passing to PEI core. It-
> could be overridden by this function.-- @return The platform specific PPI list
> to be passed to PEI core or- NULL if there is no need of such platform
> specific PPI list.--**/-EFI_PEI_PPI_DESCRIPTOR *-EFIAPI-SecPlatformMain (-
> IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData- )-{-
> EFI_PEI_PPI_DESCRIPTOR *PpiList;- UINT8
> TopOfTemporaryRamPpiIndex;- UINT8
> *CopyDestinationPointer;-- DEBUG ((DEBUG_INFO, "FSP Wrapper
> BootFirmwareVolumeBase - 0x%x\n", SecCoreData-
> >BootFirmwareVolumeBase));- DEBUG ((DEBUG_INFO, "FSP Wrapper
> BootFirmwareVolumeSize - 0x%x\n", SecCoreData-
> >BootFirmwareVolumeSize));- DEBUG ((DEBUG_INFO, "FSP Wrapper
> TemporaryRamBase - 0x%x\n", SecCoreData->TemporaryRamBase));-
> DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamSize - 0x%x\n",
> SecCoreData->TemporaryRamSize));- DEBUG ((DEBUG_INFO, "FSP Wrapper
> PeiTemporaryRamBase - 0x%x\n", SecCoreData-
> >PeiTemporaryRamBase));- DEBUG ((DEBUG_INFO, "FSP Wrapper
> PeiTemporaryRamSize - 0x%x\n", SecCoreData->PeiTemporaryRamSize));-
> DEBUG ((DEBUG_INFO, "FSP Wrapper StackBase - 0x%x\n",
> SecCoreData->StackBase));- DEBUG ((DEBUG_INFO, "FSP Wrapper StackSize
> - 0x%x\n", SecCoreData->StackSize));-- InitializeApicTimer (0, (UINT32) -1,
> TRUE, 5);-- //- // Set all 8259 interrupts to edge triggered and disabled- //-
> Interrupt8259WriteMask (0xFFFF, 0x0000);-- //- // Use middle of Heap as
> temp buffer, it will be copied by caller.- // Do not use Stack, because it will
> cause wrong calculation on stack by PeiCore- //- PpiList = (VOID *)((UINTN)
> SecCoreData->PeiTemporaryRamBase + (UINTN) SecCoreData-
> >PeiTemporaryRamSize/2);- CopyDestinationPointer = (UINT8 *) PpiList;-
> TopOfTemporaryRamPpiIndex = 0;- if (PcdGet8 (PcdFspModeSelection) ==
> 0) {- //- // In Dispatch mode, wrapper should provide
> PeiCoreFvLocationPpi.- //- CopyMem (CopyDestinationPointer,
> mPeiCoreFvLocationPpiList, sizeof (mPeiCoreFvLocationPpiList));-
> TopOfTemporaryRamPpiIndex = 1;- CopyDestinationPointer += sizeof
> (mPeiCoreFvLocationPpiList);- }- CopyMem (CopyDestinationPointer,
> mPeiSecPlatformPpi, sizeof(mPeiSecPlatformPpi));- //- // Patch
> TopOfTemporaryRamPpi- //- PpiList[TopOfTemporaryRamPpiIndex].Ppi =
> (VOID *)((UINTN) SecCoreData->TemporaryRamBase + SecCoreData-
> >TemporaryRamSize);-- return PpiList;-}diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/FsptCoreUpd.h
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/FsptCoreUpd.h
> deleted file mode 100644
> index 7c0f605b92..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/FsptCoreUpd.h
> +++ /dev/null
> @@ -1,40 +0,0 @@
> -/** @file--Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>-
> SPDX-License-Identifier: BSD-2-Clause-Patent--**/--#ifndef
> __FSPT_CORE_UPD_H__-#define __FSPT_CORE_UPD_H__--#pragma
> pack(1)--/** Fsp T Core UPD-**/-typedef struct {--/** Offset 0x0020-**/-
> UINT32 MicrocodeRegionBase;--/** Offset 0x0024-**/- UINT32
> MicrocodeRegionSize;--/** Offset 0x0028-**/- UINT32
> CodeRegionBase;--/** Offset 0x002C-**/- UINT32
> CodeRegionSize;--/** Offset 0x0030-**/- UINT8 Reserved[16];-}
> FSPT_CORE_UPD;--#pragma pack()--#endifdiff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/Ia32/Fsp.h
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/Ia32/Fsp.h
> deleted file mode 100644
> index 9f6cdcf476..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/Ia32/Fsp.h
> +++ /dev/null
> @@ -1,42 +0,0 @@
> -/** @file- Fsp related definitions--Copyright (c) 2017, Intel Corporation. All
> rights reserved.<BR>-SPDX-License-Identifier: BSD-2-Clause-Patent--**/--
> #ifndef __FSP_H__-#define __FSP_H__--//-// Fv Header-//-#define
> FVH_SIGINATURE_OFFSET 0x28-#define
> FVH_SIGINATURE_VALID_VALUE 0x4856465F // valid signature:_FVH-
> #define FVH_HEADER_LENGTH_OFFSET 0x30-#define
> FVH_EXTHEADER_OFFSET_OFFSET 0x34-#define
> FVH_EXTHEADER_SIZE_OFFSET 0x10--//-// Ffs Header-//-#define
> FSP_HEADER_GUID_DWORD1 0x912740BE-#define
> FSP_HEADER_GUID_DWORD2 0x47342284-#define
> FSP_HEADER_GUID_DWORD3 0xB08471B9-#define
> FSP_HEADER_GUID_DWORD4 0x0C3F3527-#define
> FFS_HEADER_SIZE_VALUE 0x18--//-// Section Header-//-#define
> SECTION_HEADER_TYPE_OFFSET 0x03-#define
> RAW_SECTION_HEADER_SIZE_VALUE 0x04--//-// Fsp Header-//-#define
> FSP_HEADER_IMAGEBASE_OFFSET 0x1C-#define
> FSP_HEADER_TEMPRAMINIT_OFFSET 0x30--#endifdiff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/Ia32/PeiCoreEntry.nasm
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/Ia32/PeiCoreEntry.nasm
> deleted file mode 100644
> index 5c5b788085..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/Ia32/PeiCoreEntry.nasm
> +++ /dev/null
> @@ -1,130 +0,0 @@
> -;-------------------------------------------------------------------------------;-;
> Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>-; SPDX-
> License-Identifier: BSD-2-Clause-Patent-;-; Module Name:-;-;
> PeiCoreEntry.nasm-;-; Abstract:-;-; Find and call SecStartup-;-;-----------------
> ---------------------------------------------------------------SECTION .text--extern
> ASM_PFX(SecStartup)-extern ASM_PFX(PlatformInit)--global
> ASM_PFX(CallPeiCoreEntryPoint)-ASM_PFX(CallPeiCoreEntryPoint):- ;- ;
> Obtain the hob list pointer- ;- mov eax, [esp+4]- ;- ; Obtain the stack
> information- ; ECX: start of range- ; EDX: end of range- ;- mov ecx,
> [esp+8]- mov edx, [esp+0xC]-- ;- ; Platform init- ;- pushad- push edx-
> push ecx- push eax- call ASM_PFX(PlatformInit)- pop eax- pop eax- pop
> eax- popad-- ;- ; Set stack top pointer- ;- mov esp, edx-- ;- ; Push the
> hob list pointer- ;- push eax-- ;- ; Save the value- ; ECX: start of range- ;
> EDX: end of range- ;- mov ebp, esp- push ecx- push edx-- ;- ; Push
> processor count to stack first, then BIST status (AP then BSP)- ;- mov eax,
> 1- cpuid- shr ebx, 16- and ebx, 0xFF- cmp bl, 1- jae
> PushProcessorCount-- ;- ; Some processors report 0 logical processors.
> Effectively 0 = 1.- ; So we fix up the processor count- ;- inc ebx--
> PushProcessorCount:- push ebx-- ;- ; We need to implement a long-term
> solution for BIST capture. For now, we just copy BSP BIST- ; for all processor
> threads- ;- xor ecx, ecx- mov cl, bl-PushBist:- movd eax, mm0- push
> eax- loop PushBist-- ; Save Time-Stamp Counter- movd eax, mm5- push
> eax-- movd eax, mm6- push eax-- ;- ; Pass entry point of the PEI core- ;-
> mov edi, 0xFFFFFFE0- push DWORD [edi]-- ;- ; Pass BFV into the PEI
> Core- ;- mov edi, 0xFFFFFFFC- push DWORD [edi]-- ;- ; Pass stack size
> into the PEI Core- ;- mov ecx, [ebp - 4]- mov edx, [ebp - 8]- push ecx
> ; RamBase-- sub edx, ecx- push edx ; RamSize-- ;- ; Pass Control into
> the PEI Core- ;- call ASM_PFX(SecStartup)-diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/Ia32/SecEntry.nasm
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/Ia32/SecEntry.nasm
> deleted file mode 100644
> index 7f6d771e41..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/Ia32/SecEntry.nasm
> +++ /dev/null
> @@ -1,361 +0,0 @@
> -;-------------------------------------------------------------------------------;-;
> Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>-; SPDX-
> License-Identifier: BSD-2-Clause-Patent-; Module Name:-;-; SecEntry.nasm-
> ;-; Abstract:-;-; This is the code that goes from real-mode to protected
> mode.-; It consumes the reset vector, calls TempRamInit API from FSP
> binary.-;-;--------------------------------------------------------------------------------
> #include "Fsp.h"--SECTION .text--extern ASM_PFX(CallPeiCoreEntryPoint)-
> extern ASM_PFX(FsptUpdDataPtr)-extern
> ASM_PFX(BoardBeforeTempRamInit)-; Pcds-extern ASM_PFX(PcdGet32
> (PcdFspTemporaryRamSize))-extern ASM_PFX(PcdGet32
> (PcdFsptBaseAddress))--;--------------------------------------------------------------
> ---------------;-; Procedure: _ModuleEntryPoint-;-; Input: None-;-;
> Output: None-;-; Destroys: Assume all registers-;-; Description:-;-;
> Transition to non-paged flat-model protected mode from a-; hard-coded
> GDT that provides exactly two descriptors.-; This is a bare bones transition
> to protected mode only-; used for a while in PEI and possibly DXE.-;-; After
> enabling protected mode, a far jump is executed to-; transfer to PEI using
> the newly loaded GDT.-;-; Return: None-;-; MMX Usage:-; MM0 =
> BIST State-; MM5 = Save time-stamp counter value high32bit-;
> MM6 = Save time-stamp counter value low32bit.-;-;-------------------------------
> -----------------------------------------------BITS 16-align 4-global
> ASM_PFX(_ModuleEntryPoint)-ASM_PFX(_ModuleEntryPoint):- fninit
> ; clear any pending Floating point exceptions- ;- ; Store the BIST value in
> mm0- ;- movd mm0, eax- cli-- ;- ; Check INIT# is asserted by port 0xCF9-
> ;- mov dx, 0CF9h- in al, dx- cmp al, 04h- jnz NotWarmStart--- ;- ; @note
> Issue warm reset, since if CPU only reset is issued not all MSRs are restored
> to their defaults- ;- mov dx, 0CF9h- mov al, 06h- out dx, al--NotWarmStart:-
> ;- ; Save time-stamp counter value- ; rdtsc load 64bit time-stamp counter to
> EDX:EAX- ;- rdtsc- movd mm5, edx- movd mm6, eax-- ;- ; Load the GDT
> table in GdtDesc- ;- mov esi, GdtDesc- DB 66h- lgdt [cs:si]-- ;- ;
> Transition to 16 bit protected mode- ;- mov eax, cr0 ; Get control
> register 0- or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1)-
> mov cr0, eax ; Activate protected mode-- mov eax, cr4
> ; Get control register 4- or eax, 00000600h ; Set OSFXSR bit (bit #9) &
> OSXMMEXCPT bit (bit #10)- mov cr4, eax-- ;- ; Now we're in 16 bit
> protected mode- ; Set up the selectors for 32 bit protected mode entry- ;-
> mov ax, SYS_DATA_SEL- mov ds, ax- mov es, ax- mov fs, ax- mov
> gs, ax- mov ss, ax-- ;- ; Transition to Flat 32 bit protected mode- ; The
> jump to a far pointer causes the transition to 32 bit mode- ;- mov esi,
> ProtectedModeEntryLinearAddress- jmp dword far [cs:si]--;------------------
> -----------------------------------------------------------;-; Procedure:
> ProtectedModeEntryPoint-;-; Input: None-;-; Output: None-;-;
> Destroys: Assume all registers-;-; Description:-;-; This function handles:-;
> Call two basic APIs from FSP binary-; Initializes stack with some early data
> (BIST, PEI entry, etc)-;-; Return: None-;-;-----------------------------------------
> -------------------------------------BITS 32-align 4-ProtectedModeEntryPoint:- ;-
> ; Early board hooks- ;- mov esp, BoardBeforeTempRamInitRet- jmp
> ASM_PFX(BoardBeforeTempRamInit)--BoardBeforeTempRamInitRet:-- ;
> Find the fsp info header- mov edi, [ASM_PFX(PcdGet32
> (PcdFsptBaseAddress))]-- mov eax, dword [edi +
> FVH_SIGINATURE_OFFSET]- cmp eax, FVH_SIGINATURE_VALID_VALUE-
> jnz FspHeaderNotFound-- xor eax, eax- mov ax, word [edi +
> FVH_EXTHEADER_OFFSET_OFFSET]- cmp ax, 0- jnz FspFvExtHeaderExist--
> xor eax, eax- mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass
> Fv Header- add edi, eax- jmp FspCheckFfsHeader--FspFvExtHeaderExist:-
> add edi, eax- mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ;
> Bypass Ext Fv Header- add edi, eax-- ; Round up to 8 byte alignment- mov
> eax, edi- and al, 07h- jz FspCheckFfsHeader-- and edi, 0FFFFFFF8h- add
> edi, 08h--FspCheckFfsHeader:- ; Check the ffs guid- mov eax, dword [edi]-
> cmp eax, FSP_HEADER_GUID_DWORD1- jnz FspHeaderNotFound-- mov
> eax, dword [edi + 4]- cmp eax, FSP_HEADER_GUID_DWORD2- jnz
> FspHeaderNotFound-- mov eax, dword [edi + 8]- cmp eax,
> FSP_HEADER_GUID_DWORD3- jnz FspHeaderNotFound-- mov eax, dword
> [edi + 0Ch]- cmp eax, FSP_HEADER_GUID_DWORD4- jnz
> FspHeaderNotFound-- add edi, FFS_HEADER_SIZE_VALUE ; Bypass the
> ffs header-- ; Check the section type as raw section- mov al, byte [edi +
> SECTION_HEADER_TYPE_OFFSET]- cmp al, 019h- jnz FspHeaderNotFound--
> add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header-
> jmp FspHeaderFound--FspHeaderNotFound:- jmp $--FspHeaderFound:- ;
> Get the fsp TempRamInit Api address- mov eax, dword [edi +
> FSP_HEADER_IMAGEBASE_OFFSET]- add eax, dword [edi +
> FSP_HEADER_TEMPRAMINIT_OFFSET]-- ; Setup the hardcode stack- mov
> esp, TempRamInitStack-- ; Call the fsp TempRamInit Api- jmp eax--
> TempRamInitDone:- cmp eax, 8000000Eh ;Check if EFI_NOT_FOUND
> returned. Error code for Microcode Update not found.- je CallSecFspInit
> ;If microcode not found, don't hang, but continue.-- cmp eax, 0 ;Check
> if EFI_SUCCESS retuned.- jnz FspApiFailed-- ; ECX: start of range- ; EDX:
> end of range-CallSecFspInit:- sub edx, [ASM_PFX(PcdGet32
> (PcdFspTemporaryRamSize))] ; TemporaryRam for FSP- xor eax, eax- mov
> esp, edx-- ; Align the stack at DWORD- add esp, 3- and esp, 0FFFFFFFCh--
> push edx- push ecx- push eax ; zero - no hob list yet- call
> ASM_PFX(CallPeiCoreEntryPoint)--FspApiFailed:- jmp $--align 10h-
> TempRamInitStack:- DD TempRamInitDone- DD
> ASM_PFX(FsptUpdDataPtr); TempRamInitParams--;-; ROM-based Global-
> Descriptor Table for the Tiano PEI Phase-;-align 16-global
> ASM_PFX(BootGdtTable)--;-; GDT[0]: 0x00: Null entry, never used.-;-
> NULL_SEL EQU $ - GDT_BASE ; Selector [0]-GDT_BASE:-
> ASM_PFX(BootGdtTable):- DD 0- DD 0-;-; Linear data
> segment descriptor-;-LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8]-
> DW 0FFFFh ; limit 0xFFFFF- DW 0 ; base 0- DB
> 0- DB 092h ; present, ring 0, data, expand-up, writable- DB
> 0CFh ; page-granular, 32-bit- DB 0-;-; Linear code segment
> descriptor-;-LINEAR_CODE_SEL EQU $ - GDT_BASE ; Selector [0x10]- DW
> 0FFFFh ; limit 0xFFFFF- DW 0 ; base 0- DB 0-
> DB 09Bh ; present, ring 0, data, expand-up, not-writable- DB
> 0CFh ; page-granular, 32-bit- DB 0-;-; System data segment
> descriptor-;-SYS_DATA_SEL EQU $ - GDT_BASE ; Selector [0x18]- DW
> 0FFFFh ; limit 0xFFFFF- DW 0 ; base 0- DB 0-
> DB 093h ; present, ring 0, data, expand-up, not-writable- DB
> 0CFh ; page-granular, 32-bit- DB 0--;-; System code segment
> descriptor-;-SYS_CODE_SEL EQU $ - GDT_BASE ; Selector [0x20]- DW
> 0FFFFh ; limit 0xFFFFF- DW 0 ; base 0- DB 0-
> DB 09Ah ; present, ring 0, data, expand-up, writable- DB 0CFh
> ; page-granular, 32-bit- DB 0-;-; Spare segment descriptor-;-
> SYS16_CODE_SEL EQU $ - GDT_BASE ; Selector [0x28]- DW 0FFFFh
> ; limit 0xFFFFF- DW 0 ; base 0- DB 0Eh ;
> Changed from F000 to E000.- DB 09Bh ; present, ring 0, code,
> expand-up, writable- DB 00h ; byte-granular, 16-bit- DB 0-;-;
> Spare segment descriptor-;-SYS16_DATA_SEL EQU $ - GDT_BASE ;
> Selector [0x30]- DW 0FFFFh ; limit 0xFFFF- DW 0
> ; base 0- DB 0- DB 093h ; present, ring 0, data, expand-up,
> not-writable- DB 00h ; byte-granular, 16-bit- DB 0--;-; Spare
> segment descriptor-;-SPARE5_SEL EQU $ - GDT_BASE ; Selector [0x38]-
> DW 0 ; limit 0- DW 0 ; base 0- DB 0- DB 0
> ; present, ring 0, data, expand-up, writable- DB 0 ; page-
> granular, 32-bit- DB 0-GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes--;-
> ; GDT Descriptor-;-GdtDesc: ; GDT descriptor- DW GDT_SIZE
> - 1 ; GDT limit- DD GDT_BASE ; GDT base address---
> ProtectedModeEntryLinearAddress:-ProtectedModeEntryLinear:- DD
> ProtectedModeEntryPoint ; Offset of our 32 bit code- DW
> LINEAR_CODE_SELdiff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/Ia32/Stack.nasm
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/Ia32/Stack.nasm
> deleted file mode 100644
> index 47db32d64c..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/Ia32/Stack.nasm
> +++ /dev/null
> @@ -1,72 +0,0 @@
> -;-------------------------------------------------------------------------------;-;
> Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>-; SPDX-
> License-Identifier: BSD-2-Clause-Patent-; Abstract:-;-; Switch the stack from
> temporary memory to permanent memory.-;-;-------------------------------------
> ------------------------------------------- SECTION .text--;----------------------------
> ---------------------------------------------------; VOID-; EFIAPI-; SecSwitchStack (-;
> UINT32 TemporaryMemoryBase,-; UINT32 PermanentMemoryBase-; );-
> ;-------------------------------------------------------------------------------global
> ASM_PFX(SecSwitchStack)-ASM_PFX(SecSwitchStack):- ;- ; Save three
> register: eax, ebx, ecx- ;- push eax- push ebx- push ecx- push edx--
> ;- ; !!CAUTION!! this function address's is pushed into stack after- ;
> migration of whole temporary memory, so need save it to permanent- ;
> memory at first!- ;-- mov ebx, [esp + 20] ; Save the first parameter-
> mov ecx, [esp + 24] ; Save the second parameter-- ;- ; Save this
> function's return address into permanent memory at first.- ; Then, Fixup
> the esp point to permanent memory- ;- mov eax, esp- sub eax, ebx-
> add eax, ecx- mov edx, dword [esp] ; copy pushed register's value to
> permanent memory- mov dword [eax], edx- mov edx, dword [esp + 4]-
> mov dword [eax + 4], edx- mov edx, dword [esp + 8]- mov dword [eax
> + 8], edx- mov edx, dword [esp + 12]- mov dword [eax + 12], edx- mov
> edx, dword [esp + 16] ; Update this function's return address into
> permanent memory- mov dword [eax + 16], edx- mov esp, eax
> ; From now, esp is pointed to permanent memory-- ;- ; Fixup the ebp
> point to permanent memory- ;- mov eax, ebp- sub eax, ebx- add
> eax, ecx- mov ebp, eax ; From now, ebp is pointed to permanent
> memory-- pop edx- pop ecx- pop ebx- pop eax- ret-diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/PlatformInit.c
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/PlatformInit.c
> deleted file mode 100644
> index ef89e3f310..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/PlatformInit.c
> +++ /dev/null
> @@ -1,47 +0,0 @@
> -/** @file- Provide platform init function.--Copyright (c) 2017, Intel
> Corporation. All rights reserved.<BR>-SPDX-License-Identifier: BSD-2-Clause-
> Patent--**/---#include <PiPei.h>-#include <Library/DebugLib.h>-#include
> <Library/SerialPortLib.h>-#include <Library/SecBoardInitLib.h>-#include
> <Library/TestPointCheckLib.h>--/**- Platform initialization.-- @param[in]
> FspHobList HobList produced by FSP.- @param[in] StartOfRange Start of
> temporary RAM.- @param[in] EndOfRange End of temporary RAM.-**/-
> VOID-EFIAPI-PlatformInit (- IN VOID *FspHobList,- IN VOID
> *StartOfRange,- IN VOID *EndOfRange- )-{- //- // Platform
> initialization- // Enable Serial port here- //- if
> (PcdGetBool(PcdSecSerialPortDebugEnable)) {- SerialPortInitialize ();- }--
> DEBUG ((DEBUG_INFO, "PrintPeiCoreEntryPointParam in PlatformInit\n"));-
> DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList));- DEBUG
> ((DEBUG_INFO, "StartOfRange - 0x%x\n", StartOfRange));- DEBUG
> ((DEBUG_INFO, "EndOfRange - 0x%x\n", EndOfRange));--
> BoardAfterTempRamInit ();-- TestPointTempMemoryFunction
> (StartOfRange, EndOfRange);-}diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> deleted file mode 100644
> index c99dd5ecdd..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> +++ /dev/null
> @@ -1,97 +0,0 @@
> -## @file-# Provide FSP wrapper platform sec related function.-#-#
> Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>-#-#
> SPDX-License-Identifier: BSD-2-Clause-Patent-#-#-##--
> ##########################################################
> ######################-#-# Defines Section - statements that will be
> processed to create a Makefile.-#-
> ##########################################################
> ######################-[Defines]- INF_VERSION =
> 0x00010005- BASE_NAME = SecFspWrapperPlatformSecLib-
> FILE_GUID = 4E1C4F95-90EA-47de-9ACC-B8920189A1F5-
> MODULE_TYPE = SEC- VERSION_STRING = 1.0-
> LIBRARY_CLASS = PlatformSecLib---#-# The following information is
> for reference only and not required by the build tools.-#-#
> VALID_ARCHITECTURES = IA32 X64-#--
> ##########################################################
> ######################-#-# Sources Section - list of files that are
> required for the build to succeed.-#-
> ##########################################################
> ######################--[Sources]- FspWrapperPlatformSecLib.c-
> SecRamInitData.c- SecPlatformInformation.c- SecGetPerformance.c-
> SecTempRamDone.c- PlatformInit.c--[Sources.IA32]- Ia32/SecEntry.nasm-
> Ia32/PeiCoreEntry.nasm- Ia32/Stack.nasm- Ia32/Fsp.h--
> ##########################################################
> ######################-#-# Package Dependency Section - list of
> Package files that are required for-# this module.-#-
> ##########################################################
> ######################--[Packages]- MdePkg/MdePkg.dec-
> MdeModulePkg/MdeModulePkg.dec- UefiCpuPkg/UefiCpuPkg.dec-
> IntelFsp2Pkg/IntelFsp2Pkg.dec-
> IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec-
> MinPlatformPkg/MinPlatformPkg.dec- KabylakeSiliconPkg/SiPkg.dec--
> [LibraryClasses]- LocalApicLib- SerialPortLib- FspWrapperPlatformLib-
> FspWrapperApiLib- BoardInitLib- SecBoardInitLib- TestPointCheckLib-
> PeiServicesTablePointerLib--[Ppis]- gEfiSecPlatformInformationPpiGuid
> ## CONSUMES- gPeiSecPerformancePpiGuid ## CONSUMES-
> gTopOfTemporaryRamPpiGuid ## PRODUCES-
> gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES-
> gFspTempRamExitPpiGuid ## CONSUMES--[Pcd]-
> gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize ##
> CONSUMES- gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress
> ## CONSUMES- gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize
> ## CONSUMES-
> gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ##
> CONSUMES--[FixedPcd]-
> gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress ##
> CONSUMES-
> gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ##
> CONSUMES- gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset
> ## CONSUMES-
> gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ##
> CONSUMES- gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize
> ## CONSUMES- gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress
> ## CONSUMES- gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection
> ## CONSUMESdiff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/SecGetPerformance.c
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/SecGetPerformance.c
> deleted file mode 100644
> index c4eeb2b188..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/SecGetPerformance.c
> +++ /dev/null
> @@ -1,89 +0,0 @@
> -/** @file- Sample to provide SecGetPerformance function.--Copyright (c)
> 2017, Intel Corporation. All rights reserved.<BR>-SPDX-License-Identifier:
> BSD-2-Clause-Patent--**/--#include <PiPei.h>--#include
> <Ppi/SecPerformance.h>-#include <Ppi/TopOfTemporaryRam.h>--#include
> <Library/BaseMemoryLib.h>-#include <Library/TimerLib.h>-#include
> <Library/DebugLib.h>--/**- This interface conveys performance information
> out of the Security (SEC) phase into PEI.-- This service is published by the SEC
> phase. The SEC phase handoff has an optional- EFI_PEI_PPI_DESCRIPTOR list
> as its final argument when control is passed from SEC into the- PEI
> Foundation. As such, if the platform supports collecting performance data in
> SEC,- this information is encapsulated into the data structure abstracted by
> this service.- This information is collected for the boot-strap processor (BSP)
> on IA-32.-- @param[in] PeiServices The pointer to the PEI Services Table.-
> @param[in] This The pointer to this instance of the
> PEI_SEC_PERFORMANCE_PPI.- @param[out] Performance The pointer to
> performance data collected in SEC phase.-- @retval EFI_SUCCESS The data
> was successfully returned.--**/-EFI_STATUS-EFIAPI-SecGetPerformance (-
> IN CONST EFI_PEI_SERVICES **PeiServices,- IN
> PEI_SEC_PERFORMANCE_PPI *This,- OUT
> FIRMWARE_SEC_PERFORMANCE *Performance- )-{- UINT32 Size;-
> UINT32 Count;- UINT32 TopOfTemporaryRam;- UINT64 Ticker;-
> VOID *TopOfTemporaryRamPpi;- EFI_STATUS Status;-- DEBUG
> ((DEBUG_INFO, "SecGetPerformance\n"));-- Status = (*PeiServices)-
> >LocatePpi (- PeiServices,-
> &gTopOfTemporaryRamPpiGuid,- 0,- NULL,-
> (VOID **) &TopOfTemporaryRamPpi- );- if (EFI_ERROR
> (Status)) {- return EFI_NOT_FOUND;- }- //- // |--------------| <-
> TopOfTemporaryRam - BL- // | List Ptr |- // |--------------|- // | BL RAM
> Start |- // |--------------|- // | BL RAM End |- // |--------------|- // |Number
> of BSPs|- // |--------------|- // | BIST |- // |--------------|- // | .... |-
> // |--------------|- // | TSC[63:32] |- // |--------------|- // | TSC[31:00] |- //
> |--------------|- //- TopOfTemporaryRam =
> (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof(UINT32);-
> TopOfTemporaryRam -= sizeof(UINT32) * 2;- Count = *(UINT32 *)
> (UINTN) (TopOfTemporaryRam - sizeof (UINT32));- Size = Count *
> sizeof (UINT32);-- Ticker = *(UINT64 *) (UINTN) (TopOfTemporaryRam -
> sizeof (UINT32) - Size - sizeof (UINT32) * 2);- Performance->ResetEnd =
> GetTimeInNanoSecond (Ticker);-- return EFI_SUCCESS;-}diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/SecPlatformInformation.c
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/SecPlatformInformation.c
> deleted file mode 100644
> index 5b94ed2bef..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/SecPlatformInformation.c
> +++ /dev/null
> @@ -1,78 +0,0 @@
> -/** @file- Provide SecPlatformInformation function.--Copyright (c) 2017,
> Intel Corporation. All rights reserved.<BR>-SPDX-License-Identifier: BSD-2-
> Clause-Patent--**/--#include <PiPei.h>--#include
> <Ppi/SecPlatformInformation.h>-#include <Ppi/TopOfTemporaryRam.h>--
> #include <Library/BaseMemoryLib.h>-#include <Library/DebugLib.h>--/**-
> This interface conveys state information out of the Security (SEC) phase into
> PEI.-- @param[in] PeiServices Pointer to the PEI Services Table.-
> @param[in,out] StructureSize Pointer to the variable describing size of
> the input buffer.- @param[out] PlatformInformationRecord Pointer to the
> EFI_SEC_PLATFORM_INFORMATION_RECORD.-- @retval EFI_SUCCESS
> The data was successfully returned.- @retval EFI_BUFFER_TOO_SMALL The
> buffer was too small.--**/-EFI_STATUS-EFIAPI-SecPlatformInformation (- IN
> CONST EFI_PEI_SERVICES **PeiServices,- IN OUT UINT64
> *StructureSize,- OUT EFI_SEC_PLATFORM_INFORMATION_RECORD
> *PlatformInformationRecord- )-{- UINT32 *Bist;- UINT32 Size;- UINT32
> Count;- UINT32 TopOfTemporaryRam;- VOID
> *TopOfTemporaryRamPpi;- EFI_STATUS Status;-- DEBUG ((DEBUG_INFO,
> "SecPlatformInformation\n"));-- Status = (*PeiServices)->LocatePpi (-
> PeiServices,- &gTopOfTemporaryRamPpiGuid,-
> 0,- NULL,- (VOID **) &TopOfTemporaryRamPpi-
> );- if (EFI_ERROR (Status)) {- return EFI_NOT_FOUND;- }-- //- // The
> entries of BIST information, together with the number of them,- // reside in
> the bottom of stack, left untouched by normal stack operation.- // This
> routine copies the BIST information to the buffer pointed by- //
> PlatformInformationRecord for output.- //- TopOfTemporaryRam =
> (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof (UINT32);-
> TopOfTemporaryRam -= sizeof(UINT32) * 2;- Count = *((UINT32
> *)(UINTN) (TopOfTemporaryRam - sizeof (UINT32)));- Size = Count *
> sizeof (IA32_HANDOFF_STATUS);-- if ((*StructureSize) < (UINT64) Size) {-
> *StructureSize = Size;- return EFI_BUFFER_TOO_SMALL;- }--
> *StructureSize = Size;- Bist = (UINT32 *) (TopOfTemporaryRam - sizeof
> (UINT32) - Size);-- CopyMem (PlatformInformationRecord, Bist, Size);--
> return EFI_SUCCESS;-}diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/SecRamInitData.c
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/SecRamInitData.c
> deleted file mode 100644
> index b356327b4c..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/SecRamInitData.c
> +++ /dev/null
> @@ -1,36 +0,0 @@
> -/** @file- Provide TempRamInitParams data.--Copyright (c) 2017, Intel
> Corporation. All rights reserved.<BR>-SPDX-License-Identifier: BSD-2-Clause-
> Patent--**/--#include <Library/PcdLib.h>-#include <FspEas.h>-#include
> "FsptCoreUpd.h"--typedef struct {- FSP_UPD_HEADER FspUpdHeader;-
> FSPT_CORE_UPD FsptCoreUpd;-} FSPT_UPD_CORE_DATA;--
> GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA
> FsptUpdDataPtr = {- {- 0x4450555F54505346,- 0x00,- { 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,- 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00- }- },- {- ((UINT32)FixedPcdGet64
> (PcdCpuMicrocodePatchAddress) + FixedPcdGet32
> (PcdFlashMicrocodeOffset)),- ((UINT32)FixedPcdGet64
> (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet32
> (PcdFlashMicrocodeOffset)),- 0, // Set CodeRegionBase as 0, so that
> caching will be 4GB-(CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize)
> will be used.- FixedPcdGet32 (PcdFlashCodeCacheSize),- { 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,- 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00- }- }-};-diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/SecTempRamDone.c
> b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap
> perPlatformSecLib/SecTempRamDone.c
> deleted file mode 100644
> index 922e4ec204..0000000000
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/SecTempRamDone.c
> +++ /dev/null
> @@ -1,73 +0,0 @@
> -/** @file- Provide SecTemporaryRamDone function.--Copyright (c) 2017 -
> 2019, Intel Corporation. All rights reserved.<BR>-SPDX-License-Identifier:
> BSD-2-Clause-Patent--**/--#include <PiPei.h>--#include
> <Ppi/TemporaryRamDone.h>-#include <Ppi/TempRamExitPpi.h>--#include
> <Library/BaseMemoryLib.h>-#include <Library/DebugLib.h>-#include
> <Library/PcdLib.h>-#include <Library/DebugAgentLib.h>-#include
> <Library/FspWrapperPlatformLib.h>-#include
> <Library/FspWrapperApiLib.h>-#include <Library/BoardInitLib.h>-#include
> <Library/PeiServicesTablePointerLib.h>--/**-This interface disables
> temporary memory in SEC Phase.-**/-VOID-EFIAPI-
> SecPlatformDisableTemporaryMemory (- VOID- )-{- EFI_STATUS
> Status;- VOID *TempRamExitParam;- CONST EFI_PEI_SERVICES
> **PeiServices;- FSP_TEMP_RAM_EXIT_PPI *TempRamExitPpi;-- DEBUG
> ((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n"));-- Status
> = BoardInitBeforeTempRamExit ();- ASSERT_EFI_ERROR (Status);-- if
> (PcdGet8 (PcdFspModeSelection) == 1) {- //- // FSP API mode- //-
> TempRamExitParam = UpdateTempRamExitParam ();- Status =
> CallTempRamExit (TempRamExitParam);- DEBUG ((DEBUG_INFO,
> "TempRamExit status: 0x%x\n", Status));- ASSERT_EFI_ERROR (Status);- }
> else {- //- // FSP Dispatch mode- //- PeiServices =
> GetPeiServicesTablePointer ();- Status = (*PeiServices)->LocatePpi (-
> PeiServices,- &gFspTempRamExitPpiGuid,- 0,-
> NULL,- (VOID **) &TempRamExitPpi- );-
> ASSERT_EFI_ERROR (Status);- if (EFI_ERROR (Status)) {- return;- }-
> TempRamExitPpi->TempRamExit (NULL);- }-- Status =
> BoardInitAfterTempRamExit ();- ASSERT_EFI_ERROR (Status);-- return ;-}diff
> --git
> a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> index 2bc2b4126b..acdc31e708 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> +++
> b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
> @@ -126,7 +126,7 @@
> #######################################
> GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpan
> derLib/BaseGpioExpanderLib.inf
> I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2
> cAccessLib.inf-
> PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFs
> pWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf+
> PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/SecFspWrapperPlatformSecLib.inf # Thunderbolt !if
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUEdiff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> index 77e4a6a610..4b07c0a684 100644
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> +++
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
> @@ -166,7 +166,7 @@
> EcLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseEcLib/BaseEcLib.inf
> GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpan
> derLib/BaseGpioExpanderLib.inf
> I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2
> cAccessLib.inf-
> PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFs
> pWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf+
> PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapp
> erPlatformSecLib/SecFspWrapperPlatformSecLib.inf # Thunderbolt !if
> gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE--
> 2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 13/13] MinPlatformPkg: Remove BoardInitLib dependency from PlatformSecLib
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 13/13] MinPlatformPkg: Remove BoardInitLib dependency from PlatformSecLib Nate DeSimone
2019-11-14 15:18 ` Chiu, Chasel
@ 2019-11-16 2:56 ` Kubacki, Michael A
1 sibling, 0 replies; 44+ messages in thread
From: Kubacki, Michael A @ 2019-11-16 2:56 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io; +Cc: Chiu, Chasel, Gao, Liming
SecFspWrapperPlatformSecLib.inf:
* Line 72: It seems BoardInitLib should be able to be removed from [LibraryClasses] with gPlatformInitTempRamExitPpiGuid
Can you please check?
> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Wednesday, November 13, 2019 10:07 PM
> To: devel@edk2.groups.io
> Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Chiu, Chasel
> <chasel.chiu@intel.com>; Gao, Liming <liming.gao@intel.com>
> Subject: [edk2-platforms] [PATCH V1 13/13] MinPlatformPkg: Remove
> BoardInitLib dependency from PlatformSecLib
>
> SecFspWrapperPlatformSecLib contains the implementation of
> SecPlatformDisableTemporaryMemory(), which SecMain in UefiCpuPkg will
> call as part of its implementation of EFI_PEI_TEMPORARY_RAM_DONE_PPI.
> For platforms that use FSP, the implementation of
> SecPlatformDisableTemporaryMemory() can be made generic since the
> chipset specifics will be contained in FspTempRamExit().
>
> The Minimum Platform Specification provides the BoardPkg two interface
> hook points, BoardInitBeforeTempRamExit() and
> BoardInitAfterTempRamExit() which must be called during
> SecPlatformDisableTemporaryMemory(). Due to
> EFI_PEI_TEMPORARY_RAM_DONE_PPI being a special case of a PPI that is
> implemented in SEC, these two functions are the only ones in BoardInitLib
> that need to be called by SEC.
>
> Linking BoardInitLib with SEC places many restrictions on the implementation
> of that library. The features available to SEC phase code are very minimal.
> Since this code runs during PEI phase, these restrictions are not actually
> required.
>
> Instead of directly linking with BoardInitLib,
> SecPlatformDisableTemporaryMemory() shall call BoardInitLib indirectly
> through a PPI (PLATFORM_INIT_TEMP_RAM_EXIT_PPI.) This PPI is produced
> by PlatformInitPreMem, which implements the other BoardInitLib calls
> already, so this change should also slightly reduce the size of the final binary
> image since less PE/COFF images will need to link with BoardInitLib.
>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../SecFspWrapperPlatformSecLib.inf | 1 +
> .../SecTempRamDone.c | 36 +++++++--
> .../Include/Ppi/PlatformInitTempRamExitPpi.h | 55 ++++++++++++++
> .../Intel/MinPlatformPkg/MinPlatformPkg.dec | 2 +
> .../PlatformInitPei/PlatformInitPreMem.c | 76 ++++++++++++++++++-
> .../PlatformInitPei/PlatformInitPreMem.inf | 1 +
> 6 files changed, 159 insertions(+), 12 deletions(-) create mode 100644
> Platform/Intel/MinPlatformPkg/Include/Ppi/PlatformInitTempRamExitPpi.h
>
> diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatf
> ormSecLib/SecFspWrapperPlatformSecLib.inf
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatf
> ormSecLib/SecFspWrapperPlatformSecLib.inf
> index 02c720c73d..3465f50126 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatf
> ormSecLib/SecFspWrapperPlatformSecLib.inf
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/SecFspWrapperPlatformSecLib.inf
> @@ -80,6 +80,7 @@
> gTopOfTemporaryRamPpiGuid ## PRODUCES
> gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES
> gFspTempRamExitPpiGuid ## CONSUMES+
> gPlatformInitTempRamExitPpiGuid ## CONSUMES [Pcd]
> gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize ##
> CONSUMESdiff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatf
> ormSecLib/SecTempRamDone.c
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatf
> ormSecLib/SecTempRamDone.c
> index 922e4ec204..b22cf57d6c 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatf
> ormSecLib/SecTempRamDone.c
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/SecTempRamDone.c
> @@ -10,6 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> #include <Ppi/TemporaryRamDone.h> #include
> <Ppi/TempRamExitPpi.h>+#include <Ppi/PlatformInitTempRamExitPpi.h>
> #include <Library/BaseMemoryLib.h> #include <Library/DebugLib.h>@@ -
> 17,7 +18,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include
> <Library/DebugAgentLib.h> #include <Library/FspWrapperPlatformLib.h>
> #include <Library/FspWrapperApiLib.h>-#include <Library/BoardInitLib.h>
> #include <Library/PeiServicesTablePointerLib.h> /**@@ -29,14 +29,35 @@
> SecPlatformDisableTemporaryMemory (
> VOID ) {- EFI_STATUS Status;- VOID
> *TempRamExitParam;- CONST EFI_PEI_SERVICES **PeiServices;-
> FSP_TEMP_RAM_EXIT_PPI *TempRamExitPpi;+ EFI_STATUS
> Status;+ VOID *TempRamExitParam;+ CONST
> EFI_PEI_SERVICES **PeiServices;+ FSP_TEMP_RAM_EXIT_PPI
> *TempRamExitPpi;+ PLATFORM_INIT_TEMP_RAM_EXIT_PPI
> *PlatformInitTempRamExitPpi; DEBUG ((DEBUG_INFO,
> "SecPlatformDisableTemporaryMemory enter\n"));+ PeiServices =
> GetPeiServicesTablePointer ();+ ASSERT (PeiServices != NULL);+ if
> (PeiServices == NULL) {+ return;+ }+ ASSERT ((*PeiServices) != NULL);+ if
> ((*PeiServices) == NULL) {+ return;+ }+ Status = (*PeiServices)->LocatePpi
> (+ PeiServices,+
> &gPlatformInitTempRamExitPpiGuid,+ 0,+ NULL,+
> (VOID **) &PlatformInitTempRamExitPpi+ );+
> ASSERT_EFI_ERROR (Status);+ if (EFI_ERROR (Status)) {+ return;+ } - Status
> = BoardInitBeforeTempRamExit ();+ Status = PlatformInitTempRamExitPpi-
> >PlatformInitBeforeTempRamExit (); ASSERT_EFI_ERROR (Status); if
> (PcdGet8 (PcdFspModeSelection) == 1) {@@ -51,7 +72,6 @@
> SecPlatformDisableTemporaryMemory (
> // // FSP Dispatch mode //- PeiServices = GetPeiServicesTablePointer
> (); Status = (*PeiServices)->LocatePpi ( PeiServices,
> &gFspTempRamExitPpiGuid,@@ -66,7 +86,7 @@
> SecPlatformDisableTemporaryMemory (
> TempRamExitPpi->TempRamExit (NULL); } - Status =
> BoardInitAfterTempRamExit ();+ Status = PlatformInitTempRamExitPpi-
> >PlatformInitAfterTempRamExit (); ASSERT_EFI_ERROR (Status); return
> ;diff --git
> a/Platform/Intel/MinPlatformPkg/Include/Ppi/PlatformInitTempRamExitPpi.
> h
> b/Platform/Intel/MinPlatformPkg/Include/Ppi/PlatformInitTempRamExitPpi.
> h
> new file mode 100644
> index 0000000000..590647738c
> --- /dev/null
> +++
> b/Platform/Intel/MinPlatformPkg/Include/Ppi/PlatformInitTempRamExitP
> +++ pi.h
> @@ -0,0 +1,55 @@
> +/** @file+ This file defines the PPI for notifying PlatformInitPreMem+ of
> temporary memory being disabled.++Copyright (c) 2019, Intel Corporation.
> All rights reserved.<BR>+SPDX-License-Identifier: BSD-2-Clause-
> Patent++**/++#ifndef
> _PLATFORM_INIT_TEMP_RAM_EXIT_PPI_H_+#define
> _PLATFORM_INIT_TEMP_RAM_EXIT_PPI_H_++#include <PiPei.h>++//+//
> Forward declaration for the
> PLATFORM_INIT_TEMP_RAM_EXIT_PPI.+//+typedef struct
> _PLATFORM_INIT_TEMP_RAM_EXIT_PPI
> PLATFORM_INIT_TEMP_RAM_EXIT_PPI;++/**+ A hook for platform-specific
> initialization prior to disabling temporary RAM.++ @retval EFI_SUCCESS The
> platform initialization was successful.+ @retval EFI_NOT_READY The
> platform has not been detected yet.+**/+typedef+EFI_STATUS+(EFIAPI
> *PLATFORM_INIT_BEFORE_TEMP_RAM_EXIT) (+ VOID+ );++/**+ A hook
> for platform-specific initialization after disabling temporary RAM.++ @retval
> EFI_SUCCESS The platform initialization was successful.+ @retval
> EFI_NOT_READY The platform has not been detected
> yet.+**/+typedef+EFI_STATUS+(EFIAPI
> *PLATFORM_INIT_AFTER_TEMP_RAM_EXIT) (+ VOID+ );++///+/// This PPI
> provides functions for notifying PlatformInitPreMem+/// of temporary
> memory being disabled.+///+struct
> _PLATFORM_INIT_TEMP_RAM_EXIT_PPI {+
> PLATFORM_INIT_BEFORE_TEMP_RAM_EXIT
> PlatformInitBeforeTempRamExit;+
> PLATFORM_INIT_AFTER_TEMP_RAM_EXIT
> PlatformInitAfterTempRamExit;+};++extern EFI_GUID
> gPlatformInitTempRamExitPpiGuid;++#endif //
> _PLATFORM_INIT_TEMP_RAM_EXIT_PPI_H_diff --git
> a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> index c6b5881646..5dfa4d420e 100644
> --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
> @@ -28,6 +28,8 @@
> gPeiBaseMemoryTestPpiGuid = {0xb6ec423c, 0x21d2, 0x490d, {0x85,
> 0xc6, 0xdd, 0x58, 0x64, 0xea, 0xa6, 0x74}} gPeiPlatformMemorySizePpiGuid
> = {0x9a7ef41e, 0xc140, 0x4bd1, {0xb8, 0x84, 0x1e, 0x11, 0x24, 0x0b, 0x4c,
> 0xe6}} + gPlatformInitTempRamExitPpiGuid = {0xbae23646, 0xbd60, 0x4f8b,
> {0xb3, 0xf9, 0xf3, 0x91, 0xee, 0x7e, 0xe6, 0xc8}}+ [Guids]
> gMinPlatformPkgTokenSpaceGuid = {0x69d13bf0, 0xaf91, 0x4d96, {0xaa,
> 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}} diff --git
> a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitP
> reMem.c
> b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitP
> reMem.c
> index c579ff008e..efdeb6a91c 100644
> ---
> a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitP
> reMem.c
> +++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/Platfor
> +++ mInitPreMem.c
> @@ -29,6 +29,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include
> <Guid/MemoryTypeInformation.h> #include <Ppi/PlatformMemorySize.h>
> #include <Ppi/BaseMemoryTest.h>+#include
> <Ppi/PlatformInitTempRamExitPpi.h> EFI_STATUS EFIAPI@@ -72,7 +73,31
> @@ BaseMemoryTest (
> OUT EFI_PHYSICAL_ADDRESS *ErrorAddress ); -static
> EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList = {+/**+ A hook
> for platform-specific initialization prior to disabling temporary RAM.++
> @retval EFI_SUCCESS The platform initialization was successful.+ @retval
> EFI_NOT_READY The platform has not been detected
> yet.+**/+EFI_STATUS+EFIAPI+PlatformInitBeforeTempRamExit (+ VOID+
> );++/**+ A hook for platform-specific initialization after disabling temporary
> RAM.++ @retval EFI_SUCCESS The platform initialization was successful.+
> @retval EFI_NOT_READY The platform has not been detected
> yet.+**/+EFI_STATUS+EFIAPI+PlatformInitAfterTempRamExit (+ VOID+
> );++GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_NOTIFY_DESCRIPTOR
> mMemDiscoveredNotifyList = {
> (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
> &gEfiPeiMemoryDiscoveredPpiGuid, (EFI_PEIM_NOTIFY_ENTRY_POINT)
> MemoryDiscoveredPpiNotifyCallback@@ -90,11 +115,11 @@
> GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR
> mPpiBootMode = {
> NULL }; -static PEI_BASE_MEMORY_TEST_PPI mPeiBaseMemoryTestPpi =
> { BaseMemoryTest };+GLOBAL_REMOVE_IF_UNREFERENCED
> PEI_BASE_MEMORY_TEST_PPI mPeiBaseMemoryTestPpi = {
> BaseMemoryTest }; -static PEI_PLATFORM_MEMORY_SIZE_PPI
> mMemoryMemorySizePpi = { GetPlatformMemorySize
> };+GLOBAL_REMOVE_IF_UNREFERENCED
> PEI_PLATFORM_MEMORY_SIZE_PPI mMemoryMemorySizePpi = {
> GetPlatformMemorySize }; -static EFI_PEI_PPI_DESCRIPTOR
> mMemPpiList[] = {+GLOBAL_REMOVE_IF_UNREFERENCED
> EFI_PEI_PPI_DESCRIPTOR mMemPpiList[] = { {
> EFI_PEI_PPI_DESCRIPTOR_PPI, &gPeiBaseMemoryTestPpiGuid,@@ -107,6
> +132,17 @@ static EFI_PEI_PPI_DESCRIPTOR mMemPpiList[] = {
> }, }; +GLOBAL_REMOVE_IF_UNREFERENCED
> PLATFORM_INIT_TEMP_RAM_EXIT_PPI mPlatformInitTempRamExitPpi = {+
> PlatformInitBeforeTempRamExit,+
> PlatformInitAfterTempRamExit+};++GLOBAL_REMOVE_IF_UNREFERENCED
> EFI_PEI_PPI_DESCRIPTOR mPlatformInitTempRamExitPpiDesc = {+
> (EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),+
> &gPlatformInitTempRamExitPpiGuid,+ &mPlatformInitTempRamExitPpi+};+
> /// /// Memory Reserved should be between 125% to 150% of the Current
> required memory /// otherwise BdsMisc.c would do a reset to make it 125%
> to avoid s4 resume issues.@@ -391,6 +427,35 @@
> MemoryDiscoveredPpiNotifyCallback (
> return Status; } +/**+ A hook for platform-specific initialization prior to
> disabling temporary RAM.++ @retval EFI_SUCCESS The platform
> initialization was successful.+ @retval EFI_NOT_READY The platform has not
> been detected
> yet.+**/+EFI_STATUS+EFIAPI+PlatformInitBeforeTempRamExit (+ VOID+
> )+{+ return BoardInitBeforeTempRamExit ();+}++/**+ A hook for platform-
> specific initialization after disabling temporary RAM.++ @retval EFI_SUCCESS
> The platform initialization was successful.+ @retval EFI_NOT_READY The
> platform has not been detected
> yet.+**/+EFI_STATUS+EFIAPI+PlatformInitAfterTempRamExit (+ VOID+
> )+{+ return BoardInitAfterTempRamExit ();+} /** This function handles
> PlatformInit task after PeiReadOnlyVariable2 PPI produced@@ -446,6 +511,9
> @@ PlatformInitPreMem (
> Status = BoardInitBeforeMemoryInit (); ASSERT_EFI_ERROR (Status); +
> Status = PeiServicesInstallPpi (&mPlatformInitTempRamExitPpiDesc);+
> ASSERT_EFI_ERROR (Status);+ return Status; } diff --git
> a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitP
> reMem.inf
> b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitP
> reMem.inf
> index af5dbe8772..7ee18eb6d5 100644
> ---
> a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitP
> reMem.inf
> +++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/Platfor
> +++ mInitPreMem.inf
> @@ -53,6 +53,7 @@
> gEfiPeiMemoryDiscoveredPpiGuid gEfiPeiMasterBootModePpiGuid
> ## PRODUCES gEfiPeiBootInRecoveryModePpiGuid ## PRODUCES+
> gPlatformInitTempRamExitPpiGuid ## PRODUCES
> gEfiPeiReadOnlyVariable2PpiGuid gPeiBaseMemoryTestPpiGuid
> gPeiPlatformMemorySizePpiGuid--
> 2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 03/13] KabylakeSiliconPkg: Cleanup old comments
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 03/13] KabylakeSiliconPkg: Cleanup old comments Nate DeSimone
2019-11-14 15:16 ` Chiu, Chasel
2019-11-16 2:53 ` Kubacki, Michael A
@ 2019-11-18 9:15 ` Chaganty, Rangasai V
2 siblings, 0 replies; 44+ messages in thread
From: Chaganty, Rangasai V @ 2019-11-18 9:15 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io
Cc: Chiu, Chasel, Kubacki, Michael A
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Desimone, Nathaniel L
Sent: Wednesday, November 13, 2019 10:07 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A <michael.a.kubacki@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>
Subject: [edk2-platforms] [PATCH V1 03/13] KabylakeSiliconPkg: Cleanup old comments
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
.../Library/PeiSiliconInitLib/SiliconInitPreMem.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMem.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMem.c
index 65a67a6795..384877fba3 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMem.c
+++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/Silicon
+++ InitPreMem.c
@@ -31,9 +31,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/PeiServicesTablePointerLib.h> #include <Library/PchSerialIoLib.h> -//@todo it should be moved to Si Pkg. /**- Early Platform PCH initialization+ Early PCH initialization **/ VOID EarlySiliconInit (@@ -233,4 +232,3 @@ SiliconInit (
} }---
2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 04/13] CoffeeLakeSiliconPkg: Move TcoWdtHob.h
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 04/13] CoffeeLakeSiliconPkg: Move TcoWdtHob.h Nate DeSimone
2019-11-14 15:16 ` Chiu, Chasel
2019-11-16 2:53 ` Kubacki, Michael A
@ 2019-11-18 9:41 ` Chaganty, Rangasai V
2 siblings, 0 replies; 44+ messages in thread
From: Chaganty, Rangasai V @ 2019-11-18 9:41 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io
Cc: Chiu, Chasel, Kubacki, Michael A
I understand we are moving the header file around but can we take this opportunity to cleanup this file? (Maybe in a different patch).
The TcoWdtHob.h is redefining HOB structures that are already defined in MdePkg (e.g. EFI_HOB_GENERIC_HEADER)
Regards,
Sai
-----Original Message-----
From: Desimone, Nathaniel L
Sent: Wednesday, November 13, 2019 10:07 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A <michael.a.kubacki@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>
Subject: [edk2-platforms] [PATCH V1 04/13] CoffeeLakeSiliconPkg: Move TcoWdtHob.h
Moves TcoWdtHob.h from WhiskeylakeOpenBoardPkg to CoffeelakeSiliconPkg.
Oddly, gTcoWdtHobGuid was defined in CoffeelakeSiliconPkg/SiPkg.dec while the HOB definition itself was in WhiskeylakeOpenBoardPkg, this change cleans up the disparity.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
.../Intel/CoffeelakeSiliconPkg}/Include/Guid/TcoWdtHob.h | 0
1 file changed, 0 insertions(+), 0 deletions(-) rename {Platform/Intel/WhiskeylakeOpenBoardPkg => Silicon/Intel/CoffeelakeSiliconPkg}/Include/Guid/TcoWdtHob.h (100%)
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Guid/TcoWdtHob.h b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Guid/TcoWdtHob.h
similarity index 100%
rename from Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Guid/TcoWdtHob.h
rename to Silicon/Intel/CoffeelakeSiliconPkg/Include/Guid/TcoWdtHob.h
--
2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [edk2-platforms] [PATCH V1 05/13] CoffeelakeSiliconPkg: Add SiliconInitLib
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 05/13] CoffeelakeSiliconPkg: Add SiliconInitLib Nate DeSimone
2019-11-14 15:16 ` Chiu, Chasel
2019-11-16 2:53 ` Kubacki, Michael A
@ 2019-11-18 19:14 ` Chaganty, Rangasai V
2 siblings, 0 replies; 44+ messages in thread
From: Chaganty, Rangasai V @ 2019-11-18 19:14 UTC (permalink / raw)
To: Desimone, Nathaniel L, devel@edk2.groups.io
Cc: Chiu, Chasel, Kubacki, Michael A
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
Minor feedback - The comments surrounding the new APIs (Early PCH Init) is not matching with the API function name (EarlySiliconInit). It's good to keep them consistent.
-----Original Message-----
From: Desimone, Nathaniel L
Sent: Wednesday, November 13, 2019 10:07 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A <michael.a.kubacki@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>
Subject: [edk2-platforms] [PATCH V1 05/13] CoffeelakeSiliconPkg: Add SiliconInitLib
SiliconInitLib contains Silicon Init APIs that can be reused by BoardInitLib. It is expected that several implementations of BoardInitLib exist for a given SOC, these APIs allow the various BoardInitLib implementations to reuse common silicon initialization code. This matches the implementation already found in KabylakeSiliconPkg. This change also adds halting the TCO watch dog timer to PEI, which was previously done in SEC.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
.../Include/Library/SiliconInitLib.h | 28 +++++
.../PeiSiliconInitLib/PeiSiliconInitLib.inf | 46 ++++++++
.../Library/PeiSiliconInitLib/SiliconInit.c | 19 +++
.../PeiSiliconInitLib/SiliconInitPreMem.c | 109 ++++++++++++++++++
4 files changed, 202 insertions(+)
create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.h
create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c
create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMem.c
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.h
new file mode 100644
index 0000000000..a3411126a7
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.
+++ h
@@ -0,0 +1,28 @@
+/** @file++Copyright (c) 2019, Intel Corporation. All rights
+reserved.<BR>+SPDX-License-Identifier:
+BSD-2-Clause-Patent++**/++#ifndef _SILICON_INIT_LIB_H_+#define
+_SILICON_INIT_LIB_H_++#include <PiPei.h>++VOID+EarlySiliconInit (+
+VOID+ );++VOID+SiliconInit (+ VOID+ );++VOID+LateSiliconInit (+
+VOID+ );++#endif
\ No newline at end of file
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
new file mode 100644
index 0000000000..47da5f608b
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSi
+++ liconInitLib.inf
@@ -0,0 +1,46 @@
+### @file+#+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>+#+# SPDX-License-Identifier: BSD-2-Clause-Patent+#+###++[Defines]+ INF_VERSION = 0x00010017+ BASE_NAME = SiliconInitLib+ FILE_GUID = 82F2ACF0-2EBE-48C8-AC58-9D0F8BC1E16E+ VERSION_STRING = 1.0+ MODULE_TYPE = PEIM+ LIBRARY_CLASS = SiliconInitLib+#+# The following information is for reference only and not required by the build tools.+#+# VALID_ARCHITECTURES = IA32 X64 IPF EBC+#++[LibraryClasses]+ BaseLib+ BaseMemoryLib+ DebugLib+ HobLib+ IoLib+ PcdLib+ PeiServicesLib+ PchCycleDecodingLib+ PmcLib++[Packages]+ MdePkg/MdePkg.dec+ CoffeelakeSiliconPkg/SiPkg.dec++[Sources]+ SiliconInit.c+ SiliconInitPreMem.c++[Guids]+ gTcoWdtHobGuid ## CONSUMES++[Pcd]+ gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ## CONSUMESdiff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c
new file mode 100644
index 0000000000..122c02a3e5
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/Silic
+++ onInit.c
@@ -0,0 +1,19 @@
+/** @file+ Silicon Init APIs for MinPlatform BoardInitLib
+implementations.++Copyright (c) 2019, Intel Corporation. All rights
+reserved.<BR>+SPDX-License-Identifier:
+BSD-2-Clause-Patent++**/++#include <PiPei.h>++/**+ Late PCH
+Init+**/+VOID+LateSiliconInit (+ VOID+ )+{+}diff --git
+a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconI
+nitPreMem.c
+b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconI
+nitPreMem.c
new file mode 100644
index 0000000000..23e4a3d4a0
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/Silic
+++ onInitPreMem.c
@@ -0,0 +1,109 @@
+/** @file+ Silicon Init APIs for MinPlatform BoardInitLib implementations.++Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>+SPDX-License-Identifier: BSD-2-Clause-Patent++**/++#include <PiPei.h>+#include <Guid/TcoWdtHob.h>+#include <Library/IoLib.h>+#include <Library/DebugLib.h>+#include <Library/HobLib.h>+#include <Library/PcdLib.h>+#include <Library/PeiServicesLib.h>+#include <Library/PchCycleDecodingLib.h>+#include <Library/PmcLib.h>+#include <Register/PchRegsLpc.h>+#include <Register/PchRegsPmc.h>++/**+ Early PCH initialization+**/+VOID+EarlySiliconInit (+ VOID+ )+{+ UINT16 Data16;+ UINT8 Data8;+ UINT8 TcoRebootHappened;+ TCO_WDT_HOB *TcoWdtHobPtr;+ EFI_STATUS Status;++ ///+ /// LPC I/O Configuration+ ///+ PchLpcIoDecodeRangesSet (+ (V_LPC_CFG_IOD_LPT_378 << N_LPC_CFG_IOD_LPT) |+ (V_LPC_CFG_IOD_COMB_3E8 << N_LPC_CFG_IOD_COMB) |+ (V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA)+ );++ PchLpcIoEnableDecodingSet (+ B_LPC_CFG_IOE_ME2 |+ B_LPC_CFG_IOE_SE |+ B_LPC_CFG_IOE_ME1 |+ B_LPC_CFG_IOE_KE |+ B_LPC_CFG_IOE_HGE |+ B_LPC_CFG_IOE_LGE |+ B_LPC_CFG_IOE_FDE |+ B_LPC_CFG_IOE_PPE |+ B_LPC_CFG_IOE_CBE |+ B_LPC_CFG_IOE_CAE+ );++ ///+ /// Halt the TCO timer+ ///+ Data16 = IoRead16 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT);+ Data16 |= B_TCO_IO_TCO1_CNT_TMR_HLT;+ IoWrite16 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT, Data16);++ ///+ /// Read the Second TO status bit+ ///+ Data8 = IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS);+ if ((Data8 & B_TCO_IO_TCO2_STS_SECOND_TO) == B_TCO_IO_TCO2_STS_SECOND_TO) {+ TcoRebootHappened = 1;+ DEBUG ((DEBUG_INFO, "PlatformInitPreMem - TCO Second TO status bit is set. This might be a TCO reboot\n"));+ }+ else {+ TcoRebootHappened = 0;+ }++ ///+ /// Create HOB+ ///+ Status = PeiServicesCreateHob (EFI_HOB_TYPE_GUID_EXTENSION, sizeof(TCO_WDT_HOB), (VOID **)&TcoWdtHobPtr);+ if (!EFI_ERROR (Status)) {+ TcoWdtHobPtr->Header.Name = gTcoWdtHobGuid;+ TcoWdtHobPtr->TcoRebootHappened = TcoRebootHappened;+ }++ ///+ /// Clear the Second TO status bit+ ///+ IoWrite8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS, B_TCO_IO_TCO2_STS_SECOND_TO);+}++/**+ Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal inversion registers++**/+VOID+SiliconInit (+ VOID+ )+{+ UINT16 ABase;++ ABase = PmcGetAcpiBase ();++ ///+ /// Clear all pending SMI. On S3 clear power button enable so it will not generate an SMI.+ ///+ IoWrite16 (ABase + R_ACPI_IO_PM1_EN, 0);+ IoWrite32 (ABase + R_ACPI_IO_GPE0_EN_127_96, 0);+}--
2.23.0.windows.1
^ permalink raw reply [flat|nested] 44+ messages in thread
end of thread, other threads:[~2019-11-18 19:14 UTC | newest]
Thread overview: 44+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-11-14 6:06 [edk2-platforms] [PATCH V1 00/13] SecFspWrapperPlatformSecLib Cleanup Nate DeSimone
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 01/13] KabylakeSiliconPkg: Change MODULE_TYPE of SiliconInitLib to PEIM Nate DeSimone
2019-11-14 15:15 ` Chiu, Chasel
2019-11-15 8:59 ` Chaganty, Rangasai V
2019-11-16 2:53 ` Kubacki, Michael A
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 02/13] KabylakeOpenBoardPkg: Update location of SiliconInitLib Nate DeSimone
2019-11-14 15:15 ` Chiu, Chasel
2019-11-16 2:53 ` Kubacki, Michael A
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 03/13] KabylakeSiliconPkg: Cleanup old comments Nate DeSimone
2019-11-14 15:16 ` Chiu, Chasel
2019-11-16 2:53 ` Kubacki, Michael A
2019-11-18 9:15 ` Chaganty, Rangasai V
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 04/13] CoffeeLakeSiliconPkg: Move TcoWdtHob.h Nate DeSimone
2019-11-14 15:16 ` Chiu, Chasel
2019-11-16 2:53 ` Kubacki, Michael A
2019-11-18 9:41 ` Chaganty, Rangasai V
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 05/13] CoffeelakeSiliconPkg: Add SiliconInitLib Nate DeSimone
2019-11-14 15:16 ` Chiu, Chasel
2019-11-16 2:53 ` Kubacki, Michael A
2019-11-18 19:14 ` Chaganty, Rangasai V
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 06/13] WhiskeylakeOpenBoardPkg: Add SiliconInitLib APIs to BoardInitLib Nate DeSimone
2019-11-14 15:16 ` Chiu, Chasel
2019-11-16 2:53 ` Kubacki, Michael A
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 07/13] WhiskeylakeOpenBoardPkg: Whitespace cleanup in BoardInitLib Nate DeSimone
2019-11-14 15:17 ` Chiu, Chasel
2019-11-16 2:53 ` Kubacki, Michael A
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 08/13] WhiskeylakeOpenBoardPkg: Remove SecFspWrapperPlatformSecLib override Nate DeSimone
2019-11-14 15:17 ` Chiu, Chasel
2019-11-16 2:53 ` Kubacki, Michael A
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 09/13] MinPlatformPkg: FSP Dispatch Mode Support for PlatformSecLib Nate DeSimone
2019-11-14 15:17 ` Chiu, Chasel
2019-11-16 2:54 ` Kubacki, Michael A
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 10/13] MinPlatformPkg: Coding style cleanups in MinPlatformPkg.dec Nate DeSimone
2019-11-14 15:17 ` Chiu, Chasel
2019-11-16 2:54 ` Kubacki, Michael A
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 11/13] KabylakeOpenBoardPkg: Add support for PcdFspDispatchModeUseFspPeiMain Nate DeSimone
2019-11-14 15:18 ` Chiu, Chasel
2019-11-16 2:54 ` Kubacki, Michael A
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 12/13] KabylakeOpenBoardPkg: Remove SecFspWrapperPlatformSecLib override Nate DeSimone
2019-11-14 15:18 ` Chiu, Chasel
2019-11-16 2:54 ` Kubacki, Michael A
2019-11-14 6:06 ` [edk2-platforms] [PATCH V1 13/13] MinPlatformPkg: Remove BoardInitLib dependency from PlatformSecLib Nate DeSimone
2019-11-14 15:18 ` Chiu, Chasel
2019-11-16 2:56 ` Kubacki, Michael A
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox