From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga18.intel.com (mga18.intel.com []) by mx.groups.io with SMTP id smtpd.web10.21388.1574326763463229475 for ; Thu, 21 Nov 2019 00:59:26 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: nathaniel.l.desimone@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Nov 2019 00:59:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,224,1571727600"; d="scan'208";a="210033067" Received: from nldesimo-desk1.amr.corp.intel.com ([10.7.159.63]) by orsmga006.jf.intel.com with ESMTP; 21 Nov 2019 00:59:21 -0800 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Michael Kubacki , Chasel Chiu , Liming Gao Subject: [edk2-platforms] [PATCH V2 10/14] MinPlatformPkg: FSP Dispatch Mode Support for PlatformSecLib Date: Thu, 21 Nov 2019 00:58:49 -0800 Message-Id: <20191121085853.2626-11-nathaniel.l.desimone@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20191121085853.2626-1-nathaniel.l.desimone@intel.com> References: <20191121085853.2626-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Cc: Michael Kubacki Cc: Chasel Chiu Cc: Liming Gao Signed-off-by: Nate DeSimone --- .../FspWrapperPlatformSecLib.c | 34 ++++++++++++--- .../SecFspWrapperPlatformSecLib.inf | 7 +++- .../SecTempRamDone.c | 42 +++++++++++++++---- .../Intel/MinPlatformPkg/MinPlatformPkg.dec | 28 ++++++++++++- 4 files changed, 95 insertions(+), 16 deletions(-) diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/FspWrapperPlatformSecLib.c b/Platform/Intel/MinPlatformPkg/F= spWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c index 303f3aac40..36bdc1dee8 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/FspWrapperPlatformSecLib.c +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/FspWrapperPlatformSecLib.c @@ -1,7 +1,7 @@ /** @file=0D Provide FSP wrapper platform sec related function.=0D =0D -Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -12,6 +12,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include =0D #include =0D #include =0D +#include =0D #include =0D =0D #include =0D @@ -66,6 +67,18 @@ PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi =3D { SecGetPerformance=0D };=0D =0D +EFI_PEI_CORE_FV_LOCATION_PPI mPeiCoreFvLocationPpi =3D {=0D + (VOID *) (UINTN) FixedPcdGet32 (PcdFspmBaseAddress)=0D +};=0D +=0D +EFI_PEI_PPI_DESCRIPTOR mPeiCoreFvLocationPpiList[] =3D {=0D + {=0D + EFI_PEI_PPI_DESCRIPTOR_PPI,=0D + &gEfiPeiCoreFvLocationPpiGuid,=0D + &mPeiCoreFvLocationPpi=0D + }=0D +};=0D +=0D EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] =3D {=0D {=0D EFI_PEI_PPI_DESCRIPTOR_PPI,=0D @@ -129,6 +142,8 @@ SecPlatformMain ( )=0D {=0D EFI_PEI_PPI_DESCRIPTOR *PpiList;=0D + UINT8 TopOfTemporaryRamPpiIndex;=0D + UINT8 *CopyDestinationPointer;=0D =0D DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeBase - 0x%x\n", SecCo= reData->BootFirmwareVolumeBase));=0D DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeSize - 0x%x\n", SecCo= reData->BootFirmwareVolumeSize));=0D @@ -150,13 +165,22 @@ SecPlatformMain ( // Use middle of Heap as temp buffer, it will be copied by caller.=0D // Do not use Stack, because it will cause wrong calculation on stack by= PeiCore=0D //=0D - PpiList =3D (VOID *)((UINTN)SecCoreData->PeiTemporaryRamBase + (UINTN)Se= cCoreData->PeiTemporaryRamSize/2);=0D - CopyMem (PpiList, mPeiSecPlatformPpi, sizeof(mPeiSecPlatformPpi));=0D -=0D + PpiList =3D (VOID *)((UINTN) SecCoreData->PeiTemporaryRamBase + (UINTN) = SecCoreData->PeiTemporaryRamSize/2);=0D + CopyDestinationPointer =3D (UINT8 *) PpiList;=0D + TopOfTemporaryRamPpiIndex =3D 0;=0D + if ((PcdGet8 (PcdFspModeSelection) =3D=3D 0) && PcdGetBool (PcdFspDispat= chModeUseFspPeiMain)) {=0D + //=0D + // In Dispatch mode, wrapper should provide PeiCoreFvLocationPpi.=0D + //=0D + CopyMem (CopyDestinationPointer, mPeiCoreFvLocationPpiList, sizeof (mP= eiCoreFvLocationPpiList));=0D + TopOfTemporaryRamPpiIndex =3D 1;=0D + CopyDestinationPointer +=3D sizeof (mPeiCoreFvLocationPpiList);=0D + }=0D + CopyMem (CopyDestinationPointer, mPeiSecPlatformPpi, sizeof (mPeiSecPlat= formPpi));=0D //=0D // Patch TopOfTemporaryRamPpi=0D //=0D - PpiList[0].Ppi =3D (VOID *)((UINTN)SecCoreData->TemporaryRamBase + SecCo= reData->TemporaryRamSize);=0D + PpiList[TopOfTemporaryRamPpiIndex].Ppi =3D (VOID *)((UINTN) SecCoreData-= >TemporaryRamBase + SecCoreData->TemporaryRamSize);=0D =0D return PpiList;=0D }=0D diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/SecFspWrapperPlatformSecLib.inf b/Platform/Intel/MinPlatform= Pkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSec= Lib.inf index 3f5a63f273..02c720c73d 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecFspWrapperPlatformSecLib.inf +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecFspWrapperPlatformSecLib.inf @@ -72,18 +72,20 @@ BoardInitLib=0D SecBoardInitLib=0D TestPointCheckLib=0D + PeiServicesTablePointerLib=0D =0D [Ppis]=0D gEfiSecPlatformInformationPpiGuid ## CONSUMES=0D gPeiSecPerformancePpiGuid ## CONSUMES=0D gTopOfTemporaryRamPpiGuid ## PRODUCES=0D gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES=0D + gFspTempRamExitPpiGuid ## CONSUMES=0D =0D [Pcd]=0D gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize ## C= ONSUMES=0D gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress ## C= ONSUMES=0D gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## C= ONSUMES=0D - gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ## CONS= UMES=0D + gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ## C= ONSUMES=0D =0D [FixedPcd]=0D gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## C= ONSUMES=0D @@ -91,3 +93,6 @@ gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset ## C= ONSUMES=0D gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ## C= ONSUMES=0D gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize ## C= ONSUMES=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## C= ONSUMES=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## C= ONSUMES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain ## C= ONSUMES=0D diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/SecTempRamDone.c b/Platform/Intel/MinPlatformPkg/FspWrapper/= Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c index cde8a80a4e..922e4ec204 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecTempRamDone.c +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecTempRamDone.c @@ -1,7 +1,7 @@ /** @file=0D Provide SecTemporaryRamDone function.=0D =0D -Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -9,6 +9,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include =0D =0D #include =0D +#include =0D =0D #include =0D #include =0D @@ -17,6 +18,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include =0D #include =0D #include =0D +#include =0D =0D /**=0D This interface disables temporary memory in SEC Phase.=0D @@ -29,17 +31,41 @@ SecPlatformDisableTemporaryMemory ( {=0D EFI_STATUS Status;=0D VOID *TempRamExitParam;=0D + CONST EFI_PEI_SERVICES **PeiServices;=0D + FSP_TEMP_RAM_EXIT_PPI *TempRamExitPpi;=0D +=0D + DEBUG ((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n"));=0D =0D - DEBUG((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n"));=0D - =0D Status =3D BoardInitBeforeTempRamExit ();=0D ASSERT_EFI_ERROR (Status);=0D =0D - TempRamExitParam =3D UpdateTempRamExitParam ();=0D - Status =3D CallTempRamExit (TempRamExitParam);=0D - DEBUG((DEBUG_INFO, "TempRamExit status: 0x%x\n", Status));=0D - ASSERT_EFI_ERROR(Status);=0D - =0D + if (PcdGet8 (PcdFspModeSelection) =3D=3D 1) {=0D + //=0D + // FSP API mode=0D + //=0D + TempRamExitParam =3D UpdateTempRamExitParam ();=0D + Status =3D CallTempRamExit (TempRamExitParam);=0D + DEBUG ((DEBUG_INFO, "TempRamExit status: 0x%x\n", Status));=0D + ASSERT_EFI_ERROR (Status);=0D + } else {=0D + //=0D + // FSP Dispatch mode=0D + //=0D + PeiServices =3D GetPeiServicesTablePointer ();=0D + Status =3D (*PeiServices)->LocatePpi (=0D + PeiServices,=0D + &gFspTempRamExitPpiGuid,=0D + 0,=0D + NULL,=0D + (VOID **) &TempRamExitPpi=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D + if (EFI_ERROR (Status)) {=0D + return;=0D + }=0D + TempRamExitPpi->TempRamExit (NULL);=0D + }=0D +=0D Status =3D BoardInitAfterTempRamExit ();=0D ASSERT_EFI_ERROR (Status);=0D =0D diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec b/Platform/In= tel/MinPlatformPkg/MinPlatformPkg.dec index 92bda3784f..fb069145ce 100644 --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec @@ -71,8 +71,6 @@ SetCacheMtrrLib|Include/Library/SetCacheMtrrLib.h =0D [PcdsFixedAtBuild, PcdsPatchableInModule]=0D =0D -gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|FALSE|BOOLEAN|0x800000= 08=0D -=0D gMinPlatformPkgTokenSpaceGuid.PcdFspMaxUpdSize|0x00000000|UINT32|0x8000000= 0=0D gMinPlatformPkgTokenSpaceGuid.PcdFspReservedSizeOnStackTop|0x00000040|UINT= 32|0x80000001=0D gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0x00000000|UINT32|0x8000= 0002=0D @@ -274,6 +272,32 @@ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UI= NT32|0x90000019 #=0D gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4|UINT8|0xF00000A0=0D =0D + ## FSP Boot Mode Selector=0D + # FALSE: The board is not a FSP wrapper (FSP binary not used)=0D + # TRUE: The board is a FSP wrapper (FSP binary is used)=0D + #=0D + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|FALSE|BOOLEAN|0x8000= 0008=0D +=0D + ## FSP Dispatch Mode: Use the PEI Main Binary Included in FSP-M=0D + # FALSE: The PEI Main included in FvPreMemory is used to dispatch all PE= IMs=0D + # (both inside FSP and outside FSP).=0D + # Pros:=0D + # * PEI Main is re-built from source and is always the latest v= ersion=0D + # * Platform code can link any desired LibraryClass to PEI Main= =0D + # (Ex: Custom DebugLib instance, SerialPortLib, etc.)=0D + # Cons:=0D + # * The PEI Main being used to execute FSP PEIMs is not the PEI= Main=0D + # that the FSP PEIMs were tested with, adding risk of breakag= e.=0D + # * Two copies of PEI Main will exist in the final binary,=0D + # #1 in FSP-M, #2 in FvPreMemory. The copy in FSP-M is never= =0D + # executed, wasting space.=0D + #=0D + # TRUE: The PEI Main included in FSP is used to dispatch all PEI= Ms=0D + # (both inside FSP and outside FSP). PEI Main will not be include= d in=0D + # FvPreMemory. This is the default and is the recommended choice.= =0D + #=0D + gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE|BOOLE= AN|0xF00000A8=0D +=0D [PcdsFeatureFlag]=0D =0D gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit |FALSE|BOOLEAN|0= xF00000A1=0D --=20 2.24.0.windows.2