From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga18.intel.com (mga18.intel.com []) by mx.groups.io with SMTP id smtpd.web10.21389.1574326764546050137 for ; Thu, 21 Nov 2019 00:59:26 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: nathaniel.l.desimone@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Nov 2019 00:59:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,224,1571727600"; d="scan'208";a="210033074" Received: from nldesimo-desk1.amr.corp.intel.com ([10.7.159.63]) by orsmga006.jf.intel.com with ESMTP; 21 Nov 2019 00:59:21 -0800 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Michael Kubacki , Jeremy Soller Subject: [edk2-platforms] [PATCH V2 13/14] KabylakeOpenBoardPkg: Remove SecFspWrapperPlatformSecLib override Date: Thu, 21 Nov 2019 00:58:52 -0800 Message-Id: <20191121085853.2626-14-nathaniel.l.desimone@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20191121085853.2626-1-nathaniel.l.desimone@intel.com> References: <20191121085853.2626-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Cc: Chasel Chiu Cc: Michael Kubacki Cc: Jeremy Soller Signed-off-by: Nate DeSimone --- .../FspWrapperPlatformSecLib.c | 186 --------- .../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 40 -- .../SecFspWrapperPlatformSecLib/Ia32/Fsp.h | 42 -- .../Ia32/PeiCoreEntry.nasm | 130 ------- .../Ia32/SecEntry.nasm | 361 ------------------ .../Ia32/Stack.nasm | 72 ---- .../PlatformInit.c | 47 --- .../SecFspWrapperPlatformSecLib.inf | 97 ----- .../SecGetPerformance.c | 89 ----- .../SecPlatformInformation.c | 78 ---- .../SecRamInitData.c | 36 -- .../SecTempRamDone.c | 73 ---- .../GalagoPro3/OpenBoardPkg.dsc | 2 +- .../KabylakeRvp3/OpenBoardPkg.dsc | 2 +- 14 files changed, 2 insertions(+), 1253 deletions(-) delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/= SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/= SecFspWrapperPlatformSecLib/FsptCoreUpd.h delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/= SecFspWrapperPlatformSecLib/Ia32/Fsp.h delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/= SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/= SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/= SecFspWrapperPlatformSecLib/Ia32/Stack.nasm delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/= SecFspWrapperPlatformSecLib/PlatformInit.c delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/= SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/= SecFspWrapperPlatformSecLib/SecGetPerformance.c delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/= SecFspWrapperPlatformSecLib/SecPlatformInformation.c delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/= SecFspWrapperPlatformSecLib/SecRamInitData.c delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/= SecFspWrapperPlatformSecLib/SecTempRamDone.c diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspW= rapperPlatformSecLib/FspWrapperPlatformSecLib.c b/Platform/Intel/KabylakeOp= enBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatfor= mSecLib.c deleted file mode 100644 index d40eecae95..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP= latformSecLib/FspWrapperPlatformSecLib.c +++ /dev/null @@ -1,186 +0,0 @@ -/** @file=0D - Provide FSP wrapper platform sec related function.=0D -=0D -Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D -SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -#include =0D -=0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -=0D -#include =0D -#include =0D -#include =0D -#include =0D -=0D -/**=0D - This interface conveys state information out of the Security (SEC) phase= into PEI.=0D -=0D - @param[in] PeiServices Pointer to the PEI Services Tab= le.=0D - @param[in,out] StructureSize Pointer to the variable describ= ing size of the input buffer.=0D - @param[out] PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM= _INFORMATION_RECORD.=0D -=0D - @retval EFI_SUCCESS The data was successfully returned.=0D - @retval EFI_BUFFER_TOO_SMALL The buffer was too small.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -SecPlatformInformation (=0D - IN CONST EFI_PEI_SERVICES **PeiServices,=0D - IN OUT UINT64 *StructureSize,=0D - OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord= =0D - );=0D -=0D -/**=0D - This interface conveys performance information out of the Security (SEC)= phase into PEI.=0D -=0D - This service is published by the SEC phase. The SEC phase handoff has an= optional=0D - EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed= from SEC into the=0D - PEI Foundation. As such, if the platform supports collecting performance= data in SEC,=0D - this information is encapsulated into the data structure abstracted by t= his service.=0D - This information is collected for the boot-strap processor (BSP) on IA-3= 2.=0D -=0D - @param[in] PeiServices The pointer to the PEI Services Table.=0D - @param[in] This The pointer to this instance of the PEI_SEC_PER= FORMANCE_PPI.=0D - @param[out] Performance The pointer to performance data collected in SE= C phase.=0D -=0D - @retval EFI_SUCCESS The data was successfully returned.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -SecGetPerformance (=0D - IN CONST EFI_PEI_SERVICES **PeiServices,=0D - IN PEI_SEC_PERFORMANCE_PPI *This,=0D - OUT FIRMWARE_SEC_PERFORMANCE *Performance=0D - );=0D -=0D -PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi =3D {=0D - SecGetPerformance=0D -};=0D -=0D -EFI_PEI_CORE_FV_LOCATION_PPI mPeiCoreFvLocationPpi =3D {=0D - (VOID *) (UINTN) FixedPcdGet32 (PcdFspmBaseAddress)=0D -};=0D -=0D -EFI_PEI_PPI_DESCRIPTOR mPeiCoreFvLocationPpiList[] =3D {=0D - {=0D - EFI_PEI_PPI_DESCRIPTOR_PPI,=0D - &gEfiPeiCoreFvLocationPpiGuid,=0D - &mPeiCoreFvLocationPpi=0D - }=0D -};=0D -=0D -EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] =3D {=0D - {=0D - EFI_PEI_PPI_DESCRIPTOR_PPI,=0D - &gTopOfTemporaryRamPpiGuid,=0D - NULL // To be patched later.=0D - },=0D - {=0D - EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,=0D - &gPeiSecPerformancePpiGuid,=0D - &mSecPerformancePpi=0D - },=0D -};=0D -=0D -#define LEGACY_8259_MASK_REGISTER_MASTER 0x21=0D -#define LEGACY_8259_MASK_REGISTER_SLAVE 0xA1=0D -#define LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER 0x4D0=0D -#define LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE 0x4D1=0D -=0D -/**=0D - Write to mask and edge/level triggered registers of master and slave 825= 9 PICs.=0D -=0D - @param[in] Mask low byte for master PIC mask register,=0D - high byte for slave PIC mask register.=0D - @param[in] EdgeLevel low byte for master PIC edge/level triggered regi= ster,=0D - high byte for slave PIC edge/level triggered regi= ster.=0D -=0D -**/=0D -VOID=0D -Interrupt8259WriteMask (=0D - IN UINT16 Mask,=0D - IN UINT16 EdgeLevel=0D - )=0D -{=0D - IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, (UINT8) Mask);=0D - IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, (UINT8) (Mask >> 8));=0D - IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER, (UINT8) Edge= Level);=0D - IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE, (UINT8) (Edge= Level >> 8));=0D -}=0D -=0D -/**=0D - A developer supplied function to perform platform specific operations.=0D -=0D - It's a developer supplied function to perform any operations appropriate= to a=0D - given platform. It's invoked just before passing control to PEI core by = SEC=0D - core. Platform developer may modify the SecCoreData passed to PEI Core.= =0D - It returns a platform specific PPI list that platform wishes to pass to = PEI core.=0D - The Generic SEC core module will merge this list to join the final list = passed to=0D - PEI core.=0D -=0D - @param[in,out] SecCoreData The same parameter as passing to PE= I core. It=0D - could be overridden by this functio= n.=0D -=0D - @return The platform specific PPI list to be passed to PEI core or=0D - NULL if there is no need of such platform specific PPI list.=0D -=0D -**/=0D -EFI_PEI_PPI_DESCRIPTOR *=0D -EFIAPI=0D -SecPlatformMain (=0D - IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData=0D - )=0D -{=0D - EFI_PEI_PPI_DESCRIPTOR *PpiList;=0D - UINT8 TopOfTemporaryRamPpiIndex;=0D - UINT8 *CopyDestinationPointer;=0D -=0D - DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeBase - 0x%x\n", SecCo= reData->BootFirmwareVolumeBase));=0D - DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeSize - 0x%x\n", SecCo= reData->BootFirmwareVolumeSize));=0D - DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamBase - 0x%x\n", SecCo= reData->TemporaryRamBase));=0D - DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamSize - 0x%x\n", SecCo= reData->TemporaryRamSize));=0D - DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamBase - 0x%x\n", SecCo= reData->PeiTemporaryRamBase));=0D - DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamSize - 0x%x\n", SecCo= reData->PeiTemporaryRamSize));=0D - DEBUG ((DEBUG_INFO, "FSP Wrapper StackBase - 0x%x\n", SecCo= reData->StackBase));=0D - DEBUG ((DEBUG_INFO, "FSP Wrapper StackSize - 0x%x\n", SecCo= reData->StackSize));=0D -=0D - InitializeApicTimer (0, (UINT32) -1, TRUE, 5);=0D -=0D - //=0D - // Set all 8259 interrupts to edge triggered and disabled=0D - //=0D - Interrupt8259WriteMask (0xFFFF, 0x0000);=0D -=0D - //=0D - // Use middle of Heap as temp buffer, it will be copied by caller.=0D - // Do not use Stack, because it will cause wrong calculation on stack by= PeiCore=0D - //=0D - PpiList =3D (VOID *)((UINTN) SecCoreData->PeiTemporaryRamBase + (UINTN) = SecCoreData->PeiTemporaryRamSize/2);=0D - CopyDestinationPointer =3D (UINT8 *) PpiList;=0D - TopOfTemporaryRamPpiIndex =3D 0;=0D - if (PcdGet8 (PcdFspModeSelection) =3D=3D 0) {=0D - //=0D - // In Dispatch mode, wrapper should provide PeiCoreFvLocationPpi.=0D - //=0D - CopyMem (CopyDestinationPointer, mPeiCoreFvLocationPpiList, sizeof (mP= eiCoreFvLocationPpiList));=0D - TopOfTemporaryRamPpiIndex =3D 1;=0D - CopyDestinationPointer +=3D sizeof (mPeiCoreFvLocationPpiList);=0D - }=0D - CopyMem (CopyDestinationPointer, mPeiSecPlatformPpi, sizeof(mPeiSecPlatf= ormPpi));=0D - //=0D - // Patch TopOfTemporaryRamPpi=0D - //=0D - PpiList[TopOfTemporaryRamPpiIndex].Ppi =3D (VOID *)((UINTN) SecCoreData-= >TemporaryRamBase + SecCoreData->TemporaryRamSize);=0D -=0D - return PpiList;=0D -}=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspW= rapperPlatformSecLib/FsptCoreUpd.h b/Platform/Intel/KabylakeOpenBoardPkg/Fs= pWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h deleted file mode 100644 index 7c0f605b92..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP= latformSecLib/FsptCoreUpd.h +++ /dev/null @@ -1,40 +0,0 @@ -/** @file=0D -=0D -Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D -SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -#ifndef __FSPT_CORE_UPD_H__=0D -#define __FSPT_CORE_UPD_H__=0D -=0D -#pragma pack(1)=0D -=0D -/** Fsp T Core UPD=0D -**/=0D -typedef struct {=0D -=0D -/** Offset 0x0020=0D -**/=0D - UINT32 MicrocodeRegionBase;=0D -=0D -/** Offset 0x0024=0D -**/=0D - UINT32 MicrocodeRegionSize;=0D -=0D -/** Offset 0x0028=0D -**/=0D - UINT32 CodeRegionBase;=0D -=0D -/** Offset 0x002C=0D -**/=0D - UINT32 CodeRegionSize;=0D -=0D -/** Offset 0x0030=0D -**/=0D - UINT8 Reserved[16];=0D -} FSPT_CORE_UPD;=0D -=0D -#pragma pack()=0D -=0D -#endif=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspW= rapperPlatformSecLib/Ia32/Fsp.h b/Platform/Intel/KabylakeOpenBoardPkg/FspWr= apper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h deleted file mode 100644 index 9f6cdcf476..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP= latformSecLib/Ia32/Fsp.h +++ /dev/null @@ -1,42 +0,0 @@ -/** @file=0D - Fsp related definitions=0D -=0D -Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D -SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -#ifndef __FSP_H__=0D -#define __FSP_H__=0D -=0D -//=0D -// Fv Header=0D -//=0D -#define FVH_SIGINATURE_OFFSET 0x28=0D -#define FVH_SIGINATURE_VALID_VALUE 0x4856465F // valid signature:_FVH= =0D -#define FVH_HEADER_LENGTH_OFFSET 0x30=0D -#define FVH_EXTHEADER_OFFSET_OFFSET 0x34=0D -#define FVH_EXTHEADER_SIZE_OFFSET 0x10=0D -=0D -//=0D -// Ffs Header=0D -//=0D -#define FSP_HEADER_GUID_DWORD1 0x912740BE=0D -#define FSP_HEADER_GUID_DWORD2 0x47342284=0D -#define FSP_HEADER_GUID_DWORD3 0xB08471B9=0D -#define FSP_HEADER_GUID_DWORD4 0x0C3F3527=0D -#define FFS_HEADER_SIZE_VALUE 0x18=0D -=0D -//=0D -// Section Header=0D -//=0D -#define SECTION_HEADER_TYPE_OFFSET 0x03=0D -#define RAW_SECTION_HEADER_SIZE_VALUE 0x04=0D -=0D -//=0D -// Fsp Header=0D -//=0D -#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C=0D -#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30=0D -=0D -#endif=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspW= rapperPlatformSecLib/Ia32/PeiCoreEntry.nasm b/Platform/Intel/KabylakeOpenBo= ardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm deleted file mode 100644 index 5c5b788085..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP= latformSecLib/Ia32/PeiCoreEntry.nasm +++ /dev/null @@ -1,130 +0,0 @@ -;-------------------------------------------------------------------------= -----=0D -;=0D -; Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D -; SPDX-License-Identifier: BSD-2-Clause-Patent=0D -;=0D -; Module Name:=0D -;=0D -; PeiCoreEntry.nasm=0D -;=0D -; Abstract:=0D -;=0D -; Find and call SecStartup=0D -;=0D -;-------------------------------------------------------------------------= -----=0D -=0D -SECTION .text=0D -=0D -extern ASM_PFX(SecStartup)=0D -extern ASM_PFX(PlatformInit)=0D -=0D -global ASM_PFX(CallPeiCoreEntryPoint)=0D -ASM_PFX(CallPeiCoreEntryPoint):=0D - ;=0D - ; Obtain the hob list pointer=0D - ;=0D - mov eax, [esp+4]=0D - ;=0D - ; Obtain the stack information=0D - ; ECX: start of range=0D - ; EDX: end of range=0D - ;=0D - mov ecx, [esp+8]=0D - mov edx, [esp+0xC]=0D -=0D - ;=0D - ; Platform init=0D - ;=0D - pushad=0D - push edx=0D - push ecx=0D - push eax=0D - call ASM_PFX(PlatformInit)=0D - pop eax=0D - pop eax=0D - pop eax=0D - popad=0D -=0D - ;=0D - ; Set stack top pointer=0D - ;=0D - mov esp, edx=0D -=0D - ;=0D - ; Push the hob list pointer=0D - ;=0D - push eax=0D -=0D - ;=0D - ; Save the value=0D - ; ECX: start of range=0D - ; EDX: end of range=0D - ;=0D - mov ebp, esp=0D - push ecx=0D - push edx=0D -=0D - ;=0D - ; Push processor count to stack first, then BIST status (AP then BSP)=0D - ;=0D - mov eax, 1=0D - cpuid=0D - shr ebx, 16=0D - and ebx, 0xFF=0D - cmp bl, 1=0D - jae PushProcessorCount=0D -=0D - ;=0D - ; Some processors report 0 logical processors. Effectively 0 =3D 1.=0D - ; So we fix up the processor count=0D - ;=0D - inc ebx=0D -=0D -PushProcessorCount:=0D - push ebx=0D -=0D - ;=0D - ; We need to implement a long-term solution for BIST capture. For now, = we just copy BSP BIST=0D - ; for all processor threads=0D - ;=0D - xor ecx, ecx=0D - mov cl, bl=0D -PushBist:=0D - movd eax, mm0=0D - push eax=0D - loop PushBist=0D -=0D - ; Save Time-Stamp Counter=0D - movd eax, mm5=0D - push eax=0D -=0D - movd eax, mm6=0D - push eax=0D -=0D - ;=0D - ; Pass entry point of the PEI core=0D - ;=0D - mov edi, 0xFFFFFFE0=0D - push DWORD [edi]=0D -=0D - ;=0D - ; Pass BFV into the PEI Core=0D - ;=0D - mov edi, 0xFFFFFFFC=0D - push DWORD [edi]=0D -=0D - ;=0D - ; Pass stack size into the PEI Core=0D - ;=0D - mov ecx, [ebp - 4]=0D - mov edx, [ebp - 8]=0D - push ecx ; RamBase=0D -=0D - sub edx, ecx=0D - push edx ; RamSize=0D -=0D - ;=0D - ; Pass Control into the PEI Core=0D - ;=0D - call ASM_PFX(SecStartup)=0D -=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspW= rapperPlatformSecLib/Ia32/SecEntry.nasm b/Platform/Intel/KabylakeOpenBoardP= kg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm deleted file mode 100644 index 7f6d771e41..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP= latformSecLib/Ia32/SecEntry.nasm +++ /dev/null @@ -1,361 +0,0 @@ -;-------------------------------------------------------------------------= -----=0D -;=0D -; Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D -; SPDX-License-Identifier: BSD-2-Clause-Patent=0D -; Module Name:=0D -;=0D -; SecEntry.nasm=0D -;=0D -; Abstract:=0D -;=0D -; This is the code that goes from real-mode to protected mode.=0D -; It consumes the reset vector, calls TempRamInit API from FSP binary.=0D -;=0D -;-------------------------------------------------------------------------= -----=0D -=0D -#include "Fsp.h"=0D -=0D -SECTION .text=0D -=0D -extern ASM_PFX(CallPeiCoreEntryPoint)=0D -extern ASM_PFX(FsptUpdDataPtr)=0D -extern ASM_PFX(BoardBeforeTempRamInit)=0D -; Pcds=0D -extern ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))=0D -extern ASM_PFX(PcdGet32 (PcdFsptBaseAddress))=0D -=0D -;-------------------------------------------------------------------------= ---=0D -;=0D -; Procedure: _ModuleEntryPoint=0D -;=0D -; Input: None=0D -;=0D -; Output: None=0D -;=0D -; Destroys: Assume all registers=0D -;=0D -; Description:=0D -;=0D -; Transition to non-paged flat-model protected mode from a=0D -; hard-coded GDT that provides exactly two descriptors.=0D -; This is a bare bones transition to protected mode only=0D -; used for a while in PEI and possibly DXE.=0D -;=0D -; After enabling protected mode, a far jump is executed to=0D -; transfer to PEI using the newly loaded GDT.=0D -;=0D -; Return: None=0D -;=0D -; MMX Usage:=0D -; MM0 =3D BIST State=0D -; MM5 =3D Save time-stamp counter value high32bit=0D -; MM6 =3D Save time-stamp counter value low32bit.=0D -;=0D -;-------------------------------------------------------------------------= ---=0D -=0D -BITS 16=0D -align 4=0D -global ASM_PFX(_ModuleEntryPoint)=0D -ASM_PFX(_ModuleEntryPoint):=0D - fninit ; clear any pending Floating point= exceptions=0D - ;=0D - ; Store the BIST value in mm0=0D - ;=0D - movd mm0, eax=0D - cli=0D -=0D - ;=0D - ; Check INIT# is asserted by port 0xCF9=0D - ;=0D - mov dx, 0CF9h=0D - in al, dx=0D - cmp al, 04h=0D - jnz NotWarmStart=0D -=0D -=0D - ;=0D - ; @note Issue warm reset, since if CPU only reset is issued not all MSRs= are restored to their defaults=0D - ;=0D - mov dx, 0CF9h=0D - mov al, 06h=0D - out dx, al=0D -=0D -NotWarmStart:=0D - ;=0D - ; Save time-stamp counter value=0D - ; rdtsc load 64bit time-stamp counter to EDX:EAX=0D - ;=0D - rdtsc=0D - movd mm5, edx=0D - movd mm6, eax=0D -=0D - ;=0D - ; Load the GDT table in GdtDesc=0D - ;=0D - mov esi, GdtDesc=0D - DB 66h=0D - lgdt [cs:si]=0D -=0D - ;=0D - ; Transition to 16 bit protected mode=0D - ;=0D - mov eax, cr0 ; Get control register 0=0D - or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #= 1)=0D - mov cr0, eax ; Activate protected mode=0D -=0D - mov eax, cr4 ; Get control register 4=0D - or eax, 00000600h ; Set OSFXSR bit (bit #9) & OSXMMEXCP= T bit (bit #10)=0D - mov cr4, eax=0D -=0D - ;=0D - ; Now we're in 16 bit protected mode=0D - ; Set up the selectors for 32 bit protected mode entry=0D - ;=0D - mov ax, SYS_DATA_SEL=0D - mov ds, ax=0D - mov es, ax=0D - mov fs, ax=0D - mov gs, ax=0D - mov ss, ax=0D -=0D - ;=0D - ; Transition to Flat 32 bit protected mode=0D - ; The jump to a far pointer causes the transition to 32 bit mode=0D - ;=0D - mov esi, ProtectedModeEntryLinearAddress=0D - jmp dword far [cs:si]=0D -=0D -;-------------------------------------------------------------------------= ---=0D -;=0D -; Procedure: ProtectedModeEntryPoint=0D -;=0D -; Input: None=0D -;=0D -; Output: None=0D -;=0D -; Destroys: Assume all registers=0D -;=0D -; Description:=0D -;=0D -; This function handles:=0D -; Call two basic APIs from FSP binary=0D -; Initializes stack with some early data (BIST, PEI entry, etc)=0D -;=0D -; Return: None=0D -;=0D -;-------------------------------------------------------------------------= ---=0D -=0D -BITS 32=0D -align 4=0D -ProtectedModeEntryPoint:=0D - ;=0D - ; Early board hooks=0D - ;=0D - mov esp, BoardBeforeTempRamInitRet=0D - jmp ASM_PFX(BoardBeforeTempRamInit)=0D -=0D -BoardBeforeTempRamInitRet:=0D -=0D - ; Find the fsp info header=0D - mov edi, [ASM_PFX(PcdGet32 (PcdFsptBaseAddress))]=0D -=0D - mov eax, dword [edi + FVH_SIGINATURE_OFFSET]=0D - cmp eax, FVH_SIGINATURE_VALID_VALUE=0D - jnz FspHeaderNotFound=0D -=0D - xor eax, eax=0D - mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET]=0D - cmp ax, 0=0D - jnz FspFvExtHeaderExist=0D -=0D - xor eax, eax=0D - mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header=0D - add edi, eax=0D - jmp FspCheckFfsHeader=0D -=0D -FspFvExtHeaderExist:=0D - add edi, eax=0D - mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Heade= r=0D - add edi, eax=0D -=0D - ; Round up to 8 byte alignment=0D - mov eax, edi=0D - and al, 07h=0D - jz FspCheckFfsHeader=0D -=0D - and edi, 0FFFFFFF8h=0D - add edi, 08h=0D -=0D -FspCheckFfsHeader:=0D - ; Check the ffs guid=0D - mov eax, dword [edi]=0D - cmp eax, FSP_HEADER_GUID_DWORD1=0D - jnz FspHeaderNotFound=0D -=0D - mov eax, dword [edi + 4]=0D - cmp eax, FSP_HEADER_GUID_DWORD2=0D - jnz FspHeaderNotFound=0D -=0D - mov eax, dword [edi + 8]=0D - cmp eax, FSP_HEADER_GUID_DWORD3=0D - jnz FspHeaderNotFound=0D -=0D - mov eax, dword [edi + 0Ch]=0D - cmp eax, FSP_HEADER_GUID_DWORD4=0D - jnz FspHeaderNotFound=0D -=0D - add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header=0D -=0D - ; Check the section type as raw section=0D - mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET]=0D - cmp al, 019h=0D - jnz FspHeaderNotFound=0D -=0D - add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header=0D - jmp FspHeaderFound=0D -=0D -FspHeaderNotFound:=0D - jmp $=0D -=0D -FspHeaderFound:=0D - ; Get the fsp TempRamInit Api address=0D - mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]=0D - add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]=0D -=0D - ; Setup the hardcode stack=0D - mov esp, TempRamInitStack=0D -=0D - ; Call the fsp TempRamInit Api=0D - jmp eax=0D -=0D -TempRamInitDone:=0D - cmp eax, 8000000Eh ;Check if EFI_NOT_FOUND returned. Error code for= Microcode Update not found.=0D - je CallSecFspInit ;If microcode not found, don't hang, but continu= e.=0D -=0D - cmp eax, 0 ;Check if EFI_SUCCESS retuned.=0D - jnz FspApiFailed=0D -=0D - ; ECX: start of range=0D - ; EDX: end of range=0D -CallSecFspInit:=0D - sub edx, [ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))] ; TemporaryRam= for FSP=0D - xor eax, eax=0D - mov esp, edx=0D -=0D - ; Align the stack at DWORD=0D - add esp, 3=0D - and esp, 0FFFFFFFCh=0D -=0D - push edx=0D - push ecx=0D - push eax ; zero - no hob list yet=0D - call ASM_PFX(CallPeiCoreEntryPoint)=0D -=0D -FspApiFailed:=0D - jmp $=0D -=0D -align 10h=0D -TempRamInitStack:=0D - DD TempRamInitDone=0D - DD ASM_PFX(FsptUpdDataPtr); TempRamInitParams=0D -=0D -;=0D -; ROM-based Global-Descriptor Table for the Tiano PEI Phase=0D -;=0D -align 16=0D -global ASM_PFX(BootGdtTable)=0D -=0D -;=0D -; GDT[0]: 0x00: Null entry, never used.=0D -;=0D -NULL_SEL EQU $ - GDT_BASE ; Selector [0]=0D -GDT_BASE:=0D -ASM_PFX(BootGdtTable):=0D - DD 0=0D - DD 0=0D -;=0D -; Linear data segment descriptor=0D -;=0D -LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8]=0D - DW 0FFFFh ; limit 0xFFFFF=0D - DW 0 ; base 0=0D - DB 0=0D - DB 092h ; present, ring 0, data, expand-up= , writable=0D - DB 0CFh ; page-granular, 32-bit=0D - DB 0=0D -;=0D -; Linear code segment descriptor=0D -;=0D -LINEAR_CODE_SEL EQU $ - GDT_BASE ; Selector [0x10]=0D - DW 0FFFFh ; limit 0xFFFFF=0D - DW 0 ; base 0=0D - DB 0=0D - DB 09Bh ; present, ring 0, data, expand-up= , not-writable=0D - DB 0CFh ; page-granular, 32-bit=0D - DB 0=0D -;=0D -; System data segment descriptor=0D -;=0D -SYS_DATA_SEL EQU $ - GDT_BASE ; Selector [0x18]=0D - DW 0FFFFh ; limit 0xFFFFF=0D - DW 0 ; base 0=0D - DB 0=0D - DB 093h ; present, ring 0, data, expand-up= , not-writable=0D - DB 0CFh ; page-granular, 32-bit=0D - DB 0=0D -=0D -;=0D -; System code segment descriptor=0D -;=0D -SYS_CODE_SEL EQU $ - GDT_BASE ; Selector [0x20]=0D - DW 0FFFFh ; limit 0xFFFFF=0D - DW 0 ; base 0=0D - DB 0=0D - DB 09Ah ; present, ring 0, data, expand-up= , writable=0D - DB 0CFh ; page-granular, 32-bit=0D - DB 0=0D -;=0D -; Spare segment descriptor=0D -;=0D -SYS16_CODE_SEL EQU $ - GDT_BASE ; Selector [0x28]=0D - DW 0FFFFh ; limit 0xFFFFF=0D - DW 0 ; base 0=0D - DB 0Eh ; Changed from F000 to E000.=0D - DB 09Bh ; present, ring 0, code, expand-up= , writable=0D - DB 00h ; byte-granular, 16-bit=0D - DB 0=0D -;=0D -; Spare segment descriptor=0D -;=0D -SYS16_DATA_SEL EQU $ - GDT_BASE ; Selector [0x30]=0D - DW 0FFFFh ; limit 0xFFFF=0D - DW 0 ; base 0=0D - DB 0=0D - DB 093h ; present, ring 0, data, expand-up= , not-writable=0D - DB 00h ; byte-granular, 16-bit=0D - DB 0=0D -=0D -;=0D -; Spare segment descriptor=0D -;=0D -SPARE5_SEL EQU $ - GDT_BASE ; Selector [0x38]=0D - DW 0 ; limit 0=0D - DW 0 ; base 0=0D - DB 0=0D - DB 0 ; present, ring 0, data, expand-up= , writable=0D - DB 0 ; page-granular, 32-bit=0D - DB 0=0D -GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes=0D -=0D -;=0D -; GDT Descriptor=0D -;=0D -GdtDesc: ; GDT descriptor=0D - DW GDT_SIZE - 1 ; GDT limit=0D - DD GDT_BASE ; GDT base address=0D -=0D -=0D -ProtectedModeEntryLinearAddress:=0D -ProtectedModeEntryLinear:=0D - DD ProtectedModeEntryPoint ; Offset of our 32 bit code=0D - DW LINEAR_CODE_SEL=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspW= rapperPlatformSecLib/Ia32/Stack.nasm b/Platform/Intel/KabylakeOpenBoardPkg/= FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm deleted file mode 100644 index 47db32d64c..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP= latformSecLib/Ia32/Stack.nasm +++ /dev/null @@ -1,72 +0,0 @@ -;-------------------------------------------------------------------------= -----=0D -;=0D -; Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D -; SPDX-License-Identifier: BSD-2-Clause-Patent=0D -; Abstract:=0D -;=0D -; Switch the stack from temporary memory to permanent memory.=0D -;=0D -;-------------------------------------------------------------------------= -----=0D -=0D - SECTION .text=0D -=0D -;-------------------------------------------------------------------------= -----=0D -; VOID=0D -; EFIAPI=0D -; SecSwitchStack (=0D -; UINT32 TemporaryMemoryBase,=0D -; UINT32 PermanentMemoryBase=0D -; );=0D -;-------------------------------------------------------------------------= -----=0D -global ASM_PFX(SecSwitchStack)=0D -ASM_PFX(SecSwitchStack):=0D - ;=0D - ; Save three register: eax, ebx, ecx=0D - ;=0D - push eax=0D - push ebx=0D - push ecx=0D - push edx=0D -=0D - ;=0D - ; !!CAUTION!! this function address's is pushed into stack after=0D - ; migration of whole temporary memory, so need save it to permanent=0D - ; memory at first!=0D - ;=0D -=0D - mov ebx, [esp + 20] ; Save the first parameter=0D - mov ecx, [esp + 24] ; Save the second parameter=0D -=0D - ;=0D - ; Save this function's return address into permanent memory at first.= =0D - ; Then, Fixup the esp point to permanent memory=0D - ;=0D - mov eax, esp=0D - sub eax, ebx=0D - add eax, ecx=0D - mov edx, dword [esp] ; copy pushed register's value to perma= nent memory=0D - mov dword [eax], edx=0D - mov edx, dword [esp + 4]=0D - mov dword [eax + 4], edx=0D - mov edx, dword [esp + 8]=0D - mov dword [eax + 8], edx=0D - mov edx, dword [esp + 12]=0D - mov dword [eax + 12], edx=0D - mov edx, dword [esp + 16] ; Update this function's return address= into permanent memory=0D - mov dword [eax + 16], edx=0D - mov esp, eax ; From now, esp is pointed to perma= nent memory=0D -=0D - ;=0D - ; Fixup the ebp point to permanent memory=0D - ;=0D - mov eax, ebp=0D - sub eax, ebx=0D - add eax, ecx=0D - mov ebp, eax ; From now, ebp is pointed to permanent = memory=0D -=0D - pop edx=0D - pop ecx=0D - pop ebx=0D - pop eax=0D - ret=0D -=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspW= rapperPlatformSecLib/PlatformInit.c b/Platform/Intel/KabylakeOpenBoardPkg/F= spWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c deleted file mode 100644 index ef89e3f310..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP= latformSecLib/PlatformInit.c +++ /dev/null @@ -1,47 +0,0 @@ -/** @file=0D - Provide platform init function.=0D -=0D -Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D -SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -=0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -=0D -/**=0D - Platform initialization.=0D -=0D - @param[in] FspHobList HobList produced by FSP.=0D - @param[in] StartOfRange Start of temporary RAM.=0D - @param[in] EndOfRange End of temporary RAM.=0D -**/=0D -VOID=0D -EFIAPI=0D -PlatformInit (=0D - IN VOID *FspHobList,=0D - IN VOID *StartOfRange,=0D - IN VOID *EndOfRange=0D - )=0D -{=0D - //=0D - // Platform initialization=0D - // Enable Serial port here=0D - //=0D - if (PcdGetBool(PcdSecSerialPortDebugEnable)) {=0D - SerialPortInitialize ();=0D - }=0D -=0D - DEBUG ((DEBUG_INFO, "PrintPeiCoreEntryPointParam in PlatformInit\n"));=0D - DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList));=0D - DEBUG ((DEBUG_INFO, "StartOfRange - 0x%x\n", StartOfRange));=0D - DEBUG ((DEBUG_INFO, "EndOfRange - 0x%x\n", EndOfRange));=0D -=0D - BoardAfterTempRamInit ();=0D -=0D - TestPointTempMemoryFunction (StartOfRange, EndOfRange);=0D -}=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspW= rapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf b/Platform/Intel/Kabyl= akeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrappe= rPlatformSecLib.inf deleted file mode 100644 index c99dd5ecdd..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP= latformSecLib/SecFspWrapperPlatformSecLib.inf +++ /dev/null @@ -1,97 +0,0 @@ -## @file=0D -# Provide FSP wrapper platform sec related function.=0D -#=0D -# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D -#=0D -# SPDX-License-Identifier: BSD-2-Clause-Patent=0D -#=0D -#=0D -##=0D -=0D -##########################################################################= ######=0D -#=0D -# Defines Section - statements that will be processed to create a Makefile= .=0D -#=0D -##########################################################################= ######=0D -[Defines]=0D - INF_VERSION =3D 0x00010005=0D - BASE_NAME =3D SecFspWrapperPlatformSecLib=0D - FILE_GUID =3D 4E1C4F95-90EA-47de-9ACC-B8920189A1F5= =0D - MODULE_TYPE =3D SEC=0D - VERSION_STRING =3D 1.0=0D - LIBRARY_CLASS =3D PlatformSecLib=0D -=0D -=0D -#=0D -# The following information is for reference only and not required by the = build tools.=0D -#=0D -# VALID_ARCHITECTURES =3D IA32 X64=0D -#=0D -=0D -##########################################################################= ######=0D -#=0D -# Sources Section - list of files that are required for the build to succe= ed.=0D -#=0D -##########################################################################= ######=0D -=0D -[Sources]=0D - FspWrapperPlatformSecLib.c=0D - SecRamInitData.c=0D - SecPlatformInformation.c=0D - SecGetPerformance.c=0D - SecTempRamDone.c=0D - PlatformInit.c=0D -=0D -[Sources.IA32]=0D - Ia32/SecEntry.nasm=0D - Ia32/PeiCoreEntry.nasm=0D - Ia32/Stack.nasm=0D - Ia32/Fsp.h=0D -=0D -##########################################################################= ######=0D -#=0D -# Package Dependency Section - list of Package files that are required for= =0D -# this module.=0D -#=0D -##########################################################################= ######=0D -=0D -[Packages]=0D - MdePkg/MdePkg.dec=0D - MdeModulePkg/MdeModulePkg.dec=0D - UefiCpuPkg/UefiCpuPkg.dec=0D - IntelFsp2Pkg/IntelFsp2Pkg.dec=0D - IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec=0D - MinPlatformPkg/MinPlatformPkg.dec=0D - KabylakeSiliconPkg/SiPkg.dec=0D -=0D -[LibraryClasses]=0D - LocalApicLib=0D - SerialPortLib=0D - FspWrapperPlatformLib=0D - FspWrapperApiLib=0D - BoardInitLib=0D - SecBoardInitLib=0D - TestPointCheckLib=0D - PeiServicesTablePointerLib=0D -=0D -[Ppis]=0D - gEfiSecPlatformInformationPpiGuid ## CONSUMES=0D - gPeiSecPerformancePpiGuid ## CONSUMES=0D - gTopOfTemporaryRamPpiGuid ## PRODUCES=0D - gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES=0D - gFspTempRamExitPpiGuid ## CONSUMES=0D -=0D -[Pcd]=0D - gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize ## C= ONSUMES=0D - gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress ## C= ONSUMES=0D - gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## C= ONSUMES=0D - gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ## C= ONSUMES=0D -=0D -[FixedPcd]=0D - gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## C= ONSUMES=0D - gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## C= ONSUMES=0D - gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset ## C= ONSUMES=0D - gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ## C= ONSUMES=0D - gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize ## C= ONSUMES=0D - gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## C= ONSUMES=0D - gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## C= ONSUMES=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspW= rapperPlatformSecLib/SecGetPerformance.c b/Platform/Intel/KabylakeOpenBoard= Pkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c deleted file mode 100644 index c4eeb2b188..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP= latformSecLib/SecGetPerformance.c +++ /dev/null @@ -1,89 +0,0 @@ -/** @file=0D - Sample to provide SecGetPerformance function.=0D -=0D -Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D -SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -#include =0D -=0D -#include =0D -#include =0D -=0D -#include =0D -#include =0D -#include =0D -=0D -/**=0D - This interface conveys performance information out of the Security (SEC)= phase into PEI.=0D -=0D - This service is published by the SEC phase. The SEC phase handoff has an= optional=0D - EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed= from SEC into the=0D - PEI Foundation. As such, if the platform supports collecting performance= data in SEC,=0D - this information is encapsulated into the data structure abstracted by t= his service.=0D - This information is collected for the boot-strap processor (BSP) on IA-3= 2.=0D -=0D - @param[in] PeiServices The pointer to the PEI Services Table.=0D - @param[in] This The pointer to this instance of the PEI_SEC_PER= FORMANCE_PPI.=0D - @param[out] Performance The pointer to performance data collected in SE= C phase.=0D -=0D - @retval EFI_SUCCESS The data was successfully returned.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -SecGetPerformance (=0D - IN CONST EFI_PEI_SERVICES **PeiServices,=0D - IN PEI_SEC_PERFORMANCE_PPI *This,=0D - OUT FIRMWARE_SEC_PERFORMANCE *Performance=0D - )=0D -{=0D - UINT32 Size;=0D - UINT32 Count;=0D - UINT32 TopOfTemporaryRam;=0D - UINT64 Ticker;=0D - VOID *TopOfTemporaryRamPpi;=0D - EFI_STATUS Status;=0D -=0D - DEBUG ((DEBUG_INFO, "SecGetPerformance\n"));=0D -=0D - Status =3D (*PeiServices)->LocatePpi (=0D - PeiServices,=0D - &gTopOfTemporaryRamPpiGuid,=0D - 0,=0D - NULL,=0D - (VOID **) &TopOfTemporaryRamPpi=0D - );=0D - if (EFI_ERROR (Status)) {=0D - return EFI_NOT_FOUND;=0D - }=0D - //=0D - // |--------------| <- TopOfTemporaryRam - BL=0D - // | List Ptr |=0D - // |--------------|=0D - // | BL RAM Start |=0D - // |--------------|=0D - // | BL RAM End |=0D - // |--------------|=0D - // |Number of BSPs|=0D - // |--------------|=0D - // | BIST |=0D - // |--------------|=0D - // | .... |=0D - // |--------------|=0D - // | TSC[63:32] |=0D - // |--------------|=0D - // | TSC[31:00] |=0D - // |--------------|=0D - //=0D - TopOfTemporaryRam =3D (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof(UINT3= 2);=0D - TopOfTemporaryRam -=3D sizeof(UINT32) * 2;=0D - Count =3D *(UINT32 *) (UINTN) (TopOfTemporaryRam - sizeof (U= INT32));=0D - Size =3D Count * sizeof (UINT32);=0D -=0D - Ticker =3D *(UINT64 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32) - Si= ze - sizeof (UINT32) * 2);=0D - Performance->ResetEnd =3D GetTimeInNanoSecond (Ticker);=0D -=0D - return EFI_SUCCESS;=0D -}=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspW= rapperPlatformSecLib/SecPlatformInformation.c b/Platform/Intel/KabylakeOpen= BoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformat= ion.c deleted file mode 100644 index 5b94ed2bef..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP= latformSecLib/SecPlatformInformation.c +++ /dev/null @@ -1,78 +0,0 @@ -/** @file=0D - Provide SecPlatformInformation function.=0D -=0D -Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D -SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -#include =0D -=0D -#include =0D -#include =0D -=0D -#include =0D -#include =0D -=0D -/**=0D - This interface conveys state information out of the Security (SEC) phase= into PEI.=0D -=0D - @param[in] PeiServices Pointer to the PEI Services Tab= le.=0D - @param[in,out] StructureSize Pointer to the variable describ= ing size of the input buffer.=0D - @param[out] PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM= _INFORMATION_RECORD.=0D -=0D - @retval EFI_SUCCESS The data was successfully returned.=0D - @retval EFI_BUFFER_TOO_SMALL The buffer was too small.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -SecPlatformInformation (=0D - IN CONST EFI_PEI_SERVICES **PeiServices,=0D - IN OUT UINT64 *StructureSize,=0D - OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord= =0D - )=0D -{=0D - UINT32 *Bist;=0D - UINT32 Size;=0D - UINT32 Count;=0D - UINT32 TopOfTemporaryRam;=0D - VOID *TopOfTemporaryRamPpi;=0D - EFI_STATUS Status;=0D -=0D - DEBUG ((DEBUG_INFO, "SecPlatformInformation\n"));=0D -=0D - Status =3D (*PeiServices)->LocatePpi (=0D - PeiServices,=0D - &gTopOfTemporaryRamPpiGuid,=0D - 0,=0D - NULL,=0D - (VOID **) &TopOfTemporaryRamPpi=0D - );=0D - if (EFI_ERROR (Status)) {=0D - return EFI_NOT_FOUND;=0D - }=0D -=0D - //=0D - // The entries of BIST information, together with the number of them,=0D - // reside in the bottom of stack, left untouched by normal stack operati= on.=0D - // This routine copies the BIST information to the buffer pointed by=0D - // PlatformInformationRecord for output.=0D - //=0D - TopOfTemporaryRam =3D (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof (UINT= 32);=0D - TopOfTemporaryRam -=3D sizeof(UINT32) * 2;=0D - Count =3D *((UINT32 *)(UINTN) (TopOfTemporaryRam - sizeof (U= INT32)));=0D - Size =3D Count * sizeof (IA32_HANDOFF_STATUS);=0D -=0D - if ((*StructureSize) < (UINT64) Size) {=0D - *StructureSize =3D Size;=0D - return EFI_BUFFER_TOO_SMALL;=0D - }=0D -=0D - *StructureSize =3D Size;=0D - Bist =3D (UINT32 *) (TopOfTemporaryRam - sizeof (UINT32) - Si= ze);=0D -=0D - CopyMem (PlatformInformationRecord, Bist, Size);=0D -=0D - return EFI_SUCCESS;=0D -}=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspW= rapperPlatformSecLib/SecRamInitData.c b/Platform/Intel/KabylakeOpenBoardPkg= /FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c deleted file mode 100644 index b356327b4c..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP= latformSecLib/SecRamInitData.c +++ /dev/null @@ -1,36 +0,0 @@ -/** @file=0D - Provide TempRamInitParams data.=0D -=0D -Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D -SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -#include =0D -#include =0D -#include "FsptCoreUpd.h"=0D -=0D -typedef struct {=0D - FSP_UPD_HEADER FspUpdHeader;=0D - FSPT_CORE_UPD FsptCoreUpd;=0D -} FSPT_UPD_CORE_DATA;=0D -=0D -GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA FsptUpdDataPtr =3D = {=0D - {=0D - 0x4450555F54505346,=0D - 0x00,=0D - { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D - }=0D - },=0D - {=0D - ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + FixedPcdGet32 (= PcdFlashMicrocodeOffset)),=0D - ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet3= 2 (PcdFlashMicrocodeOffset)),=0D - 0, // Set CodeRegionBase as 0, so that caching will be 4GB-(C= odeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used.=0D - FixedPcdGet32 (PcdFlashCodeCacheSize),=0D - { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D - }=0D - }=0D -};=0D -=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspW= rapperPlatformSecLib/SecTempRamDone.c b/Platform/Intel/KabylakeOpenBoardPkg= /FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c deleted file mode 100644 index 922e4ec204..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperP= latformSecLib/SecTempRamDone.c +++ /dev/null @@ -1,73 +0,0 @@ -/** @file=0D - Provide SecTemporaryRamDone function.=0D -=0D -Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D -SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -#include =0D -=0D -#include =0D -#include =0D -=0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -=0D -/**=0D -This interface disables temporary memory in SEC Phase.=0D -**/=0D -VOID=0D -EFIAPI=0D -SecPlatformDisableTemporaryMemory (=0D - VOID=0D - )=0D -{=0D - EFI_STATUS Status;=0D - VOID *TempRamExitParam;=0D - CONST EFI_PEI_SERVICES **PeiServices;=0D - FSP_TEMP_RAM_EXIT_PPI *TempRamExitPpi;=0D -=0D - DEBUG ((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n"));=0D -=0D - Status =3D BoardInitBeforeTempRamExit ();=0D - ASSERT_EFI_ERROR (Status);=0D -=0D - if (PcdGet8 (PcdFspModeSelection) =3D=3D 1) {=0D - //=0D - // FSP API mode=0D - //=0D - TempRamExitParam =3D UpdateTempRamExitParam ();=0D - Status =3D CallTempRamExit (TempRamExitParam);=0D - DEBUG ((DEBUG_INFO, "TempRamExit status: 0x%x\n", Status));=0D - ASSERT_EFI_ERROR (Status);=0D - } else {=0D - //=0D - // FSP Dispatch mode=0D - //=0D - PeiServices =3D GetPeiServicesTablePointer ();=0D - Status =3D (*PeiServices)->LocatePpi (=0D - PeiServices,=0D - &gFspTempRamExitPpiGuid,=0D - 0,=0D - NULL,=0D - (VOID **) &TempRamExitPpi=0D - );=0D - ASSERT_EFI_ERROR (Status);=0D - if (EFI_ERROR (Status)) {=0D - return;=0D - }=0D - TempRamExitPpi->TempRamExit (NULL);=0D - }=0D -=0D - Status =3D BoardInitAfterTempRamExit ();=0D - ASSERT_EFI_ERROR (Status);=0D -=0D - return ;=0D -}=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.ds= c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc index 2bc2b4126b..acdc31e708 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc @@ -126,7 +126,7 @@ #######################################=0D GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/Ba= seGpioExpanderLib.inf=0D I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAcc= essLib.inf=0D - PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFspWrappe= rPlatformSecLib/SecFspWrapperPlatformSecLib.inf=0D + PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatf= ormSecLib/SecFspWrapperPlatformSecLib.inf=0D =0D # Thunderbolt=0D !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.= dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index 77e4a6a610..4b07c0a684 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -166,7 +166,7 @@ EcLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseEcLib/BaseEcLib.inf=0D GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/Ba= seGpioExpanderLib.inf=0D I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAcc= essLib.inf=0D - PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFspWrappe= rPlatformSecLib/SecFspWrapperPlatformSecLib.inf=0D + PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatf= ormSecLib/SecFspWrapperPlatformSecLib.inf=0D =0D # Thunderbolt=0D !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE=0D --=20 2.24.0.windows.2