From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga18.intel.com (mga18.intel.com []) by mx.groups.io with SMTP id smtpd.web10.21389.1574326764546050137 for ; Thu, 21 Nov 2019 00:59:25 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: nathaniel.l.desimone@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Nov 2019 00:59:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,224,1571727600"; d="scan'208";a="210033053" Received: from nldesimo-desk1.amr.corp.intel.com ([10.7.159.63]) by orsmga006.jf.intel.com with ESMTP; 21 Nov 2019 00:59:20 -0800 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Michael Kubacki , Sai Chaganty Subject: [edk2-platforms] [PATCH V2 06/14] CoffeelakeSiliconPkg: Add SiliconInitLib Date: Thu, 21 Nov 2019 00:58:45 -0800 Message-Id: <20191121085853.2626-7-nathaniel.l.desimone@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20191121085853.2626-1-nathaniel.l.desimone@intel.com> References: <20191121085853.2626-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable SiliconInitLib contains Silicon Init APIs that can be reused by BoardInitLib. It is expected that several implementations of BoardInitLib exist for a given SOC, these APIs allow the various BoardInitLib implementations to reuse common silicon initialization code. This matches the implementation already found in KabylakeSiliconPkg. This change also adds halting the TCO watch dog timer to PEI, which was previously done in SEC. Cc: Chasel Chiu Cc: Michael Kubacki Cc: Sai Chaganty Signed-off-by: Nate DeSimone --- .../Include/Library/SiliconInitLib.h | 28 +++++ .../PeiSiliconInitLib/PeiSiliconInitLib.inf | 46 ++++++++ .../Library/PeiSiliconInitLib/SiliconInit.c | 19 +++ .../PeiSiliconInitLib/SiliconInitPreMem.c | 109 ++++++++++++++++++ 4 files changed, 202 insertions(+) create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/Sili= conInitLib.h create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconIn= itLib/PeiSiliconInitLib.inf create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconIn= itLib/SiliconInit.c create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconIn= itLib/SiliconInitPreMem.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInit= Lib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.h new file mode 100644 index 0000000000..a3411126a7 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.h @@ -0,0 +1,28 @@ +/** @file=0D +=0D +Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef _SILICON_INIT_LIB_H_=0D +#define _SILICON_INIT_LIB_H_=0D +=0D +#include =0D +=0D +VOID=0D +EarlySiliconInit (=0D + VOID=0D + );=0D +=0D +VOID=0D +SiliconInit (=0D + VOID=0D + );=0D +=0D +VOID=0D +LateSiliconInit (=0D + VOID=0D + );=0D +=0D +#endif \ No newline at end of file diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/P= eiSiliconInitLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSilico= nInitLib/PeiSiliconInitLib.inf new file mode 100644 index 0000000000..1534a24dd2 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSilic= onInitLib.inf @@ -0,0 +1,46 @@ +### @file=0D +#=0D +# Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +###=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D SiliconInitLib=0D + FILE_GUID =3D 82F2ACF0-2EBE-48C8-AC58-9D0F8BC1E16E= =0D + VERSION_STRING =3D 1.0=0D + MODULE_TYPE =3D PEIM=0D + LIBRARY_CLASS =3D SiliconInitLib|SEC PEIM=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC=0D +#=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + BaseMemoryLib=0D + DebugLib=0D + HobLib=0D + IoLib=0D + PcdLib=0D + PeiServicesLib=0D + PchCycleDecodingLib=0D + PmcLib=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + CoffeelakeSiliconPkg/SiPkg.dec=0D +=0D +[Sources]=0D + SiliconInit.c=0D + SiliconInitPreMem.c=0D +=0D +[Guids]=0D + gTcoWdtHobGuid ## CONSUMES=0D +=0D +[Pcd]=0D + gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES=0D + gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ## CONSUMES=0D diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/S= iliconInit.c b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib= /SiliconInit.c new file mode 100644 index 0000000000..1c15e0e54e --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconI= nit.c @@ -0,0 +1,19 @@ +/** @file=0D + Silicon Init APIs for MinPlatform BoardInitLib implementations.=0D +=0D +Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +=0D +/**=0D + Late Silicon Initialization=0D +**/=0D +VOID=0D +LateSiliconInit (=0D + VOID=0D + )=0D +{=0D +}=0D diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/S= iliconInitPreMem.c b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconI= nitLib/SiliconInitPreMem.c new file mode 100644 index 0000000000..ab98b6ccc5 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconI= nitPreMem.c @@ -0,0 +1,109 @@ +/** @file=0D + Silicon Init APIs for MinPlatform BoardInitLib implementations.=0D +=0D +Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Early Silicon initialization=0D +**/=0D +VOID=0D +EarlySiliconInit (=0D + VOID=0D + )=0D +{=0D + UINT16 Data16;=0D + UINT8 Data8;=0D + UINT8 TcoRebootHappened;=0D + TCO_WDT_HOB *TcoWdtHobPtr;=0D + EFI_STATUS Status;=0D +=0D + ///=0D + /// LPC I/O Configuration=0D + ///=0D + PchLpcIoDecodeRangesSet (=0D + (V_LPC_CFG_IOD_LPT_378 << N_LPC_CFG_IOD_LPT) |=0D + (V_LPC_CFG_IOD_COMB_3E8 << N_LPC_CFG_IOD_COMB) |=0D + (V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA)=0D + );=0D +=0D + PchLpcIoEnableDecodingSet (=0D + B_LPC_CFG_IOE_ME2 |=0D + B_LPC_CFG_IOE_SE |=0D + B_LPC_CFG_IOE_ME1 |=0D + B_LPC_CFG_IOE_KE |=0D + B_LPC_CFG_IOE_HGE |=0D + B_LPC_CFG_IOE_LGE |=0D + B_LPC_CFG_IOE_FDE |=0D + B_LPC_CFG_IOE_PPE |=0D + B_LPC_CFG_IOE_CBE |=0D + B_LPC_CFG_IOE_CAE=0D + );=0D +=0D + ///=0D + /// Halt the TCO timer=0D + ///=0D + Data16 =3D IoRead16 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT);= =0D + Data16 |=3D B_TCO_IO_TCO1_CNT_TMR_HLT;=0D + IoWrite16 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT, Data16);=0D +=0D + ///=0D + /// Read the Second TO status bit=0D + ///=0D + Data8 =3D IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS);=0D + if ((Data8 & B_TCO_IO_TCO2_STS_SECOND_TO) =3D=3D B_TCO_IO_TCO2_STS_SECON= D_TO) {=0D + TcoRebootHappened =3D 1;=0D + DEBUG ((DEBUG_INFO, "PlatformInitPreMem - TCO Second TO status bit is = set. This might be a TCO reboot\n"));=0D + }=0D + else {=0D + TcoRebootHappened =3D 0;=0D + }=0D +=0D + ///=0D + /// Create HOB=0D + ///=0D + Status =3D PeiServicesCreateHob (EFI_HOB_TYPE_GUID_EXTENSION, sizeof(TCO= _WDT_HOB), (VOID **)&TcoWdtHobPtr);=0D + if (!EFI_ERROR (Status)) {=0D + TcoWdtHobPtr->Header.Name =3D gTcoWdtHobGuid;=0D + TcoWdtHobPtr->TcoRebootHappened =3D TcoRebootHappened;=0D + }=0D +=0D + ///=0D + /// Clear the Second TO status bit=0D + ///=0D + IoWrite8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS, B_TCO_IO_TCO= 2_STS_SECOND_TO);=0D +}=0D +=0D +/**=0D + Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal in= version registers=0D +=0D +**/=0D +VOID=0D +SiliconInit (=0D + VOID=0D + )=0D +{=0D + UINT16 ABase;=0D +=0D + ABase =3D PmcGetAcpiBase ();=0D +=0D + ///=0D + /// Clear all pending SMI. On S3 clear power button enable so it will no= t generate an SMI.=0D + ///=0D + IoWrite16 (ABase + R_ACPI_IO_PM1_EN, 0);=0D + IoWrite32 (ABase + R_ACPI_IO_GPE0_EN_127_96, 0);=0D +}=0D --=20 2.24.0.windows.2