From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66]) by mx.groups.io with SMTP id smtpd.web09.26187.1574353472449351649 for ; Thu, 21 Nov 2019 08:24:32 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=CAw15MzO; spf=pass (domain: linaro.org, ip: 209.85.128.66, mailfrom: leif.lindholm@linaro.org) Received: by mail-wm1-f66.google.com with SMTP id g206so4149187wme.1 for ; Thu, 21 Nov 2019 08:24:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=e5lS5E2madP1n5ZAo9oXpEh8NsE2lyEu75FqhVs5L9w=; b=CAw15MzOeZ8UZCnSin4cjBBvhcplwxCX2J0Td6UBsobNmL3oL9oqh+/t1rrfzaMpq3 Zhm+mhtt7ZBmDqGsdy8C97KQ/P9CmqXm42hd06964gewayA3F4Gso5bscr0jsA5jelcB 119D2DGdc/RXCGldevNacuELg0abJFgVhU18ne2jVQ4D31bUEXP4ydygbD/CVB4IEBTu gpXG9yjN8QCwTi3bnV6VQ6LqLLAa7NpjoiWsakT/LiX5qpk9a1MOUfUNkG15SfxuyzJq yRIqlH7B5/6rgGTdYiAXgxuKGMOSHpaS5CSvDr2PFh1GttvwSl3gIjMqGS9C8vj3nuDR ormw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=e5lS5E2madP1n5ZAo9oXpEh8NsE2lyEu75FqhVs5L9w=; b=mKmapZ6KpvHQbeBOFO5IRdicF9gyZ0OJ0WM3zOiM63biag403GPtexRLjfy9fys0c8 /untlqCk0vmyGphzdo4OobnJQq/G0EP7FP/KWDzD01s3STN/AdrDkorlXapvn/+vDryf mu3Fj8OTPNDIItVtI+/SlzVWrNJUoY5hWlhQJvL9VqQTLsINFuupgncKjVKONz6MUrqZ 2Vj1xD7DEMCGNldz0hZVYzSeXNTPfXCXxs52BWMjJXroQlMfHiooTgCHnuTrpRtpEzC6 Ybxb7OXlJ0rhNcR1zMZvt7GuIkC9WK/NI2+VSC6NoENg4W98FTbe78x+fbiPra0+/eXC XESg== X-Gm-Message-State: APjAAAUEqHRwh2pXdD/SEkfUE/u5hGPatFmXtBZTN0bxllkkRJwCgBEd 15GRCPceZpB0nu5hvAdBjr/QPg== X-Google-Smtp-Source: APXvYqy/Yhr4BS2AY8CDixhxiDcguO0XBdn5tvP55wOL+mNY8lKIX7Wby6n7tlCbcR23C41syI2HvA== X-Received: by 2002:a1c:6a09:: with SMTP id f9mr10948595wmc.15.1574353470844; Thu, 21 Nov 2019 08:24:30 -0800 (PST) Return-Path: Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id j17sm1465117wrr.75.2019.11.21.08.24.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 08:24:29 -0800 (PST) Date: Thu, 21 Nov 2019 16:24:28 +0000 From: "Leif Lindholm" To: Abner Chang Cc: devel@edk2.groups.io, Gilbert Chen , Palmer Dabbelt , "Kinney, Michael D" Subject: Re: [edk2-staging/RISC-V-V2 PATCH v3 03/39] RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support Message-ID: <20191121162428.GJ7359@bivouac.eciton.net> References: <1572227957-13169-1-git-send-email-abner.chang@hpe.com> <1572227957-13169-4-git-send-email-abner.chang@hpe.com> MIME-Version: 1.0 In-Reply-To: <1572227957-13169-4-git-send-email-abner.chang@hpe.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Oct 28, 2019 at 09:58:41 +0800, Abner Chang wrote: > Add EDK2 RISC-V OpenSBI header files. > > Signed-off-by: Abner Chang > > Cc: Leif Lindholm > Cc: Gilbert Chen > --- > RiscVPkg/Include/sbi/SbiFirmwareContext.h | 33 ++++++++++++++++++++ > RiscVPkg/Include/sbi/sbi.h | 52 +++++++++++++++++++++++++++++++ > RiscVPkg/Include/sbi/sbi_bits.h | 17 ++++++++++ > RiscVPkg/Include/sbi/sbi_types.h | 45 ++++++++++++++++++++++++++ > 4 files changed, 147 insertions(+) > create mode 100644 RiscVPkg/Include/sbi/SbiFirmwareContext.h > create mode 100644 RiscVPkg/Include/sbi/sbi.h > create mode 100644 RiscVPkg/Include/sbi/sbi_bits.h > create mode 100644 RiscVPkg/Include/sbi/sbi_types.h > > diff --git a/RiscVPkg/Include/sbi/SbiFirmwareContext.h b/RiscVPkg/Include/sbi/SbiFirmwareContext.h > new file mode 100644 > index 0000000..c3d3489 > --- /dev/null > +++ b/RiscVPkg/Include/sbi/SbiFirmwareContext.h > @@ -0,0 +1,33 @@ > +/** @file > + RISC-V OpesbSBI Platform Firmware context definition > + > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > +#ifndef SBI_FIRMWARE_CONTEXT_H_ > +#define SBI_FIRMWARE_CONTEXT_H_ > + > +#include > + > +#define RISC_V_MAX_HART_SUPPORTED 16 > + > +// > +// keep the structure member in 64-bit alignment. > +// > +typedef struct { > + UINT64 IsaExtensionSupported; // The ISA extension this core supported. > + RISCV_UINT128 MachineVendorId; // Machine vendor ID > + RISCV_UINT128 MachineArchId; // Machine Architecture ID > + RISCV_UINT128 MachineImplId; // Machine Implementation ID > +} EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC; > + > +#define FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE (64 * 7) > + > +typedef struct { > + VOID *PeiServiceTable; // PEI Service table > + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_SUPPORTED]; > +} EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT; > +#endif > + > diff --git a/RiscVPkg/Include/sbi/sbi.h b/RiscVPkg/Include/sbi/sbi.h > new file mode 100644 > index 0000000..04e7f18 > --- /dev/null > +++ b/RiscVPkg/Include/sbi/sbi.h > @@ -0,0 +1,52 @@ > +/** @file > + SBI inline function calls. > + > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef EDK2_SBI_H_ > +#define EDK2_SBI_H_ > + > +#include // Reference to header file wrapper > +#include // Reference to header file in opensbi This whole sbi situation is too much of a hornets' nest, and really does need to get sorted before we even push this to -staging. (But I do think is is one of the last things we need to address.) And I think the starting point to untangle it is to rename the wrapper include files in RiscVPkg/Include/sbi (and indeed the directory itself) to conform with the TianoCore standard. That means: RiscVPkg/Include/IndustryStandard/Sbi/Sbi.h RiscVPkg/Include/IndustryStandard/Sbi/SbiBits.h RiscVPkg/Include/IndustryStandard/Sbi/SbiTypes.h Unless all of the wrappers can be combined into a single RiscVPkg/Include/IndustryStandard/Sbi.h ...and then tested on a case-sensitive filesystem. For the record, doing that immediately results in the non-wrapper versions being pulled in and then the build failing. / Leif > + > +#define SBI_SET_TIMER 0 > +#define SBI_CONSOLE_PUTCHAR 1 > +#define SBI_CONSOLE_GETCHAR 2 > +#define SBI_CLEAR_IPI 3 > +#define SBI_SEND_IPI 4 > +#define SBI_REMOTE_FENCE_I 5 > +#define SBI_REMOTE_SFENCE_VMA 6 > +#define SBI_REMOTE_SFENCE_VMA_ASID 7 > +#define SBI_SHUTDOWN 8 > + > +#define SBI_CALL(which, arg0, arg1, arg2) ({ \ > + register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \ > + register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); \ > + register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); \ > + register uintptr_t a7 asm ("a7") = (uintptr_t)(which); \ > + asm volatile ("ecall" \ > + : "+r" (a0) \ > + : "r" (a1), "r" (a2), "r" (a7) \ > + : "memory"); \ > + a0; \ > +}) > + > +#define SBI_CALL_0(which) SBI_CALL(which, 0, 0, 0) > +#define SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0) > +#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0) > + > +#define sbi_console_putchar(ch) SBI_CALL_1(SBI_CONSOLE_PUTCHAR, ch) > +#define sbi_console_getchar() SBI_CALL_0(SBI_CONSOLE_GETCHAR) > +#define sbi_set_timer(stime_value) SBI_CALL_1(SBI_SET_TIMER, stime_value) > +#define sbi_shutdown() SBI_CALL_0(SBI_SHUTDOWN) > +#define sbi_clear_ipi() SBI_CALL_0(SBI_CLEAR_IPI) > +#define sbi_send_ipi(hart_mask) SBI_CALL_1(SBI_SEND_IPI, hart_mask) > +#define sbi_remote_fence_i(hart_mask) SBI_CALL_1(SBI_REMOTE_FENCE_I, hart_mask) > +#define sbi_remote_sfence_vma(hart_mask, start, size) SBI_CALL_1(SBI_REMOTE_SFENCE_VMA, hart_mask) > +#define sbi_remote_sfence_vma_asid(hart_mask, start, size, asid) SBI_CALL_1(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask) > + > +#endif > diff --git a/RiscVPkg/Include/sbi/sbi_bits.h b/RiscVPkg/Include/sbi/sbi_bits.h > new file mode 100644 > index 0000000..c935547 > --- /dev/null > +++ b/RiscVPkg/Include/sbi/sbi_bits.h > @@ -0,0 +1,17 @@ > +/** @file > + RISC-V OpesbSBI header file reference. > + > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > +#ifndef EDK2_SBI_BITS_H_ > +#define EDK2_SBI_BITS_H_ > + > +#undef MAX > +#undef MIN > + > +#include "include/sbi/sbi_bits.h" // Reference to header file in opensbi > + > +#endif > diff --git a/RiscVPkg/Include/sbi/sbi_types.h b/RiscVPkg/Include/sbi/sbi_types.h > new file mode 100644 > index 0000000..95ee213 > --- /dev/null > +++ b/RiscVPkg/Include/sbi/sbi_types.h > @@ -0,0 +1,45 @@ > +/** @file > + RISC-V OpesbSBI header file reference. > + > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > +#ifndef EDK2_SBI_TYPES_H_ > +#define EDK2_SBI_TYPES_H_ > + > +typedef INT8 s8; > +typedef UINT8 u8; > +typedef UINT8 uint8_t; > + > +typedef INT16 s16; > +typedef UINT16 u16; > +typedef INT16 int16_t; > +typedef UINT16 uint16_t; > + > +typedef INT32 s32; > +typedef UINT32 u32; > +typedef INT32 int32_t; > +typedef UINT32 uint32_t; > + > +typedef INT64 s64; > +typedef UINT64 u64; > +typedef INT64 int64_t; > +typedef UINT64 uint64_t; > + > +#define PRILX "016lx" > + > +typedef INT32 bool; > +typedef unsigned long ulong; > +typedef UINT64 uintptr_t; > +typedef UINT64 size_t; > +typedef INT64 ssize_t; > +typedef UINT64 virtual_addr_t; > +typedef UINT64 virtual_size_t; > +typedef UINT64 physical_addr_t; > +typedef UINT64 physical_size_t; > + > +#define __packed __attribute__((packed)) > +#define __noreturn __attribute__((noreturn)) > +#endif > -- > 2.7.4 >