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[2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id 189sm320733wmc.7.2019.11.21.09.09.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2019 09:09:06 -0800 (PST) Date: Thu, 21 Nov 2019 17:09:05 +0000 From: "Leif Lindholm" To: Abner Chang Cc: devel@edk2.groups.io, Gilbert Chen Subject: Re: [edk2-staging/RISC-V-V2 PATCH v3 37/39] edk2-staging:RISC-V-V2: Add RiscVEdk2Readme.md Message-ID: <20191121170904.GQ7359@bivouac.eciton.net> References: <1572227957-13169-1-git-send-email-abner.chang@hpe.com> <1572227957-13169-38-git-send-email-abner.chang@hpe.com> MIME-Version: 1.0 In-Reply-To: <1572227957-13169-38-git-send-email-abner.chang@hpe.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Oct 28, 2019 at 09:59:15 +0800, Abner Chang wrote: > Add readme of RISC-V edk2 port. > > Signed-off-by: Abner Chang > > Cc: Leif Lindholm > Cc: Gilbert Chen > --- > RiscVEdk2Readme.md | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 64 insertions(+) > create mode 100644 RiscVEdk2Readme.md > > diff --git a/RiscVEdk2Readme.md b/RiscVEdk2Readme.md > new file mode 100644 > index 0000000..ebd7495 > --- /dev/null > +++ b/RiscVEdk2Readme.md > @@ -0,0 +1,64 @@ > +This branch is used to contribute RISC-V architecture to EDK2 > + > +The branch owner: > +Abner Chang < abner.chang@hpe.com > > +Gilbert Chen < gilbert.chen@hpe.com > > + > +## RISC-V EDK2 Port Introduction > +RISC-V is an open ISA which was designed to support research and education of > +computer architecture, but now it becomes a standard open Instruction Set > +Architecture for industry implementations. The RISC-V edk2 project is to create > +a new processor binding in UEFI spec and have the RISC-V edk2 implementation. > +The goal is to have RISC-V edk2 port as the firmware reference for RISC-V > +platforms. > + > +This branch (RISC-V-V2) on edk2-staging is RISC-V edk2 port with RISC-V > +OpenSbi (https://github.com/riscv/opensbi) library integrated. > +RiscVPkg provides the generic and common modules of RISC-V prcessor. > +Two edk2 RISC-V platforms are introduced in this branch, > +- SiFive Freedome U500 platform whcih is maintained in FreedomU500VC707Board > +under Platform/SiFive/U5SeriesPkg. > +- SiFive Freedome U540 HiFive Unleashed platform whcih is maintained in > +FreedomU540HiFiveUnleashedBoard under Platform/SiFive/U5SeriesPkg. > + > +Refer to Platform/SiFive/U5Series/Readme.md on edk2-platform repository. > + > +## RISC-V EDK2 Package > +``` > +RiscVPkg - RISC-V processor package. This package provides RISC-V > + processor related protocols/libraries accroding to UEFI > + specification and edk2 implementations. > +RiscVPlatformPkg - RISC-V platform package. This package provides RISC-V > + platform common modules, libraries, PCDs and definitoins. > +``` > +## Toolchain of RISC-V EDK2 port > +Due to not yet tracked down bugs, only the following toolchain is known to > +produce bootoable binaries. Was this issue also resolved by Mark's linker script patch? > +https://github.com/riscv/riscv-gnu-toolchain at commit ID 64879b24. > +The commit ID 64879b24 of riscv-gnu-toolchain repository is verified to build > +RISC-V edk2 platform and boot to EFI SHELL successfully. > +You have to clone the toolchain from above link and check out commit:64879b24 > +for building RISC-V edk2 port. > +The commit later than 64879b24 causes system hangs at the PEI phase to DXE phase > +transition. We are still figuring out the root cause. > + > +## EDK2 Build Target > +"RISCV64" ARCH is the RISC-V architecture which currently supported and verified. > +The verified RISC-V toolchain is https://github.com/riscv/riscv-gnu-toolchain > +@64879b24 as mentioned above, toolchain tag is "GCC5" which is declared in > +tools_def.txt. If this text is still needed: Which environment has this toolchain successfully been built in? / Leif > +Below is the edk2 build options for building RISC-V RV64 platform, > +``` > +build -a RISCV64 -p Platform/{Vendor}/{Platform}/{Platform}.dsc -t GCC5 > +``` > +For example, > +``` > +build -a RISCV64 -p Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc > +-t GCC5 > +``` > + > +Make sure RISC-V toolchain is built succesfully and the toolchain binaries are > +generated in somewhere you specified when building toolchain. > +'GCC5_RISCV64_PREFIX' is the cross compilation prefix to toolchain binraries. > +For example, set 'GCC5_RISCV64_PREFIX' to '~/RiscVToolchain/riscv64-unknown-elf-' > +before you build RISC-V edk2 port. > -- > 2.7.4 >