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[91.167.84.221]) by smtp.gmail.com with ESMTPSA id b3sm50478wmj.44.2019.11.25.10.07.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Nov 2019 10:07:22 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, Ard Biesheuvel Subject: [PATCH edk2-platforms 3/3] Platform/Overdrive: clean up stream ID descriptions in DT Date: Mon, 25 Nov 2019 19:07:10 +0100 Message-Id: <20191125180710.62600-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191125180710.62600-1-ard.biesheuvel@linaro.org> References: <20191125180710.62600-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Align the DT description of the SMMU topology and stream IDs with the actual routing of the SoC. As with the preceding IORT change, this is mostly a cleanup exercise, but it does actually fix an issue with the CCP crypto accelerator on B1 silicon. This time, let's retain the CCP description for B0 silicon, and just remove the 'iommus' DT property in this case. Since the SMMU is shared, it is no longer an error if the SMMU node is missing when attempting to delete it, so remove the warning that we issue in that case. Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/DeviceTree/OverdriveBoard.dts | 19 +++++++++++++------ Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c | 5 ++--- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/Platform/AMD/OverdriveBoard/DeviceTree/OverdriveBoard.dts b/Platform/AMD/OverdriveBoard/DeviceTree/OverdriveBoard.dts index 1ba0d403eaf0..ba31240f2e91 100644 --- a/Platform/AMD/OverdriveBoard/DeviceTree/OverdriveBoard.dts +++ b/Platform/AMD/OverdriveBoard/DeviceTree/OverdriveBoard.dts @@ -86,7 +86,7 @@ */ <0 332 4>, <0 332 4>; - #iommu-cells = <2>; + #iommu-cells = <1>; dma-coherent; }; @@ -99,7 +99,7 @@ */ <0 331 4>, <0 331 4>; - #iommu-cells = <2>; + #iommu-cells = <1>; dma-coherent; }; @@ -109,7 +109,9 @@ interrupts = <0x0 0x163 0x4>; clocks = <&sata_clk>; dma-coherent; - iommus = <&sata0_smmu 0x00 0x1f>; /* 0-31 */ + iommus = <&sata0_smmu 0x0e>, + <&sata0_smmu 0x0f>, + <&sata0_smmu 0x1e>; }; sata@e0d00000 { @@ -119,7 +121,9 @@ interrupts = <0x0 0x162 0x4>; clocks = <&sata_clk>; dma-coherent; - iommus = <&sata1_smmu 0x00 0x1f>; /* 0-31 */ + iommus = <&sata1_smmu 0x0e>, + <&sata1_smmu 0x0f>, + <&sata1_smmu 0x1e>; }; i2c@e1000000 { @@ -233,6 +237,9 @@ interrupts = <0x0 0x3 0x4>; dma-coherent; amd,zlib-support = <0x1>; + iommus = <&sata1_smmu 0x00>, + <&sata1_smmu 0x02>, + <&sata1_smmu 0x40>; }; pcie: pcie@f0000000 { @@ -409,7 +416,7 @@ phy-handle = <&xgmac0_phy>; phy-mode = "xgmii"; dma-coherent; - iommus = <&xgmac0_smmu 0x00 0x1f>; /* 0-31 */ + iommus = <&xgmac0_smmu 0x00 0x17>; /* 0-7, 16-23 */ }; xgmac@e0900000 { @@ -428,7 +435,7 @@ phy-handle = <&xgmac1_phy>; phy-mode = "xgmii"; dma-coherent; - iommus = <&xgmac1_smmu 0x00 0x1f>; /* 0-31 */ + iommus = <&xgmac1_smmu 0x00 0x17>; /* 0-7, 16-23 */ }; }; diff --git a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c index c84c1a81c3ec..5608946a5396 100644 --- a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c +++ b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c @@ -212,8 +212,6 @@ DisableSmmu ( Node = fdt_path_offset (Fdt, SmmuNodeName); if (Node <= 0) { - DEBUG ((DEBUG_WARN, "%a: Failed to find path %s: %a\n", - __FUNCTION__, SmmuNodeName, fdt_strerror (Node))); return; } @@ -253,8 +251,9 @@ SetSocIdStatus ( DisableSmmu (Fdt, "iommus", "/smb/smmu@e0200000", "/smb/sata@e0300000"); } - if (!PcdGetBool (PcdEnableSmmus) || !IsRevB1 || FixedPcdGet8 (PcdSata1PortCount) == 0) { + if (!PcdGetBool (PcdEnableSmmus) || !IsRevB1) { DisableSmmu (Fdt, "iommus", "/smb/smmu@e0c00000", "/smb/sata@e0d00000"); + DisableSmmu (Fdt, "iommus", "/smb/smmu@e0c00000", "/smb/ccp@e0100000"); } if (!FixedPcdGetBool (PcdXgbeEnable) || !PcdGetBool (PcdEnableSmmus)) { -- 2.20.1