From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66]) by mx.groups.io with SMTP id smtpd.web10.13799.1576256841389853500 for ; Fri, 13 Dec 2019 09:07:21 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@akeo-ie.20150623.gappssmtp.com header.s=20150623 header.b=IHLMObIx; spf=none, err=permanent DNS error (domain: akeo.ie, ip: 209.85.128.66, mailfrom: pete@akeo.ie) Received: by mail-wm1-f66.google.com with SMTP id p17so347022wmb.0 for ; Fri, 13 Dec 2019 09:07:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=akeo-ie.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=30ODoaKrZmodXwBDaGAklbxTxYoDRXC2xCM869iyxrM=; b=IHLMObIx3pSg9kPRIcVfGbJa1M/X0dDvKUpM2iN7sdQSIxQXgBagnLFfJtfvyemJ52 aUZ0zO79UyeixAdZJVgunPnGQCXDnkyDmGCjC3BrgWqwGJpkJGDATb4FO9qlRvgANR6J ga9lFLcC0ptxhGPUfnkwxzZ23t9r4KGBxWBUdBql9JEi29yC2rMvB+N1L0Dvamk6DiC+ 0qfj0Lr2l2Ls5FEnZxQlNOsFuSytSQPlKIWqre/dsfgQfkZDiDKg5d0b53twonOHsE90 KnqG/+dKYN11+LWsrbqgeF+RuMWNlXHgSfbYI66ujnCw3wjku9NWz0G9QjXhd3J8Gax/ KfQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=30ODoaKrZmodXwBDaGAklbxTxYoDRXC2xCM869iyxrM=; b=oF7/51id/pHIEUp4AkCb/uha1Ru5Hwjg7ZUV273gLe/6cUgHal2cR1S/a8AY4jbZIN x4sGIeNeoctTKrOcgg4VpmMYmsVlFVQuLOBB9LF3f4Jz4m53d6vIparuYG7vkdysFGlS 3d54aO2B6XTgkReKabTE6VoVhmtR/SYbB2BlNcgh+qPzK89x+ihGKWtwgIs1eG5/eb6c GnHMXgeBwBo0NhI1BKGxWp9f6iKSPeE7Y5EEwmfv1cUBgowMT5LqbptWdNb5gMxN/d+9 a30GGErXF+9ckFQVpZjchgy8i39w2u5swI1x19TckdHTfUpyMuIQIgMuG+7k+T71M5pd gK+A== X-Gm-Message-State: APjAAAWuFV42zUhRUeNaK920k7n1aKO3ZjuzT5XcjmAY6e2sjptRKQ2s UKhLSAaPsqFsYLT1T6rLGFPYRG5nh/xsJA== X-Google-Smtp-Source: APXvYqxb4pWvXceuEPyhoF4FyFB1dSZCoEM9/4IsL8ikIms65awxtBF1deJwezSQzM47SJw2hV0ymg== X-Received: by 2002:a1c:f316:: with SMTP id q22mr15055884wmq.103.1576256839646; Fri, 13 Dec 2019 09:07:19 -0800 (PST) Return-Path: Received: from localhost.localdomain ([84.203.45.230]) by smtp.gmail.com with ESMTPSA id o66sm7204203wmo.20.2019.12.13.09.07.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 13 Dec 2019 09:07:19 -0800 (PST) From: "Pete Batard" To: devel@edk2.groups.io Cc: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, philmd@redhat.com, lintonrjeremy@gmail.com Subject: [edk2-platforms][PATCH v2 1/4] Silicon/Bcm27xx: Add PCIe constants to Bcm2711.h Date: Fri, 13 Dec 2019 17:07:01 +0000 Message-Id: <20191213170704.8120-2-pete@akeo.ie> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20191213170704.8120-1-pete@akeo.ie> References: <20191213170704.8120-1-pete@akeo.ie> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Jeremy Linton This populates all of the define's we need for PCIe accesses. Four new PCDs are also introduced for the register and MMIO platform constants. Signed-off-by: Pete Batard --- Silicon/Broadcom/Bcm27xx/Bcm27xx.dec | 4 ++ Silicon/Broadcom/Bcm27xx/Include/IndustryStandard/Bcm2711.h | 71 ++++++++++++++++++++ 2 files changed, 75 insertions(+) diff --git a/Silicon/Broadcom/Bcm27xx/Bcm27xx.dec b/Silicon/Broadcom/Bcm27xx/Bcm27xx.dec index 815302f6d209..cd6f86670d9f 100644 --- a/Silicon/Broadcom/Bcm27xx/Bcm27xx.dec +++ b/Silicon/Broadcom/Bcm27xx/Bcm27xx.dec @@ -20,3 +20,7 @@ [Guids] [PcdsFixedAtBuild.common] gBcm27xxTokenSpaceGuid.PcdBcm27xxRegistersAddress|0x0|UINT32|0x00000001 + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase|0x0|UINT32|0x00000002 + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr|0x0|UINT64|0x00000003 + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen|0x0|UINT32|0x00000004 + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr|0x0|UINT64|0x00000005 diff --git a/Silicon/Broadcom/Bcm27xx/Include/IndustryStandard/Bcm2711.h b/Silicon/Broadcom/Bcm27xx/Include/IndustryStandard/Bcm2711.h index 356458024e84..a1609ce9b517 100644 --- a/Silicon/Broadcom/Bcm27xx/Include/IndustryStandard/Bcm2711.h +++ b/Silicon/Broadcom/Bcm27xx/Include/IndustryStandard/Bcm2711.h @@ -1,5 +1,6 @@ /** @file * + * Copyright (c) 2019, Jeremy Linton * Copyright (c) 2019, Pete Batard . * * SPDX-License-Identifier: BSD-2-Clause-Patent @@ -12,4 +13,74 @@ #define BCM2711_SOC_REGISTERS (FixedPcdGet64 (PcdBcm27xxRegistersAddress)) #define BCM2711_SOC_REGISTER_LENGTH 0x02000000 +/* Generic PCI addresses */ +#define PCIE_TOP_OF_MEM_WIN (FixedPcdGet64 (PcdBcm27xxPciBusMmioAdr)) +#define PCIE_CPU_MMIO_WINDOW (FixedPcdGet64 (PcdBcm27xxPciCpuMmioAdr)) +#define PCIE_BRIDGE_MMIO_LEN (FixedPcdGet32 (PcdBcm27xxPciBusMmioLen)) + +/* PCI root bridge control registers location */ +#define PCIE_REG_BASE (FixedPcdGet32 (PcdBcm27xxPciRegBase)) +#define PCIE_REG_LIMIT 0x9310 + +/* PCI root bridge control registers */ +#define BRCM_PCIE_CAP_REGS 0x00ac /* Offset to ecam like range for root port */ +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188 +#define BRCM_PCIE_CLASS 0x043c +#define PCIE_MISC_MISC_CTRL 0x4008 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010 +#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c +#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034 +#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 +#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c +#define PCIE_MISC_PCIE_STATUS 0x4068 +#define PCIE_MISC_REVISION 0x406c +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 + +#define PCIE_INTR2_CPU_STATUS 0x4300 +#define PCIE_INTR2_CPU_SET 0x4304 +#define PCIE_INTR2_CPU_CLR 0x4308 +#define PCIE_INTR2_CPU_MASK_STATUS 0x430c +#define PCIE_INTR2_CPU_MASK_SET 0x4310 +#define PCIE_INTR2_CPU_MASK_CLR 0x4314 + +#define PCIE_RGR1_SW_INIT_1 0x9210 +#define PCIE_EXT_CFG_INDEX 0x9000 +/* A small window pointing at the ECAM of the device selected by CFG_INDEX */ +#define PCIE_EXT_CFG_DATA 0x8000 + +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff + +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000 +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000 +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000 +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000 +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x7c00000 +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x1f +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f + +#define PCIE_RGR1_SW_INIT_1_INIT_MASK 0x2 +#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1 + +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 + +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2 + +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_MASK_BITS 0xc + + +#define PCIE_MISC_REVISION_MAJMIN_MASK 0xffff + +#define BURST_SIZE_128 0 +#define BURST_SIZE_256 1 +#define BURST_SIZE_512 2 + #endif /* BCM2711_H__ */ -- 2.21.0.windows.1