From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web12.3456.1576623145700261598 for ; Tue, 17 Dec 2019 14:52:26 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: michael.a.kubacki@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Dec 2019 14:52:25 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,327,1571727600"; d="scan'208";a="205634223" Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga007.jf.intel.com with ESMTP; 17 Dec 2019 14:52:25 -0800 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone Subject: [edk2-platforms][PATCH V3 1/1] WhiskeylakeOpenBoardPkg: Update PCDs to enable stack sharing Date: Tue, 17 Dec 2019 14:51:34 -0800 Message-Id: <20191217225134.40000-1-michael.a.kubacki@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 From: "Agyeman, Prince" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2409 Updated WhiskeylakeURvp PCDs to enable FSP/BL stack sharing. This fixes the boot failure seen with the latest Coffee Lake (CFL) FSP binary (v 7.0.68.41). Cc: Chasel Chiu Cc: Nate DeSimone Cc: Michael Kubacki Co-authored-by: Michael Kubacki Signed-off-by: Prince Agyeman Reviewed-by: Chasel Chiu --- Notes: 1. Michael Kubacki is taking over patch ownership since Prince is out of office. V3 Change: - Changed the value of PcdPeiTemporaryRamStackSize to 0x30000 to exceed the minimum stack size specified in the Coffee Lake FSP Integration Guide (160KB / 0x28000) with some padding. V2 Change: - The value of PcdPeiTemporaryRamStackSize was changed from 0x40000 to 0x28000 to exactly meet the minimum stack size specified in the Coffee Lake FSP Integration Guide. Note that the memory initialization code in the FSP previously exceeded the available stack size. Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc index 906f7b7ade..1ae51d9d5e 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc @@ -54,15 +54,14 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000 # - # FSP API mode does not share stack with the boot loader, - # so FSP needs more temporary memory for FSP heap + stack size. + # When sharing stack with boot loader, FSP only needs small temp ram for heap # - gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x26000 + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x10000 + # - # FSP API mode does not need to enlarge the boot loader stack size - # since the stacks are separate. + # Boot loader stack size has to be big enough to executing FSP # - gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000 + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x30000 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 -- 2.16.2.windows.1