From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by mx.groups.io with SMTP id smtpd.web11.8712.1576757696981169077 for ; Thu, 19 Dec 2019 04:14:58 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@akeo-ie.20150623.gappssmtp.com header.s=20150623 header.b=RvJ5dkrL; spf=none, err=permanent DNS error (domain: akeo.ie, ip: 209.85.128.65, mailfrom: pete@akeo.ie) Received: by mail-wm1-f65.google.com with SMTP id u2so5380073wmc.3 for ; Thu, 19 Dec 2019 04:14:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=akeo-ie.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pawb8ISAqmgEqite73Sns2/Uimpzw0Gz63I47zJfO9g=; b=RvJ5dkrLmh3JPNneOgSf5SEq2yiTpvl1LG9PXicusEIzH1LkJ0sdE1PphDBgL+XMkG yh2FMBzjEuitz8Y6zD8o6tus5ao8bLcvXJOwoLRTY8MUBKo/14l+pL/TxolFUD7l8McD AAxz3ezEb2olO2CJY2YBhGv5SXbooRqK08NiUW1Ohc+a8bSI/w02gl6NR34X0Vm0VBl8 XDH/X3Kliq5AB7eKoLudFXXDVi0sVgthCsPJRIIYX9kCgA8l7W2A99CdYXnwlc41EYxk rVjzzU2yyJhdh5p/i6Jj0sZiGzAQgLOOyawZ5hipDIDrUeFyPaSvRK7/b7Js5Oq6wWa1 0RYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pawb8ISAqmgEqite73Sns2/Uimpzw0Gz63I47zJfO9g=; b=Dej2Qjz6qFnfUT8Ux0uvB0mXYdMlYB8OvHHpTF6baLXV0yIedBElwjkQ76+uHG+fBj aOc9SZTqxB7kwVZ4a1TJP/yukMm42ziJt8saB5wFZMx/cg0v2VXxwg71CfDVBAkJwanz KVXNa8YzK4e8Tf2JiG8l1+Fw97bzJs+mMs1WLRNa9veuIZAn9Gkkhe8GwrgTxOolxMuT tOZvrdCqSTrTm3dTStsMiFFfRgz0vnczcBtwvW7lCg0AUabl2uLg7IalcmqgIp3dWtM/ frk9UGpehBynWKbqrJW4bh6fgPN4Gsb6PLQdjiYEnkBsqcvb9+DxxHte1aoHaGPWnzo2 7iIA== X-Gm-Message-State: APjAAAVF39oZlYDr9x0TEaLt1ODxKKBeyqB5MtAbhUqsTla/gIgX8LIF pD37drXPkkNUojv0nkWIbQBtBaybY10= X-Google-Smtp-Source: APXvYqzFb7esH4KRiCPNWMvAnumF72zyahz1o7VsDTubE0uoOiiUYLL0KNQJM0rhdDGDoxfb/3bh3Q== X-Received: by 2002:a05:600c:2301:: with SMTP id 1mr10160969wmo.147.1576757695294; Thu, 19 Dec 2019 04:14:55 -0800 (PST) Return-Path: Received: from localhost.localdomain ([84.203.77.210]) by smtp.gmail.com with ESMTPSA id u8sm5823147wmm.15.2019.12.19.04.14.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Dec 2019 04:14:54 -0800 (PST) From: "Pete Batard" To: devel@edk2.groups.io Cc: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, philmd@redhat.com Subject: [edk2-platforms][PATCH v2 6/7] Platform/RPi4: Add XHCI ACPI table Date: Thu, 19 Dec 2019 12:14:33 +0000 Message-Id: <20191219121434.2856-7-pete@akeo.ie> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20191219121434.2856-1-pete@akeo.ie> References: <20191219121434.2856-1-pete@akeo.ie> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Andrei Warkentin Since the RPi4 PCIe host bridge is not ECAM compliant, we can not expose it as a host bridge to the OS via ACPI. However, given the hardwired nature of this platform, we can expose the xHCI controller that is guaranteed to live at the base of the MMIO32 BAR window as a platform device directly. It should be noted that the xHCI table is not finalized at this stage, as Windows xHCI support is still a major question mark. Signed-off-by: Pete Batard --- Platform/RaspberryPi/RPi4/AcpiTables/AcpiTables.inf | 3 + Platform/RaspberryPi/RPi4/AcpiTables/Dsdt.asl | 1 + Platform/RaspberryPi/RPi4/AcpiTables/Xhci.asl | 137 ++++++++++++++++++++ 3 files changed, 141 insertions(+) diff --git a/Platform/RaspberryPi/RPi4/AcpiTables/AcpiTables.inf b/Platform/RaspberryPi/RPi4/AcpiTables/AcpiTables.inf index dcbf8d36082c..5ce4c0b52b32 100644 --- a/Platform/RaspberryPi/RPi4/AcpiTables/AcpiTables.inf +++ b/Platform/RaspberryPi/RPi4/AcpiTables/AcpiTables.inf @@ -39,6 +39,7 @@ [Packages] EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec + Silicon/Broadcom/Bcm27xx/Bcm27xx.dec Silicon/Broadcom/Bcm283x/Bcm283x.dec [FixedPcd] @@ -48,6 +49,8 @@ [FixedPcd] gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase gArmTokenSpaceGuid.PcdGicDistributorBase + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate gEmbeddedTokenSpaceGuid.PcdInterruptBaseAddress diff --git a/Platform/RaspberryPi/RPi4/AcpiTables/Dsdt.asl b/Platform/RaspberryPi/RPi4/AcpiTables/Dsdt.asl index 42e650a3ef29..b2f1d3439211 100644 --- a/Platform/RaspberryPi/RPi4/AcpiTables/Dsdt.asl +++ b/Platform/RaspberryPi/RPi4/AcpiTables/Dsdt.asl @@ -22,6 +22,7 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 5, "MSFT", "EDK2", 2) { include ("Sdhc.asl") include ("Pep.asl") + include ("Xhci.asl") Device (CPU0) { diff --git a/Platform/RaspberryPi/RPi4/AcpiTables/Xhci.asl b/Platform/RaspberryPi/RPi4/AcpiTables/Xhci.asl new file mode 100644 index 000000000000..e1fd501ab895 --- /dev/null +++ b/Platform/RaspberryPi/RPi4/AcpiTables/Xhci.asl @@ -0,0 +1,137 @@ +/** @file + * + * Copyright (c) 2019 Linaro, Limited. All rights reserved. + * Copyright (c) 2019 Andrei Warkentin + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include + +/* + * The following can be used to remove parenthesis from + * defined macros that the compiler complains about. + */ +#define ISOLATE_ARGS(...) __VA_ARGS__ +#define REMOVE_PARENTHESES(x) ISOLATE_ARGS x + +#define SANITIZED_PCIE_CPU_MMIO_WINDOW REMOVE_PARENTHESES(PCIE_CPU_MMIO_WINDOW) +#define SANITIZED_PCIE_REG_BASE REMOVE_PARENTHESES(PCIE_REG_BASE) + +/* + * According to UEFI boot log for the VLI device on Pi 4. + */ +#define XHCI_REG_LENGTH 0x1000 + +Device (SCB0) { + Name (_HID, "ACPI0004") + Name (_UID, 0x0) + Name (_CCA, 0x0) + + Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings + /* + * Container devices with _DMA must have _CRS, meaning SCB0 + * to provide all resources that XHC0 consumes (except + * interrupts). + */ + Name (RBUF, ResourceTemplate () { + QWordMemory (ResourceProducer, + , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MIN + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MAX + 0x0, + 0x1, // LEN + , + , + MMIO + ) + }) + CreateQwordField (RBUF, MMIO._MAX, MMBE) + CreateQwordField (RBUF, MMIO._LEN, MMLE) + Add (MMBE, XHCI_REG_LENGTH - 1, MMBE) + Add (MMLE, XHCI_REG_LENGTH - 1, MMLE) + Return (RBUF) + } + + Name (_DMA, ResourceTemplate() { + /* + * XHC0 is limited to DMA to first 3GB. Note this + * only applies to PCIe, not GENET or other devices + * next to the A72. + */ + QWordMemory (ResourceConsumer, + , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, + 0x0, // MIN + 0xbfffffff, // MAX + 0x0, // TRA + 0xc0000000, // LEN + , + , + ) + }) + + Device (XHC0) + { + Name (_HID, "11063483") // _HID: Hardware ID + Name (_CID, "PNP0D10") // _CID: Hardware ID + Name (_UID, 0x0) // _UID: Unique ID + Name (_CCA, 0x0) // _CCA: Cache Coherency Attribute + + Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings + Name (RBUF, ResourceTemplate () { + QWordMemory (ResourceConsumer, + , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MIN + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MAX + 0x0, + 0x1, // LEN + , + , + MMIO + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) { + 175 + } + }) + CreateQwordField (RBUF, MMIO._MAX, MMBE) + CreateQwordField (RBUF, MMIO._LEN, MMLE) + Add (MMBE, XHCI_REG_LENGTH - 1, MMBE) + Add (MMLE, XHCI_REG_LENGTH - 1, MMLE) + Return (RBUF) + } + + Method (_INI, 0, Serialized) { + OperationRegion (PCFG, SystemMemory, SANITIZED_PCIE_REG_BASE + PCIE_EXT_CFG_DATA, 0x1000) + Field (PCFG, AnyAcc, NoLock, Preserve) { + Offset (0), + VNID, 16, // Vendor ID + DVID, 16, // Device ID + CMND, 16, // Command register + STAT, 16, // Status register + } + + // Set command register to: + // 1) decode MMIO (set bit 1) + // 2) enable DMA (set bit 2) + // 3) enable interrupts (clear bit 10) + Debug = "xHCI enable" + Store (0x6, CMND) + } + } +} -- 2.21.0.windows.1