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From: "Liming Gao" <liming.gao@intel.com>
To: devel@edk2.groups.io
Cc: Jason Voelz <jason.voelz@intel.com>, Ray Ni <ray.ni@intel.com>
Subject: [Patch 2/2] UefiCpuPkg/CpuCommonFeaturesLib: SMXE bit of CR4 should set
Date: Mon, 23 Dec 2019 14:55:37 +0800	[thread overview]
Message-ID: <20191223065537.32468-3-liming.gao@intel.com> (raw)
In-Reply-To: <20191223065537.32468-1-liming.gao@intel.com>

From: Jason Voelz <jason.voelz@intel.com>

Add code to set SMXE in CR4 in the SmxInitialize flow when SMX is enabled.

Signed-off-by: Jason Voelz <jason.voelz@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
---
 UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
index 38d3f53f56..b4474d2fab 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
@@ -240,6 +240,15 @@ SmxInitialize (
     Status = RETURN_UNSUPPORTED;
   }
 
+  CPU_REGISTER_TABLE_WRITE_FIELD (
+    ProcessorNumber,
+    ControlRegister,
+    4,
+    IA32_CR4,
+    Bits.SMXE,
+    (State) ? 1 : 0
+  )
+
   CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD (
     ProcessorNumber,
     Msr,
-- 
2.13.0.windows.1


  parent reply	other threads:[~2019-12-23  6:56 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-23  6:55 [Patch 0/2] UefiCpuPkg/CpuCommonFeaturesLib: Set SMXE bit of CR4 when SMX is enabled Liming Gao
2019-12-23  6:55 ` [Patch 1/2] MdePkg BaseLib.h: Update IA32_CR4 strut to include all public fields Liming Gao
2020-01-08 14:12   ` Ni, Ray
2019-12-23  6:55 ` Liming Gao [this message]
2020-01-08 14:12   ` [Patch 2/2] UefiCpuPkg/CpuCommonFeaturesLib: SMXE bit of CR4 should set Ni, Ray

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