From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-1.mimecast.com (us-smtp-1.mimecast.com [205.139.110.120]) by mx.groups.io with SMTP id smtpd.web10.1937.1578042568363053689 for ; Fri, 03 Jan 2020 01:09:28 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=RdwyRlUD; spf=pass (domain: redhat.com, ip: 205.139.110.120, mailfrom: philmd@redhat.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1578042567; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FjgPkSnoy//FwSuDchN6LUXssKzbnnpIhiKhD4CjkOg=; b=RdwyRlUDBcayueXVAwz5ZQOK4RS582C8Vjlk8w/HIc74icN7x7MnoIFMyp0Wr2xRIthW+I B+8wkAAt2+tNm9sZH2gCmlEvro2iNXpYv/nCoAbDqSS133FQKBAyq3cTr49Ro2diSx0toq lVz+d1TcV9wjM4f0kcrG9oG0vP7St00= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-338-aJVxnAgqNuKX87BxIvNc6Q-1; Fri, 03 Jan 2020 04:09:26 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 058C310054E3; Fri, 3 Jan 2020 09:09:25 +0000 (UTC) Received: from x1w.redhat.com (ovpn-116-190.ams2.redhat.com [10.36.116.190]) by smtp.corp.redhat.com (Postfix) with ESMTPS id AA3167BA25; Fri, 3 Jan 2020 09:09:23 +0000 (UTC) From: =?UTF-8?B?UGhpbGlwcGUgTWF0aGlldS1EYXVkw6k=?= To: devel@edk2.groups.io Cc: Antoine Coeur , Michael D Kinney , Liming Gao , Philippe Mathieu-Daude Subject: [PATCH v2 28/78] MdePkg/Register: Fix various typos Date: Fri, 3 Jan 2020 10:07:22 +0100 Message-Id: <20200103090812.10592-29-philmd@redhat.com> In-Reply-To: <20200103090812.10592-1-philmd@redhat.com> References: <20200103090812.10592-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: aJVxnAgqNuKX87BxIvNc6Q-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Antoine Coeur Fix various typos in comments and documentation. Cc: Michael D Kinney Cc: Liming Gao Signed-off-by: Antoine Coeur Reviewed-by: Philippe Mathieu-Daude Reviewed-by: Michael D Kinney Signed-off-by: Philippe Mathieu-Daude --- MdePkg/Include/Register/Amd/Cpuid.h | 8 ++++---- MdePkg/Include/Register/Amd/Fam17Msr.h | 2 +- MdePkg/Include/Register/Amd/Msr.h | 2 +- MdePkg/Include/Register/Intel/Msr/GoldmontPlusMsr.h | 2 +- MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h | 2 +- MdePkg/Include/Register/Intel/StmResourceDescriptor.h | 2 +- 6 files changed, 9 insertions(+), 9 deletions(-) diff --git a/MdePkg/Include/Register/Amd/Cpuid.h b/MdePkg/Include/Register/= Amd/Cpuid.h index ad1ba4d016e0..8e91e84b767f 100644 --- a/MdePkg/Include/Register/Amd/Cpuid.h +++ b/MdePkg/Include/Register/Amd/Cpuid.h @@ -11,7 +11,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =20 @par Specification Reference: - AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.= 34 + AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.= 34 =20 **/ =20 @@ -364,7 +364,7 @@ typedef union { /// UINT32 Page1GB:1; /// - /// [Bit 27] RDTSCP intructions. + /// [Bit 27] RDTSCP instructions. /// UINT32 RDTSCP:1; /// @@ -513,9 +513,9 @@ typedef union { =20 @retval EAX Extended APIC ID described by the type CPUID_AMD_PROCESSOR_TOPOLOGY_EAX. - @retval EBX Core Indentifiers described by the type + @retval EBX Core Identifiers described by the type CPUID_AMD_PROCESSOR_TOPOLOGY_EBX. - @retval ECX Node Indentifiers described by the type + @retval ECX Node Identifiers described by the type CPUID_AMD_PROCESSOR_TOPOLOGY_ECX. @retval EDX Reserved. **/ diff --git a/MdePkg/Include/Register/Amd/Fam17Msr.h b/MdePkg/Include/Regist= er/Amd/Fam17Msr.h index 37b935dcdb30..6ef45a9b21d3 100644 --- a/MdePkg/Include/Register/Amd/Fam17Msr.h +++ b/MdePkg/Include/Register/Amd/Fam17Msr.h @@ -10,7 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =20 @par Specification Reference: - AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.= 34 + AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.= 34 =20 **/ =20 diff --git a/MdePkg/Include/Register/Amd/Msr.h b/MdePkg/Include/Register/Am= d/Msr.h index e74de7a1df48..084eb892cdd9 100644 --- a/MdePkg/Include/Register/Amd/Msr.h +++ b/MdePkg/Include/Register/Amd/Msr.h @@ -10,7 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =20 @par Specification Reference: - AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.= 34 + AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.= 34 =20 **/ =20 diff --git a/MdePkg/Include/Register/Intel/Msr/GoldmontPlusMsr.h b/MdePkg/I= nclude/Register/Intel/Msr/GoldmontPlusMsr.h index 2edc1363b7c4..c56d20df66a4 100644 --- a/MdePkg/Include/Register/Intel/Msr/GoldmontPlusMsr.h +++ b/MdePkg/Include/Register/Intel/Msr/GoldmontPlusMsr.h @@ -1,5 +1,5 @@ /** @file - MSR Defintions for Intel Atom processors based on the Goldmont Plus micr= oarchitecture. + MSR Definitions for Intel Atom processors based on the Goldmont Plus mic= roarchitecture. =20 Provides defines for Machine Specific Registers(MSR) indexes. Data struc= tures are provided for MSRs that contain one or more bit fields. If the MSR v= alue diff --git a/MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h b/MdePkg/Includ= e/Register/Intel/Msr/SkylakeMsr.h index 30f96f0e82fa..03cac77c19a6 100644 --- a/MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h +++ b/MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h @@ -1,5 +1,5 @@ /** @file - MSR Defintions for Intel processors based on the Skylake/Kabylake/Coffee= lake/Cannonlake microarchitecture. + MSR Definitions for Intel processors based on the Skylake/Kabylake/Coffe= elake/Cannonlake microarchitecture. =20 Provides defines for Machine Specific Registers(MSR) indexes. Data struc= tures are provided for MSRs that contain one or more bit fields. If the MSR v= alue diff --git a/MdePkg/Include/Register/Intel/StmResourceDescriptor.h b/MdePkg= /Include/Register/Intel/StmResourceDescriptor.h index da4c91d0f4b8..3e426701e83c 100644 --- a/MdePkg/Include/Register/Intel/StmResourceDescriptor.h +++ b/MdePkg/Include/Register/Intel/StmResourceDescriptor.h @@ -179,7 +179,7 @@ typedef struct { } STM_RSC_ALL_RESOURCES_DESC; =20 /** - STM Register Volation Descriptor + STM Register Violation Descriptor **/ typedef struct { STM_RSC_DESC_HEADER Hdr; --=20 2.21.0