From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66]) by mx.groups.io with SMTP id smtpd.web10.3576.1578388944916976593 for ; Tue, 07 Jan 2020 01:22:25 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=YTCXided; spf=pass (domain: linaro.org, ip: 209.85.128.66, mailfrom: ard.biesheuvel@linaro.org) Received: by mail-wm1-f66.google.com with SMTP id a5so18120793wmb.0 for ; Tue, 07 Jan 2020 01:22:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pJo1RVSUQv0HjVITAMxjscp0SP0JcLk4OX3/r5eRa6Q=; b=YTCXidedM/YDIvIq/F8OheVy+BzosYseYp/tmi2v4hrMwfyeEuUnEZeSs4e42NpPM7 BrDdl1wii749KVQw6ExikxgErxlDSFhSg2GN4AIqWwMA8dTZrGzdS/0s5uRPLs3UifY+ Pz32HFSgiWh4FshLh66vVmCF8M+cYMe/VqyEIPEMpQjP4PUfQJXpYfRhROGpskB59lCV xM0mMApFXRllzb3UGcbmhMyk8eROWAgMxg2hFszB9BCL15N9+z8DAvbyG3FLEvgO6L/E 5VvTvBMG5171ab4tS7IxL2DDSHGlgBxCZ9KxAGVjGqLVfp+QY87ueAgfpv7JQBROVnh4 T7+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pJo1RVSUQv0HjVITAMxjscp0SP0JcLk4OX3/r5eRa6Q=; b=EIdwEXQy0yK4u3nf7ET/QE0lVMq3Ueo2UxIW7Mtcze1qwsI2kp66kiAyJcgHF18Elk PbOG1T7a7CutFwSlfJwxDgdPdZprmdtW8eAys8TAneNM4LrEeJkK/oDUfbPDJs0Aigbw 2KtugUsUgQQaOEM9bXqs04fvlMZmwSOfqCuabacm2R0jlvuT7fRK0pFV06qdS7Y4CJt0 lIY0H7ZYpc0rm2LTlRqnemeDd5Scqr2X/Zk3sRaYyQl3ntUHVpAC4vAV3yxcBFCFweUw j/X4MZIF6Dzzlo4i12/wXSQMHUUAWInJVEpGIxFZjNdPcysMl+tt4tLQQDE0Z3o/TZsn eqkQ== X-Gm-Message-State: APjAAAVLD5+m+oTSMdcaNNPvwYP9y7exdnSlMG2csOTLuIJ4MDLKdkhj HVRrqq22LFWrE9SF/cookj+xuJvNEi7m4A== X-Google-Smtp-Source: APXvYqwySLWJb/EDjU5hfjXWEHtiMhSdjQRwYJp07Y1avZYKkbxBBvC65CHH5+wclaQSnqnek0UkSg== X-Received: by 2002:a05:600c:d6:: with SMTP id u22mr40853980wmm.77.1578388943186; Tue, 07 Jan 2020 01:22:23 -0800 (PST) Return-Path: Received: from localhost.localdomain ([2a01:cb1d:112:6f00:cc7e:d2b6:8b0c:cb36]) by smtp.gmail.com with ESMTPSA id h66sm27445476wme.41.2020.01.07.01.22.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jan 2020 01:22:22 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, Ard Biesheuvel Subject: [PATCH 2/2] ArmPlatformPkg/PrePeiCore: enable VFP at startup Date: Tue, 7 Jan 2020 10:22:15 +0100 Message-Id: <20200107092215.3271-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200107092215.3271-1-ard.biesheuvel@linaro.org> References: <20200107092215.3271-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit While the alternative PEI-less SEC implementation in PrePi already takes the EnableVFP PCD into account, the PrePeiCore code does not, and so we may end up triggering synchronous exception when code attempts to use FP or SIMD registers, which is permitted by the spec. So enable the VFP as early as feasible. Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf | 1 + ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf | 1 + ArmPlatformPkg/PrePeiCore/PrePeiCore.c | 5 +++++ 3 files changed, 7 insertions(+) diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf index f2ac45d171bc..104c7da53317 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf @@ -62,6 +62,7 @@ [FeaturePcd] [FixedPcd] gArmTokenSpaceGuid.PcdFvBaseAddress gArmTokenSpaceGuid.PcdFvSize + gArmTokenSpaceGuid.PcdVFPEnabled gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf index 84c319c3679b..ceb173d34f5d 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf @@ -60,6 +60,7 @@ [FeaturePcd] [FixedPcd] gArmTokenSpaceGuid.PcdFvBaseAddress gArmTokenSpaceGuid.PcdFvSize + gArmTokenSpaceGuid.PcdVFPEnabled gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c index 4911f67577a2..4f691d62cf3b 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c @@ -77,6 +77,11 @@ CEntryPoint ( ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0); ArmWriteVBar ((UINTN)PeiVectorTable); + // Enable Floating Point + if (FixedPcdGet32 (PcdVFPEnabled)) { + ArmEnableVFP (); + } + //Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on. // If not primary Jump to Secondary Main -- 2.20.1