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[2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id v83sm19754257wmg.16.2020.01.14.09.33.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jan 2020 09:33:47 -0800 (PST) Date: Tue, 14 Jan 2020 17:33:45 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: devel@edk2.groups.io Subject: Re: [PATCH 2/2] ArmPlatformPkg/PrePeiCore: enable VFP at startup Message-ID: <20200114173345.GC20629@bivouac.eciton.net> References: <20200107092215.3271-1-ard.biesheuvel@linaro.org> <20200107092215.3271-3-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20200107092215.3271-3-ard.biesheuvel@linaro.org> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Jan 07, 2020 at 10:22:15 +0100, Ard Biesheuvel wrote: > While the alternative PEI-less SEC implementation in PrePi already > takes the EnableVFP PCD into account, the PrePeiCore code does not, > and so we may end up triggering synchronous exception when code > attempts to use FP or SIMD registers, which is permitted by the spec. If you insert "on AARCH64" in an appropriate place in the above line: Reviewed-by: Leif Lindholm > > So enable the VFP as early as feasible. > > Signed-off-by: Ard Biesheuvel > --- > ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf | 1 + > ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf | 1 + > ArmPlatformPkg/PrePeiCore/PrePeiCore.c | 5 +++++ > 3 files changed, 7 insertions(+) > > diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf > index f2ac45d171bc..104c7da53317 100644 > --- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf > +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf > @@ -62,6 +62,7 @@ [FeaturePcd] > [FixedPcd] > gArmTokenSpaceGuid.PcdFvBaseAddress > gArmTokenSpaceGuid.PcdFvSize > + gArmTokenSpaceGuid.PcdVFPEnabled > > gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase > gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize > diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf > index 84c319c3679b..ceb173d34f5d 100644 > --- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf > +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf > @@ -60,6 +60,7 @@ [FeaturePcd] > [FixedPcd] > gArmTokenSpaceGuid.PcdFvBaseAddress > gArmTokenSpaceGuid.PcdFvSize > + gArmTokenSpaceGuid.PcdVFPEnabled > > gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase > gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize > diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c > index 4911f67577a2..4f691d62cf3b 100644 > --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c > +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c > @@ -77,6 +77,11 @@ CEntryPoint ( > ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0); > ArmWriteVBar ((UINTN)PeiVectorTable); > > + // Enable Floating Point > + if (FixedPcdGet32 (PcdVFPEnabled)) { > + ArmEnableVFP (); > + } > + > //Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on. > > // If not primary Jump to Secondary Main > -- > 2.20.1 >