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Received: from VI1PR0401MB2496.eurprd04.prod.outlook.com (10.168.65.10) by VI1PR0401MB2575.eurprd04.prod.outlook.com (10.168.62.136) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2707.21; Fri, 7 Feb 2020 07:24:21 +0000 Received: from VI1PR0401MB2496.eurprd04.prod.outlook.com ([fe80::8823:663d:c6ed:cbd6]) by VI1PR0401MB2496.eurprd04.prod.outlook.com ([fe80::8823:663d:c6ed:cbd6%12]) with mapi id 15.20.2686.036; Fri, 7 Feb 2020 07:24:21 +0000 From: "Pankaj Bansal" To: Leif Lindholm , Meenakshi Aggarwal , Michael D Kinney , Varun Sethi Cc: devel@edk2.groups.io, Pankaj Bansal Subject: [PATCH 17/19] Silicon/NXP: Add Chassis3V2 Date: Fri, 7 Feb 2020 18:13:26 +0530 Message-Id: <20200207124328.8723-18-pankaj.bansal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200207124328.8723-1-pankaj.bansal@nxp.com> References: <20200207124328.8723-1-pankaj.bansal@nxp.com> X-ClientProxiedBy: PN1PR01CA0103.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00::19) To VI1PR0401MB2496.eurprd04.prod.outlook.com (2603:10a6:800:56::10) Return-Path: pankaj.bansal@nxp.com MIME-Version: 1.0 Received: from uefi-workstation.ap.freescale.net (92.120.1.69) by PN1PR01CA0103.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2707.21 via Frontend Transport; Fri, 7 Feb 2020 07:24:19 +0000 X-Mailer: git-send-email 2.17.1 X-Originating-IP: [92.120.1.69] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: d5bbc3b6-a0b0-4649-acb3-08d7ab9ebff9 X-MS-TrafficTypeDiagnostic: VI1PR0401MB2575:|VI1PR0401MB2575: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; X-Forefront-PRVS: 0306EE2ED4 X-Forefront-Antispam-Report: SFV:NSPM;SFS:(10009020)(4636009)(346002)(366004)(376002)(39860400002)(136003)(396003)(189003)(199004)(6512007)(478600001)(86362001)(66556008)(66476007)(66946007)(52116002)(6636002)(5660300002)(19627235002)(6486002)(316002)(956004)(6666004)(26005)(8936002)(2616005)(16526019)(186003)(4326008)(44832011)(110136005)(36756003)(1076003)(8676002)(81156014)(81166006)(2906002)(6506007);DIR:OUT;SFP:1101;SCL:1;SRVR:VI1PR0401MB2575;H:VI1PR0401MB2496.eurprd04.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1; Received-SPF: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: iowGb0eYYYiVXKi/64E6qVehn8m3FXVqp885mNbj4syhSowwyc0gy7asp9GpVlYoVnoPb6Yl7/qVT/2RlvwcADTWnR9gjzqV9kwhgtmqZc2xsNxvfu1T8ZHWFDRhYhBjM+PAGL+BRSuZICrFlJc//S2t9hYdeB5vAyf7fNltryghR3h7/2R9a3pLgeSfKJesgzB1OJpEJQIPcRQPfVI4V45Zgcgs/Qn/5cw1O8sWvIPx15f2eEFpbbi/ZT3OOOWw9wwyueh7aDK9MHuACQTHUVyu+IO1SMX/2nYB2oug6Nw3ZddmyFYafgI6B8+I8iwr0EMS/xBugJPaM2i8edGNWiBvICEkPrlmuwnUdYQBltho/yWUBfH+8lxDzD0wAIBU+04zpddB+b9w4ga4hdJRXADMjtTjyVx1DhjjT8vT0CMAsdYV9WcCG0KS+9viYfhJ X-MS-Exchange-AntiSpam-MessageData: thPmiByeUdGqPwo5MW5O+rDfTOc0d7BxEZND53R4pcb1e1zsn0akSsXZxuHK35V2gk/m/DaiqNjT4aROHdxMJ7gWz2zifm7jNZocnU55BoQGgzo6p9CbjHD80tenKkXoPQPY/0Q6YNig3YTskDMV5g== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: d5bbc3b6-a0b0-4649-acb3-08d7ab9ebff9 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Feb 2020 07:24:21.3736 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: rIFvH6U5jx/M32vLygjIRIzmMZ3iqYKaXsnwqfor+62a9uLOQsO6purZM99EonePtbamFqPcS3oZFA0dfUH4dQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0401MB2575 Content-Type: text/plain Add Chassis3V2 Signed-off-by: Pankaj Bansal --- Silicon/NXP/Chassis3V2/Chassis3V2.dec | 23 +++ Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc | 10 + Silicon/NXP/Chassis3V2/Include/Chassis.h | 42 ++++ .../Library/ChassisLib/ChassisLib.c | 186 ++++++++++++++++++ .../Library/ChassisLib/ChassisLib.inf | 41 ++++ 5 files changed, 302 insertions(+) create mode 100644 Silicon/NXP/Chassis3V2/Chassis3V2.dec create mode 100644 Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc create mode 100644 Silicon/NXP/Chassis3V2/Include/Chassis.h create mode 100644 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c create mode 100644 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf diff --git a/Silicon/NXP/Chassis3V2/Chassis3V2.dec b/Silicon/NXP/Chassis3V2/Chassis3V2.dec new file mode 100644 index 0000000000..106b118188 --- /dev/null +++ b/Silicon/NXP/Chassis3V2/Chassis3V2.dec @@ -0,0 +1,23 @@ +#/** @file +# NXP Layerscape processor package. +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + DEC_SPECIFICATION = 1.27 + PACKAGE_VERSION = 0.1 + +################################################################################ +# +# Include Section - list of Include Paths that are provided by this package. +# Comments are used for Keywords and Module Types. +# +# +################################################################################ +[Includes.common] + Include # Root include for the package + diff --git a/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc b/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc new file mode 100644 index 0000000000..dabe2ae230 --- /dev/null +++ b/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc @@ -0,0 +1,10 @@ +# @file +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[LibraryClasses.common] + ChassisLib|Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf diff --git a/Silicon/NXP/Chassis3V2/Include/Chassis.h b/Silicon/NXP/Chassis3V2/Include/Chassis.h new file mode 100644 index 0000000000..2771f26fe3 --- /dev/null +++ b/Silicon/NXP/Chassis3V2/Include/Chassis.h @@ -0,0 +1,42 @@ +/** @file + + Copyright 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef __CHASSIS_H__ +#define __CHASSIS_H__ + +#define NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS 0x1E00000 + +#define TP_CLUSTER_ITYPE_IDX 0x3f +#define TP_CLUSTER_EOC BIT31 +#define TP_ITYPE_AVAILABLE BIT0 +#define TP_ITYPE_TYPE(x) (((x) & 0x06) >> 1) +#define TP_ITYPE_ARM 0x0 +#define TP_ITYPE_VERSION(x) (((x) & 0xe0) >> 5) + +#define TP_ITYPE_VERSION_A53 0x2 +#define TP_ITYPE_VERSION_A72 0x4 + +/** + The Device Configuration Unit provides general purpose configuration and status for the + device. These registers only support 32-bit accesses. +**/ +#pragma pack(1) +typedef struct { + UINT8 Reserved0[0x100 - 0x0]; + UINT32 RcwSr[32]; // Reset Control Word Status Register + UINT8 Reserved180[0x200 - 0x180]; + UINT32 ScratchRw[16]; /// Scratch Read / Write Register + UINT8 Reserved240[0x740-0x240]; + UINT32 TpItyp[65]; /// Topology Initiator Type Register + struct { + UINT32 Lower; + UINT32 Upper; + }TpCluster[8]; +} NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG; +#pragma pack() + +#endif diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c new file mode 100644 index 0000000000..99567bb76f --- /dev/null +++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c @@ -0,0 +1,186 @@ +/** @file + Chassis specific functions common to all SOCs based on a specific Chessis + + Copyright 2020 NXP + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +UINT32 +EFIAPI +DcfgRead32 ( + IN UINTN Address + ) +{ + if (FeaturePcdGet (PcdDcfgBigEndian)) { + return SwapMmioRead32 (Address); + } else { + return MmioRead32 (Address); + } +} + +UINT32 +EFIAPI +DcfgWrite32 ( + IN UINTN Address, + IN UINT32 Value + ) +{ + if (FeaturePcdGet (PcdDcfgBigEndian)) { + return SwapMmioWrite32 (Address, Value); + } else { + return MmioWrite32 (Address, Value); + } +} + +/** + Get the type of core in cluster + + The core can be of type ARM or PowerPC or Hardware Accelerator. + If the core is enabled and of type ARM EFI_SUCCESS is returned and a code for type of ARM core is returned + + @param[in] TpItypeIdx Index of Core to be searched in TpItyp in Device Config Registers. + @param[out] CoreType If the core is ARM core then the type of core i.e. A53/A72 etc. + These cores are identified based on their codes like TP_ITYPE_VERSION_A72 + + @return EFI_NOT_FOUND No enabled ARM core found + @return EFI_SUCCESS An enabled ARM core found +**/ +STATIC +EFI_STATUS +SocGetCoreType ( + IN UINT8 TpItypeIdx, + OUT UINT8 *CoreType + ) +{ + NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG *Dcfg; + UINT32 TpItype; + + Dcfg = (NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG *)NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS; + TpItype = MmioRead32 ((UINTN)&Dcfg->TpItyp[TpItypeIdx]); + if (TpItype & TP_ITYPE_AVAILABLE) { + if (TP_ITYPE_TYPE (TpItype) == TP_ITYPE_ARM) { + *CoreType = TP_ITYPE_VERSION (TpItype); + } else { + return EFI_NOT_FOUND; + } + } else { + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +/** + Return the number of cores present in SOC + + This function returns the number of cores present in SOC. + and also their position (cluster number and core number) in the form of ARM_CORE_INFO array + and NxpCoreTable array. + NxpCoreTable array can be used to find out the type of core. it's values are of type + TP_ITYPE_VERSION_*. + The number of cores present in SOC can vary depending on which flavour of SOC is being used. + This function doesn't allocte any memory and must be provided memory for array of ARM_CORE_INFO + and NxpCoreTable for maximum number of cores the SOC can have. + + @param[out] NxpCoreTable array of UINT8 for maximum number of cores the SOC can have. + @param[out] ArmCoreTable array of ARM_CORE_INFO for maximum number of cores the SOC can have. + @param[in] ArmCoreTableSize Size of ArmCoreTable + + @return Actual number of cores present in SOC. After calling this function only the returned + value number of entries in ArmCoreTable are valid entries. +**/ +UINTN +__attribute__((weak)) +SocGetMpCoreInfo ( + OUT UINT8 *NxpCoreTable, + OUT ARM_CORE_INFO *ArmCoreTable, + IN UINTN CoreTableSize + ) +{ + NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG *Dcfg; + UINT32 TpClusterLower; + UINT8 TpClusterParser; + UINT8 ClusterIndex; + UINT8 CoreIndex; + UINTN CoreCount; + UINT8 CoreType; + EFI_STATUS Status; + + Dcfg = (NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG *)NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS; + ClusterIndex = 0; + CoreCount = 0; + while (TRUE) { + TpClusterLower = MmioRead32 ((UINTN)&Dcfg->TpCluster[ClusterIndex].Lower); + for (CoreIndex = 0; CoreIndex < (sizeof (TpClusterLower) / sizeof (TpClusterParser)); CoreIndex++) { + TpClusterParser = (TpClusterLower >> (8 * CoreIndex)); + Status = SocGetCoreType (TpClusterParser & TP_CLUSTER_ITYPE_IDX, &CoreType); + if (Status != EFI_NOT_FOUND) { + ArmCoreTable[CoreCount].ClusterId = ClusterIndex; + ArmCoreTable[CoreCount].CoreId = CoreIndex; + ArmCoreTable[CoreCount].MailboxSetAddress = 0; + ArmCoreTable[CoreCount].MailboxGetAddress = 0; + ArmCoreTable[CoreCount].MailboxClearAddress = 0; + ArmCoreTable[CoreCount].MailboxClearValue = ~0; + + NxpCoreTable[CoreCount] = CoreType; + CoreCount++; + if (CoreCount == CoreTableSize) { + break; + } + } + } + if (TpClusterLower & TP_CLUSTER_EOC) { + break; + } + if (CoreCount == CoreTableSize) { + break; + } + ClusterIndex++; + } + + return CoreCount; +} + +/** + Function to initialize Chassis Specific functions + **/ +VOID +ChassisInit ( + VOID + ) +{ + UINT64 BaudRate; + UINT32 ReceiveFifoDepth; + EFI_PARITY_TYPE Parity; + UINT8 DataBits; + EFI_STOP_BITS_TYPE StopBits; + UINT32 Timeout; + + BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate); + ReceiveFifoDepth = FixedPcdGet16 (PcdUartDefaultReceiveFifoDepth); + Timeout = 0; + Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity); + DataBits = FixedPcdGet8 (PcdUartDefaultDataBits); + StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits); + + // + // Early init serial Port to get board information. + // + SerialPortSetAttributes ( + &BaudRate, + &ReceiveFifoDepth, + &Timeout, + &Parity, + &DataBits, + &StopBits + ); +} diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf new file mode 100644 index 0000000000..302296bf65 --- /dev/null +++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf @@ -0,0 +1,41 @@ +#/** @file +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = Chassis3V2Lib + FILE_GUID = fae0d077-5fc2-494f-b8e1-c51a3023ee3e + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ChassisLib + +[Packages] + MdePkg/MdePkg.dec + ArmPkg/ArmPkg.dec + Silicon/NXP/NxpQoriqLs.dec + Silicon/NXP/Chassis3V2/Chassis3V2.dec + +[LibraryClasses] + IoLib + IoAccessLib + PcdLib + SerialPortLib + +[Sources.common] + ChassisLib.c + +[FeaturePcd] + gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian + +[FixedPcd] + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth + -- 2.17.1