* [PATCH 00/19] ADD LX2160ARDB Platform Support
@ 2020-02-07 12:43 Pankaj Bansal
2020-02-07 12:43 ` [PATCH 01/19] Silicon/NXP: Add I2c lib Pankaj Bansal
` (18 more replies)
0 siblings, 19 replies; 49+ messages in thread
From: Pankaj Bansal @ 2020-02-07 12:43 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, Varun Sethi
Cc: devel, Pankaj Bansal
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=y, Size: 13814 bytes --]
This patch series aims to add support of LX2160ARDB Platform, which is
based on LX2160A Soc in edk2-platforms. Also We have modified the directory
structure of NXP code and added PEI Phase support also for NXP platforms.
This series can be divied into 4 phases:
1. Cleaning up the old code
This phase aims to remove the information and compoenents which are not
needed for boot process. we plan to reintroduce only required components
one by one later on, once PEI phase changes have been accepted.
This phase has 10 patches:
Silicon/NXP: Add I2c lib
Silicon/NXP: changes to use I2clib in i2cdxe
NXP/LS1043aRdb: Move Soc specific components to soc files
Silicon/NXP: Remove DuartLib and use BaseSerialPortLib16550
NXP/BaseSerialPortLib16550: remove SerialPortInitalize functionality
Silicon/NXP: remove print information from Soc lib
Silicon/NXP: remove not needed components
Silicon/NXP: Remove unnecessary PCDs
Silicon/NXP: Move dsc file
Platform/NXP: rename the ArmPlatformLib as per ArmPlatformPkg
2. Adding components necessary for PEI Phase
This phase adds the necessary components required for PEI Phase.
Also we change the directory structure to bring more consistency.
This phase has 4 patches:
Silicon/NXP: Add Chassis Lib for Chassis2
Silicon/NXP/LS1043A: Add SocLib
Silicon/NXP: Move RAM retrieval from SocLib
Silicon/NXP/LS1043A: Replce SocLib
3. Add PEI Phase for LS1043ARDB
This phase adds PEI phase support to LS1043ARDB platform.
This phase has 1 patch:
Platform/NXP/LS1043ARDB: introduce PEI Phase
4. Add LX2160ARDB platform
This phase adds necessary components for LX2160ARDB platform.
The code structure for LS1043A has been mimiced for LX2160A.
This phase has 4 patches:
Silicon/NXP: Add Pl011 Serial port lib
Silicon/NXP: Add Chassis3V2
Silicon/NXP: Add LX2160A SocLib
Platform/NXP: Add LX2160ARDBPKG
After all these patches, this is the directory tree for Silicon/NXP:
Silicon/NXP/
├── Chassis2
│ ├── Include
│ ├── Library
│ │ └── ChassisLib
│ └── LS1043A
│ ├── Include
│ └── Library
│ └── SocLib
├── Chassis3V2
│ ├── Include
│ ├── Library
│ │ └── ChassisLib
│ └── LX2160A
│ ├── Include
│ └── Library
│ └── SocLib
├── Drivers
│ └── I2cDxe
├── Include
│ ├── Library
│ └── Ppi
└── Library
├── BaseSerialPortLib16550
├── I2cLib
├── IoAccessLib
├── MemoryInitPeiLib
├── Pcf8563RealTimeClockLib
├── PL011SerialPortLib
└── PlatformPeiLib
Pankaj Bansal (19):
Silicon/NXP: Add I2c lib
Silicon/NXP: changes to use I2clib in i2cdxe
NXP/LS1043aRdb: Move Soc specific components to soc files
Silicon/NXP: Remove DuartLib and use BaseSerialPortLib16550
NXP/BaseSerialPortLib16550: remove SerialPortInitalize functionality
Silicon/NXP: remove print information from Soc lib
Silicon/NXP: remove not needed components
Silicon/NXP: Remove unnecessary PCDs
Silicon/NXP: Move dsc file
Platform/NXP: rename the ArmPlatformLib as per ArmPlatformPkg
Silicon/NXP: Add Chassis Lib for Chassis2
Silicon/NXP/LS1043A: Add SocLib
Silicon/NXP: Move RAM retrieval from SocLib
Silicon/NXP/LS1043A: Replce SocLib
Platform/NXP/LS1043ARDB: introduce PEI Phase
Silicon/NXP: Add Pl011 Serial port lib
Silicon/NXP: Add Chassis3V2
Silicon/NXP: Add LX2160A SocLib
Platform/NXP: Add LX2160ARDBPKG
Platform/NXP/FVRules.fdf.inc | 60 +-
Platform/NXP/Include/Qixis.h | 40 +
.../Drivers/PlatformDxe/PlatformDxe.c | 15 +-
.../Drivers/PlatformDxe/PlatformDxe.inf | 9 +-
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 28 +-
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 19 +-
.../AArch64/ArmPlatformHelper.S | 46 ++
.../Library/ArmPlatformLib/ArmPlatformLib.c | 141 ++++
.../Library/ArmPlatformLib/ArmPlatformLib.inf | 43 +
.../ArmPlatformLib/ArmPlatformLibMem.c | 136 ++++
.../Library/PlatformLib/ArmPlatformLib.c | 98 ---
.../Library/PlatformLib/ArmPlatformLib.inf | 55 --
.../Library/PlatformLib/NxpQoriqLsHelper.S | 31 -
.../Library/PlatformLib/NxpQoriqLsMem.c | 144 ----
Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc | 91 +++
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec | 23 +
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc | 54 ++
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf | 172 ++++
.../AArch64/ArmPlatformHelper.S | 46 ++
.../Library/ArmPlatformLib/ArmPlatformLib.c | 168 ++++
.../Library/ArmPlatformLib/ArmPlatformLib.inf | 45 ++
.../ArmPlatformLib/ArmPlatformLibInternal.h | 26 +
.../ArmPlatformLib/ArmPlatformLibMem.c | 80 ++
Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc | 90 +++
Platform/NXP/NxpQoriqLsPlatform.dec | 23 +
.../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c | 23 +-
Silicon/NXP/Chassis2/Chassis2.dec | 23 +
Silicon/NXP/Chassis2/Chassis2.dsc.inc | 10 +
Silicon/NXP/Chassis2/Include/Chassis.h | 54 ++
Silicon/NXP/Chassis2/LS1043A/Include/Soc.h | 56 ++
Silicon/NXP/Chassis2/LS1043A/LS1043A.dec | 23 +
Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc | 31 +
.../Chassis2/LS1043A/Library/SocLib/SocLib.c | 101 +++
.../LS1043A/Library/SocLib/SocLib.inf | 40 +
.../Chassis2/Library/ChassisLib/ChassisLib.c | 211 +++++
.../Library/ChassisLib/ChassisLib.inf | 41 +
Silicon/NXP/Chassis3V2/Chassis3V2.dec | 23 +
Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc | 10 +
Silicon/NXP/Chassis3V2/Include/Chassis.h | 42 +
Silicon/NXP/Chassis3V2/LX2160A/Include/Soc.h | 39 +
Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec | 23 +
.../NXP/Chassis3V2/LX2160A/LX2160A.dsc.inc | 34 +
.../LX2160A/Library/SocLib/SocLib.c | 79 ++
.../LX2160A/Library/SocLib/SocLib.inf | 31 +
.../Library/ChassisLib/ChassisLib.c | 186 +++++
.../Library/ChassisLib/ChassisLib.inf | 41 +
Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 526 +------------
Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 51 +-
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 9 +-
Silicon/NXP/Include/Chassis2/LsSerDes.h | 62 --
Silicon/NXP/Include/Chassis2/NxpSoc.h | 361 ---------
Silicon/NXP/Include/DramInfo.h | 38 -
Silicon/NXP/Include/Library/ChassisLib.h | 39 +
Silicon/NXP/Include/Library/I2cLib.h | 99 +++
Silicon/NXP/Include/Library/SocLib.h | 80 ++
Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h | 47 ++
Silicon/NXP/LS1043A/Include/SocSerDes.h | 51 --
Silicon/NXP/LS1043A/LS1043A.dec | 16 -
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 61 --
.../BaseSerialPortLib16550.c | 738 ++++++++++++++++++
.../BaseSerialPortLib16550.inf | 40 +
.../BaseSerialPortLib16550.uni | 17 +
Silicon/NXP/Library/DUartPortLib/DUart.h | 122 ---
.../NXP/Library/DUartPortLib/DUartPortLib.c | 364 ---------
.../NXP/Library/DUartPortLib/DUartPortLib.inf | 34 -
Silicon/NXP/Library/I2cLib/I2cLib.c | 532 +++++++++++++
Silicon/NXP/Library/I2cLib/I2cLib.inf | 30 +
Silicon/NXP/Library/I2cLib/I2cLibInternal.h | 95 +++
.../Library/MemoryInitPei/MemoryInitPeiLib.c | 140 ----
.../MemoryInitPeiLib/MemoryInitPeiLib.c | 311 ++++++++
.../MemoryInitPeiLib/MemoryInitPeiLib.h | 23 +
.../MemoryInitPeiLib.inf | 26 +-
.../PL011SerialPortLib/PL011SerialPortLib.c | 229 ++++++
.../PL011SerialPortLib/PL011SerialPortLib.inf | 42 +
.../Library/PlatformPeiLib/PlatformPeiLib.c | 30 +
.../Library/PlatformPeiLib/PlatformPeiLib.inf | 50 ++
Silicon/NXP/Library/SocLib/Chassis.c | 495 ------------
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 162 ----
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 45 --
Silicon/NXP/Library/SocLib/NxpChassis.h | 136 ----
Silicon/NXP/Library/SocLib/SerDes.c | 268 -------
Silicon/NXP/NxpQoriqLs.dec | 101 +--
{Platform => Silicon}/NXP/NxpQoriqLs.dsc.inc | 74 +-
83 files changed, 4916 insertions(+), 3432 deletions(-)
create mode 100644 Platform/NXP/Include/Qixis.h
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
delete mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
delete mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
delete mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
delete mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
create mode 100644 Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
create mode 100644 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec
create mode 100644 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc
create mode 100644 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
create mode 100644 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
create mode 100644 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
create mode 100644 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
create mode 100644 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibInternal.h
create mode 100644 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
create mode 100644 Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc
create mode 100644 Platform/NXP/NxpQoriqLsPlatform.dec
create mode 100644 Silicon/NXP/Chassis2/Chassis2.dec
create mode 100644 Silicon/NXP/Chassis2/Chassis2.dsc.inc
create mode 100644 Silicon/NXP/Chassis2/Include/Chassis.h
create mode 100644 Silicon/NXP/Chassis2/LS1043A/Include/Soc.h
create mode 100644 Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
create mode 100644 Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
create mode 100644 Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
create mode 100644 Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
create mode 100644 Silicon/NXP/Chassis3V2/Chassis3V2.dec
create mode 100644 Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
create mode 100644 Silicon/NXP/Chassis3V2/Include/Chassis.h
create mode 100644 Silicon/NXP/Chassis3V2/LX2160A/Include/Soc.h
create mode 100644 Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec
create mode 100644 Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dsc.inc
create mode 100644 Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.c
create mode 100644 Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.inf
create mode 100644 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
create mode 100644 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
delete mode 100644 Silicon/NXP/Include/Chassis2/LsSerDes.h
delete mode 100644 Silicon/NXP/Include/Chassis2/NxpSoc.h
delete mode 100644 Silicon/NXP/Include/DramInfo.h
create mode 100644 Silicon/NXP/Include/Library/ChassisLib.h
create mode 100644 Silicon/NXP/Include/Library/I2cLib.h
create mode 100644 Silicon/NXP/Include/Library/SocLib.h
create mode 100644 Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h
delete mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h
delete mode 100644 Silicon/NXP/LS1043A/LS1043A.dec
delete mode 100644 Silicon/NXP/LS1043A/LS1043A.dsc.inc
create mode 100644 Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
create mode 100644 Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
create mode 100644 Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.uni
delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUart.h
delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
create mode 100644 Silicon/NXP/Library/I2cLib/I2cLib.c
create mode 100644 Silicon/NXP/Library/I2cLib/I2cLib.inf
create mode 100644 Silicon/NXP/Library/I2cLib/I2cLibInternal.h
delete mode 100644 Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
create mode 100644 Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
create mode 100644 Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.h
rename Silicon/NXP/Library/{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.inf (63%)
create mode 100644 Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.c
create mode 100644 Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.inf
create mode 100644 Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c
create mode 100644 Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
delete mode 100644 Silicon/NXP/Library/SocLib/Chassis.c
delete mode 100644 Silicon/NXP/Library/SocLib/Chassis2/Soc.c
delete mode 100644 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
delete mode 100644 Silicon/NXP/Library/SocLib/NxpChassis.h
delete mode 100644 Silicon/NXP/Library/SocLib/SerDes.c
rename {Platform => Silicon}/NXP/NxpQoriqLs.dsc.inc (84%)
--
2.17.1
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 01/19] Silicon/NXP: Add I2c lib
2020-02-07 12:43 [PATCH 00/19] ADD LX2160ARDB Platform Support Pankaj Bansal
@ 2020-02-07 12:43 ` Pankaj Bansal
2020-02-08 17:13 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 02/19] Silicon/NXP: changes to use I2clib in i2cdxe Pankaj Bansal
` (17 subsequent siblings)
18 siblings, 1 reply; 49+ messages in thread
From: Pankaj Bansal @ 2020-02-07 12:43 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, Varun Sethi
Cc: devel, Pankaj Bansal
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=y, Size: 28738 bytes --]
I2c lib is going to be used in PrePeiCore sec module to get the
System clock information from devices connected to i2c (like fpga
or clcok generator)
since we don't have support of DXE modules this early in boot stage,
move the i2c controller functionality in library.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Platform/NXP/NxpQoriqLs.dsc.inc | 4 +-
Silicon/NXP/Include/Library/I2cLib.h | 99 ++++
Silicon/NXP/Library/I2cLib/I2cLib.c | 532 ++++++++++++++++++++
Silicon/NXP/Library/I2cLib/I2cLib.inf | 30 ++
Silicon/NXP/Library/I2cLib/I2cLibInternal.h | 95 ++++
Silicon/NXP/NxpQoriqLs.dec | 10 +-
6 files changed, 768 insertions(+), 2 deletions(-)
create mode 100644 Silicon/NXP/Include/Library/I2cLib.h
create mode 100644 Silicon/NXP/Library/I2cLib/I2cLib.c
create mode 100644 Silicon/NXP/Library/I2cLib/I2cLib.inf
create mode 100644 Silicon/NXP/Library/I2cLib/I2cLibInternal.h
diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc
index fa5f30dd39..b28e0615f7 100644
--- a/Platform/NXP/NxpQoriqLs.dsc.inc
+++ b/Platform/NXP/NxpQoriqLs.dsc.inc
@@ -1,6 +1,6 @@
# @file
#
-# Copyright 2017-2019 NXP.
+# Copyright 2017-2020 NXP.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -94,6 +94,8 @@
NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+ I2cLib|Silicon/NXP/Library/I2cLib/I2cLib.inf
+
[LibraryClasses.common.SEC]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
diff --git a/Silicon/NXP/Include/Library/I2cLib.h b/Silicon/NXP/Include/Library/I2cLib.h
new file mode 100644
index 0000000000..3594e3fc2f
--- /dev/null
+++ b/Silicon/NXP/Include/Library/I2cLib.h
@@ -0,0 +1,99 @@
+/** @file
+ I2c Lib to control I2c controller.
+
+ Copyright 2020 NXP
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __I2C_LIB_H__
+#define __I2C_LIB_H__
+
+#include <Pi/PiI2c.h>
+
+/**
+ Early init I2C for reading the sysclk from I2c slave device.
+ I2c bus clock is determined from the clock input to I2c controller.
+ The clock input to I2c controller is derived from the sysclk.
+ sysclk is determined by clock generator, which is controller by i2c.
+
+ So, it's a chicken-egg problem to read the sysclk from clock generator.
+ To break this cycle (i.e. to read the sysclk), we setup the i2c bus clock to
+ lowest value, in the hope that it won't be out of clock generator's supported
+ i2c clock frequency. Once we have the correct sysclk, we can setup the correct
+ i2c bus clock.
+
+ @param[in] Base Base Address of I2c controller's registers
+
+ @return EFI_SUCCESS successfuly setup the i2c bus for reading sysclk
+ @return DEVICE_ERROR There was an error setting up the I2c bus
+**/
+EFI_STATUS
+I2cEarlyInitialize (
+ IN UINTN Base
+ );
+
+/**
+ Configure I2c bus to opearte at a given speed
+
+ @param[in] Base Base Address of I2c controller's registers
+ @param[in] I2cBusClock Input clock to I2c controller
+ @param[in] Speed speed to be configured for I2c bus
+**/
+EFI_STATUS
+I2cInitialize (
+ IN UINTN Base,
+ IN UINT64 I2cBusClock,
+ IN UINT64 Speed
+ );
+
+/**
+ Transfer data to/from I2c slave device
+
+ @param[in] Base Base Address of I2c controller's registers
+ @param[in] SlaveAddress Slave Address from which data is to be read
+ @param[in] RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET structure
+ describing the I2C transaction
+
+ @return EFI_SUCCESS successfuly setup the i2c bus for reading sysclk
+ @return EFI_DEVICE_ERROR There was an error while transferring data through I2c bus
+ @return EFI_NO_RESPONSE There was no Ack from i2c device
+ @return EFI_TIMEOUT I2c Bus is busy
+ @return EFI_NOT_READY I2c Bus Arbitration lost
+**/
+EFI_STATUS
+I2cBusXfer (
+ IN UINTN Base,
+ IN UINT32 SlaveAddress,
+ IN EFI_I2C_REQUEST_PACKET *RequestPacket
+ );
+
+/**
+ Read a register from I2c slave device. This API is wrapper around I2cBusXfer
+
+ @param[in] Base Base Address of I2c controller's registers
+ @param[in] SlaveAddress Slave Address from which register value is to be read
+ @param[in] RegAddress Register Address in Slave's memory map
+ @param[in] RegAddressWidthInBytes Number of bytes in RegAddress to send to I2c Slave
+ for simple reads without any register, make this value = 0
+ (RegAddress is don't care in that case)
+ @param[out] RegValue Value to be read from I2c slave's regiser
+ @param[in] RegValueNumBytes Number of bytes to read from I2c slave register
+
+ @return EFI_SUCCESS successfuly setup the i2c bus for reading sysclk
+ @return EFI_DEVICE_ERROR There was an error while transferring data through I2c bus
+ @return EFI_NO_RESPONSE There was no Ack from i2c device
+ @return EFI_TIMEOUT I2c Bus is busy
+ @return EFI_NOT_READY I2c Bus Arbitration lost
+**/
+EFI_STATUS
+I2cBusReadReg (
+ IN UINTN Base,
+ IN UINT32 SlaveAddress,
+ IN UINT64 RegAddress,
+ IN UINT8 RegAddressWidthInBytes,
+ OUT UINT8 *RegValue,
+ IN UINT8 RegValueNumBytes
+ );
+
+#endif // __I2C_LIB_H__
diff --git a/Silicon/NXP/Library/I2cLib/I2cLib.c b/Silicon/NXP/Library/I2cLib/I2cLib.c
new file mode 100644
index 0000000000..f33c09d6d1
--- /dev/null
+++ b/Silicon/NXP/Library/I2cLib/I2cLib.c
@@ -0,0 +1,532 @@
+/** @file
+ I2c Lib to control I2c controller.
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include <Uefi.h>
+#include <Library/I2cLib.h>
+#include <Library/TimerLib.h>
+#include <Library/IoLib.h>
+#include <Library/BaseMemoryLib.h>
+
+#include "I2cLibInternal.h"
+
+/*
+ * I2C divider and hold values when glitch filter is enabled
+ * taken from table 21-14, LX2160ARM_RevE 01/2020
+ *
+ * In case of duplicate SCL Divider value, the IBC value
+ * with high MUL value has been selected.
+ * A higher MUL value results in a lower sampling rate of the I2C signals.
+ * This gives the I2C module greater immunity against glitches in the I2C signals.
+ */
+STATIC I2C_CLOCK_DIVIDER_PAIR I2cClockDividerGlitchEnabled[] = {
+ { 34, 0x0 }, { 36, 0x1 }, { 38, 0x2 }, { 40, 0x3 },
+ { 42, 0x4 }, { 44, 0x8 }, { 48, 0x9 }, { 52, 0xA },
+ { 54, 0x7 }, { 56, 0xB }, { 60, 0xC }, { 64, 0x10 },
+ { 68, 0x40 }, { 72, 0x41 }, { 76, 0x42 }, { 80, 0x43 },
+ { 84, 0x44 }, { 88, 0x48 }, { 96, 0x49 }, { 104, 0x4A },
+ { 108, 0x47 }, { 112, 0x4B }, { 120, 0x4C }, { 128, 0x50 },
+ { 136, 0x80 }, { 144, 0x81 }, { 152, 0x82 }, { 160, 0x83 },
+ { 168, 0x84 }, { 176, 0x88 }, { 192, 0x89 }, { 208, 0x8A },
+ { 216, 0x87 }, { 224, 0x8B }, { 240, 0x8C }, { 256, 0x90 },
+ { 288, 0x91 }, { 320, 0x92 }, { 336, 0x8F }, { 352, 0x93 },
+ { 384, 0x98 }, { 416, 0x95 }, { 448, 0x99 }, { 480, 0x96 },
+ { 512, 0x9A }, { 576, 0x9B }, { 640, 0xA0 }, { 704, 0x9D },
+ { 768, 0xA1 }, { 832, 0x9E }, { 896, 0xA2 }, { 960, 0x67 },
+ { 1024, 0xA3 }, { 1152, 0xA4 }, { 1280, 0xA8 }, { 1536, 0xA9 },
+ { 1792, 0xAA }, { 1920, 0xA7 }, { 2048, 0xAB }, { 2304, 0xAC },
+ { 2560, 0xB0 }, { 3072, 0xB1 }, { 3584, 0xB2 }, { 3840, 0xAF },
+ { 4096, 0xB3 }, { 4608, 0xB4 }, { 5120, 0xB8 }, { 6144, 0xB9 },
+ { 7168, 0xBA }, { 7680, 0xB7 }, { 8192, 0xBB }, { 9216, 0xBC },
+ { 10240, 0xBD }, { 12288, 0xBE }, { 15360, 0xBF }
+};
+
+/*
+ * I2C divider and hold values when glitch filter is disabled
+ * taken from table 21-13, LX2160ARM_RevE 01/2020
+ *
+ * In case of duplicate SCL Divider value, the IBC value
+ * with high MUL value has been selected.
+ * A higher MUL value results in a lower sampling rate of the I2C signals.
+ * This gives the I2C module greater immunity against glitches in the I2C signals.
+ */
+STATIC I2C_CLOCK_DIVIDER_PAIR I2cClockDividerGlitchDisabled[] = {
+ { 20, 0x0 },{ 22, 0x1 },{ 24, 0x2 },{ 26, 0x3 },
+ { 28, 0x8 },{ 30, 0x5 },{ 32, 0x9 },{ 34, 0x6 },
+ { 36, 0x0A },{ 40, 0x40 },{ 44, 0x41 },{ 48, 0x42 },
+ { 52, 0x43 },{ 56, 0x48 },{ 60, 0x45 },{ 64, 0x49 },
+ { 68, 0x46 },{ 72, 0x4A },{ 80, 0x80 },{ 88, 0x81 },
+ { 96, 0x82 },{ 104, 0x83 },{ 112, 0x88 },{ 120, 0x85 },
+ { 128, 0x89 },{ 136, 0x86 },{ 144, 0x8A },{ 160, 0x8B },
+ { 176, 0x8C },{ 192, 0x90 },{ 208, 0x56 },{ 224, 0x91 },
+ { 240, 0x1F },{ 256, 0x92 },{ 272, 0x8F },{ 288, 0x93 },
+ { 320, 0x98 },{ 352, 0x95 },{ 384, 0x99 },{ 416, 0x96 },
+ { 448, 0x9A },{ 480, 0x5F },{ 512, 0x9B },{ 576, 0x9C },
+ { 640, 0xA0 },{ 768, 0xA1 },{ 896, 0xA2 },{ 960, 0x9F },
+ { 1024, 0xA3 },{ 1152, 0xA4 },{ 1280, 0xA8 },{ 1536, 0xA9 },
+ { 1792, 0xAA },{ 1920, 0xA7 },{ 2048, 0xAB },{ 2304, 0xAC },
+ { 2560, 0xAD },{ 3072, 0xB1 },{ 3584, 0xB2 },{ 3840, 0xAF },
+ { 4096, 0xB3 },{ 4608, 0xB4 },{ 5120, 0xB8 },{ 6144, 0xB9 },
+ { 7168, 0xBA },{ 7680, 0xB7 },{ 8192, 0xBB },{ 9216, 0xBC },
+ { 10240, 0xBD },{ 12288, 0xBE },{ 15360, 0xBF }
+};
+
+/**
+ ERR009203 : I2C may not work reliably with the default setting
+
+ Description : The clocking circuitry of I2C module may not work reliably due to the slow
+ rise time of SCL signal.
+ Workaround : Enable the receiver digital filter by setting IBDBG[GLFLT_EN] to 1.
+*/
+STATIC
+VOID
+ I2cErratumA009203 (
+ IN UINTN Base
+ )
+{
+ I2C_REGS *Regs;
+
+ Regs = (I2C_REGS *)Base;
+
+ MmioOr8 ( (UINTN)&Regs->Ibdbg, I2C_IBDBG_GLFLT_EN);
+}
+
+/**
+ Early init I2C for reading the sysclk from I2c slave device.
+ I2c bus clock is determined from the clock input to I2c controller.
+ The clock input to I2c controller is derived from the sysclk.
+ sysclk is determined by clock generator, which is controller by i2c.
+
+ So, it's a chicken-egg problem to read the sysclk from clock generator.
+ To break this cycle (i.e. to read the sysclk), we setup the i2c bus clock to
+ lowest value, in the hope that it won't be out of clock generator's supported
+ i2c clock frequency. Once we have the correct sysclk, we can setup the correct
+ i2c bus clock.
+
+ @param[in] Base Base Address of I2c controller's registers
+
+ @return EFI_SUCCESS successfuly setup the i2c bus for reading sysclk
+**/
+EFI_STATUS
+I2cEarlyInitialize (
+ IN UINTN Base
+ )
+{
+ I2C_REGS *Regs;
+ UINT8 Ibc;
+
+ Regs = (I2C_REGS *)Base;
+ if (FeaturePcdGet (PcdI2cErratumA009203)) {
+ I2cErratumA009203 (Base);
+ }
+
+ if (MmioRead8 ( (UINTN)&Regs->Ibdbg) & I2C_IBDBG_GLFLT_EN) {
+ Ibc = I2cClockDividerGlitchEnabled[ARRAY_SIZE (I2cClockDividerGlitchEnabled) - 1].Ibc;
+ } else {
+ Ibc = I2cClockDividerGlitchDisabled[ARRAY_SIZE (I2cClockDividerGlitchDisabled) - 1].Ibc;
+ }
+
+ MmioWrite8 ( (UINTN)&Regs->Ibfd, Ibc);
+ // Reset Module
+ MmioOr8 ( (UINTN)&Regs->Ibcr, I2C_IBCR_MDIS);
+ MmioAnd8 ( (UINTN)&Regs->Ibcr, ~(I2C_IBCR_IBIE | I2C_IBCR_DMAEN));
+ MmioAnd8 ( (UINTN)&Regs->Ibic, (UINT8)(~I2C_IBIC_BIIE));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Configure I2c bus to opearte at a given speed
+
+ @param[in] Base Base Address of I2c controller's registers
+ @param[in] I2cBusClock Input clock to I2c controller
+ @param[in] Speed speed to be configured for I2c bus
+**/
+EFI_STATUS
+I2cInitialize (
+ IN UINTN Base,
+ IN UINT64 I2cBusClock,
+ IN UINT64 Speed
+ )
+{
+ I2C_REGS *Regs;
+ UINT16 ClockDivider;
+ UINT8 Ibc;
+ I2C_CLOCK_DIVIDER_PAIR *ClockDividerPair;
+ UINT32 ClockDividerPairSize;
+ UINT32 Index;
+
+ Regs = (I2C_REGS *)Base;
+ if (FeaturePcdGet (PcdI2cErratumA009203)) {
+ I2cErratumA009203 (Base);
+ }
+
+ Ibc = 0;
+ ClockDivider = (I2cBusClock + Speed - 1) / Speed;
+
+ if (MmioRead8 ( (UINTN)&Regs->Ibdbg) & I2C_IBDBG_GLFLT_EN) {
+ ClockDividerPair = I2cClockDividerGlitchEnabled;
+ ClockDividerPairSize = ARRAY_SIZE (I2cClockDividerGlitchEnabled);
+ } else {
+ ClockDividerPair = I2cClockDividerGlitchDisabled;
+ ClockDividerPairSize = ARRAY_SIZE (I2cClockDividerGlitchDisabled);
+ }
+
+ if (ClockDivider > ClockDividerPair[ClockDividerPairSize - 1].Divider) {
+ Ibc = ClockDividerPair[ClockDividerPairSize - 1].Ibc;
+ } else {
+ for (Index = 0; Index < ClockDividerPairSize; Index++) {
+ if (ClockDividerPair[Index].Divider >= ClockDivider) {
+ Ibc = ClockDividerPair[Index].Ibc;
+ break;
+ }
+ }
+ }
+
+ MmioWrite8 ( (UINTN)&Regs->Ibfd, Ibc);
+ // Reset Module
+ MmioOr8 ( (UINTN)&Regs->Ibcr, I2C_IBCR_MDIS);
+ MmioAnd8 ( (UINTN)&Regs->Ibcr, ~(I2C_IBCR_IBIE | I2C_IBCR_DMAEN));
+ MmioAnd8 ( (UINTN)&Regs->Ibic, (UINT8)(~I2C_IBIC_BIIE));
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+I2cBusTestBusBusy (
+ IN I2C_REGS *Regs,
+ IN BOOLEAN TestBusy
+ )
+{
+ UINT8 Index;
+ UINT8 Reg;
+
+ for (Index = 0; Index < 500; Index++) {
+ Reg = MmioRead8 ( (UINTN)&Regs->Ibsr);
+
+ if (Reg & I2C_IBSR_IBAL) {
+ MmioWrite8 ( (UINTN)&Regs->Ibsr, Reg);
+ return EFI_NOT_READY;
+ }
+
+ if (TestBusy && (Reg & I2C_IBSR_IBB)) {
+ break;
+ }
+
+ if (!TestBusy && !(Reg & I2C_IBSR_IBB)) {
+ break;
+ }
+
+ MicroSecondDelay (1);
+ }
+
+ if (Index == 500) {
+ return EFI_TIMEOUT;
+ } else {
+ return EFI_SUCCESS;
+ }
+}
+
+STATIC
+EFI_STATUS
+I2cTransferComplete (
+ IN I2C_REGS *Regs,
+ IN BOOLEAN TestRxAck
+)
+{
+ UINT8 Index;
+ UINT8 Reg;
+
+ for (Index = 0; Index < 500; Index++) {
+ Reg = MmioRead8 ( (UINTN)&Regs->Ibsr);
+
+ if (Reg & I2C_IBSR_IBIF) {
+ // Write 1 to clear the IBIF field
+ MmioWrite8 ( (UINTN)&Regs->Ibsr, Reg);
+ break;
+ }
+
+ MicroSecondDelay (1);
+ }
+
+ if (Index == 500) {
+ return EFI_TIMEOUT;
+ }
+
+ if (TestRxAck && (Reg & I2C_IBSR_RXAK)) {
+ return EFI_NO_RESPONSE;
+ }
+
+ if (Reg & I2C_IBSR_TCF) {
+ return EFI_SUCCESS;
+ }
+ return EFI_DEVICE_ERROR;
+}
+
+STATIC
+EFI_STATUS
+I2cRead (
+ IN I2C_REGS *Regs,
+ IN UINT32 SlaveAddress,
+ IN EFI_I2C_OPERATION *Operation,
+ IN BOOLEAN IsLastOperation
+)
+{
+ EFI_STATUS Status;
+ UINTN Index;
+
+ // Write Slave Address
+ MmioWrite8 ( (UINTN)&Regs->Ibdr, (SlaveAddress << BIT0) | BIT0);
+ Status = I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ // select Receive mode.
+ MmioAnd8 ( (UINTN)&Regs->Ibcr, ~I2C_IBCR_TXRX);
+ // Perform a dummy read to initiate the receive operation.
+ MmioRead8 ( (UINTN)&Regs->Ibdr);
+
+ for (Index = 0; Index < Operation->LengthInBytes; Index++) {
+ Status = I2cTransferComplete (Regs, I2C_BUS_NO_TEST_RX_ACK);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ if (Index == (Operation->LengthInBytes - 2)) {
+ // Set No ACK = 1
+ MmioOr8 ( (UINTN)&Regs->Ibcr, I2C_IBCR_NOACK);
+ } else if (Index == (Operation->LengthInBytes - 1)) {
+ if (!IsLastOperation) {
+ // select Transmit mode (for repeat start)
+ MmioOr8 ( (UINTN)&Regs->Ibcr, I2C_IBCR_TXRX);
+ } else {
+ // Generate Stop Signal
+ MmioAnd8 ( (UINTN)&Regs->Ibcr, ~(I2C_IBCR_MSSL | I2C_IBCR_TXRX));
+ Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+ }
+ Operation->Buffer[Index] = MmioRead8 ( (UINTN)&Regs->Ibdr);
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+I2cWrite (
+ IN I2C_REGS *Regs,
+ IN UINT32 SlaveAddress,
+ IN EFI_I2C_OPERATION *Operation
+)
+{
+ EFI_STATUS Status;
+ UINTN Index;
+
+ // Write Slave Address
+ MmioWrite8 ( (UINTN)&Regs->Ibdr, (SlaveAddress << BIT0) & (UINT8)(~BIT0));
+ Status = I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Write Data
+ for (Index = 0; Index < Operation->LengthInBytes; Index++) {
+ MmioWrite8 ( (UINTN)&Regs->Ibdr, Operation->Buffer[Index]);
+ Status = I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+I2cStop (
+ IN I2C_REGS *Regs
+ )
+{
+ EFI_STATUS Status;
+ UINT8 Reg;
+
+ Reg = MmioRead8 ( (UINTN)&Regs->Ibsr);
+ if (Reg & I2C_IBSR_IBB) {
+ // Generate Stop Signal
+ MmioAnd8 ( (UINTN)&Regs->Ibcr, ~(I2C_IBCR_MSSL | I2C_IBCR_TXRX));
+ Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+
+ // Disable I2c Controller
+ MmioOr8 ( (UINTN)&Regs->Ibcr, I2C_IBCR_MDIS);
+
+ return Status;
+}
+
+STATIC
+EFI_STATUS
+I2cStart (
+ IN I2C_REGS *Regs
+ )
+{
+ EFI_STATUS Status;
+
+ MmioOr8 ( (UINTN)&Regs->Ibsr, (I2C_IBSR_IBAL | I2C_IBSR_IBIF));
+ MmioAnd8 ( (UINTN)&Regs->Ibcr, (UINT8)(~I2C_IBCR_MDIS));
+
+ // Generate Start Signal
+ MmioOr8 ( (UINTN)&Regs->Ibcr, I2C_IBCR_MSSL);
+ Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_BUSY);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ MmioOr8 ( (UINTN)&Regs->Ibcr, I2C_IBCR_TXRX | I2C_IBCR_NOACK);
+ return Status;
+}
+
+/**
+ Transfer data to/from I2c slave device
+
+ @param[in] Base Base Address of I2c controller's registers
+ @param[in] SlaveAddress Slave Address from which data is to be read
+ @param[in] RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET structure
+ describing the I2C transaction
+
+ @return EFI_SUCCESS successfuly setup the i2c bus for reading sysclk
+ @return EFI_DEVICE_ERROR There was an error while transferring data through I2c bus
+ @return EFI_NO_RESPONSE There was no Ack from i2c device
+ @return EFI_TIMEOUT I2c Bus is busy
+ @return EFI_NOT_READY I2c Bus Arbitration lost
+**/
+EFI_STATUS
+I2cBusXfer (
+ IN UINTN Base,
+ IN UINT32 SlaveAddress,
+ IN EFI_I2C_REQUEST_PACKET *RequestPacket
+ )
+{
+ UINTN Index;
+ I2C_REGS *Regs;
+ EFI_I2C_OPERATION *Operation;
+ EFI_STATUS Status;
+ BOOLEAN IsLastOperation;
+
+ Regs = (I2C_REGS *)Base;
+ IsLastOperation = FALSE;
+
+ Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE);
+ if (EFI_ERROR (Status)) {
+ goto ErrorExit;
+ }
+
+ Status = I2cStart (Regs);
+ if (EFI_ERROR (Status)) {
+ goto ErrorExit;
+ }
+
+ for (Index = 0, Operation = RequestPacket->Operation;
+ Index < RequestPacket->OperationCount;
+ Index++, Operation++) {
+ if (Index == (RequestPacket->OperationCount - 1)) {
+ IsLastOperation = TRUE;
+ }
+ // Send repeat start after first transmit/recieve
+ if (Index) {
+ MmioOr8 ( (UINTN)&Regs->Ibcr, I2C_IBCR_RSTA);
+ Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_BUSY);
+ if (EFI_ERROR (Status)) {
+ goto ErrorExit;
+ }
+ }
+ // Read/write data
+ if (Operation->Flags & I2C_FLAG_READ) {
+ Status = I2cRead (Regs, SlaveAddress, Operation, IsLastOperation);
+ } else {
+ Status = I2cWrite (Regs, SlaveAddress, Operation);
+ }
+ if (EFI_ERROR (Status)) {
+ goto ErrorExit;
+ }
+ }
+
+ErrorExit:
+
+ I2cStop (Regs);
+
+ return Status;
+}
+
+/**
+ Read a register from I2c slave device. This API is wrapper around I2cBusXfer
+
+ @param[in] Base Base Address of I2c controller's registers
+ @param[in] SlaveAddress Slave Address from which register value is to be read
+ @param[in] RegAddress Register Address in Slave's memory map
+ @param[in] RegAddressWidthInBytes Number of bytes in RegAddress to send to I2c Slave
+ for simple reads without any register, make this value = 0
+ (RegAddress is don't care in that case)
+ @param[out] RegValue Value to be read from I2c slave's regiser
+ @param[in] RegValueNumBytes Number of bytes to read from I2c slave register
+
+ @return EFI_SUCCESS successfuly setup the i2c bus for reading sysclk
+ @return EFI_DEVICE_ERROR There was an error while transferring data through I2c bus
+ @return EFI_NO_RESPONSE There was no Ack from i2c device
+ @return EFI_TIMEOUT I2c Bus is busy
+ @return EFI_NOT_READY I2c Bus Arbitration lost
+**/
+EFI_STATUS
+I2cBusReadReg (
+ IN UINTN Base,
+ IN UINT32 SlaveAddress,
+ IN UINT64 RegAddress,
+ IN UINT8 RegAddressWidthInBytes,
+ OUT UINT8 *RegValue,
+ IN UINT8 RegValueNumBytes
+ )
+{
+ EFI_I2C_OPERATION *Operations;
+ I2C_REG_REQUEST RequestPacket;
+ UINTN OperationCount;
+ UINT8 Address[8];
+ UINT8 *Ptr;
+ EFI_STATUS Status;
+
+ ZeroMem (&RequestPacket, sizeof (RequestPacket));
+ OperationCount = 0;
+ Operations = RequestPacket.Operation;
+ Ptr = Address;
+
+ if (RegAddressWidthInBytes > ARRAY_SIZE (Address)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (RegAddressWidthInBytes != 0) {
+ Operations[OperationCount].LengthInBytes = RegAddressWidthInBytes;
+ Operations[OperationCount].Buffer = Ptr;
+ while (RegAddressWidthInBytes--) {
+ *Ptr++ = RegAddress >> (8 * RegAddressWidthInBytes);
+ }
+ OperationCount++;
+ }
+
+ Operations[OperationCount].LengthInBytes = RegValueNumBytes;
+ Operations[OperationCount].Buffer = RegValue;
+ Operations[OperationCount].Flags = I2C_FLAG_READ;
+ OperationCount++;
+
+ RequestPacket.OperationCount = OperationCount;
+
+ Status = I2cBusXfer (Base, SlaveAddress, (EFI_I2C_REQUEST_PACKET *)&RequestPacket);
+
+ return Status;
+}
+
diff --git a/Silicon/NXP/Library/I2cLib/I2cLib.inf b/Silicon/NXP/Library/I2cLib/I2cLib.inf
new file mode 100644
index 0000000000..9c8aae100b
--- /dev/null
+++ b/Silicon/NXP/Library/I2cLib/I2cLib.inf
@@ -0,0 +1,30 @@
+#/** @file
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+#**/
+
+[Defines]
+ INF_VERSION = 1.27
+ BASE_NAME = I2cLib
+ FILE_GUID = f22393b1-98b6-4067-9ec2-6aa436321f03
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = I2cLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ TimerLib
+ IoLib
+
+[Sources.common]
+ I2cLib.c
+
+[FeaturePcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203
+
diff --git a/Silicon/NXP/Library/I2cLib/I2cLibInternal.h b/Silicon/NXP/Library/I2cLib/I2cLibInternal.h
new file mode 100644
index 0000000000..14be9cb740
--- /dev/null
+++ b/Silicon/NXP/Library/I2cLib/I2cLibInternal.h
@@ -0,0 +1,95 @@
+/** @file
+ I2c Lib to control I2c controller.
+
+ Copyright 2020 NXP
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __I2C_LIB_INTERNAL_H__
+#define __I2C_LIB_INTERNAL_H__
+
+#include <Pi/PiI2c.h>
+#include <Uefi.h>
+
+/* Module Disable
+ * 0b - The module is enabled. You must clear this field before any other IBCR fields have any effect.
+ * 1b - The module is reset and disabled. This is the power-on reset situation. When high, the
+ * interface is held in reset, but registers can still be accessed. Status register fields (IBSR) are not
+ * valid when the module is disabled.
+ */
+#define I2C_IBCR_MDIS BIT7
+// I2c Bus Interrupt Enable
+#define I2C_IBCR_IBIE BIT6
+/* Master / Slave Mode 0b - Slave mode 1b - Master mode
+ * When you change this field from 0 to 1, the module generates a START signal on the bus and selects the
+ * master mode. When you change this field from 1 to 0, the module generates a STOP signal and changes
+ * the operation mode from master to slave. You should generate a STOP signal only if IBSR[IBIF]=1. The
+ * module clears this field without generating a STOP signal when the master loses arbitration.
+*/
+#define I2C_IBCR_MSSL BIT5
+// 0b - Receive 1b - Transmit
+#define I2C_IBCR_TXRX BIT4
+/* Data acknowledge disable
+ * Values written to this field are only used when the I2C module is a receiver, not a transmitter.
+ * 0b - The module sends an acknowledge signal to the bus at the 9th clock bit after receiving one
+ * byte of data.
+ * 1b - The module does not send an acknowledge-signal response (that is, acknowledge bit = 1).
+ */
+#define I2C_IBCR_NOACK BIT3
+/* Repeat START
+ * If the I2C module is the current bus master, and you program RSTA=1, the I2C module generates a
+ * repeated START condition. This field always reads as a 0. If you attempt a repeated START at the wrong
+ * time—if the bus is owned by another master—the result is loss of arbitration.
+ */
+#define I2C_IBCR_RSTA BIT2
+// DMA enable
+#define I2C_IBCR_DMAEN BIT1
+
+// Transfer Complete
+#define I2C_IBSR_TCF BIT7
+// I2C bus Busy. 0b - Bus is idle, 1b - Bus is busy
+#define I2C_IBSR_IBB BIT5
+// Arbitration Lost. software must clear this field by writing a one to it.
+#define I2C_IBSR_IBAL BIT4
+// I2C bus interrupt flag
+#define I2C_IBSR_IBIF BIT1
+// Received acknowledge 0b - Acknowledge received 1b - No acknowledge received
+#define I2C_IBSR_RXAK BIT0
+
+//Bus idle interrupt enable
+#define I2C_IBIC_BIIE BIT7
+
+// Glitch filter enable
+#define I2C_IBDBG_GLFLT_EN BIT3
+
+#define I2C_BUS_TEST_BUSY TRUE
+#define I2C_BUS_TEST_IDLE !I2C_BUS_TEST_BUSY
+#define I2C_BUS_TEST_RX_ACK TRUE
+#define I2C_BUS_NO_TEST_RX_ACK !I2C_BUS_TEST_RX_ACK
+
+typedef struct _I2C_REGS {
+ UINT8 Ibad; // I2c Bus Address Register
+ UINT8 Ibfd; // I2c Bus Frequency Dividor Register
+ UINT8 Ibcr; // I2c Bus Control Register
+ UINT8 Ibsr; // I2c Bus Status Register
+ UINT8 Ibdr; // I2C Bus Data I/O Register
+ UINT8 Ibic; // I2C Bus Interrupt Config Register
+ UINT8 Ibdbg; // I2C Bus Debug Register
+} I2C_REGS;
+
+/*
+ * sorted list of clock divider, register value pairs
+ */
+typedef struct _I2C_CLOCK_DIVIDER_PAIR {
+ UINT16 Divider;
+ UINT16 Ibc;
+} I2C_CLOCK_DIVIDER_PAIR;
+
+typedef struct {
+ UINTN OperationCount;
+ EFI_I2C_OPERATION Operation[2];
+} I2C_REG_REQUEST;
+
+#endif // __I2C_LIB_INTERNAL_H__
+
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 764b9bb0e2..4a1cfb3e27 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -1,6 +1,6 @@
# @file.
#
-# Copyright 2017-2019 NXP
+# Copyright 2017-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -13,6 +13,10 @@
[Includes]
Include
+[LibraryClasses]
+ ## @libraryclass Provides services to read/write to I2c devices
+ I2cLib|Include/Library/I2cLib.h
+
[Guids.common]
gNxpQoriqLsTokenSpaceGuid = {0x98657342, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
@@ -101,3 +105,7 @@
gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000312
gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|FALSE|BOOLEAN|0x00000313
gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314
+
+[PcdsFeatureFlag]
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315
+
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 02/19] Silicon/NXP: changes to use I2clib in i2cdxe
2020-02-07 12:43 [PATCH 00/19] ADD LX2160ARDB Platform Support Pankaj Bansal
2020-02-07 12:43 ` [PATCH 01/19] Silicon/NXP: Add I2c lib Pankaj Bansal
@ 2020-02-07 12:43 ` Pankaj Bansal
2020-02-08 17:23 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 03/19] NXP/LS1043aRdb: Move Soc specific components to soc files Pankaj Bansal
` (16 subsequent siblings)
18 siblings, 1 reply; 49+ messages in thread
From: Pankaj Bansal @ 2020-02-07 12:43 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, Varun Sethi
Cc: devel, Pankaj Bansal
I2c lib contains the i2c controller functionality. this can be used
in I2c DXE driver to communicate with i2c devices.
There was a bug in I2C DXE implementation, which caused the Ds1307 RTC
device to issue two operation for register write, while this is a single
operation task. refer page 12 (Slave Receiver Mode (Write Mode)) on
https://datasheets.maximintegrated.com/en/ds/DS1307.pdf
with i2c lib implementation, this bug has been fixed. so modify ds1307
code accordingly.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
.../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c | 23 +-
Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 526 +-----------------
Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 44 +-
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 3 +-
4 files changed, 31 insertions(+), 565 deletions(-)
diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
index 88dc198ffe..444e011248 100644
--- a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
+++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
@@ -5,7 +5,7 @@
EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
- Copyright 2017 NXP
+ Copyright 2017, 2020 NXP
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -28,6 +28,11 @@ STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster;
/**
Read RTC register.
+ Data Read-Slave Transmitter Mode
+
+ <Slave Address> <Word Address (n)> <Slave Address> <Data(n)> <Data(n+1)> <Data(n+2)> <Data(n+X)>
+
+ The first byte is received and handled as in the slave receiver mode.
@param RtcRegAddr Register offset of RTC to be read.
@@ -69,6 +74,9 @@ RtcRead (
/**
Write RTC register.
+ Data Write-Slave Receiver Mode
+
+ <Slave Address> <Word Address (n)> <Data(n)> <Data(n+1)> <Data(n+X)>
@param RtcRegAddr Register offset of RTC to write.
@param Val Value to be written
@@ -84,16 +92,15 @@ RtcWrite (
{
RTC_I2C_REQUEST Req;
EFI_STATUS Status;
+ UINT8 Buffer[2];
- Req.OperationCount = 2;
+ Req.OperationCount = 1;
+ Buffer[0] = RtcRegAddr;
+ Buffer[1] = Val;
Req.SetAddressOp.Flags = 0;
- Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
- Req.SetAddressOp.Buffer = &RtcRegAddr;
-
- Req.GetSetDateTimeOp.Flags = 0;
- Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
- Req.GetSetDateTimeOp.Buffer = &Val;
+ Req.SetAddressOp.LengthInBytes = sizeof (Buffer);
+ Req.SetAddressOp.Buffer = Buffer;
Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSlaveAddress),
(VOID *)&Req,
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
index 853c426fbc..8e3a82efca 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
@@ -1,7 +1,7 @@
/** I2cDxe.c
I2c driver APIs for read, write, initialize, set speed and reset
- Copyright 2017-2019 NXP
+ Copyright 2017-2020 NXP
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -15,6 +15,7 @@
#include <Library/TimerLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
+#include <Library/I2cLib.h>
#include "I2cDxe.h"
@@ -25,444 +26,6 @@ STATIC CONST EFI_I2C_CONTROLLER_CAPABILITIES mI2cControllerCapabilities = {
0
};
-STATIC CONST CLK_DIV mClkDiv[] = {
- { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
- { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
- { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
- { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
- { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
- { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
- { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
- { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
- { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
- { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
- { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
- { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
- { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
- { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
- { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }
-};
-
-/**
- Calculate and return proper clock divider
-
- @param Rate desired clock rate
-
- @retval ClkDiv Index value used to get Bus Clock Rate
-
-**/
-STATIC
-UINT8
-GetClkDivIndex (
- IN UINT32 Rate
- )
-{
- UINTN ClkRate;
- UINT32 Div;
- UINT8 Index;
-
- Index = 0;
- ClkRate = GetBusFrequency ();
-
- Div = (ClkRate + Rate - 1) / Rate;
-
- if (Div < mClkDiv[0].SCLDivider) {
- return 0;
- }
-
- do {
- if (mClkDiv[Index].SCLDivider >= Div ) {
- return Index;
- }
- Index++;
- } while (Index < ARRAY_SIZE (mClkDiv));
-
- return (ARRAY_SIZE (mClkDiv) - 1);
-}
-
-/**
- Function used to check if i2c is in mentioned state or not
-
- @param I2cRegs Pointer to I2C registers
- @param State i2c state need to be checked
-
- @retval EFI_NOT_READY Arbitration was lost
- @retval EFI_TIMEOUT Timeout occured
- @retval CurrState Value of state register
-
-**/
-STATIC
-EFI_STATUS
-WaitForI2cState (
- IN I2C_REGS *I2cRegs,
- IN UINT32 State
- )
-{
- UINT8 CurrState;
- UINT64 Count;
-
- for (Count = 0; Count < I2C_STATE_RETRIES; Count++) {
- MemoryFence ();
- CurrState = MmioRead8 ((UINTN)&I2cRegs->I2cSr);
- if (CurrState & I2C_SR_IAL) {
- MmioWrite8 ((UINTN)&I2cRegs->I2cSr, CurrState | I2C_SR_IAL);
- return EFI_NOT_READY;
- }
-
- if ((CurrState & (State >> 8)) == (UINT8)State) {
- return CurrState;
- }
- }
-
- return EFI_TIMEOUT;
-}
-
-/**
- Function to transfer byte on i2c
-
- @param I2cRegs Pointer to i2c registers
- @param Byte Byte to be transferred on i2c bus
-
- @retval EFI_NOT_READY Arbitration was lost
- @retval EFI_TIMEOUT Timeout occured
- @retval EFI_NOT_FOUND ACK was not recieved
- @retval EFI_SUCCESS Data transfer was succesful
-
-**/
-STATIC
-EFI_STATUS
-TransferByte (
- IN I2C_REGS *I2cRegs,
- IN UINT8 Byte
- )
-{
- EFI_STATUS RetVal;
-
- MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
- MmioWrite8 ((UINTN)&I2cRegs->I2cDr, Byte);
-
- RetVal = WaitForI2cState (I2cRegs, IIF);
- if ((RetVal == EFI_TIMEOUT) || (RetVal == EFI_NOT_READY)) {
- return RetVal;
- }
-
- if (RetVal & I2C_SR_RX_NO_AK) {
- return EFI_NOT_FOUND;
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Function to stop transaction on i2c bus
-
- @param I2cRegs Pointer to i2c registers
-
- @retval EFI_NOT_READY Arbitration was lost
- @retval EFI_TIMEOUT Timeout occured
- @retval EFI_SUCCESS Stop operation was successful
-
-**/
-STATIC
-EFI_STATUS
-I2cStop (
- IN I2C_REGS *I2cRegs
- )
-{
- EFI_STATUS RetVal;
- UINT32 Temp;
-
- Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
-
- Temp &= ~(I2C_CR_MSTA | I2C_CR_MTX);
- MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
-
- RetVal = WaitForI2cState (I2cRegs, BUS_IDLE);
-
- if (RetVal < 0) {
- return RetVal;
- } else {
- return EFI_SUCCESS;
- }
-}
-
-/**
- Function to send start signal, Chip Address and
- memory offset
-
- @param I2cRegs Pointer to i2c base registers
- @param Chip Chip Address
- @param Offset Slave memory's offset
- @param AddressLength length of chip address
-
- @retval EFI_NOT_READY Arbitration lost
- @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
- @retval EFI_NOT_FOUND ACK was not recieved
- @retval EFI_SUCCESS Read was successful
-
-**/
-STATIC
-EFI_STATUS
-InitTransfer (
- IN I2C_REGS *I2cRegs,
- IN UINT8 Chip,
- IN UINT32 Offset,
- IN INT32 AddressLength
- )
-{
- UINT32 Temp;
- EFI_STATUS RetVal;
-
- // Enable I2C controller
- if (MmioRead8 ((UINTN)&I2cRegs->I2cCr) & I2C_CR_IDIS) {
- MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IEN);
- }
-
- if (MmioRead8 ((UINTN)&I2cRegs->I2cAdr) == (Chip << 1)) {
- MmioWrite8 ((UINTN)&I2cRegs->I2cAdr, (Chip << 1) ^ 2);
- }
-
- MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
- RetVal = WaitForI2cState (I2cRegs, BUS_IDLE);
- if ((RetVal == EFI_TIMEOUT) || (RetVal == EFI_NOT_READY)) {
- return RetVal;
- }
-
- // Start I2C transaction
- Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
- // set to master mode
- Temp |= I2C_CR_MSTA;
- MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
-
- RetVal = WaitForI2cState (I2cRegs, BUS_BUSY);
- if ((RetVal == EFI_TIMEOUT) || (RetVal == EFI_NOT_READY)) {
- return RetVal;
- }
-
- Temp |= I2C_CR_MTX | I2C_CR_TX_NO_AK;
- MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
-
- // write slave Address
- RetVal = TransferByte (I2cRegs, Chip << 1);
- if (RetVal != EFI_SUCCESS) {
- return RetVal;
- }
-
- if (AddressLength >= 0) {
- while (AddressLength--) {
- RetVal = TransferByte (I2cRegs, (Offset >> (AddressLength * 8)) & 0xff);
- if (RetVal != EFI_SUCCESS)
- return RetVal;
- }
- }
- return EFI_SUCCESS;
-}
-
-/**
- Function to check if i2c bus is idle
-
- @param Base Pointer to base address of I2c controller
-
- @retval EFI_SUCCESS
-
-**/
-STATIC
-INT32
-I2cBusIdle (
- IN VOID *Base
- )
-{
- return EFI_SUCCESS;
-}
-
-/**
- Function to initiate data transfer on i2c bus
-
- @param I2cRegs Pointer to i2c base registers
- @param Chip Chip Address
- @param Offset Slave memory's offset
- @param AddressLength length of chip address
-
- @retval EFI_NOT_READY Arbitration lost
- @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
- @retval EFI_NOT_FOUND ACK was not recieved
- @retval EFI_SUCCESS Read was successful
-
-**/
-STATIC
-EFI_STATUS
-InitDataTransfer (
- IN I2C_REGS *I2cRegs,
- IN UINT8 Chip,
- IN UINT32 Offset,
- IN INT32 AddressLength
- )
-{
- EFI_STATUS RetVal;
- INT32 Retry;
-
- for (Retry = 0; Retry < RETRY_COUNT; Retry++) {
- RetVal = InitTransfer (I2cRegs, Chip, Offset, AddressLength);
- if (RetVal == EFI_SUCCESS) {
- return EFI_SUCCESS;
- }
-
- I2cStop (I2cRegs);
-
- if (EFI_NOT_FOUND == RetVal) {
- return RetVal;
- }
-
- // Disable controller
- if (RetVal != EFI_NOT_READY) {
- MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS);
- }
-
- if (I2cBusIdle (I2cRegs) < 0) {
- break;
- }
- }
- return RetVal;
-}
-
-/**
- Function to read data using i2c bus
-
- @param BaseAddr I2c Controller Base Address
- @param Chip Address of slave device from where data to be read
- @param Offset Offset of slave memory
- @param AddressLength Address length of slave
- @param Buffer A pointer to the destination buffer for the data
- @param Len Length of data to be read
-
- @retval EFI_NOT_READY Arbitration lost
- @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
- @retval EFI_NOT_FOUND ACK was not recieved
- @retval EFI_SUCCESS Read was successful
-
-**/
-STATIC
-EFI_STATUS
-I2cDataRead (
- IN UINTN BaseAddr,
- IN UINT8 Chip,
- IN UINT32 Offset,
- IN UINT32 AddressLength,
- IN UINT8 *Buffer,
- IN UINT32 Len
- )
-{
- EFI_STATUS RetVal;
- UINT32 Temp;
- INT32 I;
- I2C_REGS *I2cRegs;
-
- I2cRegs = (I2C_REGS *)(BaseAddr);
-
- RetVal = InitDataTransfer (I2cRegs, Chip, Offset, AddressLength);
- if (RetVal != EFI_SUCCESS) {
- return RetVal;
- }
-
- Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
- Temp |= I2C_CR_RSTA;
- MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
-
- RetVal = TransferByte (I2cRegs, (Chip << 1) | 1);
- if (RetVal != EFI_SUCCESS) {
- I2cStop (I2cRegs);
- return RetVal;
- }
-
- // setup bus to read data
- Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
- Temp &= ~(I2C_CR_MTX | I2C_CR_TX_NO_AK);
- if (Len == 1) {
- Temp |= I2C_CR_TX_NO_AK;
- }
-
- MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
- MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
-
- // Dummy Read to initiate recieve operation
- MmioRead8 ((UINTN)&I2cRegs->I2cDr);
-
- for (I = 0; I < Len; I++) {
- RetVal = WaitForI2cState (I2cRegs, IIF);
- if ((RetVal == EFI_TIMEOUT) || (RetVal == EFI_NOT_READY)) {
- I2cStop (I2cRegs);
- return RetVal;
- }
- //
- // It must generate STOP before read I2DR to prevent
- // controller from generating another clock cycle
- //
- if (I == (Len - 1)) {
- I2cStop (I2cRegs);
- } else if (I == (Len - 2)) {
- Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
- Temp |= I2C_CR_TX_NO_AK;
- MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
- }
- MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
- Buffer[I] = MmioRead8 ((UINTN)&I2cRegs->I2cDr);
- }
-
- I2cStop (I2cRegs);
-
- return EFI_SUCCESS;
-}
-
-/**
- Function to write data using i2c bus
-
- @param BaseAddr I2c Controller Base Address
- @param Chip Address of slave device where data to be written
- @param Offset Offset of slave memory
- @param AddressLength Address length of slave
- @param Buffer A pointer to the source buffer for the data
- @param Len Length of data to be write
-
- @retval EFI_NOT_READY Arbitration lost
- @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
- @retval EFI_NOT_FOUND ACK was not recieved
- @retval EFI_SUCCESS Read was successful
-
-**/
-STATIC
-EFI_STATUS
-I2cDataWrite (
- IN UINTN BaseAddr,
- IN UINT8 Chip,
- IN UINT32 Offset,
- IN INT32 AddressLength,
- OUT UINT8 *Buffer,
- IN INT32 Len
- )
-{
- EFI_STATUS RetVal;
- I2C_REGS *I2cRegs;
- INT32 I;
-
- I2cRegs = (I2C_REGS *)BaseAddr;
-
- RetVal = InitDataTransfer (I2cRegs, Chip, Offset, AddressLength);
- if (RetVal != EFI_SUCCESS) {
- return RetVal;
- }
-
- // Write operation
- for (I = 0; I < Len; I++) {
- RetVal = TransferByte (I2cRegs, Buffer[I]);
- if (RetVal != EFI_SUCCESS) {
- break;
- }
- }
-
- I2cStop (I2cRegs);
- return RetVal;
-}
-
/**
Function to set i2c bus frequency
@@ -479,22 +42,17 @@ SetBusFrequency (
IN OUT UINTN *BusClockHertz
)
{
- I2C_REGS *I2cRegs;
- UINT8 ClkId;
- UINT8 SpeedId;
+ UINTN I2cBase;
+ UINT64 I2cClock;
NXP_I2C_MASTER *I2c;
I2c = NXP_I2C_FROM_THIS (This);
- I2cRegs = (I2C_REGS *)(I2c->Dev->Resources[0].AddrRangeMin);
-
- ClkId = GetClkDivIndex (*BusClockHertz);
- SpeedId = mClkDiv[ClkId].BusClockRate;
+ I2cBase = (UINTN)(I2c->Dev->Resources[0].AddrRangeMin);
- // Store divider value
- MmioWrite8 ((UINTN)&I2cRegs->I2cFdr, SpeedId);
+ I2cClock = GetBusFrequency ();
- MemoryFence ();
+ I2cInitialize (I2cBase, I2cClock, *BusClockHertz);
return EFI_SUCCESS;
}
@@ -513,19 +71,6 @@ Reset (
IN CONST EFI_I2C_MASTER_PROTOCOL *This
)
{
- I2C_REGS *I2cRegs;
- NXP_I2C_MASTER *I2c;
-
- I2c = NXP_I2C_FROM_THIS (This);
-
- I2cRegs = (I2C_REGS *)(I2c->Dev->Resources[0].AddrRangeMin);
-
- // Reset module
- MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS);
- MmioWrite8 ((UINTN)&I2cRegs->I2cSr, 0);
-
- MemoryFence ();
-
return EFI_SUCCESS;
}
@@ -540,62 +85,17 @@ StartRequest (
OUT EFI_STATUS *I2cStatus OPTIONAL
)
{
- NXP_I2C_MASTER *I2c;
- UINT32 Count;
- INT32 RetVal;
- UINT32 Length;
- UINT8 *Buffer;
- UINT32 Flag;
- UINT32 RegAddress;
- UINT32 OffsetLength;
-
- RegAddress = 0;
+ NXP_I2C_MASTER *I2c;
+ UINTN I2cBase;
+ EFI_STATUS Status;
I2c = NXP_I2C_FROM_THIS (This);
- if (RequestPacket->OperationCount <= 0) {
- DEBUG ((DEBUG_ERROR,"%a: Operation count is not valid %d\n",
- __FUNCTION__, RequestPacket->OperationCount));
- return EFI_INVALID_PARAMETER;
- }
+ I2cBase = (UINTN)(I2c->Dev->Resources[0].AddrRangeMin);
- OffsetLength = RequestPacket->Operation[0].LengthInBytes;
- RegAddress = *RequestPacket->Operation[0].Buffer;
-
- for (Count = 1; Count < RequestPacket->OperationCount; Count++) {
- Flag = RequestPacket->Operation[Count].Flags;
- Length = RequestPacket->Operation[Count].LengthInBytes;
- Buffer = RequestPacket->Operation[Count].Buffer;
-
- if (Length <= 0) {
- DEBUG ((DEBUG_ERROR,"%a: Invalid length of buffer %d\n",
- __FUNCTION__, Length));
- return EFI_INVALID_PARAMETER;
- }
-
- if (Flag == I2C_FLAG_READ) {
- RetVal = I2cDataRead (I2c->Dev->Resources[0].AddrRangeMin, SlaveAddress,
- RegAddress, OffsetLength, Buffer, Length);
- if (RetVal != EFI_SUCCESS) {
- DEBUG ((DEBUG_ERROR,"%a: I2c read operation failed (error %d)\n",
- __FUNCTION__, RetVal));
- return RetVal;
- }
- } else if (Flag == I2C_FLAG_WRITE) {
- RetVal = I2cDataWrite (I2c->Dev->Resources[0].AddrRangeMin, SlaveAddress,
- RegAddress, OffsetLength, Buffer, Length);
- if (RetVal != EFI_SUCCESS) {
- DEBUG ((DEBUG_ERROR,"%a: I2c write operation failed (error %d)\n",
- __FUNCTION__, RetVal));
- return RetVal;
- }
- } else {
- DEBUG ((DEBUG_ERROR,"%a: Invalid Flag %d\n", __FUNCTION__, Flag));
- return EFI_INVALID_PARAMETER;
- }
- }
+ Status = I2cBusXfer (I2cBase, SlaveAddress, RequestPacket);
- return EFI_SUCCESS;
+ return Status;
}
EFI_STATUS
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
index 02a29a5cf2..88316f3133 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
@@ -1,7 +1,7 @@
/** I2cDxe.h
Header defining the constant, base address amd function for I2C controller
- Copyright 2017-2019 NXP
+ Copyright 2017-2020 NXP
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -16,32 +16,6 @@
#include <Protocol/I2cMaster.h>
#include <Protocol/NonDiscoverableDevice.h>
-#define I2C_CR_IIEN (1 << 6)
-#define I2C_CR_MSTA (1 << 5)
-#define I2C_CR_MTX (1 << 4)
-#define I2C_CR_TX_NO_AK (1 << 3)
-#define I2C_CR_RSTA (1 << 2)
-
-#define I2C_SR_ICF (1 << 7)
-#define I2C_SR_IBB (1 << 5)
-#define I2C_SR_IAL (1 << 4)
-#define I2C_SR_IIF (1 << 1)
-#define I2C_SR_RX_NO_AK (1 << 0)
-
-#define I2C_CR_IEN (0 << 7)
-#define I2C_CR_IDIS (1 << 7)
-#define I2C_SR_IIF_CLEAR (1 << 1)
-
-#define BUS_IDLE (0 | (I2C_SR_IBB << 8))
-#define BUS_BUSY (I2C_SR_IBB | (I2C_SR_IBB << 8))
-#define IIF (I2C_SR_IIF | (I2C_SR_IIF << 8))
-
-#define I2C_FLAG_WRITE 0x0
-
-#define I2C_STATE_RETRIES 50000
-
-#define RETRY_COUNT 3
-
#define NXP_I2C_SIGNATURE SIGNATURE_32 ('N', 'I', '2', 'C')
#define NXP_I2C_FROM_THIS(a) CR ((a), NXP_I2C_MASTER, \
I2cMaster, NXP_I2C_SIGNATURE)
@@ -63,22 +37,6 @@ typedef struct {
NON_DISCOVERABLE_DEVICE *Dev;
} NXP_I2C_MASTER;
-/**
- Record defining i2c registers
-**/
-typedef struct {
- UINT8 I2cAdr;
- UINT8 I2cFdr;
- UINT8 I2cCr;
- UINT8 I2cSr;
- UINT8 I2cDr;
-} I2C_REGS;
-
-typedef struct {
- UINT16 SCLDivider;
- UINT16 BusClockRate;
-} CLK_DIV;
-
extern
UINT64
GetBusFrequency (
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
index 0c0bf63bb2..784139065f 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
@@ -3,7 +3,7 @@
# Component description file for I2c driver
#
# Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved.
-# Copyright 2017-2019 NXP
+# Copyright 2017-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -35,6 +35,7 @@
UefiBootServicesTableLib
UefiDriverEntryPoint
UefiLib
+ I2cLib
[Guids]
gNxpNonDiscoverableI2cMasterGuid
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 03/19] NXP/LS1043aRdb: Move Soc specific components to soc files
2020-02-07 12:43 [PATCH 00/19] ADD LX2160ARDB Platform Support Pankaj Bansal
2020-02-07 12:43 ` [PATCH 01/19] Silicon/NXP: Add I2c lib Pankaj Bansal
2020-02-07 12:43 ` [PATCH 02/19] Silicon/NXP: changes to use I2clib in i2cdxe Pankaj Bansal
@ 2020-02-07 12:43 ` Pankaj Bansal
2020-02-08 17:27 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 04/19] Silicon/NXP: Remove DuartLib and use BaseSerialPortLib16550 Pankaj Bansal
` (15 subsequent siblings)
18 siblings, 1 reply; 49+ messages in thread
From: Pankaj Bansal @ 2020-02-07 12:43 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, Varun Sethi
Cc: devel, Pankaj Bansal
Soc specific components ought to be part of Soc files and not
platform files. move the same to SOC files
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 7 +------
Platform/NXP/NxpQoriqLs.dsc.inc | 2 ++
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 8 ++++++--
3 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index c810559353..802cccdce6 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -2,7 +2,7 @@
#
# LS1043ARDB Board package.
#
-# Copyright 2017-2019 NXP
+# Copyright 2017-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -26,11 +26,7 @@
!include Silicon/NXP/LS1043A/LS1043A.dsc.inc
[LibraryClasses.common]
- SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
- ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
- SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
- IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
[PcdsFixedAtBuild.common]
@@ -46,7 +42,6 @@
#
# Board Specific Pcds
#
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc
index b28e0615f7..94d3e53a04 100644
--- a/Platform/NXP/NxpQoriqLs.dsc.inc
+++ b/Platform/NXP/NxpQoriqLs.dsc.inc
@@ -95,6 +95,8 @@
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
I2cLib|Silicon/NXP/Library/I2cLib/I2cLib.inf
+ ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
+ IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
[LibraryClasses.common.SEC]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
index dbd680b0ad..8790db6ff8 100644
--- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
@@ -1,12 +1,16 @@
# LS1043A.dsc
# LS1043A Soc package.
#
-# Copyright 2017-2019 NXP
+# Copyright 2017-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
+[LibraryClasses.common]
+ SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+ SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+
################################################################################
#
# Pcd Section - list of all EDK II PCD Entries defined by this Platform
@@ -20,6 +24,7 @@
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01402000
[PcdsFixedAtBuild.common]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
#
# CCSR Address Space and other attached Memories
@@ -57,5 +62,4 @@
#
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|TRUE
-
##
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 04/19] Silicon/NXP: Remove DuartLib and use BaseSerialPortLib16550
2020-02-07 12:43 [PATCH 00/19] ADD LX2160ARDB Platform Support Pankaj Bansal
` (2 preceding siblings ...)
2020-02-07 12:43 ` [PATCH 03/19] NXP/LS1043aRdb: Move Soc specific components to soc files Pankaj Bansal
@ 2020-02-07 12:43 ` Pankaj Bansal
2020-02-08 17:46 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 05/19] NXP/BaseSerialPortLib16550: remove SerialPortInitalize functionality Pankaj Bansal
` (14 subsequent siblings)
18 siblings, 1 reply; 49+ messages in thread
From: Pankaj Bansal @ 2020-02-07 12:43 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, Varun Sethi
Cc: devel, Pankaj Bansal
UART in LS1043A conforms to ns16550 register set. so we can use the
SerialPortLib16550 from MdeModulePkg.
We have removed the PCIe specific part from the library and also added
the APIs to get the UART clock from SOC lib instead of using the fixed
PCD.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 2 +-
.../BaseSerialPortLib16550.c | 804 ++++++++++++++++++
.../BaseSerialPortLib16550.inf | 39 +
.../BaseSerialPortLib16550.uni | 17 +
Silicon/NXP/Library/DUartPortLib/DUart.h | 122 ---
.../NXP/Library/DUartPortLib/DUartPortLib.c | 364 --------
.../NXP/Library/DUartPortLib/DUartPortLib.inf | 34 -
7 files changed, 861 insertions(+), 521 deletions(-)
create mode 100644 Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
create mode 100644 Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
create mode 100644 Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.uni
delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUart.h
delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
index 8790db6ff8..754eff396a 100644
--- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
@@ -9,7 +9,7 @@
[LibraryClasses.common]
SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
- SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+ SerialPortLib|Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
################################################################################
#
diff --git a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
new file mode 100644
index 0000000000..2c5c54ac7d
--- /dev/null
+++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
@@ -0,0 +1,804 @@
+/** @file
+ 16550 UART Serial Port library functions
+
+ (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>
+ Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2018, AMD Incorporated. All rights reserved.<BR>
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Library/SerialPortLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/BaseLib.h>
+
+//
+// 16550 UART register offsets and bitfields
+//
+#define R_UART_RXBUF 0 // LCR_DLAB = 0
+#define R_UART_TXBUF 0 // LCR_DLAB = 0
+#define R_UART_BAUD_LOW 0 // LCR_DLAB = 1
+#define R_UART_BAUD_HIGH 1 // LCR_DLAB = 1
+#define R_UART_IER 1 // LCR_DLAB = 0
+#define R_UART_FCR 2
+#define B_UART_FCR_FIFOE BIT0
+#define B_UART_FCR_FIFO64 BIT5
+#define R_UART_LCR 3
+#define B_UART_LCR_DLAB BIT7
+#define R_UART_MCR 4
+#define B_UART_MCR_DTRC BIT0
+#define B_UART_MCR_RTS BIT1
+#define R_UART_LSR 5
+#define B_UART_LSR_RXRDY BIT0
+#define B_UART_LSR_TXRDY BIT5
+#define B_UART_LSR_TEMT BIT6
+#define R_UART_MSR 6
+#define B_UART_MSR_CTS BIT4
+#define B_UART_MSR_DSR BIT5
+#define B_UART_MSR_RI BIT6
+#define B_UART_MSR_DCD BIT7
+
+extern
+UINT64
+GetBusFrequency (
+ VOID
+ );
+
+/**
+ Read an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is read from
+ MMIO space. If PcdSerialUseMmio is FALSE, then the value is read from I/O space. The
+ parameter Offset is added to the base address of the 16550 registers that is specified
+ by PcdSerialRegisterBase. PcdSerialRegisterAccessWidth specifies the MMIO space access
+ width and defaults to 8 bit access, and supports 8 or 32 bit access.
+
+ @param Base The base address register of UART device.
+ @param Offset The offset of the 16550 register to read.
+
+ @return The value read from the 16550 register.
+
+**/
+UINT8
+SerialPortReadRegister (
+ UINTN Base,
+ UINTN Offset
+ )
+{
+ return MmioRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride));
+}
+
+/**
+ Write an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is written to
+ MMIO space. If PcdSerialUseMmio is FALSE, then the value is written to I/O space. The
+ parameter Offset is added to the base address of the 16550 registers that is specified
+ by PcdSerialRegisterBase. PcdSerialRegisterAccessWidth specifies the MMIO space access
+ width and defaults to 8 bit access, and supports 8 or 32 bit access.
+
+ @param Base The base address register of UART device.
+ @param Offset The offset of the 16550 register to write.
+ @param Value The value to write to the 16550 register specified by Offset.
+
+ @return The value written to the 16550 register.
+
+**/
+UINT8
+SerialPortWriteRegister (
+ UINTN Base,
+ UINTN Offset,
+ UINT8 Value
+ )
+{
+ return MmioWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride), Value);
+}
+
+/**
+ Retrieve the I/O or MMIO base address register for the PCI UART device.
+
+ This function assumes Root Bus Numer is Zero, and enables I/O and MMIO in PCI UART
+ Device if they are not already enabled.
+
+ @return The base address register of the UART device.
+
+**/
+UINTN
+GetSerialRegisterBase (
+ VOID
+ )
+{
+ return (UINTN)PcdGet64 (PcdSerialRegisterBase);
+}
+
+/**
+ Return whether the hardware flow control signal allows writing.
+
+ @param SerialRegisterBase The base address register of UART device.
+
+ @retval TRUE The serial port is writable.
+ @retval FALSE The serial port is not writable.
+**/
+BOOLEAN
+SerialPortWritable (
+ UINTN SerialRegisterBase
+ )
+{
+ if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
+ if (PcdGetBool (PcdSerialDetectCable)) {
+ //
+ // Wait for both DSR and CTS to be set
+ // DSR is set if a cable is connected.
+ // CTS is set if it is ok to transmit data
+ //
+ // DSR CTS Description Action
+ // === === ======================================== ========
+ // 0 0 No cable connected. Wait
+ // 0 1 No cable connected. Wait
+ // 1 0 Cable connected, but not clear to send. Wait
+ // 1 1 Cable connected, and clear to send. Transmit
+ //
+ return (BOOLEAN) ((SerialPortReadRegister (SerialRegisterBase, R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) == (B_UART_MSR_DSR | B_UART_MSR_CTS));
+ } else {
+ //
+ // Wait for both DSR and CTS to be set OR for DSR to be clear.
+ // DSR is set if a cable is connected.
+ // CTS is set if it is ok to transmit data
+ //
+ // DSR CTS Description Action
+ // === === ======================================== ========
+ // 0 0 No cable connected. Transmit
+ // 0 1 No cable connected. Transmit
+ // 1 0 Cable connected, but not clear to send. Wait
+ // 1 1 Cable connected, and clar to send. Transmit
+ //
+ return (BOOLEAN) ((SerialPortReadRegister (SerialRegisterBase, R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) != (B_UART_MSR_DSR));
+ }
+ }
+
+ return TRUE;
+}
+
+/**
+ Initialize the serial device hardware.
+
+ If no initialization is required, then return RETURN_SUCCESS.
+ If the serial device was successfully initialized, then return RETURN_SUCCESS.
+ If the serial device could not be initialized, then return RETURN_DEVICE_ERROR.
+
+ @retval RETURN_SUCCESS The serial device was initialized.
+ @retval RETURN_DEVICE_ERROR The serial device could not be initialized.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortInitialize (
+ VOID
+ )
+{
+ UINTN SerialRegisterBase;
+ UINT32 Divisor;
+ UINT32 CurrentDivisor;
+ BOOLEAN Initialized;
+ UINT64 SerialClock;
+
+ //
+ // Perform platform specific initialization required to enable use of the 16550 device
+ // at the location specified by PcdSerialUseMmio and PcdSerialRegisterBase.
+ //
+ SerialClock = GetBusFrequency ();
+ if (SerialClock == 0) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ //
+ // Calculate divisor for baud generator
+ // Ref_Clk_Rate / Baud_Rate / 16
+ //
+ Divisor = SerialClock / (PcdGet32 (PcdSerialBaudRate) * 16);
+ if ((SerialClock % (PcdGet32 (PcdSerialBaudRate) * 16)) >= PcdGet32 (PcdSerialBaudRate) * 8) {
+ Divisor++;
+ }
+
+ //
+ // Get the base address of the serial port in either I/O or MMIO space
+ //
+ SerialRegisterBase = GetSerialRegisterBase ();
+ if (SerialRegisterBase == 0) {
+ return RETURN_DEVICE_ERROR;
+ }
+
+ //
+ // See if the serial port is already initialized
+ //
+ Initialized = TRUE;
+ if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & 0x3F) != (PcdGet8 (PcdSerialLineControl) & 0x3F)) {
+ Initialized = FALSE;
+ }
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) | B_UART_LCR_DLAB));
+ CurrentDivisor = SerialPortReadRegister (SerialRegisterBase, R_UART_BAUD_HIGH) << 8;
+ CurrentDivisor |= (UINT32) SerialPortReadRegister (SerialRegisterBase, R_UART_BAUD_LOW);
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & ~B_UART_LCR_DLAB));
+ if (CurrentDivisor != Divisor) {
+ Initialized = FALSE;
+ }
+ if (Initialized) {
+ return RETURN_SUCCESS;
+ }
+
+ //
+ // Wait for the serial port to be ready.
+ // Verify that both the transmit FIFO and the shift register are empty.
+ //
+ while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY));
+
+ //
+ // Configure baud rate
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, B_UART_LCR_DLAB);
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_HIGH, (UINT8) (Divisor >> 8));
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_LOW, (UINT8) (Divisor & 0xff));
+
+ //
+ // Clear DLAB and configure Data Bits, Parity, and Stop Bits.
+ // Strip reserved bits from PcdSerialLineControl
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(PcdGet8 (PcdSerialLineControl) & 0x3F));
+
+ //
+ // Enable and reset FIFOs
+ // Strip reserved bits from PcdSerialFifoControl
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, 0x00);
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64)));
+
+ //
+ // Set FIFO Polled Mode by clearing IER after setting FCR
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_IER, 0x00);
+
+ //
+ // Put Modem Control Register(MCR) into its reset state of 0x00.
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00);
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Write data from buffer to serial device.
+
+ Writes NumberOfBytes data bytes from Buffer to the serial device.
+ The number of bytes actually written to the serial device is returned.
+ If the return value is less than NumberOfBytes, then the write operation failed.
+
+ If Buffer is NULL, then ASSERT().
+
+ If NumberOfBytes is zero, then return 0.
+
+ @param Buffer Pointer to the data buffer to be written.
+ @param NumberOfBytes Number of bytes to written to the serial device.
+
+ @retval 0 NumberOfBytes is 0.
+ @retval >0 The number of bytes written to the serial device.
+ If this value is less than NumberOfBytes, then the write operation failed.
+
+**/
+UINTN
+EFIAPI
+SerialPortWrite (
+ IN UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+ )
+{
+ UINTN SerialRegisterBase;
+ UINTN Result;
+ UINTN Index;
+ UINTN FifoSize;
+
+ if (Buffer == NULL) {
+ return 0;
+ }
+
+ SerialRegisterBase = GetSerialRegisterBase ();
+ if (SerialRegisterBase ==0) {
+ return 0;
+ }
+
+ if (NumberOfBytes == 0) {
+ //
+ // Flush the hardware
+ //
+
+ //
+ // Wait for both the transmit FIFO and shift register empty.
+ //
+ while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY));
+
+ //
+ // Wait for the hardware flow control signal
+ //
+ while (!SerialPortWritable (SerialRegisterBase));
+ return 0;
+ }
+
+ //
+ // Compute the maximum size of the Tx FIFO
+ //
+ FifoSize = 1;
+ if ((PcdGet8 (PcdSerialFifoControl) & B_UART_FCR_FIFOE) != 0) {
+ if ((PcdGet8 (PcdSerialFifoControl) & B_UART_FCR_FIFO64) == 0) {
+ FifoSize = 16;
+ } else {
+ FifoSize = PcdGet32 (PcdSerialExtendedTxFifoSize);
+ }
+ }
+
+ Result = NumberOfBytes;
+ while (NumberOfBytes != 0) {
+ //
+ // Wait for the serial port to be ready, to make sure both the transmit FIFO
+ // and shift register empty.
+ //
+ while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY));
+
+ //
+ // Fill then entire Tx FIFO
+ //
+ for (Index = 0; Index < FifoSize && NumberOfBytes != 0; Index++, NumberOfBytes--, Buffer++) {
+ //
+ // Wait for the hardware flow control signal
+ //
+ while (!SerialPortWritable (SerialRegisterBase));
+
+ //
+ // Write byte to the transmit buffer.
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_TXBUF, *Buffer);
+ }
+ }
+ return Result;
+}
+
+/**
+ Reads data from a serial device into a buffer.
+
+ @param Buffer Pointer to the data buffer to store the data read from the serial device.
+ @param NumberOfBytes Number of bytes to read from the serial device.
+
+ @retval 0 NumberOfBytes is 0.
+ @retval >0 The number of bytes read from the serial device.
+ If this value is less than NumberOfBytes, then the read operation failed.
+
+**/
+UINTN
+EFIAPI
+SerialPortRead (
+ OUT UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+ )
+{
+ UINTN SerialRegisterBase;
+ UINTN Result;
+ UINT8 Mcr;
+
+ if (NULL == Buffer) {
+ return 0;
+ }
+
+ SerialRegisterBase = GetSerialRegisterBase ();
+ if (SerialRegisterBase ==0) {
+ return 0;
+ }
+
+ Mcr = (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) & ~B_UART_MCR_RTS);
+
+ for (Result = 0; NumberOfBytes-- != 0; Result++, Buffer++) {
+ //
+ // Wait for the serial port to have some data.
+ //
+ while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_RXRDY) == 0) {
+ if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
+ //
+ // Set RTS to let the peer send some data
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(Mcr | B_UART_MCR_RTS));
+ }
+ }
+ if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
+ //
+ // Clear RTS to prevent peer from sending data
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, Mcr);
+ }
+
+ //
+ // Read byte from the receive buffer.
+ //
+ *Buffer = SerialPortReadRegister (SerialRegisterBase, R_UART_RXBUF);
+ }
+
+ return Result;
+}
+
+
+/**
+ Polls a serial device to see if there is any data waiting to be read.
+
+ Polls aserial device to see if there is any data waiting to be read.
+ If there is data waiting to be read from the serial device, then TRUE is returned.
+ If there is no data waiting to be read from the serial device, then FALSE is returned.
+
+ @retval TRUE Data is waiting to be read from the serial device.
+ @retval FALSE There is no data waiting to be read from the serial device.
+
+**/
+BOOLEAN
+EFIAPI
+SerialPortPoll (
+ VOID
+ )
+{
+ UINTN SerialRegisterBase;
+
+ SerialRegisterBase = GetSerialRegisterBase ();
+ if (SerialRegisterBase ==0) {
+ return FALSE;
+ }
+
+ //
+ // Read the serial port status
+ //
+ if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_RXRDY) != 0) {
+ if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
+ //
+ // Clear RTS to prevent peer from sending data
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) & ~B_UART_MCR_RTS));
+ }
+ return TRUE;
+ }
+
+ if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
+ //
+ // Set RTS to let the peer send some data
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) | B_UART_MCR_RTS));
+ }
+
+ return FALSE;
+}
+
+/**
+ Sets the control bits on a serial device.
+
+ @param Control Sets the bits of Control that are settable.
+
+ @retval RETURN_SUCCESS The new control bits were set on the serial device.
+ @retval RETURN_UNSUPPORTED The serial device does not support this operation.
+ @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortSetControl (
+ IN UINT32 Control
+ )
+{
+ UINTN SerialRegisterBase;
+ UINT8 Mcr;
+
+ //
+ // First determine the parameter is invalid.
+ //
+ if ((Control & (~(EFI_SERIAL_REQUEST_TO_SEND | EFI_SERIAL_DATA_TERMINAL_READY |
+ EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE))) != 0) {
+ return RETURN_UNSUPPORTED;
+ }
+
+ SerialRegisterBase = GetSerialRegisterBase ();
+ if (SerialRegisterBase ==0) {
+ return RETURN_UNSUPPORTED;
+ }
+
+ //
+ // Read the Modem Control Register.
+ //
+ Mcr = SerialPortReadRegister (SerialRegisterBase, R_UART_MCR);
+ Mcr &= (~(B_UART_MCR_DTRC | B_UART_MCR_RTS));
+
+ if ((Control & EFI_SERIAL_DATA_TERMINAL_READY) == EFI_SERIAL_DATA_TERMINAL_READY) {
+ Mcr |= B_UART_MCR_DTRC;
+ }
+
+ if ((Control & EFI_SERIAL_REQUEST_TO_SEND) == EFI_SERIAL_REQUEST_TO_SEND) {
+ Mcr |= B_UART_MCR_RTS;
+ }
+
+ //
+ // Write the Modem Control Register.
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, Mcr);
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Retrieve the status of the control bits on a serial device.
+
+ @param Control A pointer to return the current control signals from the serial device.
+
+ @retval RETURN_SUCCESS The control bits were read from the serial device.
+ @retval RETURN_UNSUPPORTED The serial device does not support this operation.
+ @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortGetControl (
+ OUT UINT32 *Control
+ )
+{
+ UINTN SerialRegisterBase;
+ UINT8 Msr;
+ UINT8 Mcr;
+ UINT8 Lsr;
+
+ SerialRegisterBase = GetSerialRegisterBase ();
+ if (SerialRegisterBase ==0) {
+ return RETURN_UNSUPPORTED;
+ }
+
+ *Control = 0;
+
+ //
+ // Read the Modem Status Register.
+ //
+ Msr = SerialPortReadRegister (SerialRegisterBase, R_UART_MSR);
+
+ if ((Msr & B_UART_MSR_CTS) == B_UART_MSR_CTS) {
+ *Control |= EFI_SERIAL_CLEAR_TO_SEND;
+ }
+
+ if ((Msr & B_UART_MSR_DSR) == B_UART_MSR_DSR) {
+ *Control |= EFI_SERIAL_DATA_SET_READY;
+ }
+
+ if ((Msr & B_UART_MSR_RI) == B_UART_MSR_RI) {
+ *Control |= EFI_SERIAL_RING_INDICATE;
+ }
+
+ if ((Msr & B_UART_MSR_DCD) == B_UART_MSR_DCD) {
+ *Control |= EFI_SERIAL_CARRIER_DETECT;
+ }
+
+ //
+ // Read the Modem Control Register.
+ //
+ Mcr = SerialPortReadRegister (SerialRegisterBase, R_UART_MCR);
+
+ if ((Mcr & B_UART_MCR_DTRC) == B_UART_MCR_DTRC) {
+ *Control |= EFI_SERIAL_DATA_TERMINAL_READY;
+ }
+
+ if ((Mcr & B_UART_MCR_RTS) == B_UART_MCR_RTS) {
+ *Control |= EFI_SERIAL_REQUEST_TO_SEND;
+ }
+
+ if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
+ *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
+ }
+
+ //
+ // Read the Line Status Register.
+ //
+ Lsr = SerialPortReadRegister (SerialRegisterBase, R_UART_LSR);
+
+ if ((Lsr & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) == (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) {
+ *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
+ }
+
+ if ((Lsr & B_UART_LSR_RXRDY) == 0) {
+ *Control |= EFI_SERIAL_INPUT_BUFFER_EMPTY;
+ }
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Sets the baud rate, receive FIFO depth, transmit/receice time out, parity,
+ data bits, and stop bits on a serial device.
+
+ @param BaudRate The requested baud rate. A BaudRate value of 0 will use the
+ device's default interface speed.
+ On output, the value actually set.
+ @param ReveiveFifoDepth The requested depth of the FIFO on the receive side of the
+ serial interface. A ReceiveFifoDepth value of 0 will use
+ the device's default FIFO depth.
+ On output, the value actually set.
+ @param Timeout The requested time out for a single character in microseconds.
+ This timeout applies to both the transmit and receive side of the
+ interface. A Timeout value of 0 will use the device's default time
+ out value.
+ On output, the value actually set.
+ @param Parity The type of parity to use on this serial device. A Parity value of
+ DefaultParity will use the device's default parity value.
+ On output, the value actually set.
+ @param DataBits The number of data bits to use on the serial device. A DataBits
+ vaule of 0 will use the device's default data bit setting.
+ On output, the value actually set.
+ @param StopBits The number of stop bits to use on this serial device. A StopBits
+ value of DefaultStopBits will use the device's default number of
+ stop bits.
+ On output, the value actually set.
+
+ @retval RETURN_SUCCESS The new attributes were set on the serial device.
+ @retval RETURN_UNSUPPORTED The serial device does not support this operation.
+ @retval RETURN_INVALID_PARAMETER One or more of the attributes has an unsupported value.
+ @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortSetAttributes (
+ IN OUT UINT64 *BaudRate,
+ IN OUT UINT32 *ReceiveFifoDepth,
+ IN OUT UINT32 *Timeout,
+ IN OUT EFI_PARITY_TYPE *Parity,
+ IN OUT UINT8 *DataBits,
+ IN OUT EFI_STOP_BITS_TYPE *StopBits
+ )
+{
+ UINTN SerialRegisterBase;
+ UINT32 SerialBaudRate;
+ UINTN Divisor;
+ UINT8 Lcr;
+ UINT8 LcrData;
+ UINT8 LcrParity;
+ UINT8 LcrStop;
+ UINT64 SerialClock;
+
+ SerialRegisterBase = GetSerialRegisterBase ();
+ if (SerialRegisterBase ==0) {
+ return RETURN_UNSUPPORTED;
+ }
+
+ SerialClock = GetBusFrequency ();
+ if (SerialClock == 0) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ //
+ // Check for default settings and fill in actual values.
+ //
+ if (*BaudRate == 0) {
+ *BaudRate = PcdGet32 (PcdSerialBaudRate);
+ }
+ SerialBaudRate = (UINT32) *BaudRate;
+
+ if (*DataBits == 0) {
+ LcrData = (UINT8) (PcdGet8 (PcdSerialLineControl) & 0x3);
+ *DataBits = LcrData + 5;
+ } else {
+ if ((*DataBits < 5) || (*DataBits > 8)) {
+ return RETURN_INVALID_PARAMETER;
+ }
+ //
+ // Map 5..8 to 0..3
+ //
+ LcrData = (UINT8) (*DataBits - (UINT8) 5);
+ }
+
+ if (*Parity == DefaultParity) {
+ LcrParity = (UINT8) ((PcdGet8 (PcdSerialLineControl) >> 3) & 0x7);
+ switch (LcrParity) {
+ case 0:
+ *Parity = NoParity;
+ break;
+
+ case 3:
+ *Parity = EvenParity;
+ break;
+
+ case 1:
+ *Parity = OddParity;
+ break;
+
+ case 7:
+ *Parity = SpaceParity;
+ break;
+
+ case 5:
+ *Parity = MarkParity;
+ break;
+
+ default:
+ break;
+ }
+ } else {
+ switch (*Parity) {
+ case NoParity:
+ LcrParity = 0;
+ break;
+
+ case EvenParity:
+ LcrParity = 3;
+ break;
+
+ case OddParity:
+ LcrParity = 1;
+ break;
+
+ case SpaceParity:
+ LcrParity = 7;
+ break;
+
+ case MarkParity:
+ LcrParity = 5;
+ break;
+
+ default:
+ return RETURN_INVALID_PARAMETER;
+ }
+ }
+
+ if (*StopBits == DefaultStopBits) {
+ LcrStop = (UINT8) ((PcdGet8 (PcdSerialLineControl) >> 2) & 0x1);
+ switch (LcrStop) {
+ case 0:
+ *StopBits = OneStopBit;
+ break;
+
+ case 1:
+ if (*DataBits == 5) {
+ *StopBits = OneFiveStopBits;
+ } else {
+ *StopBits = TwoStopBits;
+ }
+ break;
+
+ default:
+ break;
+ }
+ } else {
+ switch (*StopBits) {
+ case OneStopBit:
+ LcrStop = 0;
+ break;
+
+ case OneFiveStopBits:
+ case TwoStopBits:
+ LcrStop = 1;
+ break;
+
+ default:
+ return RETURN_INVALID_PARAMETER;
+ }
+ }
+
+ //
+ // Calculate divisor for baud generator
+ // Ref_Clk_Rate / Baud_Rate / 16
+ //
+ Divisor = SerialClock / (SerialBaudRate * 16);
+ if ((SerialClock % (SerialBaudRate * 16)) >= SerialBaudRate * 8) {
+ Divisor++;
+ }
+
+ //
+ // Configure baud rate
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, B_UART_LCR_DLAB);
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_HIGH, (UINT8) (Divisor >> 8));
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_LOW, (UINT8) (Divisor & 0xff));
+
+ //
+ // Clear DLAB and configure Data Bits, Parity, and Stop Bits.
+ // Strip reserved bits from line control value
+ //
+ Lcr = (UINT8) ((LcrParity << 3) | (LcrStop << 2) | LcrData);
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8) (Lcr & 0x3F));
+
+ return RETURN_SUCCESS;
+}
+
diff --git a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
new file mode 100644
index 0000000000..45ae9dc0af
--- /dev/null
+++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
@@ -0,0 +1,39 @@
+## @file
+# SerialPortLib instance for 16550 UART.
+#
+# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright 2020 NXP
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseSerialPortLib16550
+ MODULE_UNI_FILE = BaseSerialPortLib16550.uni
+ FILE_GUID = 9E7C00CF-355A-4d4e-BF60-0428CFF95540
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.1
+ LIBRARY_CLASS = SerialPortLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+
+[LibraryClasses]
+ PcdLib
+ IoLib
+ SocLib
+
+[Sources]
+ BaseSerialPortLib16550.c
+
+[FixedPcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable ## SOMETIMES_CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride ## CONSUMES
diff --git a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.uni b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.uni
new file mode 100644
index 0000000000..2fefe85cf8
--- /dev/null
+++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.uni
@@ -0,0 +1,17 @@
+// /** @file
+// SerialPortLib instance for 16550 UART.
+//
+// SerialPortLib instance for 16550 UART.
+//
+// Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+// Copyright 2020 NXP
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "SerialPortLib instance for 16550 UART"
+
+#string STR_MODULE_DESCRIPTION #language en-US "SerialPortLib instance for 16550 UART."
+
diff --git a/Silicon/NXP/Library/DUartPortLib/DUart.h b/Silicon/NXP/Library/DUartPortLib/DUart.h
deleted file mode 100644
index c71e2ce55d..0000000000
--- a/Silicon/NXP/Library/DUartPortLib/DUart.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/** DUart.h
-* Header defining the DUART constants (Base addresses, sizes, flags)
-*
-* Based on Serial I/O Port library headers available in PL011Uart.h
-*
-* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
-* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
-* Copyright 2017 NXP
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-
-#ifndef DUART_H_
-#define DUART_H_
-
-// FIFO Control Register
-#define DUART_FCR_FIFO_EN 0x01 /* Fifo enable */
-#define DUART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
-#define DUART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
-#define DUART_FCR_DMA_SELECT 0x08 /* For DMA applications */
-#define DUART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
-#define DUART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
-#define DUART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
-#define DUART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
-#define DUART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
-#define DUART_FCR_RXSR 0x02 /* Receiver soft reset */
-#define DUART_FCR_TXSR 0x04 /* Transmitter soft reset */
-
-// Modem Control Register
-#define DUART_MCR_DTR 0x01 /* Reserved */
-#define DUART_MCR_RTS 0x02 /* RTS */
-#define DUART_MCR_OUT1 0x04 /* Reserved */
-#define DUART_MCR_OUT2 0x08 /* Reserved */
-#define DUART_MCR_LOOP 0x10 /* Enable loopback test mode */
-#define DUART_MCR_AFE 0x20 /* AFE (Auto Flow Control) */
-#define DUART_MCR_DMA_EN 0x04
-#define DUART_MCR_TX_DFR 0x08
-
-// Line Control Register
-/*
-* Note: if the word length is 5 bits (DUART_LCR_WLEN5), then setting
-* DUART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
-*/
-#define DUART_LCR_WLS_MSK 0x03 /* character length select mask */
-#define DUART_LCR_WLS_5 0x00 /* 5 bit character length */
-#define DUART_LCR_WLS_6 0x01 /* 6 bit character length */
-#define DUART_LCR_WLS_7 0x02 /* 7 bit character length */
-#define DUART_LCR_WLS_8 0x03 /* 8 bit character length */
-#define DUART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
-#define DUART_LCR_PEN 0x08 /* Parity eneble */
-#define DUART_LCR_EPS 0x10 /* Even Parity Select */
-#define DUART_LCR_STKP 0x20 /* Stick Parity */
-#define DUART_LCR_SBRK 0x40 /* Set Break */
-#define DUART_LCR_BKSE 0x80 /* Bank select enable */
-#define DUART_LCR_DLAB 0x80 /* Divisor latch access bit */
-
-// Line Status Register
-#define DUART_LSR_DR 0x01 /* Data ready */
-#define DUART_LSR_OE 0x02 /* Overrun */
-#define DUART_LSR_PE 0x04 /* Parity error */
-#define DUART_LSR_FE 0x08 /* Framing error */
-#define DUART_LSR_BI 0x10 /* Break */
-#define DUART_LSR_THRE 0x20 /* Xmit holding register empty */
-#define DUART_LSR_TEMT 0x40 /* Xmitter empty */
-#define DUART_LSR_ERR 0x80 /* Error */
-
-// Modem Status Register
-#define DUART_MSR_DCTS 0x01 /* Delta CTS */
-#define DUART_MSR_DDSR 0x02 /* Reserved */
-#define DUART_MSR_TERI 0x04 /* Reserved */
-#define DUART_MSR_DDCD 0x08 /* Reserved */
-#define DUART_MSR_CTS 0x10 /* Clear to Send */
-#define DUART_MSR_DSR 0x20 /* Reserved */
-#define DUART_MSR_RI 0x40 /* Reserved */
-#define DUART_MSR_DCD 0x80 /* Reserved */
-
-// Interrupt Identification Register
-#define DUART_IIR_NO_INT 0x01 /* No interrupts pending */
-#define DUART_IIR_ID 0x06 /* Mask for the interrupt ID */
-#define DUART_IIR_MSI 0x00 /* Modem status interrupt */
-#define DUART_IIR_THRI 0x02 /* Transmitter holding register empty */
-#define DUART_IIR_RDI 0x04 /* Receiver data interrupt */
-#define DUART_IIR_RLSI 0x06 /* Receiver line status interrupt */
-
-// Interrupt Enable Register
-#define DUART_IER_MSI 0x08 /* Enable Modem status interrupt */
-#define DUART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
-#define DUART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
-#define DUART_IER_RDI 0x01 /* Enable receiver data interrupt */
-
-// LCR defaults
-#define DUART_LCR_8N1 0x03
-#define DUART_LCRVAL DUART_LCR_8N1 /* 8 data, 1 stop, no parity */
-#define DUART_MCRVAL (DUART_MCR_DTR | \
- DUART_MCR_RTS) /* RTS/DTR */
-#define DUART_FCRVAL (DUART_FCR_FIFO_EN | \
- DUART_FCR_RXSR | \
- DUART_FCR_TXSR) /* Clear & enable FIFOs */
-
-#define URBR 0x0
-#define UTHR 0x0
-#define UDLB 0x0
-#define UDMB 0x1
-#define UIER 0x1
-#define UIIR 0x2
-#define UFCR 0x2
-#define UAFR 0x2
-#define ULCR 0x3
-#define UMCR 0x4
-#define ULSR 0x5
-#define UMSR 0x6
-#define USCR 0x7
-#define UDSR 0x10
-
-extern
-UINT64
-GetBusFrequency (
- VOID
- );
-
-#endif /* DUART_H_ */
diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
deleted file mode 100644
index c3c738d3cc..0000000000
--- a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
+++ /dev/null
@@ -1,364 +0,0 @@
-/** DuartPortLib.c
- DUART (NS16550) library functions
-
- Based on Serial I/O Port library functions available in PL011SerialPortLib.c
-
- Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
- Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.<BR>
- Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
- Copyright 2017 NXP
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <Base.h>
-#include <Library/IoLib.h>
-#include <Library/PcdLib.h>
-#include <Library/SerialPortLib.h>
-
-#include "DUart.h"
-
-STATIC CONST UINT32 mInvalidControlBits = (EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE | \
- EFI_SERIAL_DATA_TERMINAL_READY);
-
-/**
- Assert or deassert the control signals on a serial port.
- The following control signals are set according their bit settings :
- . Request to Send
- . Data Terminal Ready
-
- @param[in] Control The following bits are taken into account :
- . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the
- "Request To Send" control signal if this bit is
- equal to one/zero.
- . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert
- the "Data Terminal Ready" control signal if this
- bit is equal to one/zero.
- . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable
- the hardware loopback if this bit is equal to
- one/zero.
- . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.
- . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/
- disable the hardware flow control based on CTS (Clear
- To Send) and RTS (Ready To Send) control signals.
-
- @retval EFI_SUCCESS The new control bits were set on the device.
- @retval EFI_UNSUPPORTED The device does not support this operation.
-
-**/
-EFI_STATUS
-EFIAPI
-SerialPortSetControl (
- IN UINT32 Control
- )
-{
- UINT32 McrBits;
- UINTN UartBase;
-
- UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
-
- if (Control & (mInvalidControlBits)) {
- return EFI_UNSUPPORTED;
- }
-
- McrBits = MmioRead8 (UartBase + UMCR);
-
- if (Control & EFI_SERIAL_REQUEST_TO_SEND) {
- McrBits |= DUART_MCR_RTS;
- } else {
- McrBits &= ~DUART_MCR_RTS;
- }
-
- if (Control & EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE) {
- McrBits |= DUART_MCR_LOOP;
- } else {
- McrBits &= ~DUART_MCR_LOOP;
- }
-
- if (Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) {
- McrBits |= DUART_MCR_AFE;
- } else {
- McrBits &= ~DUART_MCR_AFE;
- }
-
- MmioWrite32 (UartBase + UMCR, McrBits);
-
- return EFI_SUCCESS;
-}
-
-/**
- Retrieve the status of the control bits on a serial device.
-
- @param[out] Control Status of the control bits on a serial device :
-
- . EFI_SERIAL_DATA_CLEAR_TO_SEND,
- EFI_SERIAL_DATA_SET_READY,
- EFI_SERIAL_RING_INDICATE,
- EFI_SERIAL_CARRIER_DETECT,
- EFI_SERIAL_REQUEST_TO_SEND,
- EFI_SERIAL_DATA_TERMINAL_READY
- are all related to the DTE (Data Terminal Equipment)
- and DCE (Data Communication Equipment) modes of
- operation of the serial device.
- . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the
- receive buffer is empty, 0 otherwise.
- . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the
- transmit buffer is empty, 0 otherwise.
- . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if
- the hardware loopback is enabled (the ouput feeds the
- receive buffer), 0 otherwise.
- . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if
- a loopback is accomplished by software, 0 otherwise.
- . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to
- one if the hardware flow control based on CTS (Clear
- To Send) and RTS (Ready To Send) control signals is
- enabled, 0 otherwise.
-
- @retval EFI_SUCCESS The control bits were read from the serial device.
-
-**/
-EFI_STATUS
-EFIAPI
-SerialPortGetControl (
- OUT UINT32 *Control
- )
-{
- UINT32 MsrRegister;
- UINT32 McrRegister;
- UINT32 LsrRegister;
- UINTN UartBase;
-
- UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
-
- MsrRegister = MmioRead8 (UartBase + UMSR);
- McrRegister = MmioRead8 (UartBase + UMCR);
- LsrRegister = MmioRead8 (UartBase + ULSR);
-
- *Control = 0;
-
- if ((MsrRegister & DUART_MSR_CTS) == DUART_MSR_CTS) {
- *Control |= EFI_SERIAL_CLEAR_TO_SEND;
- }
-
- if ((McrRegister & DUART_MCR_RTS) == DUART_MCR_RTS) {
- *Control |= EFI_SERIAL_REQUEST_TO_SEND;
- }
-
- if ((LsrRegister & DUART_LSR_TEMT) == DUART_LSR_TEMT) {
- *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
- }
-
- if ((McrRegister & DUART_MCR_AFE) == DUART_MCR_AFE) {
- *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
- }
-
- if ((McrRegister & DUART_MCR_LOOP) == DUART_MCR_LOOP) {
- *Control |= EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE;
- }
-
- return EFI_SUCCESS;
-}
-
-/*
- * Return Baud divisor on basis of Baudrate
- */
-UINT32
-CalculateBaudDivisor (
- IN UINT64 BaudRate
- )
-{
- UINTN DUartClk;
- UINTN FreqSystemBus;
-
- FreqSystemBus = GetBusFrequency ();
- DUartClk = FreqSystemBus/PcdGet32(PcdPlatformFreqDiv);
-
- return ((DUartClk)/(BaudRate * 16));
-}
-
-/*
- Initialise the serial port to the specified settings.
- All unspecified settings will be set to the default values.
-
- @return Always return EFI_SUCCESS or EFI_INVALID_PARAMETER.
-
- **/
-VOID
-EFIAPI
-DuartInitializePort (
- IN UINT64 BaudRate
- )
-{
- UINTN UartBase;
- UINT32 BaudDivisor;
-
- UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
- BaudDivisor = CalculateBaudDivisor (BaudRate);
-
-
- while (!(MmioRead8 (UartBase + ULSR) & DUART_LSR_TEMT));
-
- //
- // Enable and assert interrupt when new data is available on
- // external device,
- // setup data format, setup baud divisor
- //
- MmioWrite8 (UartBase + UIER, 0x1);
- MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL);
- MmioWrite8 (UartBase + UDLB, 0);
- MmioWrite8 (UartBase + UDMB, 0);
- MmioWrite8 (UartBase + ULCR, DUART_LCRVAL);
- MmioWrite8 (UartBase + UMCR, DUART_MCRVAL);
- MmioWrite8 (UartBase + UFCR, DUART_FCRVAL);
- MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL);
- MmioWrite8 (UartBase + UDLB, BaudDivisor & 0xff);
- MmioWrite8 (UartBase + UDMB, (BaudDivisor >> 8) & 0xff);
- MmioWrite8 (UartBase + ULCR, DUART_LCRVAL);
-
- return;
-}
-
-/**
- Programmed hardware of Serial port.
-
- @return Always return EFI_SUCCESS.
-
-**/
-EFI_STATUS
-EFIAPI
-SerialPortInitialize (
- VOID
- )
-{
- UINT64 BaudRate;
- BaudRate = (UINTN)PcdGet64 (PcdUartDefaultBaudRate);
-
-
- DuartInitializePort (BaudRate);
-
- return EFI_SUCCESS;
-}
-
-/**
- Write data to serial device.
-
- @param Buffer Point of data buffer which need to be written.
- @param NumberOfBytes Number of output bytes which are cached in Buffer.
-
- @retval 0 Write data failed.
- @retval !0 Actual number of bytes written to serial device.
-
-**/
-UINTN
-EFIAPI
-SerialPortWrite (
- IN UINT8 *Buffer,
- IN UINTN NumberOfBytes
- )
-{
- UINT8 *Final;
- UINTN UartBase;
-
- Final = &Buffer[NumberOfBytes];
- UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
-
- while (Buffer < Final) {
- while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_THRE) == 0);
- MmioWrite8 (UartBase + UTHR, *Buffer++);
- }
-
- return NumberOfBytes;
-}
-
-/**
- Read data from serial device and save the data in buffer.
-
- @param Buffer Point of data buffer which need to be written.
- @param NumberOfBytes Number of output bytes which are cached in Buffer.
-
- @retval 0 Read data failed.
- @retval !0 Actual number of bytes read from serial device.
-
-**/
-UINTN
-EFIAPI
-SerialPortRead (
- OUT UINT8 *Buffer,
- IN UINTN NumberOfBytes
- )
-{
- UINTN Count;
- UINTN UartBase;
-
- UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
-
- for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
- // Loop while waiting for a new char(s) to arrive in the
- // RxFIFO
- while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) == 0);
-
- *Buffer = MmioRead8 (UartBase + URBR);
- }
-
- return NumberOfBytes;
-}
-
-/**
- Check to see if any data is available to be read from the debug device.
-
- @retval EFI_SUCCESS At least one byte of data is available to be read
- @retval EFI_NOT_READY No data is available to be read
- @retval EFI_DEVICE_ERROR The serial device is not functioning properly
-
-**/
-BOOLEAN
-EFIAPI
-SerialPortPoll (
- VOID
- )
-{
- UINTN UartBase;
-
- UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
-
- return ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) != 0);
-}
-
-/**
- Set new attributes to LS1043a.
-
- @param BaudRate The baud rate of the serial device. If the baud rate is not supported,
- the speed will be reduced down to the nearest supported one and the
- variable's value will be updated accordingly.
- @param ReceiveFifoDepth The number of characters the device will buffer on input. If the specified
- value is not supported, the variable's value will be reduced down to the
- nearest supported one.
- @param Timeout If applicable, the number of microseconds the device will wait
- before timing out a Read or a Write operation.
- @param Parity If applicable, this is the EFI_PARITY_TYPE that is computed or checked
- as each character is transmitted or received. If the device does not
- support parity, the value is the default parity value.
- @param DataBits The number of data bits in each character
- @param StopBits If applicable, the EFI_STOP_BITS_TYPE number of stop bits per character.
- If the device does not support stop bits, the value is the default stop
- bit value.
-
- @retval EFI_SUCCESS All attributes were set correctly on the serial device.
-
-**/
-EFI_STATUS
-EFIAPI
-SerialPortSetAttributes (
- IN OUT UINT64 *BaudRate,
- IN OUT UINT32 *ReceiveFifoDepth,
- IN OUT UINT32 *Timeout,
- IN OUT EFI_PARITY_TYPE *Parity,
- IN OUT UINT8 *DataBits,
- IN OUT EFI_STOP_BITS_TYPE *StopBits
- )
-{
- DuartInitializePort (*BaudRate);
-
- return EFI_SUCCESS;
-}
diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
deleted file mode 100644
index 7a2fa619b0..0000000000
--- a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+++ /dev/null
@@ -1,34 +0,0 @@
-# DUartPortLib.inf
-#
-# Component description file for DUartPortLib module
-#
-# Copyright (c) 2013, Freescale Ltd. All rights reserved.
-# Copyright 2017 NXP
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-
-[Defines]
- INF_VERSION = 0x0001001A
- BASE_NAME = DUartPortLib
- FILE_GUID = c42dfe79-8de5-429e-a055-2d0a58591498
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = SerialPortLib
-
-[Sources.common]
- DUartPortLib.c
-
-[LibraryClasses]
- PcdLib
- SocLib
-
-[Packages]
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
- Silicon/NXP/NxpQoriqLs.dec
-
-[Pcd]
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
- gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 05/19] NXP/BaseSerialPortLib16550: remove SerialPortInitalize functionality
2020-02-07 12:43 [PATCH 00/19] ADD LX2160ARDB Platform Support Pankaj Bansal
` (3 preceding siblings ...)
2020-02-07 12:43 ` [PATCH 04/19] Silicon/NXP: Remove DuartLib and use BaseSerialPortLib16550 Pankaj Bansal
@ 2020-02-07 12:43 ` Pankaj Bansal
2020-02-07 12:43 ` [PATCH 06/19] Silicon/NXP: remove print information from Soc lib Pankaj Bansal
` (13 subsequent siblings)
18 siblings, 0 replies; 49+ messages in thread
From: Pankaj Bansal @ 2020-02-07 12:43 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, Varun Sethi
Cc: devel, Pankaj Bansal
SerialPortInitalize is called from DebugLib constructor. so this gets
called for each of the module in system. now, during SerialPortInitalize,
we need the Uart clock to set it's baud rate.
This Uart clock retrieval is implemented in SocLib and it usually involves
reading SysClock information (from FPGA or from clock generator)
so it's an unnecessary overhead, that can be avoided because we have
already initalized SerialPort in SEC phase.
Therefore, return SUCCESS from SerialPortInitalize everytime, without doing
anything.
In SEC phase we use SerialPortSetAttributes with default parameters to
mimic SerialPortInitalize.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
.../BaseSerialPortLib16550.c | 109 ++++--------------
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 25 +++-
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 6 +-
3 files changed, 51 insertions(+), 89 deletions(-)
diff --git a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
index 2c5c54ac7d..6b2aa46ff6 100644
--- a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
+++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
@@ -176,92 +176,6 @@ SerialPortInitialize (
VOID
)
{
- UINTN SerialRegisterBase;
- UINT32 Divisor;
- UINT32 CurrentDivisor;
- BOOLEAN Initialized;
- UINT64 SerialClock;
-
- //
- // Perform platform specific initialization required to enable use of the 16550 device
- // at the location specified by PcdSerialUseMmio and PcdSerialRegisterBase.
- //
- SerialClock = GetBusFrequency ();
- if (SerialClock == 0) {
- return EFI_DEVICE_ERROR;
- }
-
- //
- // Calculate divisor for baud generator
- // Ref_Clk_Rate / Baud_Rate / 16
- //
- Divisor = SerialClock / (PcdGet32 (PcdSerialBaudRate) * 16);
- if ((SerialClock % (PcdGet32 (PcdSerialBaudRate) * 16)) >= PcdGet32 (PcdSerialBaudRate) * 8) {
- Divisor++;
- }
-
- //
- // Get the base address of the serial port in either I/O or MMIO space
- //
- SerialRegisterBase = GetSerialRegisterBase ();
- if (SerialRegisterBase == 0) {
- return RETURN_DEVICE_ERROR;
- }
-
- //
- // See if the serial port is already initialized
- //
- Initialized = TRUE;
- if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & 0x3F) != (PcdGet8 (PcdSerialLineControl) & 0x3F)) {
- Initialized = FALSE;
- }
- SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) | B_UART_LCR_DLAB));
- CurrentDivisor = SerialPortReadRegister (SerialRegisterBase, R_UART_BAUD_HIGH) << 8;
- CurrentDivisor |= (UINT32) SerialPortReadRegister (SerialRegisterBase, R_UART_BAUD_LOW);
- SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & ~B_UART_LCR_DLAB));
- if (CurrentDivisor != Divisor) {
- Initialized = FALSE;
- }
- if (Initialized) {
- return RETURN_SUCCESS;
- }
-
- //
- // Wait for the serial port to be ready.
- // Verify that both the transmit FIFO and the shift register are empty.
- //
- while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY));
-
- //
- // Configure baud rate
- //
- SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, B_UART_LCR_DLAB);
- SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_HIGH, (UINT8) (Divisor >> 8));
- SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_LOW, (UINT8) (Divisor & 0xff));
-
- //
- // Clear DLAB and configure Data Bits, Parity, and Stop Bits.
- // Strip reserved bits from PcdSerialLineControl
- //
- SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(PcdGet8 (PcdSerialLineControl) & 0x3F));
-
- //
- // Enable and reset FIFOs
- // Strip reserved bits from PcdSerialFifoControl
- //
- SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, 0x00);
- SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64)));
-
- //
- // Set FIFO Polled Mode by clearing IER after setting FCR
- //
- SerialPortWriteRegister (SerialRegisterBase, R_UART_IER, 0x00);
-
- //
- // Put Modem Control Register(MCR) into its reset state of 0x00.
- //
- SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00);
-
return RETURN_SUCCESS;
}
@@ -785,6 +699,12 @@ SerialPortSetAttributes (
Divisor++;
}
+ //
+ // Wait for the serial port to be ready.
+ // Verify that both the transmit FIFO and the shift register are empty.
+ //
+ while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY));
+
//
// Configure baud rate
//
@@ -799,6 +719,23 @@ SerialPortSetAttributes (
Lcr = (UINT8) ((LcrParity << 3) | (LcrStop << 2) | LcrData);
SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8) (Lcr & 0x3F));
+ //
+ // Enable and reset FIFOs
+ // Strip reserved bits from PcdSerialFifoControl
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, 0x00);
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64)));
+
+ //
+ // Set FIFO Polled Mode by clearing IER after setting FCR
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_IER, 0x00);
+
+ //
+ // Put Modem Control Register(MCR) into its reset state of 0x00.
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00);
+
return RETURN_SUCCESS;
}
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
index bfb8b8cb33..5a1a7376cd 100644
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -1,7 +1,7 @@
/** @Soc.c
SoC specific Library containg functions to initialize various SoC components
- Copyright 2017-2019 NXP
+ Copyright 2017-2020 NXP
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -141,12 +141,33 @@ SocInit (
VOID
)
{
+ UINT64 BaudRate;
+ UINT32 ReceiveFifoDepth;
+ EFI_PARITY_TYPE Parity;
+ UINT8 DataBits;
+ EFI_STOP_BITS_TYPE StopBits;
+ UINT32 Timeout;
+
+ BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
+ ReceiveFifoDepth = 0; // Use default FIFO depth
+ Timeout = 0;
+ Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
+ DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
+ StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);
+
SmmuInit ();
//
// Early init serial Port to get board information.
//
- SerialPortInitialize ();
+ SerialPortSetAttributes (
+ &BaudRate,
+ &ReceiveFifoDepth,
+ &Timeout,
+ &Parity,
+ &DataBits,
+ &StopBits
+ );
DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a on %a)\n",
(CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__));
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index cb670a1279..3334d4d4f1 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -1,6 +1,6 @@
# @file
#
-# Copyright 2017-2019 NXP
+# Copyright 2017-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -36,6 +36,10 @@
GCC:*_*_*_CC_FLAGS = -DCHASSIS2
[FixedPcd]
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 06/19] Silicon/NXP: remove print information from Soc lib
2020-02-07 12:43 [PATCH 00/19] ADD LX2160ARDB Platform Support Pankaj Bansal
` (4 preceding siblings ...)
2020-02-07 12:43 ` [PATCH 05/19] NXP/BaseSerialPortLib16550: remove SerialPortInitalize functionality Pankaj Bansal
@ 2020-02-07 12:43 ` Pankaj Bansal
2020-02-10 17:09 ` [EXTERNAL] " Leif Lindholm
2020-02-07 12:43 ` [PATCH 07/19] Silicon/NXP: remove not needed components Pankaj Bansal
` (12 subsequent siblings)
18 siblings, 1 reply; 49+ messages in thread
From: Pankaj Bansal @ 2020-02-07 12:43 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, Varun Sethi
Cc: devel, Pankaj Bansal
The Soc info being printed can be removed from SOC lib.
We are in the process of implementing PEI Phase.
After PEI phase impelmentation this info would be printed in
common PEIM based on the information retrieved from PPIs.
e.g. gArmMpCoreInfoPpiGuid can be used to print cluser and
core info.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Silicon/NXP/Include/Chassis2/LsSerDes.h | 62 ----
Silicon/NXP/LS1043A/Include/SocSerDes.h | 51 ---
Silicon/NXP/Library/SocLib/Chassis.c | 337 -------------------
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 8 -
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 -
Silicon/NXP/Library/SocLib/SerDes.c | 268 ---------------
6 files changed, 727 deletions(-)
delete mode 100644 Silicon/NXP/Include/Chassis2/LsSerDes.h
delete mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h
delete mode 100644 Silicon/NXP/Library/SocLib/SerDes.c
diff --git a/Silicon/NXP/Include/Chassis2/LsSerDes.h b/Silicon/NXP/Include/Chassis2/LsSerDes.h
deleted file mode 100644
index 9afbc52239..0000000000
--- a/Silicon/NXP/Include/Chassis2/LsSerDes.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/** LsSerDes.h
- The Header file of SerDes Module for Chassis 2
-
- Copyright 2017-2019 NXP
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef LS_SERDES_H_
-#define LS_SERDES_H_
-
-#include <Uefi/UefiBaseType.h>
-
-#define SRDS_MAX_LANES 4
-
-typedef enum {
- None = 0,
- Pcie1,
- Pcie2,
- Pcie3,
- Sata,
- SgmiiFm1Dtsec1,
- SgmiiFm1Dtsec2,
- SgmiiFm1Dtsec5,
- SgmiiFm1Dtsec6,
- SgmiiFm1Dtsec9,
- SgmiiFm1Dtsec10,
- QsgmiiFm1A,
- XfiFm1Mac9,
- XfiFm1Mac10,
- Sgmii2500Fm1Dtsec2,
- Sgmii2500Fm1Dtsec5,
- Sgmii2500Fm1Dtsec9,
- Sgmii2500Fm1Dtsec10,
- SerdesPrtclCount
-} SERDES_PROTOCOL;
-
-typedef enum {
- Srds1 = 0,
- Srds2,
- SrdsMaxNum
-} SERDES_NUMBER;
-
-typedef struct {
- UINT16 Protocol;
- UINT8 SrdsLane[SRDS_MAX_LANES];
-} SERDES_CONFIG;
-
-typedef VOID
-(*SERDES_PROBE_LANES_CALLBACK) (
- IN SERDES_PROTOCOL LaneProtocol,
- IN VOID *Arg
- );
-
-VOID
-SerDesProbeLanes(
- IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
- IN VOID *Arg
- );
-
-#endif /* LS_SERDES_H_ */
diff --git a/Silicon/NXP/LS1043A/Include/SocSerDes.h b/Silicon/NXP/LS1043A/Include/SocSerDes.h
deleted file mode 100644
index 2d1c6f10f9..0000000000
--- a/Silicon/NXP/LS1043A/Include/SocSerDes.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/** @file
- The Header file of SerDes Module for LS1043A
-
- Copyright 2017-2019 NXP
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef SOC_SERDES_H_
-#define SOC_SERDES_H_
-
-#ifdef CHASSIS2
-#include <Chassis2/LsSerDes.h>
-#endif
-
-SERDES_CONFIG SerDes1ConfigTbl[] = {
- /* SerDes 1 */
- {0x1555, {XfiFm1Mac9, Pcie1, Pcie2, Pcie3 } },
- {0x2555, {Sgmii2500Fm1Dtsec9, Pcie1, Pcie2, Pcie3 } },
- {0x4555, {QsgmiiFm1A, Pcie1, Pcie2, Pcie3 } },
- {0x4558, {QsgmiiFm1A, Pcie1, Pcie2, Sata } },
- {0x1355, {XfiFm1Mac9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
- {0x2355, {Sgmii2500Fm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
- {0x3335, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, Pcie3 } },
- {0x3355, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
- {0x3358, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Sata } },
- {0x3555, {SgmiiFm1Dtsec9, Pcie1, Pcie2, Pcie3 } },
- {0x3558, {SgmiiFm1Dtsec9, Pcie1, Pcie2, Sata } },
- {0x7000, {Pcie1, Pcie1, Pcie1, Pcie1 } },
- {0x9998, {Pcie1, Pcie2, Pcie3, Sata } },
- {0x6058, {Pcie1, Pcie1, Pcie2, Sata } },
- {0x1455, {XfiFm1Mac9, QsgmiiFm1A, Pcie2, Pcie3 } },
- {0x2455, {Sgmii2500Fm1Dtsec9, QsgmiiFm1A, Pcie2, Pcie3 } },
- {0x2255, {Sgmii2500Fm1Dtsec9, Sgmii2500Fm1Dtsec2, Pcie2, Pcie3 } },
- {0x3333, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 } },
- {0x1460, {XfiFm1Mac9, QsgmiiFm1A, Pcie3, Pcie3 } },
- {0x2460, {Sgmii2500Fm1Dtsec9, QsgmiiFm1A, Pcie3, Pcie3 } },
- {0x3460, {SgmiiFm1Dtsec9, QsgmiiFm1A, Pcie3, Pcie3 } },
- {0x3455, {SgmiiFm1Dtsec9, QsgmiiFm1A, Pcie2, Pcie3 } },
- {0x9960, {Pcie1, Pcie2, Pcie3, Pcie3 } },
- {0x2233, {Sgmii2500Fm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 }},
- {0x2533, {Sgmii2500Fm1Dtsec9, Pcie1, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 } },
- {}
-};
-
-SERDES_CONFIG *SerDesConfigTbl[] = {
- SerDes1ConfigTbl
-};
-
-#endif /* SOC_SERDES_H_ */
diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
index b8a8118c5e..18a1f5e4e1 100644
--- a/Silicon/NXP/Library/SocLib/Chassis.c
+++ b/Silicon/NXP/Library/SocLib/Chassis.c
@@ -25,16 +25,6 @@
#include <DramInfo.h>
#include "NxpChassis.h"
-/*
- * Structure to list available SOCs.
- * Name, Soc Version, Number of Cores
- */
-STATIC CPU_TYPE mCpuTypeList[] = {
- CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
- CPU_TYPE_ENTRY (LS1046A, LS1046A, 4),
- CPU_TYPE_ENTRY (LS2088A, LS2088A, 8),
-};
-
UINT32
EFIAPI
GurRead (
@@ -48,235 +38,6 @@ GurRead (
}
}
-/*
- * Return the type of initiator (core or hardware accelerator)
- */
-UINT32
-InitiatorType (
- IN UINT32 Cluster,
- IN UINTN InitId
- )
-{
- CCSR_GUR *GurBase;
- UINT32 Idx;
- UINT32 Type;
-
- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
- Idx = (Cluster >> (InitId * 8)) & TP_CLUSTER_INIT_MASK;
- Type = GurRead ((UINTN)&GurBase->TpItyp[Idx]);
-
- if (Type & TP_ITYP_AV_MASK) {
- return Type;
- }
-
- return 0;
-}
-
-/*
- * Return the mask for number of cores on this SOC.
- */
-UINT32
-CpuMask (
- VOID
- )
-{
- CCSR_GUR *GurBase;
- UINTN ClusterIndex;
- UINTN Count;
- UINT32 Cluster;
- UINT32 Type;
- UINT32 Mask;
- UINTN InitiatorIndex;
-
- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
- ClusterIndex = 0;
- Count = 0;
- Mask = 0;
-
- do {
- Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
- for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
- Type = InitiatorType (Cluster, InitiatorIndex);
- if (Type) {
- if (TP_ITYP_TYPE_MASK (Type) == TP_ITYP_TYPE_ARM) {
- Mask |= 1 << Count;
- }
- Count++;
- }
- }
- ClusterIndex++;
- } while (CHECK_CLUSTER (Cluster));
-
- return Mask;
-}
-
-/*
- * Return the number of cores on this SOC.
- */
-UINTN
-CpuNumCores (
- VOID
- )
-{
- UINTN Count;
- UINTN Num;
-
- Count = 0;
- Num = CpuMask ();
-
- while (Num) {
- Count += Num & 1;
- Num >>= 1;
- }
-
- return Count;
-}
-
-/*
- * Return core's cluster
- */
-INT32
-QoriqCoreToCluster (
- IN UINTN Core
- )
-{
- CCSR_GUR *GurBase;
- UINTN ClusterIndex;
- UINTN Count;
- UINT32 Cluster;
- UINT32 Type;
- UINTN InitiatorIndex;
-
- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
- ClusterIndex = 0;
- Count = 0;
- do {
- Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
- for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
- Type = InitiatorType (Cluster, InitiatorIndex);
- if (Type) {
- if (Count == Core) {
- return ClusterIndex;
- }
- Count++;
- }
- }
- ClusterIndex++;
- } while (CHECK_CLUSTER (Cluster));
-
- return -1; // cannot identify the cluster
-}
-
-/*
- * Return the type of core i.e. A53, A57 etc of inputted
- * core number.
- */
-UINTN
-QoriqCoreToType (
- IN UINTN Core
- )
-{
- CCSR_GUR *GurBase;
- UINTN ClusterIndex;
- UINTN Count;
- UINT32 Cluster;
- UINT32 Type;
- UINTN InitiatorIndex;
-
- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
- ClusterIndex = 0;
- Count = 0;
-
- do {
- Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
- for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
- Type = InitiatorType (Cluster, InitiatorIndex);
- if (Type) {
- if (Count == Core) {
- return Type;
- }
- Count++;
- }
- }
- ClusterIndex++;
- } while (CHECK_CLUSTER (Cluster));
-
- return EFI_NOT_FOUND; /* cannot identify the cluster */
-}
-
-STATIC
-UINTN
-CpuMaskNext (
- IN UINTN Cpu,
- IN UINTN Mask
- )
-{
- for (Cpu++; !((1 << Cpu) & Mask); Cpu++);
-
- return Cpu;
-}
-
-/*
- * Print CPU information
- */
-VOID
-PrintCpuInfo (
- VOID
- )
-{
- SYS_INFO SysInfo;
- UINTN CoreIndex;
- UINTN Core;
- UINT32 Type;
- UINT32 NumCpus;
- UINT32 Mask;
- CHAR8 *CoreName;
-
- GetSysInfo (&SysInfo);
- DEBUG ((DEBUG_INIT, "Clock Configuration:"));
-
- NumCpus = CpuNumCores ();
- Mask = CpuMask ();
-
- for (CoreIndex = 0, Core = CpuMaskNext(-1, Mask);
- CoreIndex < NumCpus;
- CoreIndex++, Core = CpuMaskNext(Core, Mask))
- {
- if (!(CoreIndex % 3)) {
- DEBUG ((DEBUG_INIT, "\n "));
- }
-
- Type = TP_ITYP_VERSION (QoriqCoreToType (Core));
- switch (Type) {
- case TY_ITYP_VERSION_A7:
- CoreName = "A7";
- break;
- case TY_ITYP_VERSION_A53:
- CoreName = "A53";
- break;
- case TY_ITYP_VERSION_A57:
- CoreName = "A57";
- break;
- case TY_ITYP_VERSION_A72:
- CoreName = "A72";
- break;
- default:
- CoreName = " Unknown Core ";
- }
- DEBUG ((DEBUG_INIT, "CPU%d(%a):%-4d MHz ",
- Core, CoreName, SysInfo.FreqProcessor[Core] / MHZ));
- }
-
- DEBUG ((DEBUG_INIT, "\n Bus: %-4d MHz ", SysInfo.FreqSystemBus / MHZ));
- DEBUG ((DEBUG_INIT, "DDR: %-4d MT/s", SysInfo.FreqDdrBus / MHZ));
-
- if (SysInfo.FreqFman[0] != 0) {
- DEBUG ((DEBUG_INIT, "\n FMAN: %-4d MHz ", SysInfo.FreqFman[0] / MHZ));
- }
-
- DEBUG ((DEBUG_INIT, "\n"));
-}
-
/*
* Return system bus frequency
*/
@@ -307,77 +68,6 @@ GetSdxcFrequency (
return SocSysInfo.FreqSdhc;
}
-/*
- * Print Soc information
- */
-VOID
-PrintSoc (
- VOID
- )
-{
- CHAR8 Buf[20];
- CCSR_GUR *GurBase;
- UINTN Count;
- //
- // Svr : System Version Register
- //
- UINTN Svr;
- UINTN Ver;
-
- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
-
- Svr = GurRead ((UINTN)&GurBase->Svr);
- Ver = SVR_SOC_VER (Svr);
-
- for (Count = 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) {
- if ((mCpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
- AsciiStrCpyS (Buf, sizeof (Buf), mCpuTypeList[Count].Name);
-
- if (IS_E_PROCESSOR (Svr)) {
- AsciiStrCatS (Buf, sizeof (Buf), "E");
- }
- break;
- }
- }
-
- DEBUG ((DEBUG_INFO, "SoC: %a (0x%x); Rev %d.%d\n",
- Buf, Svr, SVR_MAJOR (Svr), SVR_MINOR (Svr)));
-
- return;
-}
-
-/*
- * Dump RCW (Reset Control Word) on console
- */
-VOID
-PrintRCW (
- VOID
- )
-{
- CCSR_GUR *Base;
- UINTN Count;
-
- Base = (VOID *)PcdGet64 (PcdGutsBaseAddr);
-
- /*
- * Display the RCW, so that no one gets confused as to what RCW
- * we're actually using for this boot.
- */
-
- DEBUG ((DEBUG_INIT, "Reset Configuration Word (RCW):"));
- for (Count = 0; Count < ARRAY_SIZE (Base->RcwSr); Count++) {
- UINT32 Rcw = SwapMmioRead32 ((UINTN)&Base->RcwSr[Count]);
-
- if ((Count % 4) == 0) {
- DEBUG ((DEBUG_INIT, "\n %08x:", Count * 4));
- }
-
- DEBUG ((DEBUG_INIT, " %08x", Rcw));
- }
-
- DEBUG ((DEBUG_INIT, "\n"));
-}
-
/*
* Setup SMMU in bypass mode
* and also set its pagesize
@@ -400,33 +90,6 @@ SmmuInit (
MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
}
-/*
- * Return current Soc Name form mCpuTypeList
- */
-CHAR8 *
-GetSocName (
- VOID
- )
-{
- UINT8 Count;
- UINTN Svr;
- UINTN Ver;
- CCSR_GUR *GurBase;
-
- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
-
- Svr = GurRead ((UINTN)&GurBase->Svr);
- Ver = SVR_SOC_VER (Svr);
-
- for (Count = 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) {
- if ((mCpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
- return (CHAR8 *)mCpuTypeList[Count].Name;
- }
- }
-
- return NULL;
-}
-
UINTN
GetDramSize (
IN VOID
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
index 5a1a7376cd..3d803716c9 100644
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -171,13 +171,5 @@ SocInit (
DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a on %a)\n",
(CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__));
- PrintCpuInfo ();
-
- //
- // Print Reset control Word
- //
- PrintRCW ();
- PrintSoc ();
-
return;
}
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index 3334d4d4f1..fe77717337 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -30,7 +30,6 @@
[Sources.common]
Chassis.c
Chassis2/Soc.c
- SerDes.c
[BuildOptions]
GCC:*_*_*_CC_FLAGS = -DCHASSIS2
diff --git a/Silicon/NXP/Library/SocLib/SerDes.c b/Silicon/NXP/Library/SocLib/SerDes.c
deleted file mode 100644
index b9909d9221..0000000000
--- a/Silicon/NXP/Library/SocLib/SerDes.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/** SerDes.c
- Provides the basic interfaces for SerDes Module
-
- Copyright 2017-2019 NXP
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifdef CHASSIS2
-#include <Chassis2/LsSerDes.h>
-#include <Chassis2/NxpSoc.h>
-#elif CHASSIS3
-#include <Chassis3/LsSerDes.h>
-#include <Chassis3/NxpSoc.h>
-#endif
-#include <Library/DebugLib.h>
-#include <SocSerDes.h>
-#include <Uefi.h>
-
-/**
- Function to get serdes Lane protocol corresponding to
- serdes protocol.
-
- @param SerDes Serdes number.
- @param Cfg Serdes Protocol.
- @param Lane Serdes Lane number.
-
- @return Serdes Lane protocol.
-
-**/
-STATIC
-SERDES_PROTOCOL
-GetSerDesPrtcl (
- IN INTN SerDes,
- IN INTN Cfg,
- IN INTN Lane
- )
-{
- SERDES_CONFIG *Config;
-
- if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
- return 0;
- }
-
- Config = SerDesConfigTbl[SerDes];
- while (Config->Protocol) {
- if (Config->Protocol == Cfg) {
- return Config->SrdsLane[Lane];
- }
- Config++;
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Function to check if inputted protocol is a valid serdes protocol.
-
- @param SerDes Serdes number.
- @param Prtcl Serdes Protocol to be verified.
-
- @return EFI_INVALID_PARAMETER Input parameter in invalid.
- @return EFI_NOT_FOUND Serdes Protocol not a valid protocol.
- @return EFI_SUCCESS Serdes Protocol is a valid protocol.
-
-**/
-STATIC
-EFI_STATUS
-CheckSerDesPrtclValid (
- IN INTN SerDes,
- IN UINT32 Prtcl
- )
-{
- SERDES_CONFIG *Config;
- INTN Cnt;
-
- if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
- return EFI_INVALID_PARAMETER;
- }
-
- Config = SerDesConfigTbl[SerDes];
- while (Config->Protocol) {
- if (Config->Protocol == Prtcl) {
- DEBUG ((DEBUG_INFO, "Protocol: %x Matched with the one in Table\n", Prtcl));
- break;
- }
- Config++;
- }
-
- if (!Config->Protocol) {
- return EFI_NOT_FOUND;
- }
-
- for (Cnt = 0; Cnt < SRDS_MAX_LANES; Cnt++) {
- if (Config->SrdsLane[Cnt] != None) {
- return EFI_SUCCESS;
- }
- }
-
- return EFI_NOT_FOUND;
-}
-
-/**
- Function to fill serdes map information.
-
- @param Srds Serdes number.
- @param SerdesProtocolMask Serdes Protocol Mask.
- @param SerdesProtocolShift Serdes Protocol shift value.
- @param SerDesPrtclMap Pointer to Serdes Protocol map.
-
-**/
-STATIC
-VOID
-LSSerDesMap (
- IN UINT32 Srds,
- IN UINT32 SerdesProtocolMask,
- IN UINT32 SerdesProtocolShift,
- OUT UINT64 *SerDesPrtclMap
- )
-{
- CCSR_GUR *Gur;
- UINT32 SrdsProt;
- INTN Lane;
- UINT32 Flag;
-
- Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);
- *SerDesPrtclMap = 0x0;
- Flag = 0;
-
- SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
- SrdsProt >>= SerdesProtocolShift;
-
- DEBUG ((DEBUG_INFO, "Using SERDES%d Protocol: %d (0x%x)\n",
- Srds + 1, SrdsProt, SrdsProt));
-
- if (EFI_SUCCESS != CheckSerDesPrtclValid (Srds, SrdsProt)) {
- DEBUG ((DEBUG_ERROR, "SERDES%d[PRTCL] = 0x%x is not valid\n",
- Srds + 1, SrdsProt));
- Flag++;
- }
-
- for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
- SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
- if (LanePrtcl >= SerdesPrtclCount) {
- DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
- Flag++;
- } else {
- *SerDesPrtclMap |= (1u << LanePrtcl);
- }
- }
-
- if (Flag) {
- DEBUG ((DEBUG_ERROR, "Could not configure SerDes module!!\n"));
- } else {
- DEBUG ((DEBUG_INFO, "Successfully configured SerDes module!!\n"));
- }
-}
-
-/**
- Get lane protocol on provided serdes lane and execute callback function.
-
- @param Srds Serdes number.
- @param SerdesProtocolMask Mask to get Serdes Protocol for Srds
- @param SerdesProtocolShift Shift value to get Serdes Protocol for Srds.
- @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
- @param Arg Pointer to Arguments to be passed to callback function.
-
-**/
-STATIC
-VOID
-SerDesInstanceProbeLanes (
- IN UINT32 Srds,
- IN UINT32 SerdesProtocolMask,
- IN UINT32 SerdesProtocolShift,
- IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
- IN VOID *Arg
- )
-{
-
- CCSR_GUR *Gur;
- UINT32 SrdsProt;
- INTN Lane;
-
- Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);;
-
- SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
- SrdsProt >>= SerdesProtocolShift;
-
- /*
- * Invoke callback for all lanes in the SerDes instance:
- */
- for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
- SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
- if ((LanePrtcl >= SerdesPrtclCount) || (LanePrtcl < None)) {
- DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
- } else if (LanePrtcl != None) {
- SerDesLaneProbeCallback (LanePrtcl, Arg);
- }
- }
-}
-
-/**
- Probe all serdes lanes for lane protocol and execute provided callback function.
-
- @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
- @param Arg Pointer to Arguments to be passed to callback function.
-
-**/
-VOID
-SerDesProbeLanes (
- IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
- IN VOID *Arg
- )
-{
- SerDesInstanceProbeLanes (Srds1,
- RCWSR_SRDS1_PRTCL_MASK,
- RCWSR_SRDS1_PRTCL_SHIFT,
- SerDesLaneProbeCallback,
- Arg);
-
- if (PcdGetBool (PcdSerdes2Enabled)) {
- SerDesInstanceProbeLanes (Srds2,
- RCWSR_SRDS2_PRTCL_MASK,
- RCWSR_SRDS2_PRTCL_SHIFT,
- SerDesLaneProbeCallback,
- Arg);
- }
-}
-
-/**
- Function to return Serdes protocol map for all serdes available on board.
-
- @param SerDesPrtclMap Pointer to Serdes protocl map.
-
-**/
-VOID
-GetSerdesProtocolMaps (
- OUT UINT64 *SerDesPrtclMap
- )
-{
- LSSerDesMap (Srds1,
- RCWSR_SRDS1_PRTCL_MASK,
- RCWSR_SRDS1_PRTCL_SHIFT,
- SerDesPrtclMap);
-
- if (PcdGetBool (PcdSerdes2Enabled)) {
- LSSerDesMap (Srds2,
- RCWSR_SRDS2_PRTCL_MASK,
- RCWSR_SRDS2_PRTCL_SHIFT,
- SerDesPrtclMap);
- }
-
-}
-
-BOOLEAN
-IsSerDesLaneProtocolConfigured (
- IN UINT64 SerDesPrtclMap,
- IN SERDES_PROTOCOL Device
- )
-{
- if ((Device >= SerdesPrtclCount) || (Device < None)) {
- ASSERT ((Device > None) && (Device < SerdesPrtclCount));
- DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol Device %d\n", Device));
- }
-
- return (SerDesPrtclMap & (1u << Device)) != 0 ;
-}
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 07/19] Silicon/NXP: remove not needed components
2020-02-07 12:43 [PATCH 00/19] ADD LX2160ARDB Platform Support Pankaj Bansal
` (5 preceding siblings ...)
2020-02-07 12:43 ` [PATCH 06/19] Silicon/NXP: remove print information from Soc lib Pankaj Bansal
@ 2020-02-07 12:43 ` Pankaj Bansal
2020-02-10 17:11 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 08/19] Silicon/NXP: Remove unnecessary PCDs Pankaj Bansal
` (11 subsequent siblings)
18 siblings, 1 reply; 49+ messages in thread
From: Pankaj Bansal @ 2020-02-07 12:43 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, Varun Sethi
Cc: devel, Pankaj Bansal
We are changing the directory structure of code.
After PEI phase impelmentation this info would be put back
into appropriate location.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Silicon/NXP/Include/Chassis2/NxpSoc.h | 314 +---------------------
Silicon/NXP/Library/SocLib/Chassis.c | 15 --
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 79 ------
3 files changed, 2 insertions(+), 406 deletions(-)
diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
index f05a813750..74330b6205 100644
--- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
+++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h
@@ -1,7 +1,7 @@
/** Soc.h
* Header defining the Base addresses, sizes, flags etc for chassis 1
*
-* Copyright 2017-2019 NXP
+* Copyright 2017-2020 NXP
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -10,22 +10,7 @@
#ifndef NXP_SOC_H_
#define NXP_SOC_H_
-#define HWA_CGA_M1_CLK_SEL 0xe0000000
-#define HWA_CGA_M1_CLK_SHIFT 29
-
-#define TP_CLUSTER_EOC_MASK 0xc0000000 /* end of clusters mask */
-#define NUM_CC_PLLS 2
#define CLK_FREQ 100000000
-#define MAX_CPUS 4
-#define NUM_FMAN 1
-#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) == 0x0)
-
-/* RCW SERDES MACRO */
-#define RCWSR_INDEX 4
-#define RCWSR_SRDS1_PRTCL_MASK 0xffff0000
-#define RCWSR_SRDS1_PRTCL_SHIFT 16
-#define RCWSR_SRDS2_PRTCL_MASK 0x0000ffff
-#define RCWSR_SRDS2_PRTCL_SHIFT 0
/* SMMU Defintions */
#define SMMU_BASE_ADDR 0x09000000
@@ -41,312 +26,17 @@
#define IDR1_PAGESIZE_MASK 0x80000000
typedef struct {
- UINTN FreqProcessor[MAX_CPUS];
UINTN FreqSystemBus;
- UINTN FreqDdrBus;
- UINTN FreqLocalBus;
- UINTN FreqSdhc;
- UINTN FreqFman[NUM_FMAN];
- UINTN FreqQman;
} SYS_INFO;
/* Device Configuration and Pin Control */
typedef struct {
- UINT32 PorSr1; /* POR status 1 */
-#define CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
- UINT32 PorSr2; /* POR status 2 */
- UINT8 Res008[0x20-0x8];
- UINT32 GppOrCr1; /* General-purpose POR configuration */
- UINT32 GppOrCr2;
- UINT32 DcfgFuseSr; /* Fuse status register */
- UINT8 Res02c[0x70-0x2c];
- UINT32 DevDisr; /* Device disable control */
- UINT32 DevDisr2; /* Device disable control 2 */
- UINT32 DevDisr3; /* Device disable control 3 */
- UINT32 DevDisr4; /* Device disable control 4 */
- UINT32 DevDisr5; /* Device disable control 5 */
- UINT32 DevDisr6; /* Device disable control 6 */
- UINT32 DevDisr7; /* Device disable control 7 */
- UINT8 Res08c[0x94-0x8c];
- UINT32 CoreDisrU; /* uppper portion for support of 64 cores */
- UINT32 CoreDisrL; /* lower portion for support of 64 cores */
- UINT8 Res09c[0xa0-0x9c];
- UINT32 Pvr; /* Processor version */
- UINT32 Svr; /* System version */
- UINT32 Mvr; /* Manufacturing version */
- UINT8 Res0ac[0xb0-0xac];
- UINT32 RstCr; /* Reset control */
- UINT32 RstRqPblSr; /* Reset request preboot loader status */
- UINT8 Res0b8[0xc0-0xb8];
- UINT32 RstRqMr1; /* Reset request mask */
- UINT8 Res0c4[0xc8-0xc4];
- UINT32 RstRqSr1; /* Reset request status */
- UINT8 Res0cc[0xd4-0xcc];
- UINT32 RstRqWdTmrL; /* Reset request WDT mask */
- UINT8 Res0d8[0xdc-0xd8];
- UINT32 RstRqWdtSrL; /* Reset request WDT status */
- UINT8 Res0e0[0xe4-0xe0];
- UINT32 BrrL; /* Boot release */
- UINT8 Res0e8[0x100-0xe8];
+ UINT8 Res0[0x100-0x00];
UINT32 RcwSr[16]; /* Reset control word status */
#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
-#define CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16
-#define CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
- UINT8 Res140[0x200-0x140];
- UINT32 ScratchRw[4]; /* Scratch Read/Write */
- UINT8 Res210[0x300-0x210];
- UINT32 ScratcHw1R[4]; /* Scratch Read (Write once) */
- UINT8 Res310[0x400-0x310];
- UINT32 CrstSr[12];
- UINT8 Res430[0x500-0x430];
- /* PCI Express n Logical I/O Device Number register */
- UINT32 DcfgCcsrPex1LiodNr;
- UINT32 DcfgCcsrPex2LiodNr;
- UINT32 DcfgCcsrPex3LiodNr;
- UINT32 DcfgCcsrPex4LiodNr;
- /* RIO n Logical I/O Device Number register */
- UINT32 DcfgCcsrRio1LiodNr;
- UINT32 DcfgCcsrRio2LiodNr;
- UINT32 DcfgCcsrRio3LiodNr;
- UINT32 DcfgCcsrRio4LiodNr;
- /* USB Logical I/O Device Number register */
- UINT32 DcfgCcsrUsb1LiodNr;
- UINT32 DcfgCcsrUsb2LiodNr;
- UINT32 DcfgCcsrUsb3LiodNr;
- UINT32 DcfgCcsrUsb4LiodNr;
- /* SD/MMC Logical I/O Device Number register */
- UINT32 DcfgCcsrSdMmc1LiodNr;
- UINT32 DcfgCcsrSdMmc2LiodNr;
- UINT32 DcfgCcsrSdMmc3LiodNr;
- UINT32 DcfgCcsrSdMmc4LiodNr;
- /* RIO Message Unit Logical I/O Device Number register */
- UINT32 DcfgCcsrRiomaintLiodNr;
- UINT8 Res544[0x550-0x544];
- UINT32 SataLiodNr[4];
- UINT8 Res560[0x570-0x560];
- UINT32 DcfgCcsrMisc1LiodNr;
- UINT32 DcfgCcsrMisc2LiodNr;
- UINT32 DcfgCcsrMisc3LiodNr;
- UINT32 DcfgCcsrMisc4LiodNr;
- UINT32 DcfgCcsrDma1LiodNr;
- UINT32 DcfgCcsrDma2LiodNr;
- UINT32 DcfgCcsrDma3LiodNr;
- UINT32 DcfgCcsrDma4LiodNr;
- UINT32 DcfgCcsrSpare1LiodNr;
- UINT32 DcfgCcsrSpare2LiodNr;
- UINT32 DcfgCcsrSpare3LiodNr;
- UINT32 DcfgCcsrSpare4LiodNr;
- UINT8 Res5a0[0x600-0x5a0];
- UINT32 DcfgCcsrPblSr;
- UINT32 PamuBypENr;
- UINT32 DmaCr1;
- UINT8 Res60c[0x610-0x60c];
- UINT32 DcfgCcsrGenSr1;
- UINT32 DcfgCcsrGenSr2;
- UINT32 DcfgCcsrGenSr3;
- UINT32 DcfgCcsrGenSr4;
- UINT32 DcfgCcsrGenCr1;
- UINT32 DcfgCcsrGenCr2;
- UINT32 DcfgCcsrGenCr3;
- UINT32 DcfgCcsrGenCr4;
- UINT32 DcfgCcsrGenCr5;
- UINT32 DcfgCcsrGenCr6;
- UINT32 DcfgCcsrGenCr7;
- UINT8 Res63c[0x658-0x63c];
- UINT32 DcfgCcsrcGenSr1;
- UINT32 DcfgCcsrcGenSr0;
- UINT8 Res660[0x678-0x660];
- UINT32 DcfgCcsrcGenCr1;
- UINT32 DcfgCcsrcGenCr0;
- UINT8 Res680[0x700-0x680];
- UINT32 DcfgCcsrSrIoPstecr;
- UINT32 DcfgCcsrDcsrCr;
- UINT8 Res708[0x740-0x708]; /* add more registers when needed */
- UINT32 TpItyp[64]; /* Topology Initiator Type Register */
- struct {
- UINT32 Upper;
- UINT32 Lower;
- } TpCluster[16];
- UINT8 Res8c0[0xa00-0x8c0]; /* add more registers when needed */
- UINT32 DcfgCcsrQmBmWarmRst;
- UINT8 Resa04[0xa20-0xa04]; /* add more registers when needed */
- UINT32 DcfgCcsrReserved0;
- UINT32 DcfgCcsrReserved1;
} CCSR_GUR;
-/* Supplemental Configuration Unit */
-typedef struct {
- UINT8 Res000[0x070-0x000];
- UINT32 Usb1Prm1Cr;
- UINT32 Usb1Prm2Cr;
- UINT32 Usb1Prm3Cr;
- UINT32 Usb2Prm1Cr;
- UINT32 Usb2Prm2Cr;
- UINT32 Usb2Prm3Cr;
- UINT32 Usb3Prm1Cr;
- UINT32 Usb3Prm2Cr;
- UINT32 Usb3Prm3Cr;
- UINT8 Res094[0x100-0x094];
- UINT32 Usb2Icid;
- UINT32 Usb3Icid;
- UINT8 Res108[0x114-0x108];
- UINT32 DmaIcid;
- UINT32 SataIcid;
- UINT32 Usb1Icid;
- UINT32 QeIcid;
- UINT32 SdhcIcid;
- UINT32 EdmaIcid;
- UINT32 EtrIcid;
- UINT32 Core0SftRst;
- UINT32 Core1SftRst;
- UINT32 Core2SftRst;
- UINT32 Core3SftRst;
- UINT8 Res140[0x158-0x140];
- UINT32 AltCBar;
- UINT32 QspiCfg;
- UINT8 Res160[0x180-0x160];
- UINT32 DmaMcr;
- UINT8 Res184[0x188-0x184];
- UINT32 GicAlign;
- UINT32 DebugIcid;
- UINT8 Res190[0x1a4-0x190];
- UINT32 SnpCnfGcr;
-#define CCSR_SCFG_SNPCNFGCR_SECRDSNP BIT31
-#define CCSR_SCFG_SNPCNFGCR_SECWRSNP BIT30
-#define CCSR_SCFG_SNPCNFGCR_SATARDSNP BIT23
-#define CCSR_SCFG_SNPCNFGCR_SATAWRSNP BIT22
-#define CCSR_SCFG_SNPCNFGCR_USB1RDSNP BIT21
-#define CCSR_SCFG_SNPCNFGCR_USB1WRSNP BIT20
-#define CCSR_SCFG_SNPCNFGCR_USB2RDSNP BIT15
-#define CCSR_SCFG_SNPCNFGCR_USB2WRSNP BIT16
-#define CCSR_SCFG_SNPCNFGCR_USB3RDSNP BIT13
-#define CCSR_SCFG_SNPCNFGCR_USB3WRSNP BIT14
- UINT8 Res1a8[0x1ac-0x1a8];
- UINT32 IntpCr;
- UINT8 Res1b0[0x204-0x1b0];
- UINT32 CoreSrEnCr;
- UINT8 Res208[0x220-0x208];
- UINT32 RvBar00;
- UINT32 RvBar01;
- UINT32 RvBar10;
- UINT32 RvBar11;
- UINT32 RvBar20;
- UINT32 RvBar21;
- UINT32 RvBar30;
- UINT32 RvBar31;
- UINT32 LpmCsr;
- UINT8 Res244[0x400-0x244];
- UINT32 QspIdQScr;
- UINT32 EcgTxcMcr;
- UINT32 SdhcIoVSelCr;
- UINT32 RcwPMuxCr0;
- /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
- *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
- *Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS
- Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS*/
-#define CCSR_SCFG_RCWPMUXCRO_SELCR_USB 0x3333
- /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
- *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
- *Setting RCW PinMux Register bits 25-27 to select IIC4_SCL
- Setting RCW PinMux Register bits 29-31 to select IIC4_SDA*/
-#define CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300
- UINT32 UsbDrvVBusSelCr;
-#define CCSR_SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
-#define CCSR_SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
-#define CCSR_SCFG_USBDRVVBUS_SELCR_USB3 0x00000003
- UINT32 UsbPwrFaultSelCr;
-#define CCSR_SCFG_USBPWRFAULT_INACTIVE 0x00000000
-#define CCSR_SCFG_USBPWRFAULT_SHARED 0x00000001
-#define CCSR_SCFG_USBPWRFAULT_DEDICATED 0x00000002
-#define CCSR_SCFG_USBPWRFAULT_USB3_SHIFT 4
-#define CCSR_SCFG_USBPWRFAULT_USB2_SHIFT 2
-#define CCSR_SCFG_USBPWRFAULT_USB1_SHIFT 0
- UINT32 UsbRefclkSelcr1;
- UINT32 UsbRefclkSelcr2;
- UINT32 UsbRefclkSelcr3;
- UINT8 Res424[0x600-0x424];
- UINT32 ScratchRw[4];
- UINT8 Res610[0x680-0x610];
- UINT32 CoreBCr;
- UINT8 Res684[0x1000-0x684];
- UINT32 Pex1MsiIr;
- UINT32 Pex1MsiR;
- UINT8 Res1008[0x2000-0x1008];
- UINT32 Pex2;
- UINT32 Pex2MsiR;
- UINT8 Res2008[0x3000-0x2008];
- UINT32 Pex3MsiIr;
- UINT32 Pex3MsiR;
-} CCSR_SCFG;
-
-#define USB_TXVREFTUNE 0x9
-#define USB_SQRXTUNE 0xFC7FFFFF
-#define USB_PCSTXSWINGFULL 0x47
-#define USB_PHY_RX_EQ_VAL_1 0x0000
-#define USB_PHY_RX_EQ_VAL_2 0x8000
-#define USB_PHY_RX_EQ_VAL_3 0x8003
-#define USB_PHY_RX_EQ_VAL_4 0x800b
-
-/*USB_PHY_SS memory map*/
-typedef struct {
- UINT16 IpIdcodeLo;
- UINT16 SupIdcodeHi;
- UINT8 Res4[0x0006-0x0004];
- UINT16 RtuneDebug;
- UINT16 RtuneStat;
- UINT16 SupSsPhase;
- UINT16 SsFreq;
- UINT8 ResE[0x0020-0x000e];
- UINT16 Ateovrd;
- UINT16 MpllOvrdInLo;
- UINT8 Res24[0x0026-0x0024];
- UINT16 SscOvrdIn;
- UINT8 Res28[0x002A-0x0028];
- UINT16 LevelOvrdIn;
- UINT8 Res2C[0x0044-0x002C];
- UINT16 ScopeCount;
- UINT8 Res46[0x0060-0x0046];
- UINT16 MpllLoopCtl;
- UINT8 Res62[0x006C-0x0062];
- UINT16 SscClkCntrl;
- UINT8 Res6E[0x2002-0x006E];
- UINT16 Lane0TxOvrdInHi;
- UINT16 Lane0TxOvrdDrvLo;
- UINT8 Res2006[0x200C-0x2006];
- UINT16 Lane0RxOvrdInHi;
- UINT8 Res200E[0x2022-0x200E];
- UINT16 Lane0TxCmWaitTimeOvrd;
- UINT8 Res2024[0x202A-0x2024];
- UINT16 Lane0TxLbertCtl;
- UINT16 Lane0RxLbertCtl;
- UINT16 Lane0RxLbertErr;
- UINT8 Res2030[0x205A-0x2030];
- UINT16 Lane0TxAltBlock;
-} CCSR_USB_PHY;
-
-/* Clocking */
-typedef struct {
- struct {
- UINT32 ClkCnCSr; /* core cluster n clock control status */
- UINT8 Res004[0x0c];
- UINT32 ClkcGHwAcSr; /* Clock generator n hardware accelerator */
- UINT8 Res014[0x0c];
- } ClkcSr[4];
- UINT8 Res040[0x780]; /* 0x100 */
- struct {
- UINT32 PllCnGSr;
- UINT8 Res804[0x1c];
- } PllCgSr[NUM_CC_PLLS];
- UINT8 Res840[0x1c0];
- UINT32 ClkPCSr; /* 0xa00 Platform clock domain control/status */
- UINT8 Resa04[0x1fc];
- UINT32 PllPGSr; /* 0xc00 Platform PLL General Status */
- UINT8 Resc04[0x1c];
- UINT32 PllDGSr; /* 0xc20 DDR PLL General Status */
- UINT8 Resc24[0x3dc];
-} CCSR_CLOCK;
-
VOID
GetSysInfo (
OUT SYS_INFO *
diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
index 18a1f5e4e1..847331a631 100644
--- a/Silicon/NXP/Library/SocLib/Chassis.c
+++ b/Silicon/NXP/Library/SocLib/Chassis.c
@@ -53,21 +53,6 @@ GetBusFrequency (
return SocSysInfo.FreqSystemBus;
}
-/*
- * Return SDXC bus frequency
- */
-UINT64
-GetSdxcFrequency (
- VOID
- )
-{
- SYS_INFO SocSysInfo;
-
- GetSysInfo (&SocSysInfo);
-
- return SocSysInfo.FreqSdhc;
-}
-
/*
* Setup SMMU in bypass mode
* and also set its pagesize
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
index 3d803716c9..9baeb17ecf 100644
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -32,38 +32,14 @@ GetSysInfo (
)
{
CCSR_GUR *GurBase;
- CCSR_CLOCK *ClkBase;
- UINTN CpuIndex;
- UINT32 TempRcw;
- UINT32 CPllSel;
- UINT32 CplxPll;
- CONST UINT8 CoreCplxPll[8] = {
- [0] = 0, /* CC1 PPL / 1 */
- [1] = 0, /* CC1 PPL / 2 */
- [4] = 1, /* CC2 PPL / 1 */
- [5] = 1, /* CC2 PPL / 2 */
- };
-
- CONST UINT8 CoreCplxPllDivisor[8] = {
- [0] = 1, /* CC1 PPL / 1 */
- [1] = 2, /* CC1 PPL / 2 */
- [4] = 1, /* CC2 PPL / 1 */
- [5] = 2, /* CC2 PPL / 2 */
- };
-
- UINTN PllCount;
- UINTN FreqCPll[NUM_CC_PLLS];
- UINTN PllRatio[NUM_CC_PLLS];
UINTN SysClk;
GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
- ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
SysClk = CLK_FREQ;
SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
PtrSysInfo->FreqSystemBus = SysClk;
- PtrSysInfo->FreqDdrBus = SysClk;
//
// selects the platform clock:SYSCLK ratio and calculate
@@ -72,61 +48,6 @@ GetSysInfo (
PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
- //
- // selects the DDR PLL:SYSCLK Ratio and calculate DDR frequency
- //
- PtrSysInfo->FreqDdrBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
- CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
- CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
-
- for (PllCount = 0; PllCount < NUM_CC_PLLS; PllCount++) {
- PllRatio[PllCount] = (GurRead ((UINTN)&ClkBase->PllCgSr[PllCount].PllCnGSr) >> 1) & 0xff;
- if (PllRatio[PllCount] > 4) {
- FreqCPll[PllCount] = SysClk * PllRatio[PllCount];
- } else {
- FreqCPll[PllCount] = PtrSysInfo->FreqSystemBus * PllRatio[PllCount];
- }
- }
-
- //
- // Calculate Core frequency
- //
- for (CpuIndex = 0; CpuIndex < MAX_CPUS; CpuIndex++) {
- CPllSel = (GurRead ((UINTN)&ClkBase->ClkcSr[CpuIndex].ClkCnCSr) >> 27) & 0xf;
- CplxPll = CoreCplxPll[CPllSel];
-
- PtrSysInfo->FreqProcessor[CpuIndex] = FreqCPll[CplxPll] / CoreCplxPllDivisor[CPllSel];
- }
-
- //
- // Calculate FMAN frequency
- //
- TempRcw = GurRead ((UINTN)&GurBase->RcwSr[7]);
- switch ((TempRcw & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
- case 2:
- PtrSysInfo->FreqFman[0] = FreqCPll[0] / 2;
- break;
- case 3:
- PtrSysInfo->FreqFman[0] = FreqCPll[0] / 3;
- break;
- case 4:
- PtrSysInfo->FreqFman[0] = FreqCPll[0] / 4;
- break;
- case 5:
- PtrSysInfo->FreqFman[0] = PtrSysInfo->FreqSystemBus;
- break;
- case 6:
- PtrSysInfo->FreqFman[0] = FreqCPll[1] / 2;
- break;
- case 7:
- PtrSysInfo->FreqFman[0] = FreqCPll[1] / 3;
- break;
- default:
- DEBUG ((DEBUG_WARN, "Error: Unknown FMan1 clock select!\n"));
- break;
- }
- PtrSysInfo->FreqSdhc = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
- PtrSysInfo->FreqQman = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
}
/**
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 08/19] Silicon/NXP: Remove unnecessary PCDs
2020-02-07 12:43 [PATCH 00/19] ADD LX2160ARDB Platform Support Pankaj Bansal
` (6 preceding siblings ...)
2020-02-07 12:43 ` [PATCH 07/19] Silicon/NXP: remove not needed components Pankaj Bansal
@ 2020-02-07 12:43 ` Pankaj Bansal
2020-02-10 17:32 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 09/19] Silicon/NXP: Move dsc file Pankaj Bansal
` (10 subsequent siblings)
18 siblings, 1 reply; 49+ messages in thread
From: Pankaj Bansal @ 2020-02-07 12:43 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, Varun Sethi
Cc: devel, Pankaj Bansal
There is no need to keep SOC specific PCDs defined for each SOC.
we can do away with these PCDs.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
.../Drivers/PlatformDxe/PlatformDxe.c | 15 +--
.../Drivers/PlatformDxe/PlatformDxe.inf | 8 +-
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 1 -
.../Library/PlatformLib/ArmPlatformLib.inf | 21 +---
.../Library/PlatformLib/NxpQoriqLsMem.c | 103 +++++++++---------
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 6 -
Silicon/NXP/Include/Chassis2/NxpSoc.h | 2 +
Silicon/NXP/LS1043A/Include/Soc.h | 44 ++++++++
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 32 ------
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 2 +-
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 4 -
Silicon/NXP/NxpQoriqLs.dec | 74 -------------
12 files changed, 108 insertions(+), 204 deletions(-)
create mode 100644 Silicon/NXP/LS1043A/Include/Soc.h
diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
index f89dcdeff3..62c400eb1a 100644
--- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
+++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
@@ -1,7 +1,7 @@
/** @file
LS1043 DXE platform driver.
- Copyright 2018-2019 NXP
+ Copyright 2018-2020 NXP
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -14,6 +14,7 @@
#include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
+#include <Soc.h>
#include <Protocol/NonDiscoverableDevice.h>
@@ -22,7 +23,7 @@ typedef struct {
UINT8 EndDesc;
} ADDRESS_SPACE_DESCRIPTOR;
-STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[FixedPcdGet64 (PcdNumI2cController)];
+STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[LS1043A_I2C_NUM_CONTROLLERS];
STATIC
EFI_STATUS
@@ -65,19 +66,19 @@ PopulateI2cInformation (
{
UINT32 Index;
- for (Index = 0; Index < FixedPcdGet32 (PcdNumI2cController); Index++) {
+ for (Index = 0; Index < ARRAY_SIZE (mI2cDesc); Index++) {
mI2cDesc[Index].StartDesc.Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
mI2cDesc[Index].StartDesc.Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
mI2cDesc[Index].StartDesc.ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
mI2cDesc[Index].StartDesc.GenFlag = 0;
mI2cDesc[Index].StartDesc.SpecificFlag = 0;
mI2cDesc[Index].StartDesc.AddrSpaceGranularity = 32;
- mI2cDesc[Index].StartDesc.AddrRangeMin = FixedPcdGet64 (PcdI2c0BaseAddr) +
- (Index * FixedPcdGet32 (PcdI2cSize));
+ mI2cDesc[Index].StartDesc.AddrRangeMin = LS1043A_I2C0_PHYS_ADDRESS +
+ (Index * LS1043A_I2C_SIZE);
mI2cDesc[Index].StartDesc.AddrRangeMax = mI2cDesc[Index].StartDesc.AddrRangeMin +
- FixedPcdGet32 (PcdI2cSize) - 1;
+ LS1043A_I2C_SIZE - 1;
mI2cDesc[Index].StartDesc.AddrTranslationOffset = 0;
- mI2cDesc[Index].StartDesc.AddrLen = FixedPcdGet32 (PcdI2cSize);
+ mI2cDesc[Index].StartDesc.AddrLen = LS1043A_I2C_SIZE;
mI2cDesc[Index].EndDesc = ACPI_END_TAG_DESCRIPTOR;
}
diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
index d689cf4db5..126a1174fa 100644
--- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
@@ -2,7 +2,7 @@
#
# Component description file for LS1043 DXE platform driver.
#
-# Copyright 2018-2019 NXP
+# Copyright 2018-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -25,6 +25,7 @@
MdeModulePkg/MdeModulePkg.dec
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
Silicon/NXP/NxpQoriqLs.dec
+ Silicon/NXP/LS1043A/LS1043A.dec
[LibraryClasses]
BaseLib
@@ -43,10 +44,5 @@
gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES
gDs1307RealTimeClockLibI2cMasterProtocolGuid ## PRODUCES
-[FixedPcd]
- gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
- gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
-
[Depex]
TRUE
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index 802cccdce6..74a1948fc6 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -42,7 +42,6 @@
#
# Board Specific Pcds
#
- gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
#
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
index f7ae74afc6..054dc4d003 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -1,7 +1,7 @@
# @file
#
# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
-# Copyright 2017, 2019 NXP
+# Copyright 2017, 2019-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -20,6 +20,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
Silicon/NXP/NxpQoriqLs.dec
+ Silicon/NXP/LS1043A/LS1043A.dec
[LibraryClasses]
ArmLib
@@ -35,21 +36,3 @@
[FixedPcd]
gArmTokenSpaceGuid.PcdArmPrimaryCore
- gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
- gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize
- gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
index c6c256da07..3a72c8bdd8 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
@@ -6,7 +6,7 @@
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
-* Copyright 2017, 2019 NXP
+* Copyright 2017, 2019-2020 NXP
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -16,7 +16,7 @@
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/MemoryAllocationLib.h>
-#include <DramInfo.h>
+#include <Soc.h>
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
@@ -38,7 +38,6 @@ ArmPlatformGetVirtualMemoryMap (
{
UINTN Index;
ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
- DRAM_INFO DramInfo;
Index = 0;
@@ -51,25 +50,21 @@ ArmPlatformGetVirtualMemoryMap (
return;
}
- if (GetDramBankInfo (&DramInfo)) {
- DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n"));
- return;
- }
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_DRAM0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_DRAM0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_DRAM0_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
-
- for (Index = 0; Index < DramInfo.NumOfDrams; Index++) {
- // DRAM1 (Must be 1st entry)
- VirtualMemoryTable[Index].PhysicalBase = DramInfo.DramRegion[Index].BaseAddress;
- VirtualMemoryTable[Index].VirtualBase = DramInfo.DramRegion[Index].BaseAddress;
- VirtualMemoryTable[Index].Length = DramInfo.DramRegion[Index].Size;
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
- }
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_DRAM1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_DRAM1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_DRAM1_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
// CCSR Space
- VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdCcsrBaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdCcsrBaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_CCSR_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_CCSR_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_CCSR_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// IFC region 1
//
@@ -85,60 +80,60 @@ ArmPlatformGetVirtualMemoryMap (
// For write transactions from non-core masters (like system DMA), the address
// should be 16 byte aligned and the data size should be multiple of 16 bytes.
//
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion1Size);
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_IFC0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_IFC0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_IFC0_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// QMAN SWP
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQmanSwpSize);
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_QMAN_SW_PORTAL_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
// BMAN SWP
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdBmanSwpSize);
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_QMAN_SW_PORTAL_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
// IFC region 2
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion2Size);
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_IFC1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_IFC1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_IFC1_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// PCIe1
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp1BaseSize);
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_PCI0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// PCIe2
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp2BaseSize);
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_PCI1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// PCIe3
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp3BaseSize);
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_PCI2_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI2_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// QSPI region
- VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
- VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
- VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegionSize);
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+ VirtualMemoryTable[Index].PhysicalBase = LS1043A_QSPI_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LS1043A_QSPI_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LS1043A_QSPI_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
// End of Table
- VirtualMemoryTable[++Index].PhysicalBase = 0;
+ VirtualMemoryTable[Index].PhysicalBase = 0;
VirtualMemoryTable[Index].VirtualBase = 0;
VirtualMemoryTable[Index].Length = 0;
- VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+ VirtualMemoryTable[Index++].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
- ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+ ASSERT (Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
*VirtualMemoryMap = VirtualMemoryTable;
}
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
index 784139065f..fc4bb618fa 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
@@ -49,11 +49,5 @@
gEdkiiNonDiscoverableDeviceProtocolGuid ## TO_START
gEfiI2cMasterProtocolGuid ## BY_START
-[Pcd]
- gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed
- gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
- gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
-
[Depex]
TRUE
diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
index 74330b6205..6812beafe4 100644
--- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
+++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h
@@ -12,6 +12,8 @@
#define CLK_FREQ 100000000
+#define CHASSIS2_DCFG_ADDRESS 0x1EE0000
+
/* SMMU Defintions */
#define SMMU_BASE_ADDR 0x09000000
#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Include/Soc.h
new file mode 100644
index 0000000000..c1e00394af
--- /dev/null
+++ b/Silicon/NXP/LS1043A/Include/Soc.h
@@ -0,0 +1,44 @@
+/** @file
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef __SOC_H__
+#define __SOC_H__
+
+/**
+ Soc Memory Map
+**/
+#define LS1043A_DRAM0_PHYS_ADDRESS 0x80000000
+#define LS1043A_DRAM0_SIZE SIZE_2GB
+#define LS1043A_DRAM1_PHYS_ADDRESS 0x880000000
+#define LS1043A_DRAM1_SIZE 0x780000000 // 30 GB
+
+#define LS1043A_CCSR_PHYS_ADDRESS 0x1000000
+#define LS1043A_CCSR_SIZE 0xF000000
+
+#define LS1043A_IFC0_PHYS_ADDRESS 0x60000000
+#define LS1043A_IFC0_SIZE SIZE_512MB
+#define LS1043A_IFC1_PHYS_ADDRESS 0x620000000
+#define LS1043A_IFC1_SIZE 0xE0000000 // 3.5 GB
+
+#define LS1043A_QSPI_PHYS_ADDRESS 0x40000000
+#define LS1043A_QSPI_SIZE SIZE_512MB
+
+#define LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS 0x500000000
+#define LS1043A_QMAN_SW_PORTAL_SIZE SIZE_128MB
+#define LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS 0x508000000
+#define LS1043A_BMAN_SW_PORTAL_SIZE SIZE_128MB
+
+#define LS1043A_PCI0_PHYS_ADDRESS 0x4000000000
+#define LS1043A_PCI1_PHYS_ADDRESS 0x4800000000
+#define LS1043A_PCI2_PHYS_ADDRESS 0x5000000000
+#define LS1043A_PCI_SIZE SIZE_32GB
+
+#define LS1043A_I2C0_PHYS_ADDRESS 0x2180000
+#define LS1043A_I2C_SIZE 0x10000
+#define LS1043A_I2C_NUM_CONTROLLERS 4
+
+#endif
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
index 754eff396a..7ebbb1a495 100644
--- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
@@ -26,40 +26,8 @@
[PcdsFixedAtBuild.common]
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
- #
- # CCSR Address Space and other attached Memories
- #
- gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
- gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
- gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000
- gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA
- gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000
- gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000
- gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000
- gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000
- gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000
- gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000
- gNxpQoriqLsTokenSpaceGuid.PcdWatchdog1BaseAddr|0x02AD0000
- gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000
- gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000
- gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
- gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
-
#
# Big Endian IPs
#
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
- gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|TRUE
##
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
index 9baeb17ecf..a3dabc93d1 100644
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -34,7 +34,7 @@ GetSysInfo (
CCSR_GUR *GurBase;
UINTN SysClk;
- GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ GurBase = (CCSR_GUR *)CHASSIS2_DCFG_ADDRESS;
SysClk = CLK_FREQ;
SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index fe77717337..d8707927b7 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -40,9 +40,5 @@
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
- gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
- gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
- gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr
- gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 4a1cfb3e27..b478560450 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -22,89 +22,15 @@
gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
[PcdsFixedAtBuild.common]
- #
- # Pcds for I2C Controller
- #
- gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000001
- gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000002
-
- #
- # Pcds for base address and size
- #
- gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x0|UINT64|0x00000100
- gNxpQoriqLsTokenSpaceGuid.PcdPiFdSize|0x0|UINT32|0x00000101
- gNxpQoriqLsTokenSpaceGuid.PcdPiFdBaseAddress|0x0|UINT64|0x00000102
- gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x0|UINT64|0x00000103
- gNxpQoriqLsTokenSpaceGuid.PcdWatchdog1BaseAddr|0x0|UINT64|0x00000104
- gNxpQoriqLsTokenSpaceGuid.PcdDdrBaseAddr|0x0|UINT64|0x00000105
- gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x0|UINT64|0x00000106
- gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x0|UINT64|0x00000107
- gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x0|UINT64|0x00000108
- gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x0|UINT32|0x00000109
- gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x0|UINT64|0x0000010A
- gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0|UINT64|0x0000010B
- gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x0000010C
- gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x0000010D
- gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0|UINT64|0x0000010E
- gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0|UINT64|0x0000010F
- gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0|UINT64|0x00000110
- gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0|UINT64|0x00000111
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x0|UINT64|0x00000112
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x0|UINT64|0x00000113
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x0|UINT64|0x00000114
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x0|UINT64|0x00000115
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x0|UINT64|0x00000116
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x0|UINT64|0x00000117
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x0|UINT64|0x0000118
- gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x0|UINT64|0x0000119
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x0|UINT64|0x0000011A
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x0|UINT64|0x0000011B
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x0|UINT64|0x0000011C
- gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x0|UINT64|0x0000011D
- gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExBase|0x0|UINT64|0x0000011E
- gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExSize|0x0|UINT64|0x0000011F
- gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x0|UINT32|0x00000120
- gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x0|UINT32|0x00000121
- gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000122
- gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000123
-
- #
- # IFC PCDs
- #
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x0|UINT64|0x00000190
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x0|UINT64|0x00000191
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0|UINT64|0x00000192
- gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x0|UINT64|0x00000193
- gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x0|UINT32|0x00000194
- gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x0|UINT64|0x00000195
- gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x0|UINT64|0x00000196
-
- #
- # NV Pcd
- #
- gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase|0x0|UINT64|0x00000210
- gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize|0x0|UINT64|0x00000211
-
#
# Platform PCDs
#
gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
- gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251
-
- #
- # Clock PCDs
- #
- gNxpQoriqLsTokenSpaceGuid.PcdSysClk|0x0|UINT64|0x000002A0
- gNxpQoriqLsTokenSpaceGuid.PcdDdrClk|0x0|UINT64|0x000002A1
#
# Pcds to support Big Endian IPs
#
- gNxpQoriqLsTokenSpaceGuid.PcdMmcBigEndian|FALSE|BOOLEAN|0x0000310
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311
- gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000312
- gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|FALSE|BOOLEAN|0x00000313
- gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314
[PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 09/19] Silicon/NXP: Move dsc file
2020-02-07 12:43 [PATCH 00/19] ADD LX2160ARDB Platform Support Pankaj Bansal
` (7 preceding siblings ...)
2020-02-07 12:43 ` [PATCH 08/19] Silicon/NXP: Remove unnecessary PCDs Pankaj Bansal
@ 2020-02-07 12:43 ` Pankaj Bansal
2020-02-11 11:35 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 10/19] Platform/NXP: rename the ArmPlatformLib as per ArmPlatformPkg Pankaj Bansal
` (9 subsequent siblings)
18 siblings, 1 reply; 49+ messages in thread
From: Pankaj Bansal @ 2020-02-07 12:43 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, Varun Sethi
Cc: devel, Pankaj Bansal
As per convention being followed in edk2-platforms, keep the dec
file and dsc file together.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 2 +-
{Platform => Silicon}/NXP/NxpQoriqLs.dsc.inc | 0
2 files changed, 1 insertion(+), 1 deletion(-)
rename {Platform => Silicon}/NXP/NxpQoriqLs.dsc.inc (100%)
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index 74a1948fc6..7cffd09d7d 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -22,7 +22,7 @@
OUTPUT_DIRECTORY = Build/LS1043aRdbPkg
FLASH_DEFINITION = Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
-!include Platform/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/NxpQoriqLs.dsc.inc
!include Silicon/NXP/LS1043A/LS1043A.dsc.inc
[LibraryClasses.common]
diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
similarity index 100%
rename from Platform/NXP/NxpQoriqLs.dsc.inc
rename to Silicon/NXP/NxpQoriqLs.dsc.inc
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 10/19] Platform/NXP: rename the ArmPlatformLib as per ArmPlatformPkg
2020-02-07 12:43 [PATCH 00/19] ADD LX2160ARDB Platform Support Pankaj Bansal
` (8 preceding siblings ...)
2020-02-07 12:43 ` [PATCH 09/19] Silicon/NXP: Move dsc file Pankaj Bansal
@ 2020-02-07 12:43 ` Pankaj Bansal
2020-02-11 11:40 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 11/19] Silicon/NXP: Add Chassis Lib for Chassis2 Pankaj Bansal
` (8 subsequent siblings)
18 siblings, 1 reply; 49+ messages in thread
From: Pankaj Bansal @ 2020-02-07 12:43 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, Varun Sethi
Cc: devel, Pankaj Bansal
Keep the names and location of files as mentioned in ArmPlatformPkg.
This helps in porting the common changes (if any in future) easily.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 2 +-
.../AArch64}/NxpQoriqLsHelper.S | 2 +-
.../Library/{PlatformLib => ArmPlatformLib}/ArmPlatformLib.c | 2 +-
.../{PlatformLib => ArmPlatformLib}/ArmPlatformLib.inf | 4 ++--
.../NxpQoriqLsMem.c => ArmPlatformLib/ArmPlatformLibMem.c} | 0
5 files changed, 5 insertions(+), 5 deletions(-)
rename Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib => ArmPlatformLib/AArch64}/NxpQoriqLsHelper.S (88%)
rename Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib => ArmPlatformLib}/ArmPlatformLib.c (93%)
rename Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib => ArmPlatformLib}/ArmPlatformLib.inf (89%)
rename Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib/NxpQoriqLsMem.c => ArmPlatformLib/ArmPlatformLibMem.c} (100%)
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index 7cffd09d7d..bc6fa4f19d 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -26,7 +26,7 @@
!include Silicon/NXP/LS1043A/LS1043A.dsc.inc
[LibraryClasses.common]
- ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+ ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
[PcdsFixedAtBuild.common]
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/NxpQoriqLsHelper.S
similarity index 88%
rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/NxpQoriqLsHelper.S
index 84ee8c9f97..dfbf73675a 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/NxpQoriqLsHelper.S
@@ -1,7 +1,7 @@
# @file
#
# Copyright (c) 2012-2013, ARM Limited. All rights reserved.
-# Copyright 2017 NXP
+# Copyright 2017, 2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
similarity index 93%
rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
index eac7d4aa4e..718c71bf02 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -6,7 +6,7 @@
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
-* Copyright 2017 NXP
+* Copyright 2017, 2020 NXP
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
similarity index 89%
rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
index 054dc4d003..6396d2982b 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -27,8 +27,8 @@
SocLib
[Sources.common]
- NxpQoriqLsHelper.S | GCC
- NxpQoriqLsMem.c
+ AArch64/NxpQoriqLsHelper.S | GCC
+ ArmPlatformLibMem.c
ArmPlatformLib.c
[Ppis]
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
similarity index 100%
rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 11/19] Silicon/NXP: Add Chassis Lib for Chassis2
2020-02-07 12:43 [PATCH 00/19] ADD LX2160ARDB Platform Support Pankaj Bansal
` (9 preceding siblings ...)
2020-02-07 12:43 ` [PATCH 10/19] Platform/NXP: rename the ArmPlatformLib as per ArmPlatformPkg Pankaj Bansal
@ 2020-02-07 12:43 ` Pankaj Bansal
2020-02-11 12:28 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 12/19] Silicon/NXP/LS1043A: Add SocLib Pankaj Bansal
` (7 subsequent siblings)
18 siblings, 1 reply; 49+ messages in thread
From: Pankaj Bansal @ 2020-02-07 12:43 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, Varun Sethi
Cc: devel, Pankaj Bansal
Add ChassisLib for Chassis2.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Silicon/NXP/Chassis2/Chassis2.dec | 23 +++
Silicon/NXP/Chassis2/Chassis2.dsc.inc | 10 +
Silicon/NXP/Chassis2/Include/Chassis.h | 42 ++++
.../Chassis2/Library/ChassisLib/ChassisLib.c | 186 ++++++++++++++++++
.../Library/ChassisLib/ChassisLib.inf | 41 ++++
Silicon/NXP/Include/Library/ChassisLib.h | 41 ++++
Silicon/NXP/NxpQoriqLs.dec | 4 +
7 files changed, 347 insertions(+)
create mode 100644 Silicon/NXP/Chassis2/Chassis2.dec
create mode 100644 Silicon/NXP/Chassis2/Chassis2.dsc.inc
create mode 100644 Silicon/NXP/Chassis2/Include/Chassis.h
create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
create mode 100644 Silicon/NXP/Include/Library/ChassisLib.h
diff --git a/Silicon/NXP/Chassis2/Chassis2.dec b/Silicon/NXP/Chassis2/Chassis2.dec
new file mode 100644
index 0000000000..106b118188
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Chassis2.dec
@@ -0,0 +1,23 @@
+#/** @file
+# NXP Layerscape processor package.
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 1.27
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
+
diff --git a/Silicon/NXP/Chassis2/Chassis2.dsc.inc b/Silicon/NXP/Chassis2/Chassis2.dsc.inc
new file mode 100644
index 0000000000..db8e5a92ea
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Chassis2.dsc.inc
@@ -0,0 +1,10 @@
+# @file
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[LibraryClasses.common]
+ ChassisLib|Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h b/Silicon/NXP/Chassis2/Include/Chassis.h
new file mode 100644
index 0000000000..48ba2e7bfb
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Include/Chassis.h
@@ -0,0 +1,42 @@
+/** @file
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef __CHASSIS_H__
+#define __CHASSIS_H__
+
+#define NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS 0x1EE0000
+
+#define TP_CLUSTER_ITYPE_IDX 0x3f
+#define TP_CLUSTER_EOC BIT31
+#define TP_ITYPE_AVAILABLE BIT0
+#define TP_ITYPE_TYPE(x) (((x) & 0x06) >> 1)
+#define TP_ITYPE_ARM 0x0
+#define TP_ITYPE_VERSION(x) (((x) & 0xe0) >> 5)
+
+#define TP_ITYPE_VERSION_A53 0x2
+#define TP_ITYPE_VERSION_A72 0x4
+
+/**
+ The Device Configuration Unit provides general purpose configuration and status for the
+ device. These registers only support 32-bit accesses.
+**/
+#pragma pack(1)
+typedef struct {
+ UINT8 Reserved0[0x100 - 0x0];
+ UINT32 RcwSr[16]; // Reset Control Word Status Register
+ UINT8 Reserved140[0x200 - 0x140];
+ UINT32 ScratchRw[16]; /// Scratch Read / Write Register
+ UINT8 Reserved240[0x740-0x240];
+ UINT32 TpItyp[65]; /// Topology Initiator Type Register
+ struct {
+ UINT32 Lower;
+ UINT32 Upper;
+ }TpCluster[8];
+} NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG;
+#pragma pack()
+
+#endif
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
new file mode 100644
index 0000000000..fa6a36e96f
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
@@ -0,0 +1,186 @@
+/** @file
+ Chassis specific functions common to all SOCs based on a specific Chessis
+
+ Copyright 2020 NXP
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Chassis.h>
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/IoAccessLib.h>
+#include <Library/PcdLib.h>
+#include <Library/SerialPortLib.h>
+#include <Ppi/ArmMpCoreInfo.h>
+
+UINT32
+EFIAPI
+DcfgRead32 (
+ IN UINTN Address
+ )
+{
+ if (FeaturePcdGet (PcdDcfgBigEndian)) {
+ return SwapMmioRead32 (Address);
+ } else {
+ return MmioRead32 (Address);
+ }
+}
+
+UINT32
+EFIAPI
+DcfgWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ )
+{
+ if (FeaturePcdGet (PcdDcfgBigEndian)) {
+ return SwapMmioWrite32 (Address, Value);
+ } else {
+ return MmioWrite32 (Address, Value);
+ }
+}
+
+/**
+ Get the type of core in cluster
+
+ The core can be of type ARM or PowerPC or Hardware Accelerator.
+ If the core is enabled and of type ARM EFI_SUCCESS is returned and a code for type of ARM core is returned
+
+ @param[in] TpItypeIdx Index of Core to be searched in TpItyp in Device Config Registers.
+ @param[out] CoreType If the core is ARM core then the type of core i.e. A53/A72 etc.
+ These cores are identified based on their codes like TP_ITYPE_VERSION_A72
+
+ @return EFI_NOT_FOUND No enabled ARM core found
+ @return EFI_SUCCESS An enabled ARM core found
+**/
+STATIC
+EFI_STATUS
+SocGetCoreType (
+ IN UINT8 TpItypeIdx,
+ OUT UINT8 *CoreType
+ )
+{
+ NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG *Dcfg;
+ UINT32 TpItype;
+
+ Dcfg = (NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG *)NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS;
+ TpItype = MmioRead32 ((UINTN)&Dcfg->TpItyp[TpItypeIdx]);
+ if (TpItype & TP_ITYPE_AVAILABLE) {
+ if (TP_ITYPE_TYPE (TpItype) == TP_ITYPE_ARM) {
+ *CoreType = TP_ITYPE_VERSION (TpItype);
+ } else {
+ return EFI_NOT_FOUND;
+ }
+ } else {
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Return the number of cores present in SOC
+
+ This function returns the number of cores present in SOC.
+ and also their position (cluster number and core number) in the form of ARM_CORE_INFO array
+ and NxpCoreTable array.
+ NxpCoreTable array can be used to find out the type of core. it's values are of type
+ TP_ITYPE_VERSION_*.
+ The number of cores present in SOC can vary depending on which flavour of SOC is being used.
+ This function doesn't allocte any memory and must be provided memory for array of ARM_CORE_INFO
+ and NxpCoreTable for maximum number of cores the SOC can have.
+
+ @param[out] NxpCoreTable array of UINT8 for maximum number of cores the SOC can have.
+ @param[out] ArmCoreTable array of ARM_CORE_INFO for maximum number of cores the SOC can have.
+ @param[in] ArmCoreTableSize Size of ArmCoreTable
+
+ @return Actual number of cores present in SOC. After calling this function only the returned value number of
+ entries in ArmCoreTable are valid entries.
+**/
+UINTN
+__attribute__((weak))
+SocGetMpCoreInfo (
+ OUT UINT8 *NxpCoreTable,
+ OUT ARM_CORE_INFO *ArmCoreTable,
+ IN UINTN CoreTableSize
+ )
+{
+ NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG *Dcfg;
+ UINT32 TpClusterLower;
+ UINT8 TpClusterParser;
+ UINT8 ClusterIndex;
+ UINT8 CoreIndex;
+ UINTN CoreCount;
+ UINT8 CoreType;
+ EFI_STATUS Status;
+
+ Dcfg = (NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG *)NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS;
+ ClusterIndex = 0;
+ CoreCount = 0;
+ while (TRUE) {
+ TpClusterLower = MmioRead32 ((UINTN)&Dcfg->TpCluster[ClusterIndex].Lower);
+ for (CoreIndex = 0; CoreIndex < (sizeof (TpClusterLower) / sizeof (TpClusterParser)); CoreIndex++) {
+ TpClusterParser = (TpClusterLower >> (8 * CoreIndex));
+ Status = SocGetCoreType (TpClusterParser & TP_CLUSTER_ITYPE_IDX, &CoreType);
+ if (Status != EFI_NOT_FOUND) {
+ ArmCoreTable[CoreCount].ClusterId = ClusterIndex;
+ ArmCoreTable[CoreCount].CoreId = CoreIndex;
+ ArmCoreTable[CoreCount].MailboxSetAddress = 0;
+ ArmCoreTable[CoreCount].MailboxGetAddress = 0;
+ ArmCoreTable[CoreCount].MailboxClearAddress = 0;
+ ArmCoreTable[CoreCount].MailboxClearValue = ~0;
+
+ NxpCoreTable[CoreCount] = CoreType;
+ CoreCount++;
+ if (CoreCount == CoreTableSize) {
+ break;
+ }
+ }
+ }
+ if (TpClusterLower & TP_CLUSTER_EOC) {
+ break;
+ }
+ if (CoreCount == CoreTableSize) {
+ break;
+ }
+ ClusterIndex++;
+ }
+
+ return CoreCount;
+}
+
+/**
+ Function to initialize Chassis Specific functions
+ **/
+VOID
+ChassisInit (
+ VOID
+ )
+{
+ UINT64 BaudRate;
+ UINT32 ReceiveFifoDepth;
+ EFI_PARITY_TYPE Parity;
+ UINT8 DataBits;
+ EFI_STOP_BITS_TYPE StopBits;
+ UINT32 Timeout;
+
+ BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
+ ReceiveFifoDepth = FixedPcdGet16 (PcdUartDefaultReceiveFifoDepth); // Use default FIFO depth
+ Timeout = 0;
+ Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
+ DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
+ StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);
+
+ //
+ // Early init serial Port to get board information.
+ //
+ SerialPortSetAttributes (
+ &BaudRate,
+ &ReceiveFifoDepth,
+ &Timeout,
+ &Parity,
+ &DataBits,
+ &StopBits
+ );
+}
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
new file mode 100644
index 0000000000..4964bb4e82
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
@@ -0,0 +1,41 @@
+#/** @file
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = Chassis2Lib
+ FILE_GUID = fae0d077-5fc2-494f-b8e1-c51a3023ee3e
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ChassisLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+ Silicon/NXP/Chassis2/Chassis2.dec
+
+[LibraryClasses]
+ IoLib
+ IoAccessLib
+ PcdLib
+ SerialPortLib
+
+[Sources.common]
+ ChassisLib.c
+
+[FeaturePcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian
+
+[FixedPcd]
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth
+
diff --git a/Silicon/NXP/Include/Library/ChassisLib.h b/Silicon/NXP/Include/Library/ChassisLib.h
new file mode 100644
index 0000000000..b51b024374
--- /dev/null
+++ b/Silicon/NXP/Include/Library/ChassisLib.h
@@ -0,0 +1,41 @@
+/** @file
+ I2c Lib to control I2c controller.
+
+ Copyright 2020 NXP
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __CHASSIS_LIB_H__
+#define __CHASSIS_LIB_H__
+
+#include <Chassis.h>
+
+/**
+ Read Dcfg register
+**/
+UINT32
+EFIAPI
+DcfgRead32 (
+ IN UINTN Address
+ );
+
+/**
+ Write Dcfg register
+**/
+UINT32
+EFIAPI
+DcfgWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ );
+
+/**
+ Function to initialize Chassis Specific functions
+ **/
+VOID
+ChassisInit (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index b478560450..d8989657e6 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -14,6 +14,9 @@
Include
[LibraryClasses]
+ ## @libraryclass Provides Chassis specific functions to other modules
+ ChassisLib|Include/Library/ChassisLib.h
+
## @libraryclass Provides services to read/write to I2c devices
I2cLib|Include/Library/I2cLib.h
@@ -34,4 +37,5 @@
[PcdsFeatureFlag]
gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315
+ gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000316
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 12/19] Silicon/NXP/LS1043A: Add SocLib
2020-02-07 12:43 [PATCH 00/19] ADD LX2160ARDB Platform Support Pankaj Bansal
` (10 preceding siblings ...)
2020-02-07 12:43 ` [PATCH 11/19] Silicon/NXP: Add Chassis Lib for Chassis2 Pankaj Bansal
@ 2020-02-07 12:43 ` Pankaj Bansal
2020-02-11 12:38 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 13/19] Silicon/NXP: Move RAM retrieval from SocLib Pankaj Bansal
` (6 subsequent siblings)
18 siblings, 1 reply; 49+ messages in thread
From: Pankaj Bansal @ 2020-02-07 12:43 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, Varun Sethi
Cc: devel, Pankaj Bansal
Add SocLib for LS1043A as per new directory structure
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Silicon/NXP/Chassis2/LS1043A/Include/Soc.h | 56 +++++++++++++
Silicon/NXP/Chassis2/LS1043A/LS1043A.dec | 23 ++++++
Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc | 30 +++++++
.../Chassis2/LS1043A/Library/SocLib/SocLib.c | 73 +++++++++++++++++
.../LS1043A/Library/SocLib/SocLib.inf | 32 ++++++++
Silicon/NXP/Include/Library/SocLib.h | 81 +++++++++++++++++++
Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h | 47 +++++++++++
Silicon/NXP/NxpQoriqLs.dec | 3 +
8 files changed, 345 insertions(+)
create mode 100644 Silicon/NXP/Chassis2/LS1043A/Include/Soc.h
create mode 100644 Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
create mode 100644 Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
create mode 100644 Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
create mode 100644 Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
create mode 100644 Silicon/NXP/Include/Library/SocLib.h
create mode 100644 Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h
diff --git a/Silicon/NXP/Chassis2/LS1043A/Include/Soc.h b/Silicon/NXP/Chassis2/LS1043A/Include/Soc.h
new file mode 100644
index 0000000000..3b11b2b126
--- /dev/null
+++ b/Silicon/NXP/Chassis2/LS1043A/Include/Soc.h
@@ -0,0 +1,56 @@
+/** @file
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef __SOC_H__
+#define __SOC_H__
+
+#include <Chassis.h>
+
+/**
+ Soc Memory Map
+**/
+#define LS1043A_DRAM0_PHYS_ADDRESS 0x80000000
+#define LS1043A_DRAM0_SIZE SIZE_2GB
+#define LS1043A_DRAM1_PHYS_ADDRESS 0x880000000
+#define LS1043A_DRAM1_SIZE 0x780000000 // 30 GB
+
+#define LS1043A_CCSR_PHYS_ADDRESS 0x1000000
+#define LS1043A_CCSR_SIZE 0xF000000
+
+#define LS1043A_IFC0_PHYS_ADDRESS 0x60000000
+#define LS1043A_IFC0_SIZE SIZE_512MB
+#define LS1043A_IFC1_PHYS_ADDRESS 0x620000000
+#define LS1043A_IFC1_SIZE 0xE0000000 // 3.5 GB
+
+#define LS1043A_QSPI_PHYS_ADDRESS 0x40000000
+#define LS1043A_QSPI_SIZE SIZE_512MB
+
+#define LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS 0x500000000
+#define LS1043A_QMAN_SW_PORTAL_SIZE SIZE_128MB
+#define LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS 0x508000000
+#define LS1043A_BMAN_SW_PORTAL_SIZE SIZE_128MB
+
+#define LS1043A_PCI0_PHYS_ADDRESS 0x4000000000
+#define LS1043A_PCI1_PHYS_ADDRESS 0x4800000000
+#define LS1043A_PCI2_PHYS_ADDRESS 0x5000000000
+#define LS1043A_PCI_SIZE SIZE_32GB
+
+#define LS1043A_I2C0_PHYS_ADDRESS 0x2180000
+#define LS1043A_I2C_SIZE 0x10000
+#define LS1043A_I2C_NUM_CONTROLLERS 4
+
+#define LS1043A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS
+
+/**
+ Reset Control Word (RCW) Bits
+**/
+#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6
+
+typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1043A_DEVICE_CONFIG;
+
+#endif
+
diff --git a/Silicon/NXP/Chassis2/LS1043A/LS1043A.dec b/Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
new file mode 100644
index 0000000000..106b118188
--- /dev/null
+++ b/Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
@@ -0,0 +1,23 @@
+#/** @file
+# NXP Layerscape processor package.
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 1.27
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
+
diff --git a/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
new file mode 100644
index 0000000000..4511203443
--- /dev/null
+++ b/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
@@ -0,0 +1,30 @@
+# @file
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[LibraryClasses.common]
+ SocLib|Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFeatureFlag.common]
+ gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
+
+[PcdsFixedAtBuild.common]
+## ns16550 Serial Terminal
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x21c0500
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|4
+
+[PcdsDynamicDefault.common]
+ #
+ # ARM General Interrupt Controller
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x1401000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x1402000
+
diff --git a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
new file mode 100644
index 0000000000..2a08ad87db
--- /dev/null
+++ b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
@@ -0,0 +1,73 @@
+/** @file
+
+ Copyright 2017-2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+ **/
+#include <Library/ChassisLib.h>
+#include <Library/SocLib.h>
+
+/**
+ Return the input clock frequency to an IP Module.
+ This function reads the RCW bits and calculates the PLL multipler/divider values to be applied
+ to various IP modules.
+ If a module is disabled or doesn't exist on platform, then return zero.
+
+ @param[in] BaseClock Base clock to which PLL multipler/divider values is to be applied.
+ @param[in] ClockType IP modules whose clock value is to be retrieved
+ @param[in] Args Variable Args lists that is parsed based on the ClockType
+ e.g. if there are multiple modules of same type then this value tells the
+ instance of module for which clock is to be retrieved.
+ (e.g. if there are four i2c controllers in SOC, then this value can be 1, 2, 3, 4)
+ for IP modules which have only single instance in SOC (e.g. one QSPI controller)
+ this value can be null (i.e. no arg)
+
+ @return > 0 Return the input clock frequency to an IP Module
+ 0 either IP module doesn't exist in SOC
+ or IP module instance doesn't exist in SOC
+ or IP module instance is disabled. i.e. no input clock is provided to IP module instance.
+**/
+UINT64
+SocGetClock (
+ IN UINT64 BaseClock,
+ IN UINT32 ClockType,
+ IN VA_LIST Args
+ )
+{
+ LS1043A_DEVICE_CONFIG *Dcfg;
+ UINT32 RcwSr;
+ UINT64 ReturnValue;
+
+ ReturnValue = 0;
+ Dcfg = (LS1043A_DEVICE_CONFIG *)LS1043A_DCFG_ADDRESS;
+
+ switch (ClockType) {
+ case NXP_UART_CLOCK:
+ case NXP_I2C_CLOCK:
+ RcwSr = DcfgRead32 ((UINTN)&Dcfg->RcwSr[0]);
+ ReturnValue = BaseClock * SYS_PLL_RAT (RcwSr);
+ break;
+ default:
+ break;
+ }
+
+ return ReturnValue;
+}
+
+/**
+ Function to initialize SoC specific constructs
+ CPU Info
+ SoC Personality
+ Board Personality
+ RCW prints
+ **/
+VOID
+SocInit (
+ VOID
+ )
+{
+ ChassisInit ();
+
+ return;
+}
+
diff --git a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
new file mode 100644
index 0000000000..c9a4fbc01f
--- /dev/null
+++ b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
@@ -0,0 +1,32 @@
+#@file
+#
+# Component description file for SocLib module
+#
+# Copyright 2017-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+[Defines]
+ INF_VERSION = 0x0001000A
+ BASE_NAME = SocLib
+ FILE_GUID = 9b046753-2b4f-42d8-bfb3-468892fe17d4
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SocLib
+
+[Sources.common]
+ SocLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+ Silicon/NXP/Chassis2/Chassis2.dec
+ Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
+
+[LibraryClasses]
+ ChassisLib
+
diff --git a/Silicon/NXP/Include/Library/SocLib.h b/Silicon/NXP/Include/Library/SocLib.h
new file mode 100644
index 0000000000..3def396171
--- /dev/null
+++ b/Silicon/NXP/Include/Library/SocLib.h
@@ -0,0 +1,81 @@
+/** @file
+
+ Copyright 2020 NXP
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __SOC_LIB_H__
+#define __SOC_LIB_H__
+
+#include <Soc.h>
+#include <Uefi.h>
+#include <Ppi/ArmMpCoreInfo.h>
+#include <Ppi/NxpPlatformGetClock.h>
+
+/**
+ Return the number of cores present in SOC
+
+ This function returns the number of cores present in SOC.
+ and also their position (cluster number and core number) in the form of ARM_CORE_INFO array
+ and NxpCoreTable array.
+ NxpCoreTable array can be used to find out the type of core. it's values are of type
+ TP_ITYPE_VERSION_*.
+ The number of cores present in SOC can vary depending on which flavour of SOC is being used.
+ This function doesn't allocte any memory and must be provided memory for array of ARM_CORE_INFO
+ and NxpCoreTable for maximum number of cores the SOC can have.
+
+ @param[out] NxpCoreTable array of UINT8 for maximum number of cores the SOC can have.
+ @param[out] ArmCoreTable array of ARM_CORE_INFO for maximum number of cores the SOC can have.
+ @param[in] ArmCoreTableSize Size of ArmCoreTable
+
+ @return Actual number of cores present in SOC. After calling this function only the returned value number of
+ entries in ArmCoreTable are valid entries.
+**/
+UINTN
+SocGetMpCoreInfo (
+ OUT UINT8 *NxpCoreTable,
+ OUT ARM_CORE_INFO *ArmCoreTable,
+ IN UINTN ArmCoreTableSize
+ );
+
+/**
+ Return the input clock frequency to an IP Module.
+ This function reads the RCW bits and calculates the PLL multipler/divider values to be applied
+ to various IP modules.
+ If a module is disabled or doesn't exist on platform, then return zero.
+
+ @param[in] BaseClock Base clock to which PLL multipler/divider values is to be applied.
+ @param[in] ClockType IP modules whose clock value is to be retrieved
+ @param[in] Args Variable Args lists that is parsed based on the ClockType
+ e.g. if there are multiple modules of same type then this value tells the
+ instance of module for which clock is to be retrieved.
+ (e.g. if there are four i2c controllers in SOC, then this value can be 1, 2, 3, 4)
+ for IP modules which have only single instance in SOC (e.g. one QSPI controller)
+ this value can be null (i.e. no arg)
+
+ @return > 0 Return the input clock frequency to an IP Module
+ 0 either IP module doesn't exist in SOC
+ or IP module instance doesn't exist in SOC
+ or IP module instance is disabled. i.e. no input clock is provided to IP module instance.
+**/
+UINT64
+SocGetClock (
+ IN UINT64 BaseClock,
+ IN UINT32 ClockType,
+ IN VA_LIST Args
+ );
+
+/**
+ Function to initialize SoC specific constructs
+ CPU Info
+ SoC Personality
+ Board Personality
+ RCW prints
+ **/
+VOID
+SocInit (
+ VOID
+ );
+
+#endif // __SOC_LIB_H__
diff --git a/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h b/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h
new file mode 100644
index 0000000000..2c8c97987d
--- /dev/null
+++ b/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h
@@ -0,0 +1,47 @@
+/** @file
+*
+* Copyright 2020 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef __NXP_PLATFORM_PPI_H__
+#define __NXP_PLATFORM_PPI_H__
+
+#include <Uefi.h>
+
+#define NXP_PLATFORM_GET_CLOCK_PPI_GUID \
+ { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }
+
+typedef enum _NXP_IP_CLOCK {
+ NXP_SYSTEM_CLOCK,
+ NXP_UART_CLOCK,
+ NXP_I2C_CLOCK
+} NXP_IP_CLOCK;
+
+/**
+ Get the clocks supplied by Platform(Board) to NXP Layerscape SOC
+
+ The core can be of type ARM or PowerPC or Hardware Accelerator.
+ If the core is enabled and of type ARM EFI_SUCCESS is returned and a code for type of ARM core is returned
+
+ @param[in] ClockType Type of clock
+ @param[in] ... Variable argument list which is parsed based on ClockType
+
+ @return Actual Clock Frequency. return value 0 should be interpreted as clock not provided by Board.
+**/
+typedef
+UINT64
+(EFIAPI * NXP_PLATFORM_GET_CLOCK)(
+ IN UINT32 ClockType,
+ ...
+ );
+
+typedef struct {
+ NXP_PLATFORM_GET_CLOCK PlatformGetClock;
+} NXP_PLATFORM_GET_CLOCK_PPI;
+
+extern EFI_GUID gNxpPlatformGetClockPpiGuid;
+
+#endif
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index d8989657e6..4f14cc9848 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -14,6 +14,9 @@
Include
[LibraryClasses]
+ ## @libraryclass Provides Soc specific functions to other modules
+ SocLib|Include/Library/SocLib.h
+
## @libraryclass Provides Chassis specific functions to other modules
ChassisLib|Include/Library/ChassisLib.h
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 13/19] Silicon/NXP: Move RAM retrieval from SocLib
2020-02-07 12:43 [PATCH 00/19] ADD LX2160ARDB Platform Support Pankaj Bansal
` (11 preceding siblings ...)
2020-02-07 12:43 ` [PATCH 12/19] Silicon/NXP/LS1043A: Add SocLib Pankaj Bansal
@ 2020-02-07 12:43 ` Pankaj Bansal
2020-02-11 13:28 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 14/19] Silicon/NXP/LS1043A: Replce SocLib Pankaj Bansal
` (5 subsequent siblings)
18 siblings, 1 reply; 49+ messages in thread
From: Pankaj Bansal @ 2020-02-07 12:43 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, Varun Sethi
Cc: devel, Pankaj Bansal
RAM retrieval using SMC commands is common to all Layerscape SOCs.
Therefore, move it to commom MemoryInit Pei Lib.
Also added provision to reserve a portion of RAM.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Silicon/NXP/Include/DramInfo.h | 38 ---
.../Library/MemoryInitPei/MemoryInitPeiLib.c | 235 +++++++++++++++---
.../Library/MemoryInitPei/MemoryInitPeiLib.h | 24 ++
.../MemoryInitPei/MemoryInitPeiLib.inf | 8 +
Silicon/NXP/Library/SocLib/Chassis.c | 67 -----
Silicon/NXP/NxpQoriqLs.dec | 7 +-
6 files changed, 239 insertions(+), 140 deletions(-)
delete mode 100644 Silicon/NXP/Include/DramInfo.h
create mode 100644 Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
diff --git a/Silicon/NXP/Include/DramInfo.h b/Silicon/NXP/Include/DramInfo.h
deleted file mode 100644
index a934aaeff1..0000000000
--- a/Silicon/NXP/Include/DramInfo.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/** @file
-* Header defining the structure for Dram Information
-*
-* Copyright 2019 NXP
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-
-#ifndef DRAM_INFO_H_
-#define DRAM_INFO_H_
-
-#include <Uefi/UefiBaseType.h>
-
-#define SMC_DRAM_BANK_INFO (0xC200FF12)
-
-typedef struct {
- UINTN BaseAddress;
- UINTN Size;
-} DRAM_REGION_INFO;
-
-typedef struct {
- UINT32 NumOfDrams;
- UINT32 Reserved;
- DRAM_REGION_INFO DramRegion[3];
-} DRAM_INFO;
-
-EFI_STATUS
-GetDramBankInfo (
- IN OUT DRAM_INFO *DramInfo
- );
-
-VOID
-UpdateDpaaDram (
- IN OUT DRAM_INFO *DramInfo
- );
-
-#endif /* DRAM_INFO_H_ */
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
index 3ea7736786..eb1983bdbc 100644
--- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
+++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
@@ -17,8 +17,10 @@
#include <Library/HobLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
+#include <Library/ArmSmcLib.h>
+
+#include "MemoryInitPeiLib.h"
-#include <DramInfo.h>
VOID
BuildMemoryTypeInformationHob (
@@ -44,6 +46,85 @@ InitMmu (
}
}
+STATIC
+UINTN
+CalculateReservedMemBase (
+ IN DRAM_REGION_INFO *DramRegions,
+ IN UINT32 NumRegions,
+ IN UINTN ReservedMemSize
+)
+{
+ UINTN ReservedMemAlignment;
+ INTN Index;
+ EFI_PHYSICAL_ADDRESS AlignmentMask;
+ UINTN RegionBaseAddress;
+ UINTN RegionSize;
+ UINTN ReservedBaseAddress;
+ INTN Index2;
+
+ ReservedMemAlignment = FixedPcdGet64 (PcdReservedMemAlignment);
+ //
+ // Compute alignment bit mask
+ //
+ if (ReservedMemAlignment) {
+ AlignmentMask = LShiftU64 (1, LowBitSet64(ReservedMemAlignment)) - 1;
+ } else {
+ AlignmentMask = 0;
+ }
+ Index = NumRegions;
+ while (Index--) {
+ RegionBaseAddress = DramRegions[Index].BaseAddress;
+ RegionSize = DramRegions[Index].Size;
+
+ if (ReservedMemSize > RegionSize) {
+ continue;
+ }
+
+ ReservedBaseAddress = (RegionBaseAddress + RegionSize - ReservedMemSize) & (~AlignmentMask);
+ if (ReservedBaseAddress < RegionBaseAddress) {
+ continue;
+ }
+
+ // found the region from which reserved mem is to be carved out
+ // Need to modify the region size and create/delete region if need be
+ RegionSize -= ReservedMemSize;
+ if (!RegionSize) {
+ for (Index2 = Index; Index2 < NumRegions; Index2++) {
+ CopyMem (&DramRegions[Index2], &DramRegions[Index2 + 1], sizeof (DRAM_REGION_INFO));
+ }
+ break;
+ }
+
+ if (ReservedBaseAddress - RegionBaseAddress) {
+ DramRegions[Index].Size = ReservedBaseAddress - RegionBaseAddress;
+ RegionSize -= DramRegions[Index].Size;
+ } else {
+ DramRegions[Index].BaseAddress = ReservedBaseAddress + ReservedMemSize;
+ DramRegions[Index].Size = RegionSize;
+ RegionSize = 0;
+ }
+
+ if (!RegionSize) {
+ break;
+ }
+
+ for (Index2 = NumRegions; Index2 > (Index + 1); Index2--) {
+ CopyMem (&DramRegions[Index2], &DramRegions[Index2 - 1], sizeof (DRAM_REGION_INFO));
+ }
+ DramRegions[Index2].BaseAddress = ReservedBaseAddress + ReservedMemSize;
+ DramRegions[Index2].Size = RegionSize;
+ RegionSize = 0;
+
+ break;
+ }
+
+ if (Index == -1) {
+ return 0;
+ } else {
+ return ReservedBaseAddress;
+ }
+}
+
/*++
Routine Description:
@@ -68,10 +149,19 @@ MemoryPeim (
)
{
ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
+ ARM_SMC_ARGS ArmSmcArgs;
+ INT32 Index;
+ UINTN DramSize;
+ UINTN BaseAddress;
+ UINTN Size;
+ UINTN Top;
+ // Extra region gets created if we want to reserve a memory region and that creates a memory hole
+ // because of alignement requirements
+ DRAM_REGION_INFO DramRegions[MAX_DRAM_REGIONS + 1];
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
- EFI_PEI_HOB_POINTERS NextHob;
- BOOLEAN Found;
- DRAM_INFO DramInfo;
+ UINTN FdBase;
+ UINTN FdTop;
+ BOOLEAN FoundSystemMem;
// Get Virtual Memory Map from the Platform Library
ArmPlatformGetVirtualMemoryMap (&MemoryTable);
@@ -86,48 +176,127 @@ MemoryPeim (
// Now, the permanent memory has been installed, we can call AllocatePages()
//
ResourceAttributes = (
- EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_TESTED
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED
);
- if (GetDramBankInfo (&DramInfo)) {
- DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n"));
- return EFI_UNSUPPORTED;
- }
+ FoundSystemMem = FALSE;
+ ZeroMem (DramRegions, sizeof (DramRegions));
+
+ Index = -1;
+ do {
+ ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
+ ArmSmcArgs.Arg1 = Index++;
- while (DramInfo.NumOfDrams--) {
- //
- // Check if the resource for the main system memory has been declared
- //
- Found = FALSE;
- NextHob.Raw = GetHobList ();
- while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) {
- if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&
- (DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress >= NextHob.ResourceDescriptor->PhysicalStart) &&
- (NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength <=
- DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress + DramInfo.DramRegion[DramInfo.NumOfDrams].Size))
- {
- Found = TRUE;
- break;
+ ArmCallSmc (&ArmSmcArgs);
+ ASSERT (!(ArmSmcArgs.Arg0 && !Index));
+ if (!Index) {
+ DramSize = ArmSmcArgs.Arg1;
+ } else {
+ if (!ArmSmcArgs.Arg0) {
+ BaseAddress = ArmSmcArgs.Arg1;
+ Size = ArmSmcArgs.Arg2;
+ ASSERT (BaseAddress && Size);
+
+ DramRegions[Index - 1].BaseAddress = BaseAddress;
+ DramRegions[Index - 1].Size = Size;
+ DramSize -= Size;
+
+ DEBUG ((DEBUG_INFO, "bank[%d]: start 0x%lx, size 0x%lx\n", Index, BaseAddress, Size));
}
- NextHob.Raw = GET_NEXT_HOB (NextHob);
+ }
+ } while (DramSize && Index < MAX_DRAM_REGIONS);
+
+ ASSERT (!DramSize);
+
+ // Get the reserved memory size from non volatile storage
+ Size = FixedPcdGet64 (PcdReservedMemSize);
+ if (Size) {
+ BaseAddress = CalculateReservedMemBase (DramRegions, Index, Size);
+ if (BaseAddress) {
+ DEBUG ((DEBUG_INFO, "ReservedMem: start 0x%lx, size 0x%lx\n", BaseAddress, Size));
+ }
+ }
+
+ FdBase = (UINTN)FixedPcdGet64 (PcdFdBaseAddress);
+ FdTop = FdBase + (UINTN)FixedPcdGet32 (PcdFdSize);
+
+ // Declare memory regios to system
+ for (Index = MAX_DRAM_REGIONS; Index >= 0; Index--) {
+ if (!DramRegions[Index].Size) {
+ continue;
}
- if (!Found) {
- // Reserved the memory space occupied by the firmware volume
+ BaseAddress = DramRegions[Index].BaseAddress;
+ Top = DramRegions[Index].BaseAddress + DramRegions[Index].Size;
+
+ // EDK2 does not have the concept of boot firmware copied into DRAM. To avoid the DXE
+ // core to overwrite this area we must create a memory allocation HOB for the region,
+ // but this only works if we split off the underlying resource descriptor as well.
+ if (FdBase >= BaseAddress && FdTop <= Top) {
+ // Update Size
+ Size = FdBase - BaseAddress;
+ if (Size) {
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ BaseAddress,
+ Size
+ );
+ }
+ // create the System Memory HOB for the firmware
BuildResourceDescriptorHob (
EFI_RESOURCE_SYSTEM_MEMORY,
ResourceAttributes,
- DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress,
- DramInfo.DramRegion[DramInfo.NumOfDrams].Size
+ FdBase,
+ PcdGet32 (PcdFdSize)
+ );
+ // Create the System Memory HOB for the remaining region (top of the FD)s
+ Size = Top - FdTop;
+ if (Size) {
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ FdTop,
+ Size
+ );
+ };
+ // Mark the memory covering the Firmware Device as boot services data
+ BuildMemoryAllocationHob (FixedPcdGet64 (PcdFdBaseAddress),
+ FixedPcdGet32 (PcdFdSize),
+ EfiBootServicesData);
+ }else {
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ DramRegions[Index].BaseAddress,
+ DramRegions[Index].Size
);
}
+
+ if (FoundSystemMem) {
+ continue;
+ }
+
+ BaseAddress = DramRegions[Index].BaseAddress;
+ Size = DramRegions[Index].Size;
+ Top = DramRegions[Index].BaseAddress + DramRegions[Index].Size;
+
+ if (FdBase >= BaseAddress && FdTop <= Top) {
+ Size -= (UINTN)FixedPcdGet32 (PcdFdSize);
+ }
+
+ if (Size >= FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)) {
+ FoundSystemMem = TRUE;
+ }
}
+ ASSERT (FoundSystemMem);
+
// Build Memory Allocation Hob
InitMmu (MemoryTable);
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
new file mode 100644
index 0000000000..e563b2ba8d
--- /dev/null
+++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
@@ -0,0 +1,24 @@
+/** @file
+*
+* Copyright 2020 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef _MEMORY_INIT_PEI_LIB_H_
+#define _MEMORY_INIT_PEI_LIB_H_
+
+#include <Uefi.h>
+
+// Specifies the Maximum regions onto which DDR memory can be mapped in a Platform
+#define MAX_DRAM_REGIONS 3
+#define SMC_DRAM_BANK_INFO (0xC200FF12)
+
+typedef struct {
+ UINTN BaseAddress;
+ UINTN Size;
+} DRAM_REGION_INFO;
+
+#endif
+
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
index a5bd39415d..9adddcaf8c 100644
--- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
+++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
@@ -33,6 +33,7 @@
DebugLib
HobLib
PcdLib
+ ArmSmcLib
[Guids]
gEfiMemoryTypeInformationGuid
@@ -40,6 +41,13 @@
[FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdFdBaseAddress
+ gArmTokenSpaceGuid.PcdFdSize
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment
+
[Pcd]
gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize
diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
index 847331a631..1ef99e8de2 100644
--- a/Silicon/NXP/Library/SocLib/Chassis.c
+++ b/Silicon/NXP/Library/SocLib/Chassis.c
@@ -22,7 +22,6 @@
#include <Library/PrintLib.h>
#include <Library/SerialPortLib.h>
-#include <DramInfo.h>
#include "NxpChassis.h"
UINT32
@@ -75,69 +74,3 @@ SmmuInit (
MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
}
-UINTN
-GetDramSize (
- IN VOID
- )
-{
- ARM_SMC_ARGS ArmSmcArgs;
-
- ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
- ArmSmcArgs.Arg1 = -1;
-
- ArmCallSmc (&ArmSmcArgs);
-
- if (ArmSmcArgs.Arg0) {
- return 0;
- } else {
- return ArmSmcArgs.Arg1;
- }
-}
-
-EFI_STATUS
-GetDramBankInfo (
- IN OUT DRAM_INFO *DramInfo
- )
-{
- ARM_SMC_ARGS ArmSmcArgs;
- UINT32 I;
- UINTN DramSize;
-
- DramSize = GetDramSize ();
- DEBUG ((DEBUG_INFO, "DRAM Total Size 0x%lx \n", DramSize));
-
- // Ensure DramSize has been set
- ASSERT (DramSize != 0);
-
- I = 0;
-
- do {
- ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
- ArmSmcArgs.Arg1 = I;
-
- ArmCallSmc (&ArmSmcArgs);
- if (ArmSmcArgs.Arg0) {
- if (I > 0) {
- break;
- } else {
- ASSERT (ArmSmcArgs.Arg0 == 0);
- }
- }
-
- DramInfo->DramRegion[I].BaseAddress = ArmSmcArgs.Arg1;
- DramInfo->DramRegion[I].Size = ArmSmcArgs.Arg2;
-
- DramSize -= DramInfo->DramRegion[I].Size;
-
- DEBUG ((DEBUG_INFO, "bank[%d]: start 0x%lx, size 0x%lx\n",
- I, DramInfo->DramRegion[I].BaseAddress, DramInfo->DramRegion[I].Size));
-
- I++;
- } while (DramSize);
-
- DramInfo->NumOfDrams = I;
-
- DEBUG ((DEBUG_INFO, "Number Of DRAM in system %d \n", DramInfo->NumOfDrams));
-
- return EFI_SUCCESS;
-}
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 4f14cc9848..c327e738cc 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -38,7 +38,10 @@
#
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize|0x0|UINT64|0x00000315
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment|0x0|UINT64|0x00000316
+
[PcdsFeatureFlag]
- gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315
- gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000316
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000317
+ gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000318
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 14/19] Silicon/NXP/LS1043A: Replce SocLib
2020-02-07 12:43 [PATCH 00/19] ADD LX2160ARDB Platform Support Pankaj Bansal
` (12 preceding siblings ...)
2020-02-07 12:43 ` [PATCH 13/19] Silicon/NXP: Move RAM retrieval from SocLib Pankaj Bansal
@ 2020-02-07 12:43 ` Pankaj Bansal
2020-02-11 13:35 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 15/19] Platform/NXP/LS1043ARDB: introduce PEI Phase Pankaj Bansal
` (4 subsequent siblings)
18 siblings, 1 reply; 49+ messages in thread
From: Pankaj Bansal @ 2020-02-07 12:43 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, Varun Sethi
Cc: devel, Pankaj Bansal
Replace SocLib with new SocLib in which code structure has been
changed.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
.../Drivers/PlatformDxe/PlatformDxe.inf | 3 +-
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 3 +-
.../Library/ArmPlatformLib/ArmPlatformLib.c | 53 ++++++-
.../Library/ArmPlatformLib/ArmPlatformLib.inf | 6 +-
Silicon/NXP/Chassis2/Include/Chassis.h | 12 ++
Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc | 1 +
.../Chassis2/LS1043A/Library/SocLib/SocLib.c | 28 ++++
.../LS1043A/Library/SocLib/SocLib.inf | 8 ++
.../Chassis2/Library/ChassisLib/ChassisLib.c | 25 ++++
Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 2 +-
Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 7 +-
Silicon/NXP/Include/Chassis2/NxpSoc.h | 53 -------
Silicon/NXP/Include/Library/ChassisLib.h | 2 -
Silicon/NXP/Include/Library/SocLib.h | 1 -
Silicon/NXP/LS1043A/Include/Soc.h | 44 ------
Silicon/NXP/LS1043A/LS1043A.dec | 16 ---
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 33 -----
.../BaseSerialPortLib16550.c | 11 +-
.../BaseSerialPortLib16550.inf | 3 +-
Silicon/NXP/Library/SocLib/Chassis.c | 76 ----------
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 96 -------------
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 44 ------
Silicon/NXP/Library/SocLib/NxpChassis.h | 136 ------------------
23 files changed, 142 insertions(+), 521 deletions(-)
delete mode 100644 Silicon/NXP/Include/Chassis2/NxpSoc.h
delete mode 100644 Silicon/NXP/LS1043A/Include/Soc.h
delete mode 100644 Silicon/NXP/LS1043A/LS1043A.dec
delete mode 100644 Silicon/NXP/LS1043A/LS1043A.dsc.inc
delete mode 100644 Silicon/NXP/Library/SocLib/Chassis.c
delete mode 100644 Silicon/NXP/Library/SocLib/Chassis2/Soc.c
delete mode 100644 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
delete mode 100644 Silicon/NXP/Library/SocLib/NxpChassis.h
diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
index 126a1174fa..95f60b00f0 100644
--- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
@@ -25,7 +25,8 @@
MdeModulePkg/MdeModulePkg.dec
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
Silicon/NXP/NxpQoriqLs.dec
- Silicon/NXP/LS1043A/LS1043A.dec
+ Silicon/NXP/Chassis2/Chassis2.dec
+ Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
[LibraryClasses]
BaseLib
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index bc6fa4f19d..4bc7f6ef97 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -23,7 +23,8 @@
FLASH_DEFINITION = Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
!include Silicon/NXP/NxpQoriqLs.dsc.inc
-!include Silicon/NXP/LS1043A/LS1043A.dsc.inc
+!include Silicon/NXP/Chassis2/Chassis2.dsc.inc
+!include Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
[LibraryClasses.common]
ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
index 718c71bf02..821d413a3e 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -14,7 +14,10 @@
#include <Library/ArmPlatformLib.h>
#include <Ppi/ArmMpCoreInfo.h>
-extern VOID SocInit (VOID);
+#include <Library/DebugLib.h>
+#include <Library/I2cLib.h>
+#include <Library/SocLib.h>
+#include <Ppi/NxpPlatformGetClock.h>
/**
Return the current Boot Mode
@@ -30,6 +33,49 @@ ArmPlatformGetBootMode (
return BOOT_WITH_FULL_CONFIGURATION;
}
+/**
+ Get the clocks supplied by Platform(Board) to NXP Layerscape SOC
+
+ The core can be of type ARM or PowerPC or Hardware Accelerator.
+ If the core is enabled and of type ARM EFI_SUCCESS is returned and a code for type of ARM core is returned
+
+ @param[in] ClockType Type of clock
+ @param[in] ... Variable argument list which is parsed based on ClockType
+
+ @return Actual Clock Frequency. return value 0 should be interpreted as clock not provided by Board.
+**/
+UINT64
+EFIAPI
+NxpPlatformGetClock(
+ IN UINT32 ClockType,
+ ...
+ )
+{
+ UINT64 Clock;
+ VA_LIST Args;
+
+ Clock = 0;
+
+ VA_START (Args, ClockType);
+
+ switch (ClockType) {
+ case NXP_SYSTEM_CLOCK:
+ Clock = 100 * 1000 * 1000; // 100 MHz
+ break;
+ case NXP_I2C_CLOCK:
+ case NXP_UART_CLOCK:
+ Clock = NxpPlatformGetClock (NXP_SYSTEM_CLOCK);
+ Clock = SocGetClock (Clock, ClockType, Args);
+ break;
+ default:
+ break;
+ }
+
+ VA_END (Args);
+
+ return Clock;
+}
+
/**
Placeholder for Platform Initialization
**/
@@ -38,9 +84,9 @@ ArmPlatformInitialize (
IN UINTN MpId
)
{
- SocInit ();
+ SocInit ();
- return EFI_SUCCESS;
+ return EFI_SUCCESS;
}
ARM_CORE_INFO LS1043aMpCoreInfoCTA53x4[] = {
@@ -69,6 +115,7 @@ PrePeiCoreGetMpCoreInfo (
}
ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi = { NxpPlatformGetClock };
EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
{
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
index 6396d2982b..8b79fd7490 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -20,11 +20,14 @@
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
Silicon/NXP/NxpQoriqLs.dec
- Silicon/NXP/LS1043A/LS1043A.dec
+ Silicon/NXP/Chassis2/Chassis2.dec
+ Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
[LibraryClasses]
ArmLib
SocLib
+ I2cLib
+ DebugLib
[Sources.common]
AArch64/NxpQoriqLsHelper.S | GCC
@@ -36,3 +39,4 @@
[FixedPcd]
gArmTokenSpaceGuid.PcdArmPrimaryCore
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h b/Silicon/NXP/Chassis2/Include/Chassis.h
index 48ba2e7bfb..8f26faf297 100644
--- a/Silicon/NXP/Chassis2/Include/Chassis.h
+++ b/Silicon/NXP/Chassis2/Include/Chassis.h
@@ -20,6 +20,18 @@
#define TP_ITYPE_VERSION_A53 0x2
#define TP_ITYPE_VERSION_A72 0x4
+/* SMMU Defintions */
+#define SMMU_BASE_ADDR 0x09000000
+#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
+#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
+#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
+#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
+#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
+
+#define SCR0_USFCFG_MASK 0x00000400
+#define SCR0_CLIENTPD_MASK 0x00000001
+#define SACR_PAGESIZE_MASK 0x00010000
+
/**
The Device Configuration Unit provides general purpose configuration and status for the
device. These registers only support 32-bit accesses.
diff --git a/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
index 4511203443..8440e5f0f3 100644
--- a/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
+++ b/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
@@ -8,6 +8,7 @@
[LibraryClasses.common]
SocLib|Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
+ SerialPortLib|Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
################################################################################
#
diff --git a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
index 2a08ad87db..24241e9b02 100644
--- a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
+++ b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
@@ -4,8 +4,10 @@
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
+#include <Soc.h>
#include <Library/ChassisLib.h>
#include <Library/SocLib.h>
+#include <Library/SerialPortLib.h>
/**
Return the input clock frequency to an IP Module.
@@ -66,8 +68,34 @@ SocInit (
VOID
)
{
+ UINT64 BaudRate;
+ UINT32 ReceiveFifoDepth;
+ EFI_PARITY_TYPE Parity;
+ UINT8 DataBits;
+ EFI_STOP_BITS_TYPE StopBits;
+ UINT32 Timeout;
+
+ BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
+ ReceiveFifoDepth = FixedPcdGet16 (PcdUartDefaultReceiveFifoDepth); // Use default FIFO depth
+ Timeout = 0;
+ Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
+ DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
+ StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);
+
ChassisInit ();
+ //
+ // Early init serial Port to get board information.
+ //
+ SerialPortSetAttributes (
+ &BaudRate,
+ &ReceiveFifoDepth,
+ &Timeout,
+ &Parity,
+ &DataBits,
+ &StopBits
+ );
+
return;
}
diff --git a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
index c9a4fbc01f..fb39424bc5 100644
--- a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
+++ b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
@@ -29,4 +29,12 @@
[LibraryClasses]
ChassisLib
+ PcdLib
+ SerialPortLib
+[FixedPcd]
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
index fa6a36e96f..e7573a0e06 100644
--- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
@@ -150,6 +150,29 @@ SocGetMpCoreInfo (
return CoreCount;
}
+/*
+ * Setup SMMU in bypass mode
+ * and also set its pagesize
+ */
+STATIC
+VOID
+SmmuInit (
+ VOID
+ )
+{
+ UINT32 Value;
+
+ /* set pagesize as 64K and ssmu-500 in bypass mode */
+ Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
+ MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
+
+ Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
+ MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
+
+ Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
+ MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
+}
+
/**
Function to initialize Chassis Specific functions
**/
@@ -183,4 +206,6 @@ ChassisInit (
&DataBits,
&StopBits
);
+
+ SmmuInit();
}
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
index 8e3a82efca..e79b106c8d 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
@@ -50,7 +50,7 @@ SetBusFrequency (
I2cBase = (UINTN)(I2c->Dev->Resources[0].AddrRangeMin);
- I2cClock = GetBusFrequency ();
+ I2cClock = mPlatformGetClockPpi.PlatformGetClock (NXP_I2C_CLOCK, 0);
I2cInitialize (I2cBase, I2cClock, *BusClockHertz);
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
index 88316f3133..f446f0d4f9 100644
--- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
@@ -13,6 +13,7 @@
#include <Library/UefiLib.h>
#include <Uefi.h>
+#include <Ppi/NxpPlatformGetClock.h>
#include <Protocol/I2cMaster.h>
#include <Protocol/NonDiscoverableDevice.h>
@@ -37,11 +38,7 @@ typedef struct {
NON_DISCOVERABLE_DEVICE *Dev;
} NXP_I2C_MASTER;
-extern
-UINT64
-GetBusFrequency (
- VOID
- );
+extern NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi;
EFI_STATUS
NxpI2cInit (
diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
deleted file mode 100644
index 6812beafe4..0000000000
--- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/** Soc.h
-* Header defining the Base addresses, sizes, flags etc for chassis 1
-*
-* Copyright 2017-2020 NXP
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-
-#ifndef NXP_SOC_H_
-#define NXP_SOC_H_
-
-#define CLK_FREQ 100000000
-
-#define CHASSIS2_DCFG_ADDRESS 0x1EE0000
-
-/* SMMU Defintions */
-#define SMMU_BASE_ADDR 0x09000000
-#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
-#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
-#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
-#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
-#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
-
-#define SCR0_USFCFG_MASK 0x00000400
-#define SCR0_CLIENTPD_MASK 0x00000001
-#define SACR_PAGESIZE_MASK 0x00010000
-#define IDR1_PAGESIZE_MASK 0x80000000
-
-typedef struct {
- UINTN FreqSystemBus;
-} SYS_INFO;
-
-/* Device Configuration and Pin Control */
-typedef struct {
- UINT8 Res0[0x100-0x00];
- UINT32 RcwSr[16]; /* Reset control word status */
-#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
-#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
-} CCSR_GUR;
-
-VOID
-GetSysInfo (
- OUT SYS_INFO *
- );
-
-UINT32
-EFIAPI
-GurRead (
- IN UINTN Address
- );
-
-#endif /* NXP_SOC_H_ */
diff --git a/Silicon/NXP/Include/Library/ChassisLib.h b/Silicon/NXP/Include/Library/ChassisLib.h
index b51b024374..d07c59b82d 100644
--- a/Silicon/NXP/Include/Library/ChassisLib.h
+++ b/Silicon/NXP/Include/Library/ChassisLib.h
@@ -9,8 +9,6 @@
#ifndef __CHASSIS_LIB_H__
#define __CHASSIS_LIB_H__
-#include <Chassis.h>
-
/**
Read Dcfg register
**/
diff --git a/Silicon/NXP/Include/Library/SocLib.h b/Silicon/NXP/Include/Library/SocLib.h
index 3def396171..700e877bdf 100644
--- a/Silicon/NXP/Include/Library/SocLib.h
+++ b/Silicon/NXP/Include/Library/SocLib.h
@@ -8,7 +8,6 @@
#ifndef __SOC_LIB_H__
#define __SOC_LIB_H__
-#include <Soc.h>
#include <Uefi.h>
#include <Ppi/ArmMpCoreInfo.h>
#include <Ppi/NxpPlatformGetClock.h>
diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Include/Soc.h
deleted file mode 100644
index c1e00394af..0000000000
--- a/Silicon/NXP/LS1043A/Include/Soc.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/** @file
-
- Copyright 2020 NXP
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-#ifndef __SOC_H__
-#define __SOC_H__
-
-/**
- Soc Memory Map
-**/
-#define LS1043A_DRAM0_PHYS_ADDRESS 0x80000000
-#define LS1043A_DRAM0_SIZE SIZE_2GB
-#define LS1043A_DRAM1_PHYS_ADDRESS 0x880000000
-#define LS1043A_DRAM1_SIZE 0x780000000 // 30 GB
-
-#define LS1043A_CCSR_PHYS_ADDRESS 0x1000000
-#define LS1043A_CCSR_SIZE 0xF000000
-
-#define LS1043A_IFC0_PHYS_ADDRESS 0x60000000
-#define LS1043A_IFC0_SIZE SIZE_512MB
-#define LS1043A_IFC1_PHYS_ADDRESS 0x620000000
-#define LS1043A_IFC1_SIZE 0xE0000000 // 3.5 GB
-
-#define LS1043A_QSPI_PHYS_ADDRESS 0x40000000
-#define LS1043A_QSPI_SIZE SIZE_512MB
-
-#define LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS 0x500000000
-#define LS1043A_QMAN_SW_PORTAL_SIZE SIZE_128MB
-#define LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS 0x508000000
-#define LS1043A_BMAN_SW_PORTAL_SIZE SIZE_128MB
-
-#define LS1043A_PCI0_PHYS_ADDRESS 0x4000000000
-#define LS1043A_PCI1_PHYS_ADDRESS 0x4800000000
-#define LS1043A_PCI2_PHYS_ADDRESS 0x5000000000
-#define LS1043A_PCI_SIZE SIZE_32GB
-
-#define LS1043A_I2C0_PHYS_ADDRESS 0x2180000
-#define LS1043A_I2C_SIZE 0x10000
-#define LS1043A_I2C_NUM_CONTROLLERS 4
-
-#endif
diff --git a/Silicon/NXP/LS1043A/LS1043A.dec b/Silicon/NXP/LS1043A/LS1043A.dec
deleted file mode 100644
index cd79949790..0000000000
--- a/Silicon/NXP/LS1043A/LS1043A.dec
+++ /dev/null
@@ -1,16 +0,0 @@
-# LS1043A.dec
-#
-# Copyright 2017-2019 NXP
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-#
-
-[Defines]
- DEC_SPECIFICATION = 0x0001001A
-
-[Guids.common]
- gNxpLs1043ATokenSpaceGuid = {0x6834fe45, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
-
-[Includes]
- Include
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
deleted file mode 100644
index 7ebbb1a495..0000000000
--- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
+++ /dev/null
@@ -1,33 +0,0 @@
-# LS1043A.dsc
-# LS1043A Soc package.
-#
-# Copyright 2017-2020 NXP
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-#
-
-[LibraryClasses.common]
- SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
- SerialPortLib|Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
-
-################################################################################
-#
-# Pcd Section - list of all EDK II PCD Entries defined by this Platform
-#
-################################################################################
-[PcdsDynamicDefault.common]
-
- #
- # ARM General Interrupt Controller
- gArmTokenSpaceGuid.PcdGicDistributorBase|0x01401000
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01402000
-
-[PcdsFixedAtBuild.common]
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
-
- #
- # Big Endian IPs
- #
- gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
-##
diff --git a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
index 6b2aa46ff6..2e35f09d8f 100644
--- a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
+++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
@@ -15,6 +15,9 @@
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Library/BaseLib.h>
+#include <Ppi/NxpPlatformGetClock.h>
+
+extern NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi;
//
// 16550 UART register offsets and bitfields
@@ -42,12 +45,6 @@
#define B_UART_MSR_RI BIT6
#define B_UART_MSR_DCD BIT7
-extern
-UINT64
-GetBusFrequency (
- VOID
- );
-
/**
Read an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is read from
MMIO space. If PcdSerialUseMmio is FALSE, then the value is read from I/O space. The
@@ -577,7 +574,7 @@ SerialPortSetAttributes (
return RETURN_UNSUPPORTED;
}
- SerialClock = GetBusFrequency ();
+ SerialClock = mPlatformGetClockPpi.PlatformGetClock (NXP_UART_CLOCK, 0);
if (SerialClock == 0) {
return EFI_DEVICE_ERROR;
}
diff --git a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
index 45ae9dc0af..7823bc5be5 100644
--- a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
+++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
@@ -19,11 +19,12 @@
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
[LibraryClasses]
PcdLib
IoLib
- SocLib
+ ArmPlatformLib
[Sources]
BaseSerialPortLib16550.c
diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
deleted file mode 100644
index 1ef99e8de2..0000000000
--- a/Silicon/NXP/Library/SocLib/Chassis.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/** @file
- SoC specific Library containg functions to initialize various SoC components
-
- Copyright 2017-2020 NXP
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <Base.h>
-#ifdef CHASSIS2
-#include <Chassis2/NxpSoc.h>
-#elif CHASSIS3
-#include <Chassis3/NxpSoc.h>
-#endif
-#include <Library/ArmSmcLib.h>
-#include <Library/BaseLib.h>
-#include <Library/IoAccessLib.h>
-#include <Library/DebugLib.h>
-#include <Library/IoLib.h>
-#include <Library/PcdLib.h>
-#include <Library/PrintLib.h>
-#include <Library/SerialPortLib.h>
-
-#include "NxpChassis.h"
-
-UINT32
-EFIAPI
-GurRead (
- IN UINTN Address
- )
-{
- if (FixedPcdGetBool (PcdGurBigEndian)) {
- return SwapMmioRead32 (Address);
- } else {
- return MmioRead32 (Address);
- }
-}
-
-/*
- * Return system bus frequency
- */
-UINT64
-GetBusFrequency (
- VOID
- )
-{
- SYS_INFO SocSysInfo;
-
- GetSysInfo (&SocSysInfo);
-
- return SocSysInfo.FreqSystemBus;
-}
-
-/*
- * Setup SMMU in bypass mode
- * and also set its pagesize
- */
-VOID
-SmmuInit (
- VOID
- )
-{
- UINT32 Value;
-
- /* set pagesize as 64K and ssmu-500 in bypass mode */
- Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
- MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
-
- Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
- MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
-
- Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
- MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
-}
-
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
deleted file mode 100644
index a3dabc93d1..0000000000
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/** @Soc.c
- SoC specific Library containg functions to initialize various SoC components
-
- Copyright 2017-2020 NXP
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <Base.h>
-#include <NxpChassis.h>
-#include <Chassis2/NxpSoc.h>
-#include <Library/BaseLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/DebugLib.h>
-#include <Library/IoAccessLib.h>
-#include <Library/IoLib.h>
-#include <Library/PcdLib.h>
-#include <Library/PrintLib.h>
-#include <Library/SerialPortLib.h>
-
-/**
- Calculate the frequency of various controllers and
- populate the passed structure with frequuencies.
-
- @param PtrSysInfo Input structure to populate with
- frequencies.
-**/
-VOID
-GetSysInfo (
- OUT SYS_INFO *PtrSysInfo
- )
-{
- CCSR_GUR *GurBase;
- UINTN SysClk;
-
- GurBase = (CCSR_GUR *)CHASSIS2_DCFG_ADDRESS;
- SysClk = CLK_FREQ;
-
- SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
-
- PtrSysInfo->FreqSystemBus = SysClk;
-
- //
- // selects the platform clock:SYSCLK ratio and calculate
- // system frequency
- //
- PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
- CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
- CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
-}
-
-/**
- Function to initialize SoC specific constructs
- CPU Info
- SoC Personality
- Board Personality
- RCW prints
- **/
-VOID
-SocInit (
- VOID
- )
-{
- UINT64 BaudRate;
- UINT32 ReceiveFifoDepth;
- EFI_PARITY_TYPE Parity;
- UINT8 DataBits;
- EFI_STOP_BITS_TYPE StopBits;
- UINT32 Timeout;
-
- BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
- ReceiveFifoDepth = 0; // Use default FIFO depth
- Timeout = 0;
- Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
- DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
- StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);
-
- SmmuInit ();
-
- //
- // Early init serial Port to get board information.
- //
- SerialPortSetAttributes (
- &BaudRate,
- &ReceiveFifoDepth,
- &Timeout,
- &Parity,
- &DataBits,
- &StopBits
- );
- DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a on %a)\n",
- (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__));
-
- return;
-}
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
deleted file mode 100644
index d8707927b7..0000000000
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ /dev/null
@@ -1,44 +0,0 @@
-# @file
-#
-# Copyright 2017-2020 NXP
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-
-[Defines]
- INF_VERSION = 0x0001001A
- BASE_NAME = SocLib
- FILE_GUID = e868c5ca-9729-43ae-bff4-438c67de8c68
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = SocLib
-
-[Packages]
- ArmPkg/ArmPkg.dec
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
- Silicon/NXP/NxpQoriqLs.dec
- Silicon/NXP/LS1043A/LS1043A.dec
-
-[LibraryClasses]
- ArmSmcLib
- BaseLib
- DebugLib
- IoAccessLib
- SerialPortLib
-
-[Sources.common]
- Chassis.c
- Chassis2/Soc.c
-
-[BuildOptions]
- GCC:*_*_*_CC_FLAGS = -DCHASSIS2
-
-[FixedPcd]
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
- gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
- gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h b/Silicon/NXP/Library/SocLib/NxpChassis.h
deleted file mode 100644
index 99f6439d8f..0000000000
--- a/Silicon/NXP/Library/SocLib/NxpChassis.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/** @file
-* Header defining the Base addresses, sizes, flags etc for chassis 1
-*
-* Copyright 2017-2019 NXP
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-
-#ifndef NXP_CHASSIS_H_
-#define NXP_CHASSIS_H_
-
-#define TP_ITYP_AV_MASK 0x00000001 /* Initiator available */
-#define TP_ITYP_TYPE_MASK(x) (((x) & 0x6) >> 1) /* Initiator Type */
-#define TP_ITYP_TYPE_ARM 0x0
-#define TP_ITYP_TYPE_PPC 0x1
-#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
-#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
-#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
-#define TP_ITYP_VERSION(x) (((x) & 0xe0) >> 5) /* Initiator Version */
-#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
-#define TP_INIT_PER_CLUSTER 4
-
-#define TY_ITYP_VERSION_A7 0x1
-#define TY_ITYP_VERSION_A53 0x2
-#define TY_ITYP_VERSION_A57 0x3
-#define TY_ITYP_VERSION_A72 0x4
-
-#define CPU_TYPE_ENTRY(N, V, NC) { .Name = #N, .SocVer = SVR_##V, .NumCores = (NC)}
-
-#define SVR_WO_E 0xFFFFFE
-#define SVR_LS1043A 0x879200
-#define SVR_LS1046A 0x870700
-#define SVR_LS2088A 0x870901
-
-#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
-#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
-#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
-#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
-
-#define MHZ 1000000
-
-typedef struct {
- CHAR8 *Name;
- UINT32 SocVer;
- UINT32 NumCores;
-} CPU_TYPE;
-
-typedef struct {
- UINTN CpuClk; /* CPU clock in Hz! */
- UINTN BusClk;
- UINTN MemClk;
- UINTN PciClk;
- UINTN SdhcClk;
-} SOC_CLOCK_INFO;
-
-/*
- * Print Soc information
- */
-VOID
-PrintSoc (
- VOID
- );
-
-/*
- * Initialize Clock structure
- */
-VOID
-ClockInit (
- VOID
- );
-
-/*
- * Setup SMMU in bypass mode
- * and also set its pagesize
- */
-VOID
-SmmuInit (
- VOID
- );
-
-/*
- * Print CPU information
- */
-VOID
-PrintCpuInfo (
- VOID
- );
-
-/*
- * Dump RCW (Reset Control Word) on console
- */
-VOID
-PrintRCW (
- VOID
- );
-
-UINT32
-InitiatorType (
- IN UINT32 Cluster,
- IN UINTN InitId
- );
-
-/*
- * Return the mask for number of cores on this SOC.
- */
-UINT32
-CpuMask (
- VOID
- );
-
-/*
- * Return the number of cores on this SOC.
- */
-UINTN
-CpuNumCores (
- VOID
- );
-
-/*
- * Return the type of initiator for core/hardware accelerator for given core index.
- */
-UINTN
-QoriqCoreToType (
- IN UINTN Core
- );
-
-/*
- * Return the cluster of initiator for core/hardware accelerator for given core index.
- */
-INT32
-QoriqCoreToCluster (
- IN UINTN Core
- );
-
-#endif /* NXP_CHASSIS_H_ */
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 15/19] Platform/NXP/LS1043ARDB: introduce PEI Phase
2020-02-07 12:43 [PATCH 00/19] ADD LX2160ARDB Platform Support Pankaj Bansal
` (13 preceding siblings ...)
2020-02-07 12:43 ` [PATCH 14/19] Silicon/NXP/LS1043A: Replce SocLib Pankaj Bansal
@ 2020-02-07 12:43 ` Pankaj Bansal
2020-02-12 20:24 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 16/19] Silicon/NXP: Add Pl011 Serial port lib Pankaj Bansal
` (3 subsequent siblings)
18 siblings, 1 reply; 49+ messages in thread
From: Pankaj Bansal @ 2020-02-07 12:43 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, Varun Sethi
Cc: devel, Pankaj Bansal
Added PEI phase to LS1043ARDB.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Platform/NXP/FVRules.fdf.inc | 60 ++++---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 13 --
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 19 ++-
.../AArch64/ArmPlatformHelper.S | 46 +++++
.../ArmPlatformLib/AArch64/NxpQoriqLsHelper.S | 31 ----
.../Library/ArmPlatformLib/ArmPlatformLib.c | 86 +++++-----
.../Library/ArmPlatformLib/ArmPlatformLib.inf | 19 ++-
.../ArmPlatformLib/ArmPlatformLibMem.c | 27 ++-
Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc | 91 ++++++++++
.../MemoryInitPeiLib.c | 160 +++++++++---------
.../MemoryInitPeiLib.h | 1 -
.../MemoryInitPeiLib.inf | 24 +--
.../Library/PlatformPeiLib/PlatformPeiLib.c | 30 ++++
.../Library/PlatformPeiLib/PlatformPeiLib.inf | 50 ++++++
Silicon/NXP/NxpQoriqLs.dec | 21 +--
Silicon/NXP/NxpQoriqLs.dsc.inc | 67 +++++---
16 files changed, 481 insertions(+), 264 deletions(-)
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
delete mode 100644 Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/NxpQoriqLsHelper.S
create mode 100644 Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
rename Silicon/NXP/Library/{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.c (82%)
rename Silicon/NXP/Library/{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.h (94%)
rename Silicon/NXP/Library/{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.inf (80%)
create mode 100644 Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c
create mode 100644 Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
diff --git a/Platform/NXP/FVRules.fdf.inc b/Platform/NXP/FVRules.fdf.inc
index c9fba65dae..598262e045 100644
--- a/Platform/NXP/FVRules.fdf.inc
+++ b/Platform/NXP/FVRules.fdf.inc
@@ -1,8 +1,8 @@
-# FvRules.fdf.inc
#
-# Rules for creating FD.
-#
-# Copyright 2017-2019 NXP
+# Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+# Copyright (c) 2014-2016, Linaro Limited. All rights reserved.
+# Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+# Copyright 2017-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -16,40 +16,49 @@
#
################################################################################
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
[Rule.Common.SEC]
- FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
- TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED {
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
}
[Rule.Common.PEI_CORE]
- FILE PEI_CORE = $(NAMED_GUID) {
- TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
+ FILE PEI_CORE = $(NAMED_GUID) FIXED {
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING ="$(MODULE_NAME)" Optional
}
[Rule.Common.PEIM]
- FILE PEIM = $(NAMED_GUID) {
+ FILE PEIM = $(NAMED_GUID) FIXED {
PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
}
-[Rule.Common.PEIM.TIANOCOMPRESSED]
- FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
- PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING="$(MODULE_NAME)" Optional
- }
- }
-
[Rule.Common.DXE_CORE]
FILE DXE_CORE = $(NAMED_GUID) {
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
}
-
[Rule.Common.UEFI_DRIVER]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
@@ -62,6 +71,8 @@
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
+ RAW ACPI Optional |.acpi
+ RAW ASL Optional |.aml
}
[Rule.Common.DXE_RUNTIME_DRIVER]
@@ -73,7 +84,7 @@
[Rule.Common.UEFI_APPLICATION]
FILE APPLICATION = $(NAMED_GUID) {
- UI STRING ="$(MODULE_NAME)" Optional
+ UI STRING ="$(MODULE_NAME)" Optional
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
}
@@ -91,3 +102,10 @@
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ACPI |.acpi
+ RAW ASL |.aml
+ UI STRING="$(MODULE_NAME)" Optional
+ }
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index 4bc7f6ef97..c9f828668f 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -32,19 +32,6 @@
[PcdsFixedAtBuild.common]
- #
- # LS1043a board Specific PCDs
- # XX (DRAM - Region 1 2GB)
- # (NOR - IFC Region 1 512MB)
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
- gArmTokenSpaceGuid.PcdSystemMemorySize|0x7BE00000
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
-
- #
- # Board Specific Pcds
- #
- gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
-
#
# RTC Pcds
#
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
index 8d66f36d74..22391899b7 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
@@ -3,7 +3,7 @@
# FLASH layout file for LS1043a board.
#
# Copyright (c) 2016, Freescale Ltd. All rights reserved.
-# Copyright 2017-2019 NXP
+# Copyright 2017-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -24,10 +24,10 @@
[FD.LS1043ARDB_EFI]
BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
-Size = 0x000ED000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
+Size = 0x00100000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
ErasePolarity = 1
BlockSize = 0x1
-NumBlocks = 0xED000
+NumBlocks = 0x100000
################################################################################
#
@@ -44,10 +44,11 @@ NumBlocks = 0xED000
# RegionType <FV, DATA, or FILE>
#
################################################################################
-0x00000000|0x000ED000
+0x00000000|0x00100000
gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
FV = FVMAIN_COMPACT
+!include VarStore.fdf.inc
!include Platform/NXP/FVRules.fdf.inc
################################################################################
#
@@ -158,7 +159,15 @@ READ_STATUS = TRUE
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
- INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+ INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
new file mode 100644
index 0000000000..d1b9f1debb
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
@@ -0,0 +1,46 @@
+//
+// Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//
+
+#include <AsmMacroIoLibV8.h>
+#include <Library/ArmLib.h>
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+ ret
+
+//UINTN
+//ArmPlatformGetCorePosition (
+// IN UINTN MpId
+// );
+// With this function: CorePos = (ClusterId * 4) + CoreId
+ASM_FUNC(ArmPlatformGetCorePosition)
+ and x1, x0, #ARM_CORE_MASK
+ and x0, x0, #ARM_CLUSTER_MASK
+ add x0, x1, x0, LSR #6
+ ret
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+// VOID
+// );
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+ MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore))
+ ret
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+// IN UINTN MpId
+// );
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+ MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
+ and x0, x0, x1
+ MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore))
+ cmp w0, w1
+ mov x0, #1
+ mov x1, #0
+ csel x0, x0, x1, eq
+ ret
+
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/NxpQoriqLsHelper.S b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/NxpQoriqLsHelper.S
deleted file mode 100644
index dfbf73675a..0000000000
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/NxpQoriqLsHelper.S
+++ /dev/null
@@ -1,31 +0,0 @@
-# @file
-#
-# Copyright (c) 2012-2013, ARM Limited. All rights reserved.
-# Copyright 2017, 2020 NXP
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-
-#include <AsmMacroIoLibV8.h>
-#include <AutoGen.h>
-
-.text
-.align 2
-
-GCC_ASM_IMPORT(ArmReadMpidr)
-
-ASM_FUNC(ArmPlatformIsPrimaryCore)
- tst x0, #3
- cset x0, eq
- ret
-
-ASM_FUNC(ArmPlatformPeiBootAction)
-EL1_OR_EL2(x0)
-1:
-2:
- ret
-
-ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
- MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore))
- ldrh w0, [x0]
- ret
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
index 821d413a3e..f1d67d6c7d 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -1,8 +1,4 @@
-/** ArmPlatformLib.c
-*
-* Contains board initialization functions.
-*
-* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
+/** @file
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
@@ -19,19 +15,18 @@
#include <Library/SocLib.h>
#include <Ppi/NxpPlatformGetClock.h>
-/**
- Return the current Boot Mode
-
- This function returns the boot reason on the platform
+ARM_CORE_INFO mArmPlatformMpCoreInfoTable[] = {
+ {
+ // Cluster 0, Core 0
+ 0, 0,
-**/
-EFI_BOOT_MODE
-ArmPlatformGetBootMode (
- VOID
- )
-{
- return BOOT_WITH_FULL_CONFIGURATION;
-}
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (UINT64)0xFFFFFFFF
+ },
+};
/**
Get the clocks supplied by Platform(Board) to NXP Layerscape SOC
@@ -77,11 +72,29 @@ NxpPlatformGetClock(
}
/**
- Placeholder for Platform Initialization
+ Return the current Boot Mode
+
+ This function returns the boot reason on the platform
+
**/
-EFI_STATUS
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Initialize controllers that must setup in the normal world
+
+ This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
+ in the PEI phase.
+
+**/
+RETURN_STATUS
ArmPlatformInitialize (
- IN UINTN MpId
+ IN UINTN MpId
)
{
SocInit ();
@@ -89,29 +102,19 @@ ArmPlatformInitialize (
return EFI_SUCCESS;
}
-ARM_CORE_INFO LS1043aMpCoreInfoCTA53x4[] = {
- {
- // Cluster 0, Core 0
- 0x0, 0x0,
-
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value
- (EFI_PHYSICAL_ADDRESS)0,
- (EFI_PHYSICAL_ADDRESS)0,
- (EFI_PHYSICAL_ADDRESS)0,
- (UINT64)0xFFFFFFFF
- },
-};
-
EFI_STATUS
PrePeiCoreGetMpCoreInfo (
OUT UINTN *CoreCount,
OUT ARM_CORE_INFO **ArmCoreTable
)
{
- *CoreCount = sizeof (LS1043aMpCoreInfoCTA53x4) / sizeof (ARM_CORE_INFO);
- *ArmCoreTable = LS1043aMpCoreInfoCTA53x4;
-
- return EFI_SUCCESS;
+ if (ArmIsMpCore()) {
+ *CoreCount = sizeof (mArmPlatformMpCoreInfoTable) / sizeof (ARM_CORE_INFO);
+ *ArmCoreTable = mArmPlatformMpCoreInfoTable;
+ return EFI_SUCCESS;
+ } else {
+ return EFI_UNSUPPORTED;
+ }
}
ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
@@ -125,6 +128,7 @@ EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
}
};
+
VOID
ArmPlatformGetPlatformPpiList (
OUT UINTN *PpiListSize,
@@ -135,11 +139,3 @@ ArmPlatformGetPlatformPpiList (
*PpiList = gPlatformPpiTable;
}
-
-UINTN
-ArmPlatformGetCorePosition (
- IN UINTN MpId
- )
-{
- return 1;
-}
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
index 8b79fd7490..beb94fba64 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -1,24 +1,24 @@
-# @file
-#
+#/* @file
# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
# Copyright 2017, 2019-2020 NXP
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
+#*/
[Defines]
INF_VERSION = 0x0001001A
- BASE_NAME = PlatformLib
+ BASE_NAME = ArmPlatformLib
FILE_GUID = 736343a0-1d96-11e0-aaaa-0002a5d5c51b
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmPlatformLib
[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
- EmbeddedPkg/EmbeddedPkg.dec
- MdePkg/MdePkg.dec
Silicon/NXP/NxpQoriqLs.dec
Silicon/NXP/Chassis2/Chassis2.dec
Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
@@ -30,13 +30,14 @@
DebugLib
[Sources.common]
- AArch64/NxpQoriqLsHelper.S | GCC
+ AArch64/ArmPlatformHelper.S | GCC
ArmPlatformLibMem.c
ArmPlatformLib.c
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+
[Ppis]
gArmMpCoreInfoPpiGuid
-[FixedPcd]
- gArmTokenSpaceGuid.PcdArmPrimaryCore
- gArmPlatformTokenSpaceGuid.PcdCoreCount
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
index 3a72c8bdd8..822afb2188 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
@@ -1,8 +1,4 @@
-/** NxpQoriqLsMem.c
-*
-* Board memory specific Library.
-*
-* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c
+/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
@@ -14,10 +10,11 @@
#include <Library/ArmPlatformLib.h>
#include <Library/DebugLib.h>
-#include <Library/PcdLib.h>
+#include <Library/HobLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Soc.h>
+// Number of Virtual Memory Map Descriptors
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
/**
@@ -25,28 +22,28 @@
This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
- @param VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
- Virtual Memory mapping. This array must be ended by a zero-filled
- entry
+ @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+ Virtual Memory mapping. This array must be ended by a zero-filled
+ entry
**/
-
VOID
ArmPlatformGetVirtualMemoryMap (
- IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap
+ IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
)
{
- UINTN Index;
- ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+ UINT32 Index;
Index = 0;
ASSERT (VirtualMemoryMap != NULL);
- VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (
- EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+ VirtualMemoryTable = AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) *
+ MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
if (VirtualMemoryTable == NULL) {
+ DEBUG ((DEBUG_ERROR, "%a: Error: Failed AllocatePool()\n", __FUNCTION__));
return;
}
diff --git a/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc b/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
new file mode 100644
index 0000000000..c6cb3339d9
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
@@ -0,0 +1,91 @@
+## @file
+# FDF include file with FD definition that defines an empty variable store.
+#
+# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+# Copyright (C) 2014, Red Hat, Inc.
+# Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+# Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+# Copyright 2017-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[FD.LS1043ARDBNV_EFI]
+BaseAddress = 0x60500000
+Size = 0x000C0000
+ErasePolarity = 1
+BlockSize = 0x1
+NumBlocks = 0xC0000
+
+#
+# Place NV Storage just above Platform Data Base
+#
+DEFINE NVRAM_AREA_VARIABLE_BASE = 0x00000000
+DEFINE NVRAM_AREA_VARIABLE_SIZE = 0x00040000
+DEFINE FTW_WORKING_BASE = $(NVRAM_AREA_VARIABLE_BASE) + $(NVRAM_AREA_VARIABLE_SIZE)
+DEFINE FTW_WORKING_SIZE = 0x00040000
+DEFINE FTW_SPARE_BASE = $(FTW_WORKING_BASE) + $(FTW_WORKING_SIZE)
+DEFINE FTW_SPARE_SIZE = 0x00040000
+
+#############################################################################
+# LS1043ARDB NVRAM Area
+# LS1043ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare
+#############################################################################
+
+
+$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER
+ # ZeroVector []
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # FileSystemGuid: gEfiSystemNvDataFvGuid =
+ # { 0xFFF12B8D, 0x7696, 0x4C8B,
+ # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+ # FvLength: Flash Size : 0x4000000
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
+ # Signature "_FVH" # Attributes
+ 0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
+ # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+ 0x48, 0x00, 0x08, 0xA6, 0x00, 0x00, 0x00, 0x02,
+ # Blockmap[0]: 0x4000 Blocks * 0x1000 Bytes / Block = SIZE_64MB
+ 0x00, 0x40, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
+ # Blockmap[1]: End
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ ## This is the VARIABLE_STORE_HEADER
+ # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
+ # Signature: gEfiVariableGuid =
+ # { 0xddcf3616, 0x3275, 0x4164,
+ # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+ 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+ 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+ # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+ # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
+ # This can speed up the Variable Dispatch a bit.
+ 0xB8, 0xFF, 0x03, 0x00,
+ # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+ # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
+ # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
+ 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+ 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
+ # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+ 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
+ # WriteQueueSize: UINT64
+ 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+#NV_FTW_SPARE
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
similarity index 82%
rename from Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
rename to Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
index eb1983bdbc..3d04e05283 100644
--- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
+++ b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
@@ -1,7 +1,6 @@
/** @file
*
* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
-*
* Copyright 2019-2020 NXP
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -10,42 +9,18 @@
#include <PiPei.h>
+#include <Library/ArmSmcLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
#include <Library/ArmMmuLib.h>
#include <Library/ArmPlatformLib.h>
-#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/HobLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
-#include <Library/ArmSmcLib.h>
#include "MemoryInitPeiLib.h"
-
-VOID
-BuildMemoryTypeInformationHob (
- VOID
- );
-
-VOID
-InitMmu (
- IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable
- )
-{
-
- VOID *TranslationTableBase;
- UINTN TranslationTableSize;
- RETURN_STATUS Status;
-
- //Note: Because we called PeiServicesInstallPeiMemory() before
- //to call InitMmu() the MMU Page Table resides in DRAM
- //(even at the top of DRAM as it is the first permanent memory allocation)
- Status = ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);
- if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "Error: Failed to enable MMU\n"));
- }
-}
-
STATIC
UINTN
CalculateReservedMemBase (
@@ -62,7 +37,7 @@ CalculateReservedMemBase (
UINTN ReservedBaseAddress;
INTN Index2;
- ReservedMemAlignment = FixedPcdGet64 (PcdReservedMemAlignment);
+ ReservedMemAlignment = PcdGet64 (PcdReservedMemAlignment);
//
// Compute alignment bit mask
//
@@ -125,56 +100,26 @@ CalculateReservedMemBase (
}
}
-/*++
-
-Routine Description:
-
-
-
-Arguments:
-
- FileHandle - Handle of the file being invoked.
- PeiServices - Describes the list of possible PEI Services.
-
-Returns:
-
- Status - EFI_SUCCESS if the boot mode could be set
-
---*/
-EFI_STATUS
+RETURN_STATUS
EFIAPI
-MemoryPeim (
- IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
- IN UINT64 UefiMemorySize
+MemoryInitPeiLibConstructor (
+ VOID
)
{
- ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
- ARM_SMC_ARGS ArmSmcArgs;
- INT32 Index;
- UINTN DramSize;
- UINTN BaseAddress;
- UINTN Size;
- UINTN Top;
+ ARM_SMC_ARGS ArmSmcArgs;
+ INT32 Index;
+ UINTN DramSize;
+ UINTN BaseAddress;
+ UINTN Size;
+ UINTN Top;
// Extra region gets created if we want to reserve a memory region and that creates a memory hole
// because of alignement requirements
- DRAM_REGION_INFO DramRegions[MAX_DRAM_REGIONS + 1];
- EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
- UINTN FdBase;
- UINTN FdTop;
- BOOLEAN FoundSystemMem;
-
- // Get Virtual Memory Map from the Platform Library
- ArmPlatformGetVirtualMemoryMap (&MemoryTable);
-
- //
- // Ensure MemoryTable[0].Length which is size of DRAM has been set
- // by ArmPlatformGetVirtualMemoryMap ()
- //
- ASSERT (MemoryTable[0].Length != 0);
+ DRAM_REGION_INFO DramRegions[MAX_DRAM_REGIONS + 1];
+ EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
+ UINTN FdBase;
+ UINTN FdTop;
+ BOOLEAN FoundSystemMem;
- //
- // Now, the permanent memory has been installed, we can call AllocatePages()
- //
ResourceAttributes = (
EFI_RESOURCE_ATTRIBUTE_PRESENT |
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
@@ -214,16 +159,17 @@ MemoryPeim (
ASSERT (!DramSize);
// Get the reserved memory size from non volatile storage
- Size = FixedPcdGet64 (PcdReservedMemSize);
+ Size = PcdGet64 (PcdReservedMemSize);
if (Size) {
BaseAddress = CalculateReservedMemBase (DramRegions, Index, Size);
if (BaseAddress) {
DEBUG ((DEBUG_INFO, "ReservedMem: start 0x%lx, size 0x%lx\n", BaseAddress, Size));
+ PcdSet64S (PcdReservedMemBase, BaseAddress);
}
}
- FdBase = (UINTN)FixedPcdGet64 (PcdFdBaseAddress);
- FdTop = FdBase + (UINTN)FixedPcdGet32 (PcdFdSize);
+ FdBase = (UINTN)PcdGet64 (PcdFdBaseAddress);
+ FdTop = FdBase + (UINTN)PcdGet32 (PcdFdSize);
// Declare memory regios to system
for (Index = MAX_DRAM_REGIONS; Index >= 0; Index--) {
@@ -266,8 +212,8 @@ MemoryPeim (
);
};
// Mark the memory covering the Firmware Device as boot services data
- BuildMemoryAllocationHob (FixedPcdGet64 (PcdFdBaseAddress),
- FixedPcdGet32 (PcdFdSize),
+ BuildMemoryAllocationHob (PcdGet64 (PcdFdBaseAddress),
+ PcdGet32 (PcdFdSize),
EfiBootServicesData);
}else {
BuildResourceDescriptorHob (
@@ -287,16 +233,72 @@ MemoryPeim (
Top = DramRegions[Index].BaseAddress + DramRegions[Index].Size;
if (FdBase >= BaseAddress && FdTop <= Top) {
- Size -= (UINTN)FixedPcdGet32 (PcdFdSize);
+ Size -= (UINTN)PcdGet32 (PcdFdSize);
}
if (Size >= FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)) {
FoundSystemMem = TRUE;
+ PcdSet64S (PcdSystemMemoryBase, BaseAddress);
+ PcdSet64S (PcdSystemMemorySize, Size);
}
}
ASSERT (FoundSystemMem);
+ return EFI_SUCCESS;
+}
+
+VOID
+BuildMemoryTypeInformationHob (
+ VOID
+ );
+
+STATIC
+VOID
+InitMmu (
+ IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable
+ )
+{
+ VOID *TranslationTableBase;
+ UINTN TranslationTableSize;
+ RETURN_STATUS Status;
+
+ //Note: Because we called PeiServicesInstallPeiMemory() before to call InitMmu() the MMU Page Table resides in
+ // DRAM (even at the top of DRAM as it is the first permanent memory allocation)
+ Status = ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Error: Failed to enable MMU\n"));
+ }
+}
+
+/*++
+
+Routine Description:
+
+
+
+Arguments:
+
+ FileHandle - Handle of the file being invoked.
+ PeiServices - Describes the list of possible PEI Services.
+
+Returns:
+
+ Status - EFI_SUCCESS if the boot mode could be set
+
+--*/
+EFI_STATUS
+EFIAPI
+MemoryPeim (
+ IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
+ IN UINT64 UefiMemorySize
+ )
+{
+ ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
+
+ // Get Virtual Memory Map from the Platform Library
+ ArmPlatformGetVirtualMemoryMap (&MemoryTable);
+
// Build Memory Allocation Hob
InitMmu (MemoryTable);
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.h
similarity index 94%
rename from Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
rename to Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.h
index e563b2ba8d..c3c42ed8a3 100644
--- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
+++ b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.h
@@ -21,4 +21,3 @@ typedef struct {
} DRAM_REGION_INFO;
#endif
-
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
similarity index 80%
rename from Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
rename to Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
index 9adddcaf8c..4d932444a3 100644
--- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
+++ b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
@@ -8,32 +8,32 @@
#**/
[Defines]
- INF_VERSION = 0x0001001A
+ INF_VERSION = 0x00010005
BASE_NAME = ArmMemoryInitPeiLib
FILE_GUID = 55ddb6e0-70b5-11e0-b33e-0002a5d5c51b
MODULE_TYPE = BASE
VERSION_STRING = 1.0
- LIBRARY_CLASS = MemoryInitPeiLib|SEC PEIM DXE_DRIVER
+ LIBRARY_CLASS = MemoryInitPeiLib|PEIM
+ CONSTRUCTOR = MemoryInitPeiLibConstructor
[Sources]
MemoryInitPeiLib.c
-
[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
- EmbeddedPkg/EmbeddedPkg.dec
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
Silicon/NXP/NxpQoriqLs.dec
[LibraryClasses]
- ArmMmuLib
- ArmPlatformLib
DebugLib
HobLib
- PcdLib
+ ArmMmuLib
+ ArmPlatformLib
ArmSmcLib
+ PcdLib
[Guids]
gEfiMemoryTypeInformationGuid
@@ -44,13 +44,15 @@
[FixedPcd]
gArmTokenSpaceGuid.PcdFdBaseAddress
gArmTokenSpaceGuid.PcdFdSize
+
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize
- gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize
- gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment
[Pcd]
gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemBase
[Depex]
TRUE
diff --git a/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c
new file mode 100644
index 0000000000..f64e564469
--- /dev/null
+++ b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c
@@ -0,0 +1,30 @@
+/** @file
+*
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+* Copyright 2020 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <PiPei.h>
+
+#include <Library/HobLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+#define XPRINT(x) PRINT(x)
+#define PRINT(x) #x
+
+EFI_STATUS
+EFIAPI
+PlatformPeim (
+ VOID
+ )
+{
+ BuildFvHob (PcdGet64 (PcdFvBaseAddress), PcdGet32 (PcdFvSize));
+ DEBUG ((DEBUG_INIT, "Edk2 version is %a\n", XPRINT (WORKSPACE_GIT_VERSION)));
+ DEBUG ((DEBUG_INIT, "Edk2 platforms version is %a\n", XPRINT (PACKAGES_PATH_GIT_VERSION)));
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
new file mode 100644
index 0000000000..b0481dece0
--- /dev/null
+++ b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
@@ -0,0 +1,50 @@
+#/** @file
+#
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmPlatformPeiLib
+ FILE_GUID = 49d37060-70b5-11e0-aa2d-0002a5d5c51b
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformPeiLib
+
+[BuildOptions]
+ GCC:*_*_*_CC_FLAGS = -DWORKSPACE_GIT_VERSION="$(WORKSPACE_GIT_VERSION)"
+ GCC:*_*_*_CC_FLAGS = -DPACKAGES_PATH_GIT_VERSION="$(PACKAGES_PATH_GIT_VERSION)"
+
+[Sources]
+ PlatformPeiLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ DebugLib
+ HobLib
+ PcdLib
+
+[Ppis]
+ gEfiPeiMasterBootModePpiGuid # PPI ALWAYS_PRODUCED
+ gEfiPeiBootInRecoveryModePpiGuid # PPI SOMETIMES_PRODUCED
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdFdBaseAddress
+ gArmTokenSpaceGuid.PcdFdSize
+
+ gArmTokenSpaceGuid.PcdFvBaseAddress
+ gArmTokenSpaceGuid.PcdFvSize
+
+[depex]
+ TRUE
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index c327e738cc..0a90334c02 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -27,21 +27,12 @@
gNxpQoriqLsTokenSpaceGuid = {0x98657342, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
-[PcdsFixedAtBuild.common]
- #
- # Platform PCDs
- #
- gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
-
- #
- # Pcds to support Big Endian IPs
- #
- gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311
-
- gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize|0x0|UINT64|0x00000315
- gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment|0x0|UINT64|0x00000316
+[PcdsDynamic,PcdsPatchableInModule]
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemBase|0x0|UINT64|0x00000001
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize|0x0|UINT64|0x00000002
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment|0x0|UINT64|0x00000003
[PcdsFeatureFlag]
- gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000317
- gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000318
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000004
+ gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000005
diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index 94d3e53a04..9922686304 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -93,29 +93,35 @@
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
I2cLib|Silicon/NXP/Library/I2cLib/I2cLib.inf
ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
+ PlatformPeiLib|Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
+ MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
[LibraryClasses.common.SEC]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
- UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
- ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
- LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
- PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
- HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
- PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
- MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
- PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
- PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
- MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
- # 1/123 faster than Stm or Vstm version
- BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+
+[LibraryClasses.common.PEI_CORE]
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
- # Uncomment to turn on GDB stub in SEC.
- #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
+ PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
[LibraryClasses.common.PEIM]
PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
@@ -124,14 +130,16 @@
PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
[LibraryClasses.common.DXE_CORE]
HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
- UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
@@ -139,7 +147,6 @@
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
- MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
[LibraryClasses.common.UEFI_APPLICATION]
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
@@ -204,6 +211,10 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x0
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x0
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemBase|0x0
+
[PcdsDynamicHii.common.DEFAULT]
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10
@@ -214,7 +225,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800
gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
- gArmPlatformTokenSpaceGuid.PcdCoreCount|1 # Only one core
gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|2000000
gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
@@ -224,6 +234,12 @@
gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+ ## Base of DRAM
+ ## since TFA puts Fd at 0x2000000 offset from DRAM base, we can use this space
+ ## for temporary ram
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x80000000
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
+
!if $(TARGET) == RELEASE
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000001
@@ -281,13 +297,26 @@
################################################################################
[Components.common]
#
- # SEC
+ # PEI Phase modules
#
- ArmPlatformPkg/PrePi/PeiUniCore.inf
+ ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+
+ MdeModulePkg/Core/Pei/PeiMain.inf
MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
<LibraryClasses>
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
}
+ MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+
+ ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ ArmPkg/Drivers/CpuPei/CpuPei.inf
+ ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ }
#
# DXE
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 16/19] Silicon/NXP: Add Pl011 Serial port lib
2020-02-07 12:43 [PATCH 00/19] ADD LX2160ARDB Platform Support Pankaj Bansal
` (14 preceding siblings ...)
2020-02-07 12:43 ` [PATCH 15/19] Platform/NXP/LS1043ARDB: introduce PEI Phase Pankaj Bansal
@ 2020-02-07 12:43 ` Pankaj Bansal
2020-02-12 20:26 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 17/19] Silicon/NXP: Add Chassis3V2 Pankaj Bansal
` (2 subsequent siblings)
18 siblings, 1 reply; 49+ messages in thread
From: Pankaj Bansal @ 2020-02-07 12:43 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, Varun Sethi
Cc: devel, Pankaj Bansal
Use ArmPlatformPkg/PL011SerialPortLib with some changes:
1. add Get clock API to get the UART clock from ArmPlatformLib
2. remove SerialPortInitalize functionality
This is same as being done in Silicon/NXP/Library/BaseSerialPortLib16550.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
.../PL011SerialPortLib/PL011SerialPortLib.c | 229 ++++++++++++++++++
.../PL011SerialPortLib/PL011SerialPortLib.inf | 42 ++++
Silicon/NXP/NxpQoriqLs.dsc.inc | 1 +
3 files changed, 272 insertions(+)
create mode 100644 Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.c
create mode 100644 Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.inf
diff --git a/Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.c b/Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.c
new file mode 100644
index 0000000000..35cfe8e324
--- /dev/null
+++ b/Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.c
@@ -0,0 +1,229 @@
+/** @file
+ Serial I/O Port library functions with no library constructor/destructor
+
+ Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2012 - 2016, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PL011UartClockLib.h>
+#include <Library/PL011UartLib.h>
+#include <Library/SerialPortLib.h>
+#include <Ppi/NxpPlatformGetClock.h>
+
+extern NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi;
+
+/** Initialise the serial device hardware with default settings.
+
+ @retval RETURN_SUCCESS The serial device was initialised.
+ @retval RETURN_INVALID_PARAMETER One or more of the default settings
+ has an unsupported value.
+ **/
+RETURN_STATUS
+EFIAPI
+SerialPortInitialize (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Write data to serial device.
+
+ @param Buffer Point of data buffer which need to be written.
+ @param NumberOfBytes Number of output bytes which are cached in Buffer.
+
+ @retval 0 Write data failed.
+ @retval !0 Actual number of bytes written to serial device.
+
+**/
+UINTN
+EFIAPI
+SerialPortWrite (
+ IN UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+ )
+{
+ return PL011UartWrite ((UINTN)PcdGet64 (PcdSerialRegisterBase), Buffer, NumberOfBytes);
+}
+
+/**
+ Read data from serial device and save the data in buffer.
+
+ @param Buffer Point of data buffer which need to be written.
+ @param NumberOfBytes Number of output bytes which are cached in Buffer.
+
+ @retval 0 Read data failed.
+ @retval !0 Actual number of bytes read from serial device.
+
+**/
+UINTN
+EFIAPI
+SerialPortRead (
+ OUT UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+)
+{
+ return PL011UartRead ((UINTN)PcdGet64 (PcdSerialRegisterBase), Buffer, NumberOfBytes);
+}
+
+/**
+ Check to see if any data is available to be read from the debug device.
+
+ @retval TRUE At least one byte of data is available to be read
+ @retval FALSE No data is available to be read
+
+**/
+BOOLEAN
+EFIAPI
+SerialPortPoll (
+ VOID
+ )
+{
+ return PL011UartPoll ((UINTN)PcdGet64 (PcdSerialRegisterBase));
+}
+/**
+ Set new attributes to PL011.
+
+ @param BaudRate The baud rate of the serial device. If the
+ baud rate is not supported, the speed will
+ be reduced down to the nearest supported one
+ and the variable's value will be updated
+ accordingly.
+ @param ReceiveFifoDepth The number of characters the device will
+ buffer on input. If the specified value is
+ not supported, the variable's value will
+ be reduced down to the nearest supported one.
+ @param Timeout If applicable, the number of microseconds the
+ device will wait before timing out a Read or
+ a Write operation.
+ @param Parity If applicable, this is the EFI_PARITY_TYPE
+ that is computed or checked as each character
+ is transmitted or received. If the device
+ does not support parity, the value is the
+ default parity value.
+ @param DataBits The number of data bits in each character
+ @param StopBits If applicable, the EFI_STOP_BITS_TYPE number
+ of stop bits per character. If the device
+ does not support stop bits, the value is the
+ default stop bit value.
+
+ @retval EFI_SUCCESS All attributes were set correctly.
+ @retval EFI_INVALID_PARAMETERS One or more attributes has an unsupported
+ value.
+ @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortSetAttributes (
+ IN OUT UINT64 *BaudRate,
+ IN OUT UINT32 *ReceiveFifoDepth,
+ IN OUT UINT32 *Timeout,
+ IN OUT EFI_PARITY_TYPE *Parity,
+ IN OUT UINT8 *DataBits,
+ IN OUT EFI_STOP_BITS_TYPE *StopBits
+ )
+{
+ UINT64 SerialClock;
+
+ SerialClock = mPlatformGetClockPpi.PlatformGetClock (NXP_UART_CLOCK, 0);
+ if (SerialClock == 0) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ return PL011UartInitializePort (
+ (UINTN)PcdGet64 (PcdSerialRegisterBase),
+ SerialClock,
+ BaudRate,
+ ReceiveFifoDepth,
+ Parity,
+ DataBits,
+ StopBits
+ );
+}
+
+/**
+
+ Assert or deassert the control signals on a serial port.
+ The following control signals are set according their bit settings :
+ . Request to Send
+ . Data Terminal Ready
+
+ @param[in] Control The following bits are taken into account :
+ . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the
+ "Request To Send" control signal if this bit is
+ equal to one/zero.
+ . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert
+ the "Data Terminal Ready" control signal if this
+ bit is equal to one/zero.
+ . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable
+ the hardware loopback if this bit is equal to
+ one/zero.
+ . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.
+ . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/
+ disable the hardware flow control based on CTS (Clear
+ To Send) and RTS (Ready To Send) control signals.
+
+ @retval RETURN_SUCCESS The new control bits were set on the device.
+ @retval RETURN_UNSUPPORTED The device does not support this operation.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortSetControl (
+ IN UINT32 Control
+ )
+{
+ return PL011UartSetControl ((UINTN)PcdGet64 (PcdSerialRegisterBase), Control);
+}
+
+/**
+
+ Retrieve the status of the control bits on a serial device.
+
+ @param[out] Control Status of the control bits on a serial device :
+
+ . EFI_SERIAL_DATA_CLEAR_TO_SEND,
+ EFI_SERIAL_DATA_SET_READY,
+ EFI_SERIAL_RING_INDICATE,
+ EFI_SERIAL_CARRIER_DETECT,
+ EFI_SERIAL_REQUEST_TO_SEND,
+ EFI_SERIAL_DATA_TERMINAL_READY
+ are all related to the DTE (Data Terminal Equipment)
+ and DCE (Data Communication Equipment) modes of
+ operation of the serial device.
+ . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the
+ receive buffer is empty, 0 otherwise.
+ . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the
+ transmit buffer is empty, 0 otherwise.
+ . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if
+ the hardware loopback is enabled (the output feeds
+ the receive buffer), 0 otherwise.
+ . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one
+ if a loopback is accomplished by software, else 0.
+ . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to
+ one if the hardware flow control based on CTS (Clear
+ To Send) and RTS (Ready To Send) control signals is
+ enabled, 0 otherwise.
+
+ @retval RETURN_SUCCESS The control bits were read from the device.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortGetControl (
+ OUT UINT32 *Control
+ )
+{
+ return PL011UartGetControl ((UINTN)PcdGet64 (PcdSerialRegisterBase), Control);
+}
diff --git a/Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.inf b/Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.inf
new file mode 100644
index 0000000000..29f234027f
--- /dev/null
+++ b/Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.inf
@@ -0,0 +1,42 @@
+#/** @file
+#
+# Component description file for PL011SerialPortLib module
+#
+# Copyright (c) 2011-2016, ARM Ltd. All rights reserved.<BR>
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PL011SerialPortLib
+ FILE_GUID = 8ecefc8f-a2c4-4091-b80f-20f7aeb0567f
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SerialPortLib
+
+[Sources.common]
+ PL011SerialPortLib.c
+
+[LibraryClasses]
+ PL011UartLib
+ PcdLib
+ ArmPlatformLib
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+
+[FixedPcd]
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
index 9922686304..2ab6ee1920 100644
--- a/Silicon/NXP/NxpQoriqLs.dsc.inc
+++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
@@ -100,6 +100,7 @@
IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
PlatformPeiLib|Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
+ PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf
[LibraryClasses.common.SEC]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 17/19] Silicon/NXP: Add Chassis3V2
2020-02-07 12:43 [PATCH 00/19] ADD LX2160ARDB Platform Support Pankaj Bansal
` (15 preceding siblings ...)
2020-02-07 12:43 ` [PATCH 16/19] Silicon/NXP: Add Pl011 Serial port lib Pankaj Bansal
@ 2020-02-07 12:43 ` Pankaj Bansal
2020-02-12 20:33 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 18/19] Silicon/NXP: Add LX2160A SocLib Pankaj Bansal
2020-02-07 12:43 ` [PATCH 19/19] Platform/NXP: Add LX2160ARDBPKG Pankaj Bansal
18 siblings, 1 reply; 49+ messages in thread
From: Pankaj Bansal @ 2020-02-07 12:43 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, Varun Sethi
Cc: devel, Pankaj Bansal
Add Chassis3V2
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Silicon/NXP/Chassis3V2/Chassis3V2.dec | 23 +++
Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc | 10 +
Silicon/NXP/Chassis3V2/Include/Chassis.h | 42 ++++
.../Library/ChassisLib/ChassisLib.c | 186 ++++++++++++++++++
.../Library/ChassisLib/ChassisLib.inf | 41 ++++
5 files changed, 302 insertions(+)
create mode 100644 Silicon/NXP/Chassis3V2/Chassis3V2.dec
create mode 100644 Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
create mode 100644 Silicon/NXP/Chassis3V2/Include/Chassis.h
create mode 100644 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
create mode 100644 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
diff --git a/Silicon/NXP/Chassis3V2/Chassis3V2.dec b/Silicon/NXP/Chassis3V2/Chassis3V2.dec
new file mode 100644
index 0000000000..106b118188
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Chassis3V2.dec
@@ -0,0 +1,23 @@
+#/** @file
+# NXP Layerscape processor package.
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 1.27
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
+
diff --git a/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc b/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
new file mode 100644
index 0000000000..dabe2ae230
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
@@ -0,0 +1,10 @@
+# @file
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[LibraryClasses.common]
+ ChassisLib|Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
diff --git a/Silicon/NXP/Chassis3V2/Include/Chassis.h b/Silicon/NXP/Chassis3V2/Include/Chassis.h
new file mode 100644
index 0000000000..2771f26fe3
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Include/Chassis.h
@@ -0,0 +1,42 @@
+/** @file
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef __CHASSIS_H__
+#define __CHASSIS_H__
+
+#define NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS 0x1E00000
+
+#define TP_CLUSTER_ITYPE_IDX 0x3f
+#define TP_CLUSTER_EOC BIT31
+#define TP_ITYPE_AVAILABLE BIT0
+#define TP_ITYPE_TYPE(x) (((x) & 0x06) >> 1)
+#define TP_ITYPE_ARM 0x0
+#define TP_ITYPE_VERSION(x) (((x) & 0xe0) >> 5)
+
+#define TP_ITYPE_VERSION_A53 0x2
+#define TP_ITYPE_VERSION_A72 0x4
+
+/**
+ The Device Configuration Unit provides general purpose configuration and status for the
+ device. These registers only support 32-bit accesses.
+**/
+#pragma pack(1)
+typedef struct {
+ UINT8 Reserved0[0x100 - 0x0];
+ UINT32 RcwSr[32]; // Reset Control Word Status Register
+ UINT8 Reserved180[0x200 - 0x180];
+ UINT32 ScratchRw[16]; /// Scratch Read / Write Register
+ UINT8 Reserved240[0x740-0x240];
+ UINT32 TpItyp[65]; /// Topology Initiator Type Register
+ struct {
+ UINT32 Lower;
+ UINT32 Upper;
+ }TpCluster[8];
+} NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG;
+#pragma pack()
+
+#endif
diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
new file mode 100644
index 0000000000..99567bb76f
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
@@ -0,0 +1,186 @@
+/** @file
+ Chassis specific functions common to all SOCs based on a specific Chessis
+
+ Copyright 2020 NXP
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Chassis.h>
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/IoAccessLib.h>
+#include <Library/PcdLib.h>
+#include <Library/SerialPortLib.h>
+#include <Ppi/ArmMpCoreInfo.h>
+
+UINT32
+EFIAPI
+DcfgRead32 (
+ IN UINTN Address
+ )
+{
+ if (FeaturePcdGet (PcdDcfgBigEndian)) {
+ return SwapMmioRead32 (Address);
+ } else {
+ return MmioRead32 (Address);
+ }
+}
+
+UINT32
+EFIAPI
+DcfgWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ )
+{
+ if (FeaturePcdGet (PcdDcfgBigEndian)) {
+ return SwapMmioWrite32 (Address, Value);
+ } else {
+ return MmioWrite32 (Address, Value);
+ }
+}
+
+/**
+ Get the type of core in cluster
+
+ The core can be of type ARM or PowerPC or Hardware Accelerator.
+ If the core is enabled and of type ARM EFI_SUCCESS is returned and a code for type of ARM core is returned
+
+ @param[in] TpItypeIdx Index of Core to be searched in TpItyp in Device Config Registers.
+ @param[out] CoreType If the core is ARM core then the type of core i.e. A53/A72 etc.
+ These cores are identified based on their codes like TP_ITYPE_VERSION_A72
+
+ @return EFI_NOT_FOUND No enabled ARM core found
+ @return EFI_SUCCESS An enabled ARM core found
+**/
+STATIC
+EFI_STATUS
+SocGetCoreType (
+ IN UINT8 TpItypeIdx,
+ OUT UINT8 *CoreType
+ )
+{
+ NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG *Dcfg;
+ UINT32 TpItype;
+
+ Dcfg = (NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG *)NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS;
+ TpItype = MmioRead32 ((UINTN)&Dcfg->TpItyp[TpItypeIdx]);
+ if (TpItype & TP_ITYPE_AVAILABLE) {
+ if (TP_ITYPE_TYPE (TpItype) == TP_ITYPE_ARM) {
+ *CoreType = TP_ITYPE_VERSION (TpItype);
+ } else {
+ return EFI_NOT_FOUND;
+ }
+ } else {
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Return the number of cores present in SOC
+
+ This function returns the number of cores present in SOC.
+ and also their position (cluster number and core number) in the form of ARM_CORE_INFO array
+ and NxpCoreTable array.
+ NxpCoreTable array can be used to find out the type of core. it's values are of type
+ TP_ITYPE_VERSION_*.
+ The number of cores present in SOC can vary depending on which flavour of SOC is being used.
+ This function doesn't allocte any memory and must be provided memory for array of ARM_CORE_INFO
+ and NxpCoreTable for maximum number of cores the SOC can have.
+
+ @param[out] NxpCoreTable array of UINT8 for maximum number of cores the SOC can have.
+ @param[out] ArmCoreTable array of ARM_CORE_INFO for maximum number of cores the SOC can have.
+ @param[in] ArmCoreTableSize Size of ArmCoreTable
+
+ @return Actual number of cores present in SOC. After calling this function only the returned
+ value number of entries in ArmCoreTable are valid entries.
+**/
+UINTN
+__attribute__((weak))
+SocGetMpCoreInfo (
+ OUT UINT8 *NxpCoreTable,
+ OUT ARM_CORE_INFO *ArmCoreTable,
+ IN UINTN CoreTableSize
+ )
+{
+ NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG *Dcfg;
+ UINT32 TpClusterLower;
+ UINT8 TpClusterParser;
+ UINT8 ClusterIndex;
+ UINT8 CoreIndex;
+ UINTN CoreCount;
+ UINT8 CoreType;
+ EFI_STATUS Status;
+
+ Dcfg = (NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG *)NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS;
+ ClusterIndex = 0;
+ CoreCount = 0;
+ while (TRUE) {
+ TpClusterLower = MmioRead32 ((UINTN)&Dcfg->TpCluster[ClusterIndex].Lower);
+ for (CoreIndex = 0; CoreIndex < (sizeof (TpClusterLower) / sizeof (TpClusterParser)); CoreIndex++) {
+ TpClusterParser = (TpClusterLower >> (8 * CoreIndex));
+ Status = SocGetCoreType (TpClusterParser & TP_CLUSTER_ITYPE_IDX, &CoreType);
+ if (Status != EFI_NOT_FOUND) {
+ ArmCoreTable[CoreCount].ClusterId = ClusterIndex;
+ ArmCoreTable[CoreCount].CoreId = CoreIndex;
+ ArmCoreTable[CoreCount].MailboxSetAddress = 0;
+ ArmCoreTable[CoreCount].MailboxGetAddress = 0;
+ ArmCoreTable[CoreCount].MailboxClearAddress = 0;
+ ArmCoreTable[CoreCount].MailboxClearValue = ~0;
+
+ NxpCoreTable[CoreCount] = CoreType;
+ CoreCount++;
+ if (CoreCount == CoreTableSize) {
+ break;
+ }
+ }
+ }
+ if (TpClusterLower & TP_CLUSTER_EOC) {
+ break;
+ }
+ if (CoreCount == CoreTableSize) {
+ break;
+ }
+ ClusterIndex++;
+ }
+
+ return CoreCount;
+}
+
+/**
+ Function to initialize Chassis Specific functions
+ **/
+VOID
+ChassisInit (
+ VOID
+ )
+{
+ UINT64 BaudRate;
+ UINT32 ReceiveFifoDepth;
+ EFI_PARITY_TYPE Parity;
+ UINT8 DataBits;
+ EFI_STOP_BITS_TYPE StopBits;
+ UINT32 Timeout;
+
+ BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
+ ReceiveFifoDepth = FixedPcdGet16 (PcdUartDefaultReceiveFifoDepth);
+ Timeout = 0;
+ Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
+ DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
+ StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);
+
+ //
+ // Early init serial Port to get board information.
+ //
+ SerialPortSetAttributes (
+ &BaudRate,
+ &ReceiveFifoDepth,
+ &Timeout,
+ &Parity,
+ &DataBits,
+ &StopBits
+ );
+}
diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
new file mode 100644
index 0000000000..302296bf65
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
@@ -0,0 +1,41 @@
+#/** @file
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = Chassis3V2Lib
+ FILE_GUID = fae0d077-5fc2-494f-b8e1-c51a3023ee3e
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ChassisLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+ Silicon/NXP/Chassis3V2/Chassis3V2.dec
+
+[LibraryClasses]
+ IoLib
+ IoAccessLib
+ PcdLib
+ SerialPortLib
+
+[Sources.common]
+ ChassisLib.c
+
+[FeaturePcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian
+
+[FixedPcd]
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth
+
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 18/19] Silicon/NXP: Add LX2160A SocLib
2020-02-07 12:43 [PATCH 00/19] ADD LX2160ARDB Platform Support Pankaj Bansal
` (16 preceding siblings ...)
2020-02-07 12:43 ` [PATCH 17/19] Silicon/NXP: Add Chassis3V2 Pankaj Bansal
@ 2020-02-07 12:43 ` Pankaj Bansal
2020-02-12 21:39 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 19/19] Platform/NXP: Add LX2160ARDBPKG Pankaj Bansal
18 siblings, 1 reply; 49+ messages in thread
From: Pankaj Bansal @ 2020-02-07 12:43 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, Varun Sethi
Cc: devel, Pankaj Bansal
Add LX2160A SocLib
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Silicon/NXP/Chassis3V2/LX2160A/Include/Soc.h | 39 +++++++++
Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec | 23 ++++++
.../NXP/Chassis3V2/LX2160A/LX2160A.dsc.inc | 34 ++++++++
.../LX2160A/Library/SocLib/SocLib.c | 79 +++++++++++++++++++
.../LX2160A/Library/SocLib/SocLib.inf | 31 ++++++++
5 files changed, 206 insertions(+)
create mode 100644 Silicon/NXP/Chassis3V2/LX2160A/Include/Soc.h
create mode 100644 Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec
create mode 100644 Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dsc.inc
create mode 100644 Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.c
create mode 100644 Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.inf
diff --git a/Silicon/NXP/Chassis3V2/LX2160A/Include/Soc.h b/Silicon/NXP/Chassis3V2/LX2160A/Include/Soc.h
new file mode 100644
index 0000000000..cc1f91272d
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/LX2160A/Include/Soc.h
@@ -0,0 +1,39 @@
+/** @file
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef __SOC_H__
+#define __SOC_H__
+
+#include <Chassis.h>
+
+/**
+ Soc Memory Map
+**/
+#define LX2160A_CCSR_PHYS_ADDRESS 0x1000000
+#define LX2160A_CCSR_SIZE 0xF000000
+
+#define LX2160A_FLEXSPI_PHYS_ADDRESS 0x20000000
+#define LX2160A_FLEXSPI_SIZE SIZE_256MB
+
+#define LX2160A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS
+
+#define LX2160A_DRAM0_PHYS_ADDRESS 0x80000000
+#define LX2160A_DRAM0_SIZE SIZE_2GB
+#define LX2160A_DRAM1_PHYS_ADDRESS 0x2080000000
+#define LX2160A_DRAM1_SIZE 0x1F80000000 // 128 GB
+
+#define LX2160A_I2C0_PHYS_ADDRESS 0x2000000
+
+/**
+ Reset Control Word (RCW) Bits
+**/
+#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6
+
+typedef NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG LX2160A_DEVICE_CONFIG;
+
+#endif
+
diff --git a/Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec b/Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec
new file mode 100644
index 0000000000..106b118188
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec
@@ -0,0 +1,23 @@
+#/** @file
+# NXP Layerscape processor package.
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 1.27
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
+
diff --git a/Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dsc.inc b/Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dsc.inc
new file mode 100644
index 0000000000..f786a57ebc
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dsc.inc
@@ -0,0 +1,34 @@
+# @file
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[LibraryClasses.common]
+ SocLib|Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.inf
+ SerialPortLib|Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFeatureFlag.common]
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|TRUE
+
+[PcdsFixedAtBuild.common]
+## PL011 Serial Terminal
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x21c0000
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|16
+
+[PcdsDynamicDefault.common]
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize|0x20000000
+ gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment|0x20000000
+ #
+ # ARM General Interrupt Controller
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x6000000
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x6200000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x0c0c0000
diff --git a/Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.c b/Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.c
new file mode 100644
index 0000000000..2c19c72b5f
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.c
@@ -0,0 +1,79 @@
+/** @file
+
+ Copyright 2017-2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+ **/
+#include <Soc.h>
+#include <Library/ChassisLib.h>
+#include <Library/SocLib.h>
+
+/**
+ Return the input clock frequency to an IP Module.
+ This function reads the RCW bits and calculates the PLL multipler/divider values to be applied
+ to various IP modules.
+ If a module is disabled or doesn't exist on platform, then return zero.
+
+ @param[in] BaseClock Base clock to which PLL multipler/divider values is to be applied.
+ @param[in] ClockType IP modules whose clock value is to be retrieved
+ @param[in] Args Variable Args lists that is parsed based on the ClockType
+ e.g. if there are multiple modules of same type then this value tells the
+ instance of module for which clock is to be retrieved.
+ (e.g. if there are four i2c controllers in SOC, then this value can be 1, 2, 3, 4)
+ for IP modules which have only single instance in SOC (e.g. one QSPI controller)
+ this value can be null (i.e. no arg)
+
+ @return > 0 Return the input clock frequency to an IP Module
+ 0 either IP module doesn't exist in SOC
+ or IP module instance doesn't exist in SOC
+ or IP module instance is disabled. i.e. no input clock is provided to IP module instance.
+**/
+UINT64
+SocGetClock (
+ IN UINT64 BaseClock,
+ IN UINT32 ClockType,
+ IN VA_LIST Args
+ )
+{
+ LX2160A_DEVICE_CONFIG *Dcfg;
+ UINT32 RcwSr;
+ UINT64 ReturnValue;
+
+ ReturnValue = 0;
+ Dcfg = (LX2160A_DEVICE_CONFIG *)LX2160A_DCFG_ADDRESS;
+
+ switch (ClockType) {
+ case NXP_UART_CLOCK:
+ RcwSr = DcfgRead32 ((UINTN)&Dcfg->RcwSr[0]);
+ ReturnValue = BaseClock * SYS_PLL_RAT (RcwSr);
+ ReturnValue >>= 3; // platform pll / 8
+ break;
+ case NXP_I2C_CLOCK:
+ RcwSr = DcfgRead32 ((UINTN)&Dcfg->RcwSr[0]);
+ ReturnValue = BaseClock * SYS_PLL_RAT (RcwSr);
+ ReturnValue >>= 4; // platform pll / 16
+ break;
+ default:
+ break;
+ }
+
+ return ReturnValue;
+}
+
+/**
+ Function to initialize SoC specific constructs
+ CPU Info
+ SoC Personality
+ Board Personality
+ RCW prints
+ **/
+VOID
+SocInit (
+ VOID
+ )
+{
+ ChassisInit ();
+
+ return;
+}
+
diff --git a/Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.inf b/Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.inf
new file mode 100644
index 0000000000..ea9d45a021
--- /dev/null
+++ b/Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.inf
@@ -0,0 +1,31 @@
+#@file
+#
+# Component description file for SocLib module
+#
+# Copyright 2017-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+[Defines]
+ INF_VERSION = 0x0001000A
+ BASE_NAME = SocLib
+ FILE_GUID = 9b046753-2b4f-42d8-bfb3-468892fe17d4
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SocLib
+
+[Sources.common]
+ SocLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+ Silicon/NXP/Chassis3V2/Chassis3V2.dec
+ Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec
+
+[LibraryClasses]
+ ChassisLib
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 19/19] Platform/NXP: Add LX2160ARDBPKG
2020-02-07 12:43 [PATCH 00/19] ADD LX2160ARDB Platform Support Pankaj Bansal
` (17 preceding siblings ...)
2020-02-07 12:43 ` [PATCH 18/19] Silicon/NXP: Add LX2160A SocLib Pankaj Bansal
@ 2020-02-07 12:43 ` Pankaj Bansal
2020-02-12 21:36 ` Leif Lindholm
18 siblings, 1 reply; 49+ messages in thread
From: Pankaj Bansal @ 2020-02-07 12:43 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal, Michael D Kinney, Varun Sethi
Cc: devel, Pankaj Bansal
Add LX2160ARDBPKG
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---
Platform/NXP/Include/Qixis.h | 40 ++++
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec | 23 +++
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc | 54 ++++++
Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf | 172 ++++++++++++++++++
.../AArch64/ArmPlatformHelper.S | 46 +++++
.../Library/ArmPlatformLib/ArmPlatformLib.c | 168 +++++++++++++++++
.../Library/ArmPlatformLib/ArmPlatformLib.inf | 45 +++++
.../ArmPlatformLib/ArmPlatformLibInternal.h | 26 +++
.../ArmPlatformLib/ArmPlatformLibMem.c | 80 ++++++++
Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc | 90 +++++++++
Platform/NXP/NxpQoriqLsPlatform.dec | 23 +++
11 files changed, 767 insertions(+)
create mode 100644 Platform/NXP/Include/Qixis.h
create mode 100644 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec
create mode 100644 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc
create mode 100644 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
create mode 100644 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
create mode 100644 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
create mode 100644 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
create mode 100644 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibInternal.h
create mode 100644 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
create mode 100644 Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc
create mode 100644 Platform/NXP/NxpQoriqLsPlatform.dec
diff --git a/Platform/NXP/Include/Qixis.h b/Platform/NXP/Include/Qixis.h
new file mode 100644
index 0000000000..116e4c1b30
--- /dev/null
+++ b/Platform/NXP/Include/Qixis.h
@@ -0,0 +1,40 @@
+/** @file
+ Qixis Layout.
+
+ Copyright 2020 NXP
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __QIXIS_H__
+#define __QIXIS_H__
+
+#include <Uefi.h>
+
+typedef struct _QIXIS_MIN_LAYOUT {
+ UINT8 Id;
+ UINT8 Ver;
+ UINT8 Qver;
+ UINT8 Model;
+ UINT8 Minor;
+ UINT8 Ctl;
+ UINT8 Aux;
+ UINT8 Reserved007[0x040 - 0x007];
+ UINT8 ResetCtl;
+ UINT8 ResetStat;
+ UINT8 ResetReason;
+ UINT8 ResetForce[3];
+ UINT8 Reserved046[0x04B - 0x046];
+ UINT8 ResetMask[3];
+ UINT8 Reserved04E[0x050 - 0x04E];
+ UINT8 BoardConfig[16];
+ UINT8 DutConfig[16];
+ UINT8 Reserved070[0x090 - 0x070];
+ UINT8 IrqStat[4];
+ UINT8 IrqCtl[4];
+ UINT8 IrqDrv[8];
+ UINT8 Reserved0A0[0x0D8 - 0x0A0];
+} QIXIS_MIN_LAYOUT;
+
+#endif
+
diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec
new file mode 100644
index 0000000000..192eabc5b3
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec
@@ -0,0 +1,23 @@
+# LX2160aRdbPkg.dec
+# LX2160a board package.
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+ PACKAGE_NAME = LX2160aRdbPkg
+ PACKAGE_GUID = 6eba6648-d853-4eb3-9761-528b82d5ab04
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc
new file mode 100644
index 0000000000..773b211b7d
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc
@@ -0,0 +1,54 @@
+# LX2160aRdbPkg.dsc
+#
+# LX2160ARDB Board package.
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ #
+ # Defines for default states. These can be changed on the command line.
+ # -D FLAG=VALUE
+ #
+ PLATFORM_NAME = LX2160aRdbPkg
+ PLATFORM_GUID = 60169ec4-d2b4-44f8-825e-f8684fd42e4f
+ OUTPUT_DIRECTORY = Build/LX2160aRdbPkg
+ FLASH_DEFINITION = Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
+
+!include Silicon/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
+!include Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dsc.inc
+
+[LibraryClasses.common]
+ ArmPlatformLib|Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
+ RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
+
+[PcdsFixedAtBuild.common]
+ #
+ # RTC Pcds
+ #
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+ #
+ # Architectural Protocols
+ #
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+ <PcdsFixedAtBuild>
+ gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
+ }
+
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+
+ ##
diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
new file mode 100644
index 0000000000..ed7c39365c
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
@@ -0,0 +1,172 @@
+# LX2160aRdbPkg.fdf
+#
+# FLASH layout file for LX2160aRdb board.
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.LX2160ARDB_EFI]
+BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
+Size = 0x00100000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
+ErasePolarity = 1
+BlockSize = 0x1
+NumBlocks = 0x100000
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+0x00000000|0x00100000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+!include VarStore.fdf.inc
+!include Platform/NXP/FVRules.fdf.inc
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+FvNameGuid = 1037c42b-8452-4c41-aac7-41e6c31468da
+BlockSize = 0x1
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 8 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+
+ #
+ # Multiple Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+ INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatPkg/FatPei/FatPei.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+ INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
new file mode 100644
index 0000000000..d1b9f1debb
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
@@ -0,0 +1,46 @@
+//
+// Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//
+
+#include <AsmMacroIoLibV8.h>
+#include <Library/ArmLib.h>
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+ ret
+
+//UINTN
+//ArmPlatformGetCorePosition (
+// IN UINTN MpId
+// );
+// With this function: CorePos = (ClusterId * 4) + CoreId
+ASM_FUNC(ArmPlatformGetCorePosition)
+ and x1, x0, #ARM_CORE_MASK
+ and x0, x0, #ARM_CLUSTER_MASK
+ add x0, x1, x0, LSR #6
+ ret
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+// VOID
+// );
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+ MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore))
+ ret
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+// IN UINTN MpId
+// );
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+ MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
+ and x0, x0, x1
+ MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore))
+ cmp w0, w1
+ mov x0, #1
+ mov x1, #0
+ csel x0, x0, x1, eq
+ ret
+
diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
new file mode 100644
index 0000000000..adcc3315dd
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
@@ -0,0 +1,168 @@
+/** @file
+*
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+* Copyright 2020 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include <Soc.h>
+#include <Library/ArmPlatformLib.h>
+#include <Ppi/ArmMpCoreInfo.h>
+
+#include <Library/DebugLib.h>
+#include <Library/I2cLib.h>
+#include <Library/SocLib.h>
+#include <Ppi/NxpPlatformGetClock.h>
+
+#include "ArmPlatformLibInternal.h"
+
+ARM_CORE_INFO mArmPlatformMpCoreInfoTable[] = {
+ {
+ // Cluster 0, Core 0
+ 0, 0,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (UINT64)0xFFFFFFFF
+ },
+};
+
+/**
+ Get the clocks supplied by Platform(Board) to NXP Layerscape SOC
+
+ The core can be of type ARM or PowerPC or Hardware Accelerator.
+ If the core is enabled and of type ARM EFI_SUCCESS is returned and a code for type of ARM core is returned
+
+ @param[in] ClockType Type of clock
+ @param[in] ... Variable argument list which is parsed based on ClockType
+
+ @return Actual Clock Frequency. return value 0 should be interpreted as clock not provided by Board.
+**/
+UINT64
+EFIAPI
+NxpPlatformGetClock(
+ IN UINT32 ClockType,
+ ...
+ )
+{
+ UINT64 Clock;
+ EFI_STATUS Status;
+ VA_LIST Args;
+ UINT8 Reg;
+
+ Clock = 0;
+
+ VA_START (Args, ClockType);
+
+ switch (ClockType) {
+ case NXP_SYSTEM_CLOCK:
+ Status = I2cBusReadReg (
+ LX2160A_I2C0_PHYS_ADDRESS, QIXIS_I2C_ADDRESS,
+ OFFSET_OF (QIXIS_LAYOUT, BoardConfig[1]),
+ 1, &Reg, sizeof (Reg)
+ );
+ ASSERT_EFI_ERROR (Status);
+ switch (Reg & 0x03) {
+ case 0x00:
+ Clock = 100 * 1000 * 1000; // 100 MHz
+ break;
+ default:
+ ASSERT(0); // All other values are reserved
+ break;
+ }
+ break;
+ case NXP_I2C_CLOCK:
+ case NXP_UART_CLOCK:
+ Clock = NxpPlatformGetClock (NXP_SYSTEM_CLOCK);
+ Clock = SocGetClock (Clock, ClockType, Args);
+ break;
+ default:
+ break;
+ }
+
+ VA_END (Args);
+
+ return Clock;
+}
+
+/**
+ Return the current Boot Mode
+
+ This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Initialize controllers that must setup in the normal world
+
+ This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
+ in the PEI phase.
+
+**/
+RETURN_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ UINT64 Clock;
+
+ TimerConstructor ();
+
+ I2cEarlyInitialize (LX2160A_I2C0_PHYS_ADDRESS);
+
+ Clock = NxpPlatformGetClock (NXP_I2C_CLOCK, 0);
+
+ // Set I2c Clock 100 KHz
+ I2cInitialize (LX2160A_I2C0_PHYS_ADDRESS, Clock, 100 * 1000);
+
+ SocInit ();
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+ )
+{
+ if (ArmIsMpCore()) {
+ *CoreCount = sizeof (mArmPlatformMpCoreInfoTable) / sizeof (ARM_CORE_INFO);
+ *ArmCoreTable = mArmPlatformMpCoreInfoTable;
+ return EFI_SUCCESS;
+ } else {
+ return EFI_UNSUPPORTED;
+ }
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi = { NxpPlatformGetClock };
+
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ *PpiListSize = sizeof (gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
+}
+
diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
new file mode 100644
index 0000000000..24258e1502
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
@@ -0,0 +1,45 @@
+#/* @file
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#*/
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = ArmPlatformLib
+ FILE_GUID = 736343a0-1d96-11e0-aaaa-0002a5d5c51b
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+ Silicon/NXP/Chassis3V2/Chassis3V2.dec
+ Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec
+ Platform/NXP/NxpQoriqLsPlatform.dec
+
+[LibraryClasses]
+ ArmLib
+ SocLib
+ I2cLib
+ DebugLib
+
+[Sources.common]
+ ArmPlatformLib.c
+ ArmPlatformLibMem.c
+
+[Sources.AArch64]
+ AArch64/ArmPlatformHelper.S
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+
+[Ppis]
+ gArmMpCoreInfoPpiGuid
diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibInternal.h b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibInternal.h
new file mode 100644
index 0000000000..fefbd273c8
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibInternal.h
@@ -0,0 +1,26 @@
+/** @file
+ Platform Specific data.
+
+ Copyright 2020 NXP
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __ARM_PLATFORM_LIB_INTERNAL_H__
+#define __ARM_PLATFORM_LIB_INTERNAL_H__
+
+#include <Qixis.h>
+
+// This function should be better located into TimerLib implementation
+RETURN_STATUS
+EFIAPI
+TimerConstructor (
+ VOID
+ );
+
+#define QIXIS_I2C_ADDRESS 0x66
+
+typedef QIXIS_MIN_LAYOUT QIXIS_LAYOUT;
+
+#endif
+
diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
new file mode 100644
index 0000000000..85bd7e6307
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
@@ -0,0 +1,80 @@
+/** @file
+*
+* Copyright 2020 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Soc.h>
+
+// Number of Virtual Memory Map Descriptors
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 10
+
+/**
+ Return the Virtual Memory Map of your platform
+
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+ @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+ Virtual Memory mapping. This array must be ended by a zero-filled
+ entry
+
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+ IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+ )
+{
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+ UINT32 Index;
+
+ ASSERT (VirtualMemoryMap != NULL);
+
+ VirtualMemoryTable = AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) *
+ MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+ if (VirtualMemoryTable == NULL) {
+ DEBUG ((DEBUG_ERROR, "%a: Error: Failed AllocatePool()\n", __FUNCTION__));
+ return;
+ }
+
+ Index = 0;
+ // DRAM
+ VirtualMemoryTable[Index].PhysicalBase = LX2160A_DRAM0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LX2160A_DRAM0_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LX2160A_DRAM0_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ VirtualMemoryTable[Index].PhysicalBase = LX2160A_DRAM1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LX2160A_DRAM1_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LX2160A_DRAM1_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ // CCSR Space
+ VirtualMemoryTable[Index].PhysicalBase = LX2160A_CCSR_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LX2160A_CCSR_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LX2160A_CCSR_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // FlexSPI region
+ // TODO: check if we can change attributes for better performance
+ VirtualMemoryTable[Index].PhysicalBase = LX2160A_FLEXSPI_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].VirtualBase = LX2160A_FLEXSPI_PHYS_ADDRESS;
+ VirtualMemoryTable[Index].Length = LX2160A_FLEXSPI_SIZE;
+ VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // End of Table
+ VirtualMemoryTable[Index].PhysicalBase = 0;
+ VirtualMemoryTable[Index].VirtualBase = 0;
+ VirtualMemoryTable[Index].Length = 0;
+ VirtualMemoryTable[Index++].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+ ASSERT (Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+ *VirtualMemoryMap = VirtualMemoryTable;
+}
diff --git a/Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc b/Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc
new file mode 100644
index 0000000000..215d73dd8f
--- /dev/null
+++ b/Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc
@@ -0,0 +1,90 @@
+## @file
+# FDF include file with FD definition that defines an empty variable store.
+#
+# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+# Copyright (C) 2014, Red Hat, Inc.
+# Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+# Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+# Copyright 2017-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[FD.LX2160ARDBNV_EFI]
+
+BaseAddress = 0x20500000
+Size = 0x000C0000
+ErasePolarity = 1
+BlockSize = 0x1
+NumBlocks = 0xC0000
+
+#
+# Place NV Storage just above Platform Data Base
+#
+DEFINE NVRAM_AREA_VARIABLE_BASE = 0x00000000
+DEFINE NVRAM_AREA_VARIABLE_SIZE = 0x00040000
+DEFINE FTW_WORKING_BASE = $(NVRAM_AREA_VARIABLE_BASE) + $(NVRAM_AREA_VARIABLE_SIZE)
+DEFINE FTW_WORKING_SIZE = 0x00040000
+DEFINE FTW_SPARE_BASE = $(FTW_WORKING_BASE) + $(FTW_WORKING_SIZE)
+DEFINE FTW_SPARE_SIZE = 0x00040000
+
+#############################################################################
+# LX2160ARDB NVRAM Area
+# LX2160ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare
+#############################################################################
+
+$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER
+ # ZeroVector []
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # FileSystemGuid: gEfiSystemNvDataFvGuid =
+ # { 0xFFF12B8D, 0x7696, 0x4C8B,
+ # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+ # FvLength: Flash Size : 0x4000000
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
+ # Signature "_FVH" # Attributes
+ 0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
+ # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+ 0x48, 0x00, 0x08, 0xA6, 0x00, 0x00, 0x00, 0x02,
+ # Blockmap[0]: 0x4000 Blocks * 0x1000 Bytes / Block = SIZE_64MB
+ 0x00, 0x40, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
+ # Blockmap[1]: End
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ ## This is the VARIABLE_STORE_HEADER
+ # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
+ # Signature: gEfiVariableGuid =
+ # { 0xddcf3616, 0x3275, 0x4164,
+ # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+ 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+ 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+ # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+ # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
+ # This can speed up the Variable Dispatch a bit.
+ 0xB8, 0xFF, 0x03, 0x00,
+ # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+ # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
+ # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
+ 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+ 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
+ # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+ 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
+ # WriteQueueSize: UINT64
+ 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+#NV_FTW_SPARE
diff --git a/Platform/NXP/NxpQoriqLsPlatform.dec b/Platform/NXP/NxpQoriqLsPlatform.dec
new file mode 100644
index 0000000000..106b118188
--- /dev/null
+++ b/Platform/NXP/NxpQoriqLsPlatform.dec
@@ -0,0 +1,23 @@
+#/** @file
+# NXP Layerscape processor package.
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 1.27
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
+
--
2.17.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* Re: [PATCH 01/19] Silicon/NXP: Add I2c lib
2020-02-07 12:43 ` [PATCH 01/19] Silicon/NXP: Add I2c lib Pankaj Bansal
@ 2020-02-08 17:13 ` Leif Lindholm
2020-02-09 11:49 ` [edk2-devel] " Ard Biesheuvel
0 siblings, 1 reply; 49+ messages in thread
From: Leif Lindholm @ 2020-02-08 17:13 UTC (permalink / raw)
To: Pankaj Bansal; +Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi, devel
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=utf-8, Size: 32819 bytes --]
On Fri, Feb 07, 2020 at 18:13:10 +0530, Pankaj Bansal wrote:
> I2c lib is going to be used in PrePeiCore sec module to get the
> System clock information from devices connected to i2c (like fpga
> or clcok generator)
>
> since we don't have support of DXE modules this early in boot stage,
> move the i2c controller functionality in library.
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> Platform/NXP/NxpQoriqLs.dsc.inc | 4 +-
> Silicon/NXP/Include/Library/I2cLib.h | 99 ++++
> Silicon/NXP/Library/I2cLib/I2cLib.c | 532 ++++++++++++++++++++
> Silicon/NXP/Library/I2cLib/I2cLib.inf | 30 ++
> Silicon/NXP/Library/I2cLib/I2cLibInternal.h | 95 ++++
> Silicon/NXP/NxpQoriqLs.dec | 10 +-
> 6 files changed, 768 insertions(+), 2 deletions(-)
> create mode 100644 Silicon/NXP/Include/Library/I2cLib.h
> create mode 100644 Silicon/NXP/Library/I2cLib/I2cLib.c
> create mode 100644 Silicon/NXP/Library/I2cLib/I2cLib.inf
> create mode 100644 Silicon/NXP/Library/I2cLib/I2cLibInternal.h
>
> diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc
> index fa5f30dd39..b28e0615f7 100644
> --- a/Platform/NXP/NxpQoriqLs.dsc.inc
> +++ b/Platform/NXP/NxpQoriqLs.dsc.inc
> @@ -1,6 +1,6 @@
> # @file
> #
> -# Copyright 2017-2019 NXP.
> +# Copyright 2017-2020 NXP.
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -94,6 +94,8 @@
Can you ensure to either follow the manual git setup steps from
https://github.com/tianocore/tianocore.github.io/wiki/Laszlo%27s-unkempt-git-guide-for-edk2-contributors-and-maintainers
or execute edk2/BaseTools/Scripts/SetupGit.py in each of the tianocore
repositories?
That makes the diff show which section in this file is being modified,
and it also orders the files in decreasing order of abstraction.
> NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
> ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
>
> + I2cLib|Silicon/NXP/Library/I2cLib/I2cLib.inf
> +
> [LibraryClasses.common.SEC]
> PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
> diff --git a/Silicon/NXP/Include/Library/I2cLib.h b/Silicon/NXP/Include/Library/I2cLib.h
> new file mode 100644
> index 0000000000..3594e3fc2f
> --- /dev/null
> +++ b/Silicon/NXP/Include/Library/I2cLib.h
> @@ -0,0 +1,99 @@
> +/** @file
> + I2c Lib to control I2c controller.
> +
> + Copyright 2020 NXP
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef __I2C_LIB_H__
> +#define __I2C_LIB_H__
Please drop leading __ from include header guards.
> +
> +#include <Pi/PiI2c.h>
> +
> +/**
> + Early init I2C for reading the sysclk from I2c slave device.
> + I2c bus clock is determined from the clock input to I2c controller.
> + The clock input to I2c controller is derived from the sysclk.
> + sysclk is determined by clock generator, which is controller by i2c.
> +
> + So, it's a chicken-egg problem to read the sysclk from clock generator.
> + To break this cycle (i.e. to read the sysclk), we setup the i2c bus clock to
> + lowest value, in the hope that it won't be out of clock generator's supported
> + i2c clock frequency. Once we have the correct sysclk, we can setup the correct
> + i2c bus clock.
> +
> + @param[in] Base Base Address of I2c controller's registers
> +
> + @return EFI_SUCCESS successfuly setup the i2c bus for reading sysclk
> + @return DEVICE_ERROR There was an error setting up the I2c bus
> +**/
> +EFI_STATUS
> +I2cEarlyInitialize (
> + IN UINTN Base
> + );
> +
> +/**
> + Configure I2c bus to opearte at a given speed
> +
> + @param[in] Base Base Address of I2c controller's registers
> + @param[in] I2cBusClock Input clock to I2c controller
> + @param[in] Speed speed to be configured for I2c bus
> +**/
> +EFI_STATUS
> +I2cInitialize (
> + IN UINTN Base,
> + IN UINT64 I2cBusClock,
> + IN UINT64 Speed
> + );
> +
> +/**
> + Transfer data to/from I2c slave device
> +
> + @param[in] Base Base Address of I2c controller's registers
> + @param[in] SlaveAddress Slave Address from which data is to be read
> + @param[in] RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET structure
> + describing the I2C transaction
> +
> + @return EFI_SUCCESS successfuly setup the i2c bus for reading sysclk
> + @return EFI_DEVICE_ERROR There was an error while transferring data through I2c bus
> + @return EFI_NO_RESPONSE There was no Ack from i2c device
> + @return EFI_TIMEOUT I2c Bus is busy
> + @return EFI_NOT_READY I2c Bus Arbitration lost
> +**/
> +EFI_STATUS
> +I2cBusXfer (
> + IN UINTN Base,
> + IN UINT32 SlaveAddress,
> + IN EFI_I2C_REQUEST_PACKET *RequestPacket
> + );
> +
> +/**
> + Read a register from I2c slave device. This API is wrapper around I2cBusXfer
> +
> + @param[in] Base Base Address of I2c controller's registers
> + @param[in] SlaveAddress Slave Address from which register value is to be read
> + @param[in] RegAddress Register Address in Slave's memory map
> + @param[in] RegAddressWidthInBytes Number of bytes in RegAddress to send to I2c Slave
> + for simple reads without any register, make this value = 0
> + (RegAddress is don't care in that case)
> + @param[out] RegValue Value to be read from I2c slave's regiser
> + @param[in] RegValueNumBytes Number of bytes to read from I2c slave register
> +
> + @return EFI_SUCCESS successfuly setup the i2c bus for reading sysclk
> + @return EFI_DEVICE_ERROR There was an error while transferring data through I2c bus
> + @return EFI_NO_RESPONSE There was no Ack from i2c device
> + @return EFI_TIMEOUT I2c Bus is busy
> + @return EFI_NOT_READY I2c Bus Arbitration lost
> +**/
> +EFI_STATUS
> +I2cBusReadReg (
> + IN UINTN Base,
> + IN UINT32 SlaveAddress,
> + IN UINT64 RegAddress,
> + IN UINT8 RegAddressWidthInBytes,
> + OUT UINT8 *RegValue,
> + IN UINT8 RegValueNumBytes
> + );
> +
> +#endif // __I2C_LIB_H__
> diff --git a/Silicon/NXP/Library/I2cLib/I2cLib.c b/Silicon/NXP/Library/I2cLib/I2cLib.c
> new file mode 100644
> index 0000000000..f33c09d6d1
> --- /dev/null
> +++ b/Silicon/NXP/Library/I2cLib/I2cLib.c
> @@ -0,0 +1,532 @@
> +/** @file
> + I2c Lib to control I2c controller.
> +
> + Copyright 2020 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +#include <Uefi.h>
> +#include <Library/I2cLib.h>
> +#include <Library/TimerLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/BaseMemoryLib.h>
Please sort includes alphabetically (at least within each
subdirectory).
> +
> +#include "I2cLibInternal.h"
> +
> +/*
> + * I2C divider and hold values when glitch filter is enabled
> + * taken from table 21-14, LX2160ARM_RevE 01/2020
OK, so it looks to me like this adds a layer of abstraction compared
to what already exists in Silicon/NXP/Drivers/I2cDxe/. Which is fine.
However, that driver was added for LS1043A, which will also become a
consumer of this code once the subsequent patch gets merged.
Which is probably fine - but this comment (and the next one) would
ideally identify the SoCs supported; or if there is some common name
for the i2c controller used in all supported SoCs, that would be
ideal.
> + *
> + * In case of duplicate SCL Divider value, the IBC value
> + * with high MUL value has been selected.
> + * A higher MUL value results in a lower sampling rate of the I2C signals.
> + * This gives the I2C module greater immunity against glitches in the I2C signals.
> + */
> +STATIC I2C_CLOCK_DIVIDER_PAIR I2cClockDividerGlitchEnabled[] = {
Module-scope global variables should have 'm' prefix.
> + { 34, 0x0 }, { 36, 0x1 }, { 38, 0x2 }, { 40, 0x3 },
> + { 42, 0x4 }, { 44, 0x8 }, { 48, 0x9 }, { 52, 0xA },
> + { 54, 0x7 }, { 56, 0xB }, { 60, 0xC }, { 64, 0x10 },
> + { 68, 0x40 }, { 72, 0x41 }, { 76, 0x42 }, { 80, 0x43 },
> + { 84, 0x44 }, { 88, 0x48 }, { 96, 0x49 }, { 104, 0x4A },
> + { 108, 0x47 }, { 112, 0x4B }, { 120, 0x4C }, { 128, 0x50 },
> + { 136, 0x80 }, { 144, 0x81 }, { 152, 0x82 }, { 160, 0x83 },
> + { 168, 0x84 }, { 176, 0x88 }, { 192, 0x89 }, { 208, 0x8A },
> + { 216, 0x87 }, { 224, 0x8B }, { 240, 0x8C }, { 256, 0x90 },
> + { 288, 0x91 }, { 320, 0x92 }, { 336, 0x8F }, { 352, 0x93 },
> + { 384, 0x98 }, { 416, 0x95 }, { 448, 0x99 }, { 480, 0x96 },
> + { 512, 0x9A }, { 576, 0x9B }, { 640, 0xA0 }, { 704, 0x9D },
> + { 768, 0xA1 }, { 832, 0x9E }, { 896, 0xA2 }, { 960, 0x67 },
> + { 1024, 0xA3 }, { 1152, 0xA4 }, { 1280, 0xA8 }, { 1536, 0xA9 },
> + { 1792, 0xAA }, { 1920, 0xA7 }, { 2048, 0xAB }, { 2304, 0xAC },
> + { 2560, 0xB0 }, { 3072, 0xB1 }, { 3584, 0xB2 }, { 3840, 0xAF },
> + { 4096, 0xB3 }, { 4608, 0xB4 }, { 5120, 0xB8 }, { 6144, 0xB9 },
> + { 7168, 0xBA }, { 7680, 0xB7 }, { 8192, 0xBB }, { 9216, 0xBC },
> + { 10240, 0xBD }, { 12288, 0xBE }, { 15360, 0xBF }
> +};
> +
> +/*
> + * I2C divider and hold values when glitch filter is disabled
> + * taken from table 21-13, LX2160ARM_RevE 01/2020
> + *
> + * In case of duplicate SCL Divider value, the IBC value
> + * with high MUL value has been selected.
> + * A higher MUL value results in a lower sampling rate of the I2C signals.
> + * This gives the I2C module greater immunity against glitches in the I2C signals.
> + */
> +STATIC I2C_CLOCK_DIVIDER_PAIR I2cClockDividerGlitchDisabled[] = {
Module-scope global variables should have 'm' prefix.
> + { 20, 0x0 },{ 22, 0x1 },{ 24, 0x2 },{ 26, 0x3 },
> + { 28, 0x8 },{ 30, 0x5 },{ 32, 0x9 },{ 34, 0x6 },
> + { 36, 0x0A },{ 40, 0x40 },{ 44, 0x41 },{ 48, 0x42 },
> + { 52, 0x43 },{ 56, 0x48 },{ 60, 0x45 },{ 64, 0x49 },
> + { 68, 0x46 },{ 72, 0x4A },{ 80, 0x80 },{ 88, 0x81 },
> + { 96, 0x82 },{ 104, 0x83 },{ 112, 0x88 },{ 120, 0x85 },
> + { 128, 0x89 },{ 136, 0x86 },{ 144, 0x8A },{ 160, 0x8B },
> + { 176, 0x8C },{ 192, 0x90 },{ 208, 0x56 },{ 224, 0x91 },
> + { 240, 0x1F },{ 256, 0x92 },{ 272, 0x8F },{ 288, 0x93 },
> + { 320, 0x98 },{ 352, 0x95 },{ 384, 0x99 },{ 416, 0x96 },
> + { 448, 0x9A },{ 480, 0x5F },{ 512, 0x9B },{ 576, 0x9C },
> + { 640, 0xA0 },{ 768, 0xA1 },{ 896, 0xA2 },{ 960, 0x9F },
> + { 1024, 0xA3 },{ 1152, 0xA4 },{ 1280, 0xA8 },{ 1536, 0xA9 },
> + { 1792, 0xAA },{ 1920, 0xA7 },{ 2048, 0xAB },{ 2304, 0xAC },
> + { 2560, 0xAD },{ 3072, 0xB1 },{ 3584, 0xB2 },{ 3840, 0xAF },
> + { 4096, 0xB3 },{ 4608, 0xB4 },{ 5120, 0xB8 },{ 6144, 0xB9 },
> + { 7168, 0xBA },{ 7680, 0xB7 },{ 8192, 0xBB },{ 9216, 0xBC },
> + { 10240, 0xBD },{ 12288, 0xBE },{ 15360, 0xBF }
> +};
> +
> +/**
> + ERR009203 : I2C may not work reliably with the default setting
What erratum database does this ID refer to?
I don't need access to it, but an explanation at the end of the file
header comment would be helpful.
> +
> + Description : The clocking circuitry of I2C module may not work reliably due to the slow
> + rise time of SCL signal.
First line too long (wrap after 'due'). Second line weird indentation.
> + Workaround : Enable the receiver digital filter by setting IBDBG[GLFLT_EN] to 1.
Ideally, wrap this line after 'setting'.
> +*/
> +STATIC
> +VOID
> + I2cErratumA009203 (
No indentation of function name.
Explanation of where that A prefix of the erratum ID came from would
also be appreciated.
> + IN UINTN Base
> + )
> +{
> + I2C_REGS *Regs;
> +
> + Regs = (I2C_REGS *)Base;
> +
> + MmioOr8 ( (UINTN)&Regs->Ibdbg, I2C_IBDBG_GLFLT_EN);
No space before (UINTN).
> +}
> +
> +/**
> + Early init I2C for reading the sysclk from I2c slave device.
> + I2c bus clock is determined from the clock input to I2c controller.
> + The clock input to I2c controller is derived from the sysclk.
> + sysclk is determined by clock generator, which is controller by i2c.
> +
> + So, it's a chicken-egg problem to read the sysclk from clock generator.
> + To break this cycle (i.e. to read the sysclk), we setup the i2c bus clock to
> + lowest value, in the hope that it won't be out of clock generator's supported
> + i2c clock frequency. Once we have the correct sysclk, we can setup the correct
> + i2c bus clock.
> +
> + @param[in] Base Base Address of I2c controller's registers
> +
> + @return EFI_SUCCESS successfuly setup the i2c bus for reading sysclk
> +**/
> +EFI_STATUS
> +I2cEarlyInitialize (
> + IN UINTN Base
> + )
> +{
> + I2C_REGS *Regs;
> + UINT8 Ibc;
This is a CamelCase project.
"Regs" is clear enough, but Ibc needs to be written out.
I'm going to guess it stands for i2c bus clock.
Since we're in a function where the name starts with I2c, we don't
need to be explicit about that. And we don't seem to be having any
other clocks to keep track of in this - so how about just calling it
"Clock"?
But then from the way it's used, should is be called MaxClock?
> +
> + Regs = (I2C_REGS *)Base;
> + if (FeaturePcdGet (PcdI2cErratumA009203)) {
> + I2cErratumA009203 (Base);
> + }
> +
> + if (MmioRead8 ( (UINTN)&Regs->Ibdbg) & I2C_IBDBG_GLFLT_EN) {
No space before (UINTN).
In general, could you do a global search and replace for "( ("?
I won't mention it again, but since it is used consistently, I expect
to see much more of it in this set :)
> + Ibc = I2cClockDividerGlitchEnabled[ARRAY_SIZE (I2cClockDividerGlitchEnabled) - 1].Ibc;
> + } else {
> + Ibc = I2cClockDividerGlitchDisabled[ARRAY_SIZE (I2cClockDividerGlitchDisabled) - 1].Ibc;
This is way too hard to read.
Can you add a preprocessor macro for
X[ARRAY_SIZE (X) - 1] ?
with a helpful name like ARRAY_LAST_ELEM or something?
> + }
> +
> + MmioWrite8 ( (UINTN)&Regs->Ibfd, Ibc);
> + // Reset Module
> + MmioOr8 ( (UINTN)&Regs->Ibcr, I2C_IBCR_MDIS);
> + MmioAnd8 ( (UINTN)&Regs->Ibcr, ~(I2C_IBCR_IBIE | I2C_IBCR_DMAEN));
> + MmioAnd8 ( (UINTN)&Regs->Ibic, (UINT8)(~I2C_IBIC_BIIE));
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Configure I2c bus to opearte at a given speed
operate
> +
> + @param[in] Base Base Address of I2c controller's registers
> + @param[in] I2cBusClock Input clock to I2c controller
> + @param[in] Speed speed to be configured for I2c bus
Align comments.
> +**/
> +EFI_STATUS
> +I2cInitialize (
> + IN UINTN Base,
> + IN UINT64 I2cBusClock,
> + IN UINT64 Speed
> + )
> +{
> + I2C_REGS *Regs;
> + UINT16 ClockDivider;
> + UINT8 Ibc;
> + I2C_CLOCK_DIVIDER_PAIR *ClockDividerPair;
> + UINT32 ClockDividerPairSize;
> + UINT32 Index;
> +
> + Regs = (I2C_REGS *)Base;
> + if (FeaturePcdGet (PcdI2cErratumA009203)) {
> + I2cErratumA009203 (Base);
> + }
> +
> + Ibc = 0;
> + ClockDivider = (I2cBusClock + Speed - 1) / Speed;
> +
> + if (MmioRead8 ( (UINTN)&Regs->Ibdbg) & I2C_IBDBG_GLFLT_EN) {
> + ClockDividerPair = I2cClockDividerGlitchEnabled;
> + ClockDividerPairSize = ARRAY_SIZE (I2cClockDividerGlitchEnabled);
> + } else {
> + ClockDividerPair = I2cClockDividerGlitchDisabled;
> + ClockDividerPairSize = ARRAY_SIZE (I2cClockDividerGlitchDisabled);
> + }
> +
> + if (ClockDivider > ClockDividerPair[ClockDividerPairSize - 1].Divider) {
> + Ibc = ClockDividerPair[ClockDividerPairSize - 1].Ibc;
> + } else {
> + for (Index = 0; Index < ClockDividerPairSize; Index++) {
> + if (ClockDividerPair[Index].Divider >= ClockDivider) {
> + Ibc = ClockDividerPair[Index].Ibc;
> + break;
> + }
> + }
> + }
> +
> + MmioWrite8 ( (UINTN)&Regs->Ibfd, Ibc);
> + // Reset Module
> + MmioOr8 ( (UINTN)&Regs->Ibcr, I2C_IBCR_MDIS);
> + MmioAnd8 ( (UINTN)&Regs->Ibcr, ~(I2C_IBCR_IBIE | I2C_IBCR_DMAEN));
> + MmioAnd8 ( (UINTN)&Regs->Ibic, (UINT8)(~I2C_IBIC_BIIE));
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +EFI_STATUS
> +I2cBusTestBusBusy (
> + IN I2C_REGS *Regs,
> + IN BOOLEAN TestBusy
> + )
> +{
> + UINT8 Index;
> + UINT8 Reg;
> +
> + for (Index = 0; Index < 500; Index++) {
What does looping over something 500 times signify?
Is there a time period we're waiting for or is it just arbitrary?
If it's just arbitrary, put it in a #define and name it accordingly.
> + Reg = MmioRead8 ( (UINTN)&Regs->Ibsr);
> +
> + if (Reg & I2C_IBSR_IBAL) {
> + MmioWrite8 ( (UINTN)&Regs->Ibsr, Reg);
> + return EFI_NOT_READY;
> + }
> +
> + if (TestBusy && (Reg & I2C_IBSR_IBB)) {
> + break;
> + }
> +
> + if (!TestBusy && !(Reg & I2C_IBSR_IBB)) {
> + break;
> + }
> +
> + MicroSecondDelay (1);
Do we need a delay or do we need a barrier? Or do we need both?
> + }
> +
> + if (Index == 500) {
> + return EFI_TIMEOUT;
> + } else {
> + return EFI_SUCCESS;
> + }
> +}
> +
> +STATIC
> +EFI_STATUS
> +I2cTransferComplete (
> + IN I2C_REGS *Regs,
> + IN BOOLEAN TestRxAck
> +)
> +{
> + UINT8 Index;
> + UINT8 Reg;
> +
> + for (Index = 0; Index < 500; Index++) {
Same thing.
> + Reg = MmioRead8 ( (UINTN)&Regs->Ibsr);
> +
> + if (Reg & I2C_IBSR_IBIF) {
> + // Write 1 to clear the IBIF field
> + MmioWrite8 ( (UINTN)&Regs->Ibsr, Reg);
> + break;
> + }
> +
> + MicroSecondDelay (1);
Do we need a delay or do we need a barrier? Or do we need both?
> + }
> +
> + if (Index == 500) {
> + return EFI_TIMEOUT;
> + }
> +
> + if (TestRxAck && (Reg & I2C_IBSR_RXAK)) {
> + return EFI_NO_RESPONSE;
> + }
> +
> + if (Reg & I2C_IBSR_TCF) {
> + return EFI_SUCCESS;
> + }
> + return EFI_DEVICE_ERROR;
> +}
> +
> +STATIC
> +EFI_STATUS
> +I2cRead (
> + IN I2C_REGS *Regs,
> + IN UINT32 SlaveAddress,
> + IN EFI_I2C_OPERATION *Operation,
> + IN BOOLEAN IsLastOperation
> +)
> +{
> + EFI_STATUS Status;
> + UINTN Index;
> +
> + // Write Slave Address
> + MmioWrite8 ( (UINTN)&Regs->Ibdr, (SlaveAddress << BIT0) | BIT0);
> + Status = I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> + // select Receive mode.
> + MmioAnd8 ( (UINTN)&Regs->Ibcr, ~I2C_IBCR_TXRX);
> + // Perform a dummy read to initiate the receive operation.
> + MmioRead8 ( (UINTN)&Regs->Ibdr);
> +
> + for (Index = 0; Index < Operation->LengthInBytes; Index++) {
> + Status = I2cTransferComplete (Regs, I2C_BUS_NO_TEST_RX_ACK);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> + if (Index == (Operation->LengthInBytes - 2)) {
> + // Set No ACK = 1
> + MmioOr8 ( (UINTN)&Regs->Ibcr, I2C_IBCR_NOACK);
> + } else if (Index == (Operation->LengthInBytes - 1)) {
> + if (!IsLastOperation) {
> + // select Transmit mode (for repeat start)
> + MmioOr8 ( (UINTN)&Regs->Ibcr, I2C_IBCR_TXRX);
> + } else {
> + // Generate Stop Signal
> + MmioAnd8 ( (UINTN)&Regs->Ibcr, ~(I2C_IBCR_MSSL | I2C_IBCR_TXRX));
> + Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> + }
> + }
> + Operation->Buffer[Index] = MmioRead8 ( (UINTN)&Regs->Ibdr);
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +EFI_STATUS
> +I2cWrite (
> + IN I2C_REGS *Regs,
> + IN UINT32 SlaveAddress,
> + IN EFI_I2C_OPERATION *Operation
> +)
> +{
> + EFI_STATUS Status;
> + UINTN Index;
> +
> + // Write Slave Address
> + MmioWrite8 ( (UINTN)&Regs->Ibdr, (SlaveAddress << BIT0) & (UINT8)(~BIT0));
> + Status = I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + // Write Data
> + for (Index = 0; Index < Operation->LengthInBytes; Index++) {
> + MmioWrite8 ( (UINTN)&Regs->Ibdr, Operation->Buffer[Index]);
> + Status = I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> + }
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +EFI_STATUS
> +I2cStop (
> + IN I2C_REGS *Regs
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 Reg;
> +
> + Reg = MmioRead8 ( (UINTN)&Regs->Ibsr);
> + if (Reg & I2C_IBSR_IBB) {
> + // Generate Stop Signal
> + MmioAnd8 ( (UINTN)&Regs->Ibcr, ~(I2C_IBCR_MSSL | I2C_IBCR_TXRX));
> + Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> + }
> +
> + // Disable I2c Controller
> + MmioOr8 ( (UINTN)&Regs->Ibcr, I2C_IBCR_MDIS);
> +
> + return Status;
> +}
> +
> +STATIC
> +EFI_STATUS
> +I2cStart (
> + IN I2C_REGS *Regs
> + )
> +{
> + EFI_STATUS Status;
> +
> + MmioOr8 ( (UINTN)&Regs->Ibsr, (I2C_IBSR_IBAL | I2C_IBSR_IBIF));
> + MmioAnd8 ( (UINTN)&Regs->Ibcr, (UINT8)(~I2C_IBCR_MDIS));
> +
> + // Generate Start Signal
> + MmioOr8 ( (UINTN)&Regs->Ibcr, I2C_IBCR_MSSL);
> + Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_BUSY);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> + MmioOr8 ( (UINTN)&Regs->Ibcr, I2C_IBCR_TXRX | I2C_IBCR_NOACK);
> + return Status;
> +}
> +
> +/**
> + Transfer data to/from I2c slave device
> +
> + @param[in] Base Base Address of I2c controller's registers
> + @param[in] SlaveAddress Slave Address from which data is to be read
> + @param[in] RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET structure
> + describing the I2C transaction
> +
> + @return EFI_SUCCESS successfuly setup the i2c bus for reading sysclk
> + @return EFI_DEVICE_ERROR There was an error while transferring data through I2c bus
> + @return EFI_NO_RESPONSE There was no Ack from i2c device
> + @return EFI_TIMEOUT I2c Bus is busy
> + @return EFI_NOT_READY I2c Bus Arbitration lost
> +**/
> +EFI_STATUS
> +I2cBusXfer (
> + IN UINTN Base,
> + IN UINT32 SlaveAddress,
> + IN EFI_I2C_REQUEST_PACKET *RequestPacket
> + )
> +{
> + UINTN Index;
> + I2C_REGS *Regs;
> + EFI_I2C_OPERATION *Operation;
> + EFI_STATUS Status;
> + BOOLEAN IsLastOperation;
> +
> + Regs = (I2C_REGS *)Base;
> + IsLastOperation = FALSE;
> +
> + Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE);
> + if (EFI_ERROR (Status)) {
> + goto ErrorExit;
> + }
> +
> + Status = I2cStart (Regs);
> + if (EFI_ERROR (Status)) {
> + goto ErrorExit;
> + }
> +
> + for (Index = 0, Operation = RequestPacket->Operation;
> + Index < RequestPacket->OperationCount;
> + Index++, Operation++) {
> + if (Index == (RequestPacket->OperationCount - 1)) {
> + IsLastOperation = TRUE;
> + }
> + // Send repeat start after first transmit/recieve
> + if (Index) {
> + MmioOr8 ( (UINTN)&Regs->Ibcr, I2C_IBCR_RSTA);
> + Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_BUSY);
> + if (EFI_ERROR (Status)) {
> + goto ErrorExit;
> + }
> + }
> + // Read/write data
> + if (Operation->Flags & I2C_FLAG_READ) {
> + Status = I2cRead (Regs, SlaveAddress, Operation, IsLastOperation);
> + } else {
> + Status = I2cWrite (Regs, SlaveAddress, Operation);
> + }
> + if (EFI_ERROR (Status)) {
> + goto ErrorExit;
> + }
> + }
> +
> +ErrorExit:
> +
> + I2cStop (Regs);
> +
> + return Status;
> +}
> +
> +/**
> + Read a register from I2c slave device. This API is wrapper around I2cBusXfer
> +
> + @param[in] Base Base Address of I2c controller's registers
> + @param[in] SlaveAddress Slave Address from which register value is to be read
> + @param[in] RegAddress Register Address in Slave's memory map
> + @param[in] RegAddressWidthInBytes Number of bytes in RegAddress to send to I2c Slave
> + for simple reads without any register, make this value = 0
> + (RegAddress is don't care in that case)
> + @param[out] RegValue Value to be read from I2c slave's regiser
> + @param[in] RegValueNumBytes Number of bytes to read from I2c slave register
> +
> + @return EFI_SUCCESS successfuly setup the i2c bus for reading sysclk
> + @return EFI_DEVICE_ERROR There was an error while transferring data through I2c bus
> + @return EFI_NO_RESPONSE There was no Ack from i2c device
> + @return EFI_TIMEOUT I2c Bus is busy
> + @return EFI_NOT_READY I2c Bus Arbitration lost
Align comments. And try to keep line lengths no longer than 80 characters.
> +**/
> +EFI_STATUS
> +I2cBusReadReg (
> + IN UINTN Base,
> + IN UINT32 SlaveAddress,
> + IN UINT64 RegAddress,
> + IN UINT8 RegAddressWidthInBytes,
> + OUT UINT8 *RegValue,
> + IN UINT8 RegValueNumBytes
> + )
> +{
> + EFI_I2C_OPERATION *Operations;
> + I2C_REG_REQUEST RequestPacket;
> + UINTN OperationCount;
> + UINT8 Address[8];
Create a well named #define for that 8.
> + UINT8 *Ptr;
The name Ptr does not convey information.
Give it a name that describes what it points to.
> + EFI_STATUS Status;
> +
> + ZeroMem (&RequestPacket, sizeof (RequestPacket));
> + OperationCount = 0;
> + Operations = RequestPacket.Operation;
> + Ptr = Address;
> +
> + if (RegAddressWidthInBytes > ARRAY_SIZE (Address)) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + if (RegAddressWidthInBytes != 0) {
> + Operations[OperationCount].LengthInBytes = RegAddressWidthInBytes;
> + Operations[OperationCount].Buffer = Ptr;
> + while (RegAddressWidthInBytes--) {
> + *Ptr++ = RegAddress >> (8 * RegAddressWidthInBytes);
> + }
> + OperationCount++;
> + }
> +
> + Operations[OperationCount].LengthInBytes = RegValueNumBytes;
> + Operations[OperationCount].Buffer = RegValue;
> + Operations[OperationCount].Flags = I2C_FLAG_READ;
> + OperationCount++;
> +
> + RequestPacket.OperationCount = OperationCount;
> +
> + Status = I2cBusXfer (Base, SlaveAddress, (EFI_I2C_REQUEST_PACKET *)&RequestPacket);
> +
> + return Status;
> +}
> +
> diff --git a/Silicon/NXP/Library/I2cLib/I2cLib.inf b/Silicon/NXP/Library/I2cLib/I2cLib.inf
> new file mode 100644
> index 0000000000..9c8aae100b
> --- /dev/null
> +++ b/Silicon/NXP/Library/I2cLib/I2cLib.inf
> @@ -0,0 +1,30 @@
> +#/** @file
> +#
> +# Copyright 2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause
> +#
> +#**/
> +
> +[Defines]
> + INF_VERSION = 1.27
> + BASE_NAME = I2cLib
> + FILE_GUID = f22393b1-98b6-4067-9ec2-6aa436321f03
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = I2cLib
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + TimerLib
> + IoLib
Please sort library classes alphabetically.
> +
> +[Sources.common]
> + I2cLib.c
> +
> +[FeaturePcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203
> +
> diff --git a/Silicon/NXP/Library/I2cLib/I2cLibInternal.h b/Silicon/NXP/Library/I2cLib/I2cLibInternal.h
> new file mode 100644
> index 0000000000..14be9cb740
> --- /dev/null
> +++ b/Silicon/NXP/Library/I2cLib/I2cLibInternal.h
> @@ -0,0 +1,95 @@
> +/** @file
> + I2c Lib to control I2c controller.
> +
> + Copyright 2020 NXP
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef __I2C_LIB_INTERNAL_H__
> +#define __I2C_LIB_INTERNAL_H__
Please drop leading __ in header guards.
> +
> +#include <Pi/PiI2c.h>
> +#include <Uefi.h>
> +
> +/* Module Disable
> + * 0b - The module is enabled. You must clear this field before any other IBCR fields have any effect.
> + * 1b - The module is reset and disabled. This is the power-on reset situation. When high, the
> + * interface is held in reset, but registers can still be accessed. Status register fields (IBSR) are not
> + * valid when the module is disabled.
Please re-wrap lines at 80 characters throughout this file.
^
> + */
> +#define I2C_IBCR_MDIS BIT7
> +// I2c Bus Interrupt Enable
> +#define I2C_IBCR_IBIE BIT6
> +/* Master / Slave Mode 0b - Slave mode 1b - Master mode
> + * When you change this field from 0 to 1, the module generates a START signal on the bus and selects the
> + * master mode. When you change this field from 1 to 0, the module generates a STOP signal and changes
> + * the operation mode from master to slave. You should generate a STOP signal only if IBSR[IBIF]=1. The
> + * module clears this field without generating a STOP signal when the master loses arbitration.
> +*/
> +#define I2C_IBCR_MSSL BIT5
> +// 0b - Receive 1b - Transmit
> +#define I2C_IBCR_TXRX BIT4
> +/* Data acknowledge disable
> + * Values written to this field are only used when the I2C module is a receiver, not a transmitter.
> + * 0b - The module sends an acknowledge signal to the bus at the 9th clock bit after receiving one
> + * byte of data.
> + * 1b - The module does not send an acknowledge-signal response (that is, acknowledge bit = 1).
> + */
> +#define I2C_IBCR_NOACK BIT3
> +/* Repeat START
> + * If the I2C module is the current bus master, and you program RSTA=1, the I2C module generates a
> + * repeated START condition. This field always reads as a 0. If you attempt a repeated START at the wrong
> + * time—if the bus is owned by another master—the result is loss of arbitration.
> + */
> +#define I2C_IBCR_RSTA BIT2
> +// DMA enable
> +#define I2C_IBCR_DMAEN BIT1
> +
> +// Transfer Complete
> +#define I2C_IBSR_TCF BIT7
> +// I2C bus Busy. 0b - Bus is idle, 1b - Bus is busy
> +#define I2C_IBSR_IBB BIT5
> +// Arbitration Lost. software must clear this field by writing a one to it.
> +#define I2C_IBSR_IBAL BIT4
> +// I2C bus interrupt flag
> +#define I2C_IBSR_IBIF BIT1
> +// Received acknowledge 0b - Acknowledge received 1b - No acknowledge received
> +#define I2C_IBSR_RXAK BIT0
> +
> +//Bus idle interrupt enable
> +#define I2C_IBIC_BIIE BIT7
> +
> +// Glitch filter enable
> +#define I2C_IBDBG_GLFLT_EN BIT3
> +
> +#define I2C_BUS_TEST_BUSY TRUE
> +#define I2C_BUS_TEST_IDLE !I2C_BUS_TEST_BUSY
> +#define I2C_BUS_TEST_RX_ACK TRUE
> +#define I2C_BUS_NO_TEST_RX_ACK !I2C_BUS_TEST_RX_ACK
> +
> +typedef struct _I2C_REGS {
> + UINT8 Ibad; // I2c Bus Address Register
> + UINT8 Ibfd; // I2c Bus Frequency Dividor Register
> + UINT8 Ibcr; // I2c Bus Control Register
> + UINT8 Ibsr; // I2c Bus Status Register
> + UINT8 Ibdr; // I2C Bus Data I/O Register
> + UINT8 Ibic; // I2C Bus Interrupt Config Register
> + UINT8 Ibdbg; // I2C Bus Debug Register
> +} I2C_REGS;
> +
> +/*
> + * sorted list of clock divider, register value pairs
> + */
> +typedef struct _I2C_CLOCK_DIVIDER_PAIR {
> + UINT16 Divider;
> + UINT16 Ibc;
CamelCase - please expand Ibc.
/
Leif
> +} I2C_CLOCK_DIVIDER_PAIR;
> +
> +typedef struct {
> + UINTN OperationCount;
> + EFI_I2C_OPERATION Operation[2];
> +} I2C_REG_REQUEST;
> +
> +#endif // __I2C_LIB_INTERNAL_H__
> +
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index 764b9bb0e2..4a1cfb3e27 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -1,6 +1,6 @@
> # @file.
> #
> -# Copyright 2017-2019 NXP
> +# Copyright 2017-2020 NXP
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -13,6 +13,10 @@
> [Includes]
> Include
>
> +[LibraryClasses]
> + ## @libraryclass Provides services to read/write to I2c devices
> + I2cLib|Include/Library/I2cLib.h
> +
> [Guids.common]
> gNxpQoriqLsTokenSpaceGuid = {0x98657342, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
> gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
> @@ -101,3 +105,7 @@
> gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000312
> gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|FALSE|BOOLEAN|0x00000313
> gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314
> +
> +[PcdsFeatureFlag]
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315
> +
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 02/19] Silicon/NXP: changes to use I2clib in i2cdxe
2020-02-07 12:43 ` [PATCH 02/19] Silicon/NXP: changes to use I2clib in i2cdxe Pankaj Bansal
@ 2020-02-08 17:23 ` Leif Lindholm
0 siblings, 0 replies; 49+ messages in thread
From: Leif Lindholm @ 2020-02-08 17:23 UTC (permalink / raw)
To: Pankaj Bansal; +Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi, devel
On Fri, Feb 07, 2020 at 18:13:11 +0530, Pankaj Bansal wrote:
> I2c lib contains the i2c controller functionality. this can be used
> in I2c DXE driver to communicate with i2c devices.
This is one patch.
> There was a bug in I2C DXE implementation, which caused the Ds1307 RTC
> device to issue two operation for register write, while this is a single
> operation task. refer page 12 (Slave Receiver Mode (Write Mode)) on
>
> https://datasheets.maximintegrated.com/en/ds/DS1307.pdf
>
> with i2c lib implementation, this bug has been fixed. so modify ds1307
> code accordingly.
This is a separate patch.
Please split it out separately.
Ideally the change in I2clib would happen in the same patch.
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> .../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c | 23 +-
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 526 +-----------------
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 44 +-
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 3 +-
> 4 files changed, 31 insertions(+), 565 deletions(-)
>
> diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
> index 88dc198ffe..444e011248 100644
> --- a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
> +++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
> @@ -5,7 +5,7 @@
> EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c
>
> Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> - Copyright 2017 NXP
> + Copyright 2017, 2020 NXP
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -28,6 +28,11 @@ STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster;
>
> /**
> Read RTC register.
> + Data Read-Slave Transmitter Mode
> +
> + <Slave Address> <Word Address (n)> <Slave Address> <Data(n)> <Data(n+1)> <Data(n+2)> <Data(n+X)>
> +
> + The first byte is received and handled as in the slave receiver mode.
And while I greatly approve of the improved comments (especially if
they were wrapped at 80 characters), this is yet another separate patch.
>
> @param RtcRegAddr Register offset of RTC to be read.
>
> @@ -69,6 +74,9 @@ RtcRead (
>
> /**
> Write RTC register.
> + Data Write-Slave Receiver Mode
> +
> + <Slave Address> <Word Address (n)> <Data(n)> <Data(n+1)> <Data(n+X)>
>
> @param RtcRegAddr Register offset of RTC to write.
> @param Val Value to be written
> @@ -84,16 +92,15 @@ RtcWrite (
> {
> RTC_I2C_REQUEST Req;
> EFI_STATUS Status;
> + UINT8 Buffer[2];
>
> - Req.OperationCount = 2;
> + Req.OperationCount = 1;
> + Buffer[0] = RtcRegAddr;
> + Buffer[1] = Val;
>
> Req.SetAddressOp.Flags = 0;
> - Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
> - Req.SetAddressOp.Buffer = &RtcRegAddr;
> -
> - Req.GetSetDateTimeOp.Flags = 0;
> - Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
> - Req.GetSetDateTimeOp.Buffer = &Val;
> + Req.SetAddressOp.LengthInBytes = sizeof (Buffer);
> + Req.SetAddressOp.Buffer = Buffer;
>
> Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSlaveAddress),
> (VOID *)&Req,
> diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> index 853c426fbc..8e3a82efca 100644
> --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> @@ -1,7 +1,7 @@
> /** I2cDxe.c
> I2c driver APIs for read, write, initialize, set speed and reset
>
> - Copyright 2017-2019 NXP
> + Copyright 2017-2020 NXP
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -15,6 +15,7 @@
> #include <Library/TimerLib.h>
> #include <Library/UefiBootServicesTableLib.h>
> #include <Library/UefiLib.h>
> +#include <Library/I2cLib.h>
>
> #include "I2cDxe.h"
>
> @@ -25,444 +26,6 @@ STATIC CONST EFI_I2C_CONTROLLER_CAPABILITIES mI2cControllerCapabilities = {
> 0
> };
>
> -STATIC CONST CLK_DIV mClkDiv[] = {
> - { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
> - { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
> - { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
> - { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
> - { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
> - { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
> - { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
> - { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
> - { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
> - { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
> - { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
> - { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
> - { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
> - { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
> - { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }
> -};
> -
> -/**
> - Calculate and return proper clock divider
> -
> - @param Rate desired clock rate
> -
> - @retval ClkDiv Index value used to get Bus Clock Rate
> -
> -**/
> -STATIC
> -UINT8
> -GetClkDivIndex (
> - IN UINT32 Rate
> - )
> -{
> - UINTN ClkRate;
> - UINT32 Div;
> - UINT8 Index;
> -
> - Index = 0;
> - ClkRate = GetBusFrequency ();
> -
> - Div = (ClkRate + Rate - 1) / Rate;
> -
> - if (Div < mClkDiv[0].SCLDivider) {
> - return 0;
> - }
> -
> - do {
> - if (mClkDiv[Index].SCLDivider >= Div ) {
> - return Index;
> - }
> - Index++;
> - } while (Index < ARRAY_SIZE (mClkDiv));
> -
> - return (ARRAY_SIZE (mClkDiv) - 1);
> -}
> -
> -/**
> - Function used to check if i2c is in mentioned state or not
> -
> - @param I2cRegs Pointer to I2C registers
> - @param State i2c state need to be checked
> -
> - @retval EFI_NOT_READY Arbitration was lost
> - @retval EFI_TIMEOUT Timeout occured
> - @retval CurrState Value of state register
> -
> -**/
> -STATIC
> -EFI_STATUS
> -WaitForI2cState (
> - IN I2C_REGS *I2cRegs,
> - IN UINT32 State
> - )
> -{
> - UINT8 CurrState;
> - UINT64 Count;
> -
> - for (Count = 0; Count < I2C_STATE_RETRIES; Count++) {
> - MemoryFence ();
> - CurrState = MmioRead8 ((UINTN)&I2cRegs->I2cSr);
> - if (CurrState & I2C_SR_IAL) {
> - MmioWrite8 ((UINTN)&I2cRegs->I2cSr, CurrState | I2C_SR_IAL);
> - return EFI_NOT_READY;
> - }
> -
> - if ((CurrState & (State >> 8)) == (UINT8)State) {
> - return CurrState;
> - }
> - }
> -
> - return EFI_TIMEOUT;
> -}
> -
> -/**
> - Function to transfer byte on i2c
> -
> - @param I2cRegs Pointer to i2c registers
> - @param Byte Byte to be transferred on i2c bus
> -
> - @retval EFI_NOT_READY Arbitration was lost
> - @retval EFI_TIMEOUT Timeout occured
> - @retval EFI_NOT_FOUND ACK was not recieved
> - @retval EFI_SUCCESS Data transfer was succesful
> -
> -**/
> -STATIC
> -EFI_STATUS
> -TransferByte (
> - IN I2C_REGS *I2cRegs,
> - IN UINT8 Byte
> - )
> -{
> - EFI_STATUS RetVal;
> -
> - MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
> - MmioWrite8 ((UINTN)&I2cRegs->I2cDr, Byte);
> -
> - RetVal = WaitForI2cState (I2cRegs, IIF);
> - if ((RetVal == EFI_TIMEOUT) || (RetVal == EFI_NOT_READY)) {
> - return RetVal;
> - }
> -
> - if (RetVal & I2C_SR_RX_NO_AK) {
> - return EFI_NOT_FOUND;
> - }
> -
> - return EFI_SUCCESS;
> -}
> -
> -/**
> - Function to stop transaction on i2c bus
> -
> - @param I2cRegs Pointer to i2c registers
> -
> - @retval EFI_NOT_READY Arbitration was lost
> - @retval EFI_TIMEOUT Timeout occured
> - @retval EFI_SUCCESS Stop operation was successful
> -
> -**/
> -STATIC
> -EFI_STATUS
> -I2cStop (
> - IN I2C_REGS *I2cRegs
> - )
> -{
> - EFI_STATUS RetVal;
> - UINT32 Temp;
> -
> - Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
> -
> - Temp &= ~(I2C_CR_MSTA | I2C_CR_MTX);
> - MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> -
> - RetVal = WaitForI2cState (I2cRegs, BUS_IDLE);
> -
> - if (RetVal < 0) {
> - return RetVal;
> - } else {
> - return EFI_SUCCESS;
> - }
> -}
> -
> -/**
> - Function to send start signal, Chip Address and
> - memory offset
> -
> - @param I2cRegs Pointer to i2c base registers
> - @param Chip Chip Address
> - @param Offset Slave memory's offset
> - @param AddressLength length of chip address
> -
> - @retval EFI_NOT_READY Arbitration lost
> - @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
> - @retval EFI_NOT_FOUND ACK was not recieved
> - @retval EFI_SUCCESS Read was successful
> -
> -**/
> -STATIC
> -EFI_STATUS
> -InitTransfer (
> - IN I2C_REGS *I2cRegs,
> - IN UINT8 Chip,
> - IN UINT32 Offset,
> - IN INT32 AddressLength
> - )
> -{
> - UINT32 Temp;
> - EFI_STATUS RetVal;
> -
> - // Enable I2C controller
> - if (MmioRead8 ((UINTN)&I2cRegs->I2cCr) & I2C_CR_IDIS) {
> - MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IEN);
> - }
> -
> - if (MmioRead8 ((UINTN)&I2cRegs->I2cAdr) == (Chip << 1)) {
> - MmioWrite8 ((UINTN)&I2cRegs->I2cAdr, (Chip << 1) ^ 2);
> - }
> -
> - MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
> - RetVal = WaitForI2cState (I2cRegs, BUS_IDLE);
> - if ((RetVal == EFI_TIMEOUT) || (RetVal == EFI_NOT_READY)) {
> - return RetVal;
> - }
> -
> - // Start I2C transaction
> - Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
> - // set to master mode
> - Temp |= I2C_CR_MSTA;
> - MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> -
> - RetVal = WaitForI2cState (I2cRegs, BUS_BUSY);
> - if ((RetVal == EFI_TIMEOUT) || (RetVal == EFI_NOT_READY)) {
> - return RetVal;
> - }
> -
> - Temp |= I2C_CR_MTX | I2C_CR_TX_NO_AK;
> - MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> -
> - // write slave Address
> - RetVal = TransferByte (I2cRegs, Chip << 1);
> - if (RetVal != EFI_SUCCESS) {
> - return RetVal;
> - }
> -
> - if (AddressLength >= 0) {
> - while (AddressLength--) {
> - RetVal = TransferByte (I2cRegs, (Offset >> (AddressLength * 8)) & 0xff);
> - if (RetVal != EFI_SUCCESS)
> - return RetVal;
> - }
> - }
> - return EFI_SUCCESS;
> -}
> -
> -/**
> - Function to check if i2c bus is idle
> -
> - @param Base Pointer to base address of I2c controller
> -
> - @retval EFI_SUCCESS
> -
> -**/
> -STATIC
> -INT32
> -I2cBusIdle (
> - IN VOID *Base
> - )
> -{
> - return EFI_SUCCESS;
> -}
> -
> -/**
> - Function to initiate data transfer on i2c bus
> -
> - @param I2cRegs Pointer to i2c base registers
> - @param Chip Chip Address
> - @param Offset Slave memory's offset
> - @param AddressLength length of chip address
> -
> - @retval EFI_NOT_READY Arbitration lost
> - @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
> - @retval EFI_NOT_FOUND ACK was not recieved
> - @retval EFI_SUCCESS Read was successful
> -
> -**/
> -STATIC
> -EFI_STATUS
> -InitDataTransfer (
> - IN I2C_REGS *I2cRegs,
> - IN UINT8 Chip,
> - IN UINT32 Offset,
> - IN INT32 AddressLength
> - )
> -{
> - EFI_STATUS RetVal;
> - INT32 Retry;
> -
> - for (Retry = 0; Retry < RETRY_COUNT; Retry++) {
> - RetVal = InitTransfer (I2cRegs, Chip, Offset, AddressLength);
> - if (RetVal == EFI_SUCCESS) {
> - return EFI_SUCCESS;
> - }
> -
> - I2cStop (I2cRegs);
> -
> - if (EFI_NOT_FOUND == RetVal) {
> - return RetVal;
> - }
> -
> - // Disable controller
> - if (RetVal != EFI_NOT_READY) {
> - MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS);
> - }
> -
> - if (I2cBusIdle (I2cRegs) < 0) {
> - break;
> - }
> - }
> - return RetVal;
> -}
> -
> -/**
> - Function to read data using i2c bus
> -
> - @param BaseAddr I2c Controller Base Address
> - @param Chip Address of slave device from where data to be read
> - @param Offset Offset of slave memory
> - @param AddressLength Address length of slave
> - @param Buffer A pointer to the destination buffer for the data
> - @param Len Length of data to be read
> -
> - @retval EFI_NOT_READY Arbitration lost
> - @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
> - @retval EFI_NOT_FOUND ACK was not recieved
> - @retval EFI_SUCCESS Read was successful
> -
> -**/
> -STATIC
> -EFI_STATUS
> -I2cDataRead (
> - IN UINTN BaseAddr,
> - IN UINT8 Chip,
> - IN UINT32 Offset,
> - IN UINT32 AddressLength,
> - IN UINT8 *Buffer,
> - IN UINT32 Len
> - )
> -{
> - EFI_STATUS RetVal;
> - UINT32 Temp;
> - INT32 I;
> - I2C_REGS *I2cRegs;
> -
> - I2cRegs = (I2C_REGS *)(BaseAddr);
> -
> - RetVal = InitDataTransfer (I2cRegs, Chip, Offset, AddressLength);
> - if (RetVal != EFI_SUCCESS) {
> - return RetVal;
> - }
> -
> - Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
> - Temp |= I2C_CR_RSTA;
> - MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> -
> - RetVal = TransferByte (I2cRegs, (Chip << 1) | 1);
> - if (RetVal != EFI_SUCCESS) {
> - I2cStop (I2cRegs);
> - return RetVal;
> - }
> -
> - // setup bus to read data
> - Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
> - Temp &= ~(I2C_CR_MTX | I2C_CR_TX_NO_AK);
> - if (Len == 1) {
> - Temp |= I2C_CR_TX_NO_AK;
> - }
> -
> - MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> - MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
> -
> - // Dummy Read to initiate recieve operation
> - MmioRead8 ((UINTN)&I2cRegs->I2cDr);
> -
> - for (I = 0; I < Len; I++) {
> - RetVal = WaitForI2cState (I2cRegs, IIF);
> - if ((RetVal == EFI_TIMEOUT) || (RetVal == EFI_NOT_READY)) {
> - I2cStop (I2cRegs);
> - return RetVal;
> - }
> - //
> - // It must generate STOP before read I2DR to prevent
> - // controller from generating another clock cycle
> - //
> - if (I == (Len - 1)) {
> - I2cStop (I2cRegs);
> - } else if (I == (Len - 2)) {
> - Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
> - Temp |= I2C_CR_TX_NO_AK;
> - MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> - }
> - MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
> - Buffer[I] = MmioRead8 ((UINTN)&I2cRegs->I2cDr);
> - }
> -
> - I2cStop (I2cRegs);
> -
> - return EFI_SUCCESS;
> -}
> -
> -/**
> - Function to write data using i2c bus
> -
> - @param BaseAddr I2c Controller Base Address
> - @param Chip Address of slave device where data to be written
> - @param Offset Offset of slave memory
> - @param AddressLength Address length of slave
> - @param Buffer A pointer to the source buffer for the data
> - @param Len Length of data to be write
> -
> - @retval EFI_NOT_READY Arbitration lost
> - @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
> - @retval EFI_NOT_FOUND ACK was not recieved
> - @retval EFI_SUCCESS Read was successful
> -
> -**/
> -STATIC
> -EFI_STATUS
> -I2cDataWrite (
> - IN UINTN BaseAddr,
> - IN UINT8 Chip,
> - IN UINT32 Offset,
> - IN INT32 AddressLength,
> - OUT UINT8 *Buffer,
> - IN INT32 Len
> - )
> -{
> - EFI_STATUS RetVal;
> - I2C_REGS *I2cRegs;
> - INT32 I;
> -
> - I2cRegs = (I2C_REGS *)BaseAddr;
> -
> - RetVal = InitDataTransfer (I2cRegs, Chip, Offset, AddressLength);
> - if (RetVal != EFI_SUCCESS) {
> - return RetVal;
> - }
> -
> - // Write operation
> - for (I = 0; I < Len; I++) {
> - RetVal = TransferByte (I2cRegs, Buffer[I]);
> - if (RetVal != EFI_SUCCESS) {
> - break;
> - }
> - }
> -
> - I2cStop (I2cRegs);
> - return RetVal;
> -}
> -
> /**
> Function to set i2c bus frequency
>
> @@ -479,22 +42,17 @@ SetBusFrequency (
> IN OUT UINTN *BusClockHertz
> )
> {
> - I2C_REGS *I2cRegs;
> - UINT8 ClkId;
> - UINT8 SpeedId;
> + UINTN I2cBase;
> + UINT64 I2cClock;
> NXP_I2C_MASTER *I2c;
>
> I2c = NXP_I2C_FROM_THIS (This);
>
> - I2cRegs = (I2C_REGS *)(I2c->Dev->Resources[0].AddrRangeMin);
> -
> - ClkId = GetClkDivIndex (*BusClockHertz);
> - SpeedId = mClkDiv[ClkId].BusClockRate;
> + I2cBase = (UINTN)(I2c->Dev->Resources[0].AddrRangeMin);
>
> - // Store divider value
> - MmioWrite8 ((UINTN)&I2cRegs->I2cFdr, SpeedId);
> + I2cClock = GetBusFrequency ();
>
> - MemoryFence ();
> + I2cInitialize (I2cBase, I2cClock, *BusClockHertz);
>
> return EFI_SUCCESS;
> }
> @@ -513,19 +71,6 @@ Reset (
> IN CONST EFI_I2C_MASTER_PROTOCOL *This
> )
> {
> - I2C_REGS *I2cRegs;
> - NXP_I2C_MASTER *I2c;
> -
> - I2c = NXP_I2C_FROM_THIS (This);
> -
> - I2cRegs = (I2C_REGS *)(I2c->Dev->Resources[0].AddrRangeMin);
> -
> - // Reset module
> - MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS);
> - MmioWrite8 ((UINTN)&I2cRegs->I2cSr, 0);
> -
> - MemoryFence ();
> -
> return EFI_SUCCESS;
> }
>
> @@ -540,62 +85,17 @@ StartRequest (
> OUT EFI_STATUS *I2cStatus OPTIONAL
> )
> {
> - NXP_I2C_MASTER *I2c;
> - UINT32 Count;
> - INT32 RetVal;
> - UINT32 Length;
> - UINT8 *Buffer;
> - UINT32 Flag;
> - UINT32 RegAddress;
> - UINT32 OffsetLength;
> -
> - RegAddress = 0;
> + NXP_I2C_MASTER *I2c;
> + UINTN I2cBase;
> + EFI_STATUS Status;
>
> I2c = NXP_I2C_FROM_THIS (This);
>
> - if (RequestPacket->OperationCount <= 0) {
> - DEBUG ((DEBUG_ERROR,"%a: Operation count is not valid %d\n",
> - __FUNCTION__, RequestPacket->OperationCount));
> - return EFI_INVALID_PARAMETER;
> - }
> + I2cBase = (UINTN)(I2c->Dev->Resources[0].AddrRangeMin);
>
> - OffsetLength = RequestPacket->Operation[0].LengthInBytes;
> - RegAddress = *RequestPacket->Operation[0].Buffer;
> -
> - for (Count = 1; Count < RequestPacket->OperationCount; Count++) {
> - Flag = RequestPacket->Operation[Count].Flags;
> - Length = RequestPacket->Operation[Count].LengthInBytes;
> - Buffer = RequestPacket->Operation[Count].Buffer;
> -
> - if (Length <= 0) {
> - DEBUG ((DEBUG_ERROR,"%a: Invalid length of buffer %d\n",
> - __FUNCTION__, Length));
> - return EFI_INVALID_PARAMETER;
> - }
> -
> - if (Flag == I2C_FLAG_READ) {
> - RetVal = I2cDataRead (I2c->Dev->Resources[0].AddrRangeMin, SlaveAddress,
> - RegAddress, OffsetLength, Buffer, Length);
> - if (RetVal != EFI_SUCCESS) {
> - DEBUG ((DEBUG_ERROR,"%a: I2c read operation failed (error %d)\n",
> - __FUNCTION__, RetVal));
> - return RetVal;
> - }
> - } else if (Flag == I2C_FLAG_WRITE) {
> - RetVal = I2cDataWrite (I2c->Dev->Resources[0].AddrRangeMin, SlaveAddress,
> - RegAddress, OffsetLength, Buffer, Length);
> - if (RetVal != EFI_SUCCESS) {
> - DEBUG ((DEBUG_ERROR,"%a: I2c write operation failed (error %d)\n",
> - __FUNCTION__, RetVal));
> - return RetVal;
> - }
> - } else {
> - DEBUG ((DEBUG_ERROR,"%a: Invalid Flag %d\n", __FUNCTION__, Flag));
> - return EFI_INVALID_PARAMETER;
> - }
> - }
> + Status = I2cBusXfer (I2cBase, SlaveAddress, RequestPacket);
>
> - return EFI_SUCCESS;
> + return Status;
> }
>
> EFI_STATUS
> diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> index 02a29a5cf2..88316f3133 100644
> --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> @@ -1,7 +1,7 @@
> /** I2cDxe.h
> Header defining the constant, base address amd function for I2C controller
>
> - Copyright 2017-2019 NXP
> + Copyright 2017-2020 NXP
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -16,32 +16,6 @@
> #include <Protocol/I2cMaster.h>
> #include <Protocol/NonDiscoverableDevice.h>
>
> -#define I2C_CR_IIEN (1 << 6)
> -#define I2C_CR_MSTA (1 << 5)
> -#define I2C_CR_MTX (1 << 4)
> -#define I2C_CR_TX_NO_AK (1 << 3)
> -#define I2C_CR_RSTA (1 << 2)
> -
> -#define I2C_SR_ICF (1 << 7)
> -#define I2C_SR_IBB (1 << 5)
> -#define I2C_SR_IAL (1 << 4)
> -#define I2C_SR_IIF (1 << 1)
> -#define I2C_SR_RX_NO_AK (1 << 0)
> -
> -#define I2C_CR_IEN (0 << 7)
> -#define I2C_CR_IDIS (1 << 7)
> -#define I2C_SR_IIF_CLEAR (1 << 1)
> -
> -#define BUS_IDLE (0 | (I2C_SR_IBB << 8))
> -#define BUS_BUSY (I2C_SR_IBB | (I2C_SR_IBB << 8))
> -#define IIF (I2C_SR_IIF | (I2C_SR_IIF << 8))
> -
> -#define I2C_FLAG_WRITE 0x0
> -
> -#define I2C_STATE_RETRIES 50000
> -
> -#define RETRY_COUNT 3
> -
> #define NXP_I2C_SIGNATURE SIGNATURE_32 ('N', 'I', '2', 'C')
> #define NXP_I2C_FROM_THIS(a) CR ((a), NXP_I2C_MASTER, \
> I2cMaster, NXP_I2C_SIGNATURE)
> @@ -63,22 +37,6 @@ typedef struct {
> NON_DISCOVERABLE_DEVICE *Dev;
> } NXP_I2C_MASTER;
>
> -/**
> - Record defining i2c registers
> -**/
> -typedef struct {
> - UINT8 I2cAdr;
> - UINT8 I2cFdr;
> - UINT8 I2cCr;
> - UINT8 I2cSr;
> - UINT8 I2cDr;
> -} I2C_REGS;
> -
> -typedef struct {
> - UINT16 SCLDivider;
> - UINT16 BusClockRate;
> -} CLK_DIV;
> -
> extern
> UINT64
> GetBusFrequency (
> diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> index 0c0bf63bb2..784139065f 100644
> --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> @@ -3,7 +3,7 @@
> # Component description file for I2c driver
> #
> # Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved.
> -# Copyright 2017-2019 NXP
> +# Copyright 2017-2020 NXP
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -35,6 +35,7 @@
> UefiBootServicesTableLib
> UefiDriverEntryPoint
> UefiLib
> + I2cLib
Please sort libraryclasses alphabetically.
/
Leif
>
> [Guids]
> gNxpNonDiscoverableI2cMasterGuid
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 03/19] NXP/LS1043aRdb: Move Soc specific components to soc files
2020-02-07 12:43 ` [PATCH 03/19] NXP/LS1043aRdb: Move Soc specific components to soc files Pankaj Bansal
@ 2020-02-08 17:27 ` Leif Lindholm
0 siblings, 0 replies; 49+ messages in thread
From: Leif Lindholm @ 2020-02-08 17:27 UTC (permalink / raw)
To: Pankaj Bansal; +Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi, devel
On Fri, Feb 07, 2020 at 18:13:12 +0530, Pankaj Bansal wrote:
> Soc specific components ought to be part of Soc files and not
> platform files. move the same to SOC files
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 7 +------
> Platform/NXP/NxpQoriqLs.dsc.inc | 2 ++
> Silicon/NXP/LS1043A/LS1043A.dsc.inc | 8 ++++++--
> 3 files changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> index c810559353..802cccdce6 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> @@ -2,7 +2,7 @@
> #
> # LS1043ARDB Board package.
> #
> -# Copyright 2017-2019 NXP
> +# Copyright 2017-2020 NXP
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -26,11 +26,7 @@
> !include Silicon/NXP/LS1043A/LS1043A.dsc.inc
>
> [LibraryClasses.common]
> - SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> - ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
> - SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> - IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
> RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
>
> [PcdsFixedAtBuild.common]
> @@ -46,7 +42,6 @@
> #
> # Board Specific Pcds
> #
> - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
> gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
> gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
>
> diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc
> index b28e0615f7..94d3e53a04 100644
> --- a/Platform/NXP/NxpQoriqLs.dsc.inc
> +++ b/Platform/NXP/NxpQoriqLs.dsc.inc
> @@ -95,6 +95,8 @@
> ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
>
> I2cLib|Silicon/NXP/Library/I2cLib/I2cLib.inf
> + ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
> + IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
>
> [LibraryClasses.common.SEC]
> PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> index dbd680b0ad..8790db6ff8 100644
> --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> @@ -1,12 +1,16 @@
> # LS1043A.dsc
> # LS1043A Soc package.
> #
> -# Copyright 2017-2019 NXP
> +# Copyright 2017-2020 NXP
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> #
>
> +[LibraryClasses.common]
> + SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> + SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> +
> ################################################################################
> #
> # Pcd Section - list of all EDK II PCD Entries defined by this Platform
> @@ -20,6 +24,7 @@
> gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01402000
>
> [PcdsFixedAtBuild.common]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
>
> #
> # CCSR Address Space and other attached Memories
> @@ -57,5 +62,4 @@
> #
> gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
> gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|TRUE
> -
Please drop this spurious blank line deletion.
Once that's done:
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
/
Leif
> ##
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 04/19] Silicon/NXP: Remove DuartLib and use BaseSerialPortLib16550
2020-02-07 12:43 ` [PATCH 04/19] Silicon/NXP: Remove DuartLib and use BaseSerialPortLib16550 Pankaj Bansal
@ 2020-02-08 17:46 ` Leif Lindholm
2020-02-10 5:48 ` Pankaj Bansal
0 siblings, 1 reply; 49+ messages in thread
From: Leif Lindholm @ 2020-02-08 17:46 UTC (permalink / raw)
To: Pankaj Bansal; +Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi, devel
On Fri, Feb 07, 2020 at 18:13:13 +0530, Pankaj Bansal wrote:
> UART in LS1043A conforms to ns16550 register set. so we can use the
> SerialPortLib16550 from MdeModulePkg.
1) This patch adds a new library and deletes an existing one - those
are two operationsand hence should be two patches.
2) That is irrelevant, because if you can use BaseSerialPortLib16550,
then use BaseSerialPortLib16550. Copying an existing library in
order to make some minor tweaks is not an option.
> We have removed the PCIe specific part from the library and also added
> the APIs to get the UART clock from SOC lib instead of using the fixed
> PCD.
So, what you need to do is update BaseSerialPortLib16550 to be usable
for you. This library is already used by several ARM platforms that
don't actually implement PCIe.
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> Silicon/NXP/LS1043A/LS1043A.dsc.inc | 2 +-
> .../BaseSerialPortLib16550.c | 804 ++++++++++++++++++
> .../BaseSerialPortLib16550.inf | 39 +
> .../BaseSerialPortLib16550.uni | 17 +
Please don't leave out the --stat and --stat-graph-width when
following the format-patch instructions at
https://github.com/tianocore/tianocore.github.io/wiki/Laszlo%27s-unkempt-git-guide-for-edk2-contributors-and-maintainers
/
Leif
> Silicon/NXP/Library/DUartPortLib/DUart.h | 122 ---
> .../NXP/Library/DUartPortLib/DUartPortLib.c | 364 --------
> .../NXP/Library/DUartPortLib/DUartPortLib.inf | 34 -
> 7 files changed, 861 insertions(+), 521 deletions(-)
> create mode 100644 Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> create mode 100644 Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
> create mode 100644 Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.uni
> delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUart.h
> delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
> delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
>
> diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> index 8790db6ff8..754eff396a 100644
> --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> @@ -9,7 +9,7 @@
>
> [LibraryClasses.common]
> SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> - SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> + SerialPortLib|Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
>
> ################################################################################
> #
> diff --git a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> new file mode 100644
> index 0000000000..2c5c54ac7d
> --- /dev/null
> +++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> @@ -0,0 +1,804 @@
> +/** @file
> + 16550 UART Serial Port library functions
> +
> + (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>
> + Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2018, AMD Incorporated. All rights reserved.<BR>
> + Copyright 2020 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Base.h>
> +#include <Library/SerialPortLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/BaseLib.h>
> +
> +//
> +// 16550 UART register offsets and bitfields
> +//
> +#define R_UART_RXBUF 0 // LCR_DLAB = 0
> +#define R_UART_TXBUF 0 // LCR_DLAB = 0
> +#define R_UART_BAUD_LOW 0 // LCR_DLAB = 1
> +#define R_UART_BAUD_HIGH 1 // LCR_DLAB = 1
> +#define R_UART_IER 1 // LCR_DLAB = 0
> +#define R_UART_FCR 2
> +#define B_UART_FCR_FIFOE BIT0
> +#define B_UART_FCR_FIFO64 BIT5
> +#define R_UART_LCR 3
> +#define B_UART_LCR_DLAB BIT7
> +#define R_UART_MCR 4
> +#define B_UART_MCR_DTRC BIT0
> +#define B_UART_MCR_RTS BIT1
> +#define R_UART_LSR 5
> +#define B_UART_LSR_RXRDY BIT0
> +#define B_UART_LSR_TXRDY BIT5
> +#define B_UART_LSR_TEMT BIT6
> +#define R_UART_MSR 6
> +#define B_UART_MSR_CTS BIT4
> +#define B_UART_MSR_DSR BIT5
> +#define B_UART_MSR_RI BIT6
> +#define B_UART_MSR_DCD BIT7
> +
> +extern
> +UINT64
> +GetBusFrequency (
> + VOID
> + );
> +
> +/**
> + Read an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is read from
> + MMIO space. If PcdSerialUseMmio is FALSE, then the value is read from I/O space. The
> + parameter Offset is added to the base address of the 16550 registers that is specified
> + by PcdSerialRegisterBase. PcdSerialRegisterAccessWidth specifies the MMIO space access
> + width and defaults to 8 bit access, and supports 8 or 32 bit access.
> +
> + @param Base The base address register of UART device.
> + @param Offset The offset of the 16550 register to read.
> +
> + @return The value read from the 16550 register.
> +
> +**/
> +UINT8
> +SerialPortReadRegister (
> + UINTN Base,
> + UINTN Offset
> + )
> +{
> + return MmioRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride));
> +}
> +
> +/**
> + Write an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is written to
> + MMIO space. If PcdSerialUseMmio is FALSE, then the value is written to I/O space. The
> + parameter Offset is added to the base address of the 16550 registers that is specified
> + by PcdSerialRegisterBase. PcdSerialRegisterAccessWidth specifies the MMIO space access
> + width and defaults to 8 bit access, and supports 8 or 32 bit access.
> +
> + @param Base The base address register of UART device.
> + @param Offset The offset of the 16550 register to write.
> + @param Value The value to write to the 16550 register specified by Offset.
> +
> + @return The value written to the 16550 register.
> +
> +**/
> +UINT8
> +SerialPortWriteRegister (
> + UINTN Base,
> + UINTN Offset,
> + UINT8 Value
> + )
> +{
> + return MmioWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride), Value);
> +}
> +
> +/**
> + Retrieve the I/O or MMIO base address register for the PCI UART device.
> +
> + This function assumes Root Bus Numer is Zero, and enables I/O and MMIO in PCI UART
> + Device if they are not already enabled.
> +
> + @return The base address register of the UART device.
> +
> +**/
> +UINTN
> +GetSerialRegisterBase (
> + VOID
> + )
> +{
> + return (UINTN)PcdGet64 (PcdSerialRegisterBase);
> +}
> +
> +/**
> + Return whether the hardware flow control signal allows writing.
> +
> + @param SerialRegisterBase The base address register of UART device.
> +
> + @retval TRUE The serial port is writable.
> + @retval FALSE The serial port is not writable.
> +**/
> +BOOLEAN
> +SerialPortWritable (
> + UINTN SerialRegisterBase
> + )
> +{
> + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
> + if (PcdGetBool (PcdSerialDetectCable)) {
> + //
> + // Wait for both DSR and CTS to be set
> + // DSR is set if a cable is connected.
> + // CTS is set if it is ok to transmit data
> + //
> + // DSR CTS Description Action
> + // === === ======================================== ========
> + // 0 0 No cable connected. Wait
> + // 0 1 No cable connected. Wait
> + // 1 0 Cable connected, but not clear to send. Wait
> + // 1 1 Cable connected, and clear to send. Transmit
> + //
> + return (BOOLEAN) ((SerialPortReadRegister (SerialRegisterBase, R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) == (B_UART_MSR_DSR | B_UART_MSR_CTS));
> + } else {
> + //
> + // Wait for both DSR and CTS to be set OR for DSR to be clear.
> + // DSR is set if a cable is connected.
> + // CTS is set if it is ok to transmit data
> + //
> + // DSR CTS Description Action
> + // === === ======================================== ========
> + // 0 0 No cable connected. Transmit
> + // 0 1 No cable connected. Transmit
> + // 1 0 Cable connected, but not clear to send. Wait
> + // 1 1 Cable connected, and clar to send. Transmit
> + //
> + return (BOOLEAN) ((SerialPortReadRegister (SerialRegisterBase, R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) != (B_UART_MSR_DSR));
> + }
> + }
> +
> + return TRUE;
> +}
> +
> +/**
> + Initialize the serial device hardware.
> +
> + If no initialization is required, then return RETURN_SUCCESS.
> + If the serial device was successfully initialized, then return RETURN_SUCCESS.
> + If the serial device could not be initialized, then return RETURN_DEVICE_ERROR.
> +
> + @retval RETURN_SUCCESS The serial device was initialized.
> + @retval RETURN_DEVICE_ERROR The serial device could not be initialized.
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +SerialPortInitialize (
> + VOID
> + )
> +{
> + UINTN SerialRegisterBase;
> + UINT32 Divisor;
> + UINT32 CurrentDivisor;
> + BOOLEAN Initialized;
> + UINT64 SerialClock;
> +
> + //
> + // Perform platform specific initialization required to enable use of the 16550 device
> + // at the location specified by PcdSerialUseMmio and PcdSerialRegisterBase.
> + //
> + SerialClock = GetBusFrequency ();
> + if (SerialClock == 0) {
> + return EFI_DEVICE_ERROR;
> + }
> +
> + //
> + // Calculate divisor for baud generator
> + // Ref_Clk_Rate / Baud_Rate / 16
> + //
> + Divisor = SerialClock / (PcdGet32 (PcdSerialBaudRate) * 16);
> + if ((SerialClock % (PcdGet32 (PcdSerialBaudRate) * 16)) >= PcdGet32 (PcdSerialBaudRate) * 8) {
> + Divisor++;
> + }
> +
> + //
> + // Get the base address of the serial port in either I/O or MMIO space
> + //
> + SerialRegisterBase = GetSerialRegisterBase ();
> + if (SerialRegisterBase == 0) {
> + return RETURN_DEVICE_ERROR;
> + }
> +
> + //
> + // See if the serial port is already initialized
> + //
> + Initialized = TRUE;
> + if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & 0x3F) != (PcdGet8 (PcdSerialLineControl) & 0x3F)) {
> + Initialized = FALSE;
> + }
> + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) | B_UART_LCR_DLAB));
> + CurrentDivisor = SerialPortReadRegister (SerialRegisterBase, R_UART_BAUD_HIGH) << 8;
> + CurrentDivisor |= (UINT32) SerialPortReadRegister (SerialRegisterBase, R_UART_BAUD_LOW);
> + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & ~B_UART_LCR_DLAB));
> + if (CurrentDivisor != Divisor) {
> + Initialized = FALSE;
> + }
> + if (Initialized) {
> + return RETURN_SUCCESS;
> + }
> +
> + //
> + // Wait for the serial port to be ready.
> + // Verify that both the transmit FIFO and the shift register are empty.
> + //
> + while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY));
> +
> + //
> + // Configure baud rate
> + //
> + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, B_UART_LCR_DLAB);
> + SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_HIGH, (UINT8) (Divisor >> 8));
> + SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_LOW, (UINT8) (Divisor & 0xff));
> +
> + //
> + // Clear DLAB and configure Data Bits, Parity, and Stop Bits.
> + // Strip reserved bits from PcdSerialLineControl
> + //
> + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(PcdGet8 (PcdSerialLineControl) & 0x3F));
> +
> + //
> + // Enable and reset FIFOs
> + // Strip reserved bits from PcdSerialFifoControl
> + //
> + SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, 0x00);
> + SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64)));
> +
> + //
> + // Set FIFO Polled Mode by clearing IER after setting FCR
> + //
> + SerialPortWriteRegister (SerialRegisterBase, R_UART_IER, 0x00);
> +
> + //
> + // Put Modem Control Register(MCR) into its reset state of 0x00.
> + //
> + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00);
> +
> + return RETURN_SUCCESS;
> +}
> +
> +/**
> + Write data from buffer to serial device.
> +
> + Writes NumberOfBytes data bytes from Buffer to the serial device.
> + The number of bytes actually written to the serial device is returned.
> + If the return value is less than NumberOfBytes, then the write operation failed.
> +
> + If Buffer is NULL, then ASSERT().
> +
> + If NumberOfBytes is zero, then return 0.
> +
> + @param Buffer Pointer to the data buffer to be written.
> + @param NumberOfBytes Number of bytes to written to the serial device.
> +
> + @retval 0 NumberOfBytes is 0.
> + @retval >0 The number of bytes written to the serial device.
> + If this value is less than NumberOfBytes, then the write operation failed.
> +
> +**/
> +UINTN
> +EFIAPI
> +SerialPortWrite (
> + IN UINT8 *Buffer,
> + IN UINTN NumberOfBytes
> + )
> +{
> + UINTN SerialRegisterBase;
> + UINTN Result;
> + UINTN Index;
> + UINTN FifoSize;
> +
> + if (Buffer == NULL) {
> + return 0;
> + }
> +
> + SerialRegisterBase = GetSerialRegisterBase ();
> + if (SerialRegisterBase ==0) {
> + return 0;
> + }
> +
> + if (NumberOfBytes == 0) {
> + //
> + // Flush the hardware
> + //
> +
> + //
> + // Wait for both the transmit FIFO and shift register empty.
> + //
> + while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY));
> +
> + //
> + // Wait for the hardware flow control signal
> + //
> + while (!SerialPortWritable (SerialRegisterBase));
> + return 0;
> + }
> +
> + //
> + // Compute the maximum size of the Tx FIFO
> + //
> + FifoSize = 1;
> + if ((PcdGet8 (PcdSerialFifoControl) & B_UART_FCR_FIFOE) != 0) {
> + if ((PcdGet8 (PcdSerialFifoControl) & B_UART_FCR_FIFO64) == 0) {
> + FifoSize = 16;
> + } else {
> + FifoSize = PcdGet32 (PcdSerialExtendedTxFifoSize);
> + }
> + }
> +
> + Result = NumberOfBytes;
> + while (NumberOfBytes != 0) {
> + //
> + // Wait for the serial port to be ready, to make sure both the transmit FIFO
> + // and shift register empty.
> + //
> + while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY));
> +
> + //
> + // Fill then entire Tx FIFO
> + //
> + for (Index = 0; Index < FifoSize && NumberOfBytes != 0; Index++, NumberOfBytes--, Buffer++) {
> + //
> + // Wait for the hardware flow control signal
> + //
> + while (!SerialPortWritable (SerialRegisterBase));
> +
> + //
> + // Write byte to the transmit buffer.
> + //
> + SerialPortWriteRegister (SerialRegisterBase, R_UART_TXBUF, *Buffer);
> + }
> + }
> + return Result;
> +}
> +
> +/**
> + Reads data from a serial device into a buffer.
> +
> + @param Buffer Pointer to the data buffer to store the data read from the serial device.
> + @param NumberOfBytes Number of bytes to read from the serial device.
> +
> + @retval 0 NumberOfBytes is 0.
> + @retval >0 The number of bytes read from the serial device.
> + If this value is less than NumberOfBytes, then the read operation failed.
> +
> +**/
> +UINTN
> +EFIAPI
> +SerialPortRead (
> + OUT UINT8 *Buffer,
> + IN UINTN NumberOfBytes
> + )
> +{
> + UINTN SerialRegisterBase;
> + UINTN Result;
> + UINT8 Mcr;
> +
> + if (NULL == Buffer) {
> + return 0;
> + }
> +
> + SerialRegisterBase = GetSerialRegisterBase ();
> + if (SerialRegisterBase ==0) {
> + return 0;
> + }
> +
> + Mcr = (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) & ~B_UART_MCR_RTS);
> +
> + for (Result = 0; NumberOfBytes-- != 0; Result++, Buffer++) {
> + //
> + // Wait for the serial port to have some data.
> + //
> + while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_RXRDY) == 0) {
> + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
> + //
> + // Set RTS to let the peer send some data
> + //
> + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(Mcr | B_UART_MCR_RTS));
> + }
> + }
> + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
> + //
> + // Clear RTS to prevent peer from sending data
> + //
> + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, Mcr);
> + }
> +
> + //
> + // Read byte from the receive buffer.
> + //
> + *Buffer = SerialPortReadRegister (SerialRegisterBase, R_UART_RXBUF);
> + }
> +
> + return Result;
> +}
> +
> +
> +/**
> + Polls a serial device to see if there is any data waiting to be read.
> +
> + Polls aserial device to see if there is any data waiting to be read.
> + If there is data waiting to be read from the serial device, then TRUE is returned.
> + If there is no data waiting to be read from the serial device, then FALSE is returned.
> +
> + @retval TRUE Data is waiting to be read from the serial device.
> + @retval FALSE There is no data waiting to be read from the serial device.
> +
> +**/
> +BOOLEAN
> +EFIAPI
> +SerialPortPoll (
> + VOID
> + )
> +{
> + UINTN SerialRegisterBase;
> +
> + SerialRegisterBase = GetSerialRegisterBase ();
> + if (SerialRegisterBase ==0) {
> + return FALSE;
> + }
> +
> + //
> + // Read the serial port status
> + //
> + if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_RXRDY) != 0) {
> + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
> + //
> + // Clear RTS to prevent peer from sending data
> + //
> + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) & ~B_UART_MCR_RTS));
> + }
> + return TRUE;
> + }
> +
> + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
> + //
> + // Set RTS to let the peer send some data
> + //
> + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) | B_UART_MCR_RTS));
> + }
> +
> + return FALSE;
> +}
> +
> +/**
> + Sets the control bits on a serial device.
> +
> + @param Control Sets the bits of Control that are settable.
> +
> + @retval RETURN_SUCCESS The new control bits were set on the serial device.
> + @retval RETURN_UNSUPPORTED The serial device does not support this operation.
> + @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +SerialPortSetControl (
> + IN UINT32 Control
> + )
> +{
> + UINTN SerialRegisterBase;
> + UINT8 Mcr;
> +
> + //
> + // First determine the parameter is invalid.
> + //
> + if ((Control & (~(EFI_SERIAL_REQUEST_TO_SEND | EFI_SERIAL_DATA_TERMINAL_READY |
> + EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE))) != 0) {
> + return RETURN_UNSUPPORTED;
> + }
> +
> + SerialRegisterBase = GetSerialRegisterBase ();
> + if (SerialRegisterBase ==0) {
> + return RETURN_UNSUPPORTED;
> + }
> +
> + //
> + // Read the Modem Control Register.
> + //
> + Mcr = SerialPortReadRegister (SerialRegisterBase, R_UART_MCR);
> + Mcr &= (~(B_UART_MCR_DTRC | B_UART_MCR_RTS));
> +
> + if ((Control & EFI_SERIAL_DATA_TERMINAL_READY) == EFI_SERIAL_DATA_TERMINAL_READY) {
> + Mcr |= B_UART_MCR_DTRC;
> + }
> +
> + if ((Control & EFI_SERIAL_REQUEST_TO_SEND) == EFI_SERIAL_REQUEST_TO_SEND) {
> + Mcr |= B_UART_MCR_RTS;
> + }
> +
> + //
> + // Write the Modem Control Register.
> + //
> + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, Mcr);
> +
> + return RETURN_SUCCESS;
> +}
> +
> +/**
> + Retrieve the status of the control bits on a serial device.
> +
> + @param Control A pointer to return the current control signals from the serial device.
> +
> + @retval RETURN_SUCCESS The control bits were read from the serial device.
> + @retval RETURN_UNSUPPORTED The serial device does not support this operation.
> + @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +SerialPortGetControl (
> + OUT UINT32 *Control
> + )
> +{
> + UINTN SerialRegisterBase;
> + UINT8 Msr;
> + UINT8 Mcr;
> + UINT8 Lsr;
> +
> + SerialRegisterBase = GetSerialRegisterBase ();
> + if (SerialRegisterBase ==0) {
> + return RETURN_UNSUPPORTED;
> + }
> +
> + *Control = 0;
> +
> + //
> + // Read the Modem Status Register.
> + //
> + Msr = SerialPortReadRegister (SerialRegisterBase, R_UART_MSR);
> +
> + if ((Msr & B_UART_MSR_CTS) == B_UART_MSR_CTS) {
> + *Control |= EFI_SERIAL_CLEAR_TO_SEND;
> + }
> +
> + if ((Msr & B_UART_MSR_DSR) == B_UART_MSR_DSR) {
> + *Control |= EFI_SERIAL_DATA_SET_READY;
> + }
> +
> + if ((Msr & B_UART_MSR_RI) == B_UART_MSR_RI) {
> + *Control |= EFI_SERIAL_RING_INDICATE;
> + }
> +
> + if ((Msr & B_UART_MSR_DCD) == B_UART_MSR_DCD) {
> + *Control |= EFI_SERIAL_CARRIER_DETECT;
> + }
> +
> + //
> + // Read the Modem Control Register.
> + //
> + Mcr = SerialPortReadRegister (SerialRegisterBase, R_UART_MCR);
> +
> + if ((Mcr & B_UART_MCR_DTRC) == B_UART_MCR_DTRC) {
> + *Control |= EFI_SERIAL_DATA_TERMINAL_READY;
> + }
> +
> + if ((Mcr & B_UART_MCR_RTS) == B_UART_MCR_RTS) {
> + *Control |= EFI_SERIAL_REQUEST_TO_SEND;
> + }
> +
> + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
> + *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
> + }
> +
> + //
> + // Read the Line Status Register.
> + //
> + Lsr = SerialPortReadRegister (SerialRegisterBase, R_UART_LSR);
> +
> + if ((Lsr & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) == (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) {
> + *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
> + }
> +
> + if ((Lsr & B_UART_LSR_RXRDY) == 0) {
> + *Control |= EFI_SERIAL_INPUT_BUFFER_EMPTY;
> + }
> +
> + return RETURN_SUCCESS;
> +}
> +
> +/**
> + Sets the baud rate, receive FIFO depth, transmit/receice time out, parity,
> + data bits, and stop bits on a serial device.
> +
> + @param BaudRate The requested baud rate. A BaudRate value of 0 will use the
> + device's default interface speed.
> + On output, the value actually set.
> + @param ReveiveFifoDepth The requested depth of the FIFO on the receive side of the
> + serial interface. A ReceiveFifoDepth value of 0 will use
> + the device's default FIFO depth.
> + On output, the value actually set.
> + @param Timeout The requested time out for a single character in microseconds.
> + This timeout applies to both the transmit and receive side of the
> + interface. A Timeout value of 0 will use the device's default time
> + out value.
> + On output, the value actually set.
> + @param Parity The type of parity to use on this serial device. A Parity value of
> + DefaultParity will use the device's default parity value.
> + On output, the value actually set.
> + @param DataBits The number of data bits to use on the serial device. A DataBits
> + vaule of 0 will use the device's default data bit setting.
> + On output, the value actually set.
> + @param StopBits The number of stop bits to use on this serial device. A StopBits
> + value of DefaultStopBits will use the device's default number of
> + stop bits.
> + On output, the value actually set.
> +
> + @retval RETURN_SUCCESS The new attributes were set on the serial device.
> + @retval RETURN_UNSUPPORTED The serial device does not support this operation.
> + @retval RETURN_INVALID_PARAMETER One or more of the attributes has an unsupported value.
> + @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +SerialPortSetAttributes (
> + IN OUT UINT64 *BaudRate,
> + IN OUT UINT32 *ReceiveFifoDepth,
> + IN OUT UINT32 *Timeout,
> + IN OUT EFI_PARITY_TYPE *Parity,
> + IN OUT UINT8 *DataBits,
> + IN OUT EFI_STOP_BITS_TYPE *StopBits
> + )
> +{
> + UINTN SerialRegisterBase;
> + UINT32 SerialBaudRate;
> + UINTN Divisor;
> + UINT8 Lcr;
> + UINT8 LcrData;
> + UINT8 LcrParity;
> + UINT8 LcrStop;
> + UINT64 SerialClock;
> +
> + SerialRegisterBase = GetSerialRegisterBase ();
> + if (SerialRegisterBase ==0) {
> + return RETURN_UNSUPPORTED;
> + }
> +
> + SerialClock = GetBusFrequency ();
> + if (SerialClock == 0) {
> + return EFI_DEVICE_ERROR;
> + }
> +
> + //
> + // Check for default settings and fill in actual values.
> + //
> + if (*BaudRate == 0) {
> + *BaudRate = PcdGet32 (PcdSerialBaudRate);
> + }
> + SerialBaudRate = (UINT32) *BaudRate;
> +
> + if (*DataBits == 0) {
> + LcrData = (UINT8) (PcdGet8 (PcdSerialLineControl) & 0x3);
> + *DataBits = LcrData + 5;
> + } else {
> + if ((*DataBits < 5) || (*DataBits > 8)) {
> + return RETURN_INVALID_PARAMETER;
> + }
> + //
> + // Map 5..8 to 0..3
> + //
> + LcrData = (UINT8) (*DataBits - (UINT8) 5);
> + }
> +
> + if (*Parity == DefaultParity) {
> + LcrParity = (UINT8) ((PcdGet8 (PcdSerialLineControl) >> 3) & 0x7);
> + switch (LcrParity) {
> + case 0:
> + *Parity = NoParity;
> + break;
> +
> + case 3:
> + *Parity = EvenParity;
> + break;
> +
> + case 1:
> + *Parity = OddParity;
> + break;
> +
> + case 7:
> + *Parity = SpaceParity;
> + break;
> +
> + case 5:
> + *Parity = MarkParity;
> + break;
> +
> + default:
> + break;
> + }
> + } else {
> + switch (*Parity) {
> + case NoParity:
> + LcrParity = 0;
> + break;
> +
> + case EvenParity:
> + LcrParity = 3;
> + break;
> +
> + case OddParity:
> + LcrParity = 1;
> + break;
> +
> + case SpaceParity:
> + LcrParity = 7;
> + break;
> +
> + case MarkParity:
> + LcrParity = 5;
> + break;
> +
> + default:
> + return RETURN_INVALID_PARAMETER;
> + }
> + }
> +
> + if (*StopBits == DefaultStopBits) {
> + LcrStop = (UINT8) ((PcdGet8 (PcdSerialLineControl) >> 2) & 0x1);
> + switch (LcrStop) {
> + case 0:
> + *StopBits = OneStopBit;
> + break;
> +
> + case 1:
> + if (*DataBits == 5) {
> + *StopBits = OneFiveStopBits;
> + } else {
> + *StopBits = TwoStopBits;
> + }
> + break;
> +
> + default:
> + break;
> + }
> + } else {
> + switch (*StopBits) {
> + case OneStopBit:
> + LcrStop = 0;
> + break;
> +
> + case OneFiveStopBits:
> + case TwoStopBits:
> + LcrStop = 1;
> + break;
> +
> + default:
> + return RETURN_INVALID_PARAMETER;
> + }
> + }
> +
> + //
> + // Calculate divisor for baud generator
> + // Ref_Clk_Rate / Baud_Rate / 16
> + //
> + Divisor = SerialClock / (SerialBaudRate * 16);
> + if ((SerialClock % (SerialBaudRate * 16)) >= SerialBaudRate * 8) {
> + Divisor++;
> + }
> +
> + //
> + // Configure baud rate
> + //
> + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, B_UART_LCR_DLAB);
> + SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_HIGH, (UINT8) (Divisor >> 8));
> + SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_LOW, (UINT8) (Divisor & 0xff));
> +
> + //
> + // Clear DLAB and configure Data Bits, Parity, and Stop Bits.
> + // Strip reserved bits from line control value
> + //
> + Lcr = (UINT8) ((LcrParity << 3) | (LcrStop << 2) | LcrData);
> + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8) (Lcr & 0x3F));
> +
> + return RETURN_SUCCESS;
> +}
> +
> diff --git a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
> new file mode 100644
> index 0000000000..45ae9dc0af
> --- /dev/null
> +++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
> @@ -0,0 +1,39 @@
> +## @file
> +# SerialPortLib instance for 16550 UART.
> +#
> +# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> +# Copyright 2020 NXP
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = BaseSerialPortLib16550
> + MODULE_UNI_FILE = BaseSerialPortLib16550.uni
> + FILE_GUID = 9E7C00CF-355A-4d4e-BF60-0428CFF95540
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.1
> + LIBRARY_CLASS = SerialPortLib
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> +
> +[LibraryClasses]
> + PcdLib
> + IoLib
> + SocLib
> +
> +[Sources]
> + BaseSerialPortLib16550.c
> +
> +[FixedPcd]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl ## CONSUMES
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable ## SOMETIMES_CONSUMES
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ## CONSUMES
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ## CONSUMES
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl ## CONSUMES
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl ## CONSUMES
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize ## CONSUMES
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride ## CONSUMES
> diff --git a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.uni b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.uni
> new file mode 100644
> index 0000000000..2fefe85cf8
> --- /dev/null
> +++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.uni
> @@ -0,0 +1,17 @@
> +// /** @file
> +// SerialPortLib instance for 16550 UART.
> +//
> +// SerialPortLib instance for 16550 UART.
> +//
> +// Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> +// Copyright 2020 NXP
> +//
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +// **/
> +
> +
> +#string STR_MODULE_ABSTRACT #language en-US "SerialPortLib instance for 16550 UART"
> +
> +#string STR_MODULE_DESCRIPTION #language en-US "SerialPortLib instance for 16550 UART."
> +
> diff --git a/Silicon/NXP/Library/DUartPortLib/DUart.h b/Silicon/NXP/Library/DUartPortLib/DUart.h
> deleted file mode 100644
> index c71e2ce55d..0000000000
> --- a/Silicon/NXP/Library/DUartPortLib/DUart.h
> +++ /dev/null
> @@ -1,122 +0,0 @@
> -/** DUart.h
> -* Header defining the DUART constants (Base addresses, sizes, flags)
> -*
> -* Based on Serial I/O Port library headers available in PL011Uart.h
> -*
> -* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
> -* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> -* Copyright 2017 NXP
> -*
> -* SPDX-License-Identifier: BSD-2-Clause-Patent
> -*
> -**/
> -
> -#ifndef DUART_H_
> -#define DUART_H_
> -
> -// FIFO Control Register
> -#define DUART_FCR_FIFO_EN 0x01 /* Fifo enable */
> -#define DUART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
> -#define DUART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
> -#define DUART_FCR_DMA_SELECT 0x08 /* For DMA applications */
> -#define DUART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
> -#define DUART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
> -#define DUART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
> -#define DUART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
> -#define DUART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
> -#define DUART_FCR_RXSR 0x02 /* Receiver soft reset */
> -#define DUART_FCR_TXSR 0x04 /* Transmitter soft reset */
> -
> -// Modem Control Register
> -#define DUART_MCR_DTR 0x01 /* Reserved */
> -#define DUART_MCR_RTS 0x02 /* RTS */
> -#define DUART_MCR_OUT1 0x04 /* Reserved */
> -#define DUART_MCR_OUT2 0x08 /* Reserved */
> -#define DUART_MCR_LOOP 0x10 /* Enable loopback test mode */
> -#define DUART_MCR_AFE 0x20 /* AFE (Auto Flow Control) */
> -#define DUART_MCR_DMA_EN 0x04
> -#define DUART_MCR_TX_DFR 0x08
> -
> -// Line Control Register
> -/*
> -* Note: if the word length is 5 bits (DUART_LCR_WLEN5), then setting
> -* DUART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
> -*/
> -#define DUART_LCR_WLS_MSK 0x03 /* character length select mask */
> -#define DUART_LCR_WLS_5 0x00 /* 5 bit character length */
> -#define DUART_LCR_WLS_6 0x01 /* 6 bit character length */
> -#define DUART_LCR_WLS_7 0x02 /* 7 bit character length */
> -#define DUART_LCR_WLS_8 0x03 /* 8 bit character length */
> -#define DUART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
> -#define DUART_LCR_PEN 0x08 /* Parity eneble */
> -#define DUART_LCR_EPS 0x10 /* Even Parity Select */
> -#define DUART_LCR_STKP 0x20 /* Stick Parity */
> -#define DUART_LCR_SBRK 0x40 /* Set Break */
> -#define DUART_LCR_BKSE 0x80 /* Bank select enable */
> -#define DUART_LCR_DLAB 0x80 /* Divisor latch access bit */
> -
> -// Line Status Register
> -#define DUART_LSR_DR 0x01 /* Data ready */
> -#define DUART_LSR_OE 0x02 /* Overrun */
> -#define DUART_LSR_PE 0x04 /* Parity error */
> -#define DUART_LSR_FE 0x08 /* Framing error */
> -#define DUART_LSR_BI 0x10 /* Break */
> -#define DUART_LSR_THRE 0x20 /* Xmit holding register empty */
> -#define DUART_LSR_TEMT 0x40 /* Xmitter empty */
> -#define DUART_LSR_ERR 0x80 /* Error */
> -
> -// Modem Status Register
> -#define DUART_MSR_DCTS 0x01 /* Delta CTS */
> -#define DUART_MSR_DDSR 0x02 /* Reserved */
> -#define DUART_MSR_TERI 0x04 /* Reserved */
> -#define DUART_MSR_DDCD 0x08 /* Reserved */
> -#define DUART_MSR_CTS 0x10 /* Clear to Send */
> -#define DUART_MSR_DSR 0x20 /* Reserved */
> -#define DUART_MSR_RI 0x40 /* Reserved */
> -#define DUART_MSR_DCD 0x80 /* Reserved */
> -
> -// Interrupt Identification Register
> -#define DUART_IIR_NO_INT 0x01 /* No interrupts pending */
> -#define DUART_IIR_ID 0x06 /* Mask for the interrupt ID */
> -#define DUART_IIR_MSI 0x00 /* Modem status interrupt */
> -#define DUART_IIR_THRI 0x02 /* Transmitter holding register empty */
> -#define DUART_IIR_RDI 0x04 /* Receiver data interrupt */
> -#define DUART_IIR_RLSI 0x06 /* Receiver line status interrupt */
> -
> -// Interrupt Enable Register
> -#define DUART_IER_MSI 0x08 /* Enable Modem status interrupt */
> -#define DUART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
> -#define DUART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
> -#define DUART_IER_RDI 0x01 /* Enable receiver data interrupt */
> -
> -// LCR defaults
> -#define DUART_LCR_8N1 0x03
> -#define DUART_LCRVAL DUART_LCR_8N1 /* 8 data, 1 stop, no parity */
> -#define DUART_MCRVAL (DUART_MCR_DTR | \
> - DUART_MCR_RTS) /* RTS/DTR */
> -#define DUART_FCRVAL (DUART_FCR_FIFO_EN | \
> - DUART_FCR_RXSR | \
> - DUART_FCR_TXSR) /* Clear & enable FIFOs */
> -
> -#define URBR 0x0
> -#define UTHR 0x0
> -#define UDLB 0x0
> -#define UDMB 0x1
> -#define UIER 0x1
> -#define UIIR 0x2
> -#define UFCR 0x2
> -#define UAFR 0x2
> -#define ULCR 0x3
> -#define UMCR 0x4
> -#define ULSR 0x5
> -#define UMSR 0x6
> -#define USCR 0x7
> -#define UDSR 0x10
> -
> -extern
> -UINT64
> -GetBusFrequency (
> - VOID
> - );
> -
> -#endif /* DUART_H_ */
> diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
> deleted file mode 100644
> index c3c738d3cc..0000000000
> --- a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
> +++ /dev/null
> @@ -1,364 +0,0 @@
> -/** DuartPortLib.c
> - DUART (NS16550) library functions
> -
> - Based on Serial I/O Port library functions available in PL011SerialPortLib.c
> -
> - Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
> - Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.<BR>
> - Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> - Copyright 2017 NXP
> -
> - SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Base.h>
> -#include <Library/IoLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/SerialPortLib.h>
> -
> -#include "DUart.h"
> -
> -STATIC CONST UINT32 mInvalidControlBits = (EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE | \
> - EFI_SERIAL_DATA_TERMINAL_READY);
> -
> -/**
> - Assert or deassert the control signals on a serial port.
> - The following control signals are set according their bit settings :
> - . Request to Send
> - . Data Terminal Ready
> -
> - @param[in] Control The following bits are taken into account :
> - . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the
> - "Request To Send" control signal if this bit is
> - equal to one/zero.
> - . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert
> - the "Data Terminal Ready" control signal if this
> - bit is equal to one/zero.
> - . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable
> - the hardware loopback if this bit is equal to
> - one/zero.
> - . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.
> - . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/
> - disable the hardware flow control based on CTS (Clear
> - To Send) and RTS (Ready To Send) control signals.
> -
> - @retval EFI_SUCCESS The new control bits were set on the device.
> - @retval EFI_UNSUPPORTED The device does not support this operation.
> -
> -**/
> -EFI_STATUS
> -EFIAPI
> -SerialPortSetControl (
> - IN UINT32 Control
> - )
> -{
> - UINT32 McrBits;
> - UINTN UartBase;
> -
> - UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> -
> - if (Control & (mInvalidControlBits)) {
> - return EFI_UNSUPPORTED;
> - }
> -
> - McrBits = MmioRead8 (UartBase + UMCR);
> -
> - if (Control & EFI_SERIAL_REQUEST_TO_SEND) {
> - McrBits |= DUART_MCR_RTS;
> - } else {
> - McrBits &= ~DUART_MCR_RTS;
> - }
> -
> - if (Control & EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE) {
> - McrBits |= DUART_MCR_LOOP;
> - } else {
> - McrBits &= ~DUART_MCR_LOOP;
> - }
> -
> - if (Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) {
> - McrBits |= DUART_MCR_AFE;
> - } else {
> - McrBits &= ~DUART_MCR_AFE;
> - }
> -
> - MmioWrite32 (UartBase + UMCR, McrBits);
> -
> - return EFI_SUCCESS;
> -}
> -
> -/**
> - Retrieve the status of the control bits on a serial device.
> -
> - @param[out] Control Status of the control bits on a serial device :
> -
> - . EFI_SERIAL_DATA_CLEAR_TO_SEND,
> - EFI_SERIAL_DATA_SET_READY,
> - EFI_SERIAL_RING_INDICATE,
> - EFI_SERIAL_CARRIER_DETECT,
> - EFI_SERIAL_REQUEST_TO_SEND,
> - EFI_SERIAL_DATA_TERMINAL_READY
> - are all related to the DTE (Data Terminal Equipment)
> - and DCE (Data Communication Equipment) modes of
> - operation of the serial device.
> - . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the
> - receive buffer is empty, 0 otherwise.
> - . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the
> - transmit buffer is empty, 0 otherwise.
> - . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if
> - the hardware loopback is enabled (the ouput feeds the
> - receive buffer), 0 otherwise.
> - . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if
> - a loopback is accomplished by software, 0 otherwise.
> - . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to
> - one if the hardware flow control based on CTS (Clear
> - To Send) and RTS (Ready To Send) control signals is
> - enabled, 0 otherwise.
> -
> - @retval EFI_SUCCESS The control bits were read from the serial device.
> -
> -**/
> -EFI_STATUS
> -EFIAPI
> -SerialPortGetControl (
> - OUT UINT32 *Control
> - )
> -{
> - UINT32 MsrRegister;
> - UINT32 McrRegister;
> - UINT32 LsrRegister;
> - UINTN UartBase;
> -
> - UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> -
> - MsrRegister = MmioRead8 (UartBase + UMSR);
> - McrRegister = MmioRead8 (UartBase + UMCR);
> - LsrRegister = MmioRead8 (UartBase + ULSR);
> -
> - *Control = 0;
> -
> - if ((MsrRegister & DUART_MSR_CTS) == DUART_MSR_CTS) {
> - *Control |= EFI_SERIAL_CLEAR_TO_SEND;
> - }
> -
> - if ((McrRegister & DUART_MCR_RTS) == DUART_MCR_RTS) {
> - *Control |= EFI_SERIAL_REQUEST_TO_SEND;
> - }
> -
> - if ((LsrRegister & DUART_LSR_TEMT) == DUART_LSR_TEMT) {
> - *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
> - }
> -
> - if ((McrRegister & DUART_MCR_AFE) == DUART_MCR_AFE) {
> - *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
> - }
> -
> - if ((McrRegister & DUART_MCR_LOOP) == DUART_MCR_LOOP) {
> - *Control |= EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE;
> - }
> -
> - return EFI_SUCCESS;
> -}
> -
> -/*
> - * Return Baud divisor on basis of Baudrate
> - */
> -UINT32
> -CalculateBaudDivisor (
> - IN UINT64 BaudRate
> - )
> -{
> - UINTN DUartClk;
> - UINTN FreqSystemBus;
> -
> - FreqSystemBus = GetBusFrequency ();
> - DUartClk = FreqSystemBus/PcdGet32(PcdPlatformFreqDiv);
> -
> - return ((DUartClk)/(BaudRate * 16));
> -}
> -
> -/*
> - Initialise the serial port to the specified settings.
> - All unspecified settings will be set to the default values.
> -
> - @return Always return EFI_SUCCESS or EFI_INVALID_PARAMETER.
> -
> - **/
> -VOID
> -EFIAPI
> -DuartInitializePort (
> - IN UINT64 BaudRate
> - )
> -{
> - UINTN UartBase;
> - UINT32 BaudDivisor;
> -
> - UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> - BaudDivisor = CalculateBaudDivisor (BaudRate);
> -
> -
> - while (!(MmioRead8 (UartBase + ULSR) & DUART_LSR_TEMT));
> -
> - //
> - // Enable and assert interrupt when new data is available on
> - // external device,
> - // setup data format, setup baud divisor
> - //
> - MmioWrite8 (UartBase + UIER, 0x1);
> - MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL);
> - MmioWrite8 (UartBase + UDLB, 0);
> - MmioWrite8 (UartBase + UDMB, 0);
> - MmioWrite8 (UartBase + ULCR, DUART_LCRVAL);
> - MmioWrite8 (UartBase + UMCR, DUART_MCRVAL);
> - MmioWrite8 (UartBase + UFCR, DUART_FCRVAL);
> - MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL);
> - MmioWrite8 (UartBase + UDLB, BaudDivisor & 0xff);
> - MmioWrite8 (UartBase + UDMB, (BaudDivisor >> 8) & 0xff);
> - MmioWrite8 (UartBase + ULCR, DUART_LCRVAL);
> -
> - return;
> -}
> -
> -/**
> - Programmed hardware of Serial port.
> -
> - @return Always return EFI_SUCCESS.
> -
> -**/
> -EFI_STATUS
> -EFIAPI
> -SerialPortInitialize (
> - VOID
> - )
> -{
> - UINT64 BaudRate;
> - BaudRate = (UINTN)PcdGet64 (PcdUartDefaultBaudRate);
> -
> -
> - DuartInitializePort (BaudRate);
> -
> - return EFI_SUCCESS;
> -}
> -
> -/**
> - Write data to serial device.
> -
> - @param Buffer Point of data buffer which need to be written.
> - @param NumberOfBytes Number of output bytes which are cached in Buffer.
> -
> - @retval 0 Write data failed.
> - @retval !0 Actual number of bytes written to serial device.
> -
> -**/
> -UINTN
> -EFIAPI
> -SerialPortWrite (
> - IN UINT8 *Buffer,
> - IN UINTN NumberOfBytes
> - )
> -{
> - UINT8 *Final;
> - UINTN UartBase;
> -
> - Final = &Buffer[NumberOfBytes];
> - UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> -
> - while (Buffer < Final) {
> - while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_THRE) == 0);
> - MmioWrite8 (UartBase + UTHR, *Buffer++);
> - }
> -
> - return NumberOfBytes;
> -}
> -
> -/**
> - Read data from serial device and save the data in buffer.
> -
> - @param Buffer Point of data buffer which need to be written.
> - @param NumberOfBytes Number of output bytes which are cached in Buffer.
> -
> - @retval 0 Read data failed.
> - @retval !0 Actual number of bytes read from serial device.
> -
> -**/
> -UINTN
> -EFIAPI
> -SerialPortRead (
> - OUT UINT8 *Buffer,
> - IN UINTN NumberOfBytes
> - )
> -{
> - UINTN Count;
> - UINTN UartBase;
> -
> - UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> -
> - for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
> - // Loop while waiting for a new char(s) to arrive in the
> - // RxFIFO
> - while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) == 0);
> -
> - *Buffer = MmioRead8 (UartBase + URBR);
> - }
> -
> - return NumberOfBytes;
> -}
> -
> -/**
> - Check to see if any data is available to be read from the debug device.
> -
> - @retval EFI_SUCCESS At least one byte of data is available to be read
> - @retval EFI_NOT_READY No data is available to be read
> - @retval EFI_DEVICE_ERROR The serial device is not functioning properly
> -
> -**/
> -BOOLEAN
> -EFIAPI
> -SerialPortPoll (
> - VOID
> - )
> -{
> - UINTN UartBase;
> -
> - UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> -
> - return ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) != 0);
> -}
> -
> -/**
> - Set new attributes to LS1043a.
> -
> - @param BaudRate The baud rate of the serial device. If the baud rate is not supported,
> - the speed will be reduced down to the nearest supported one and the
> - variable's value will be updated accordingly.
> - @param ReceiveFifoDepth The number of characters the device will buffer on input. If the specified
> - value is not supported, the variable's value will be reduced down to the
> - nearest supported one.
> - @param Timeout If applicable, the number of microseconds the device will wait
> - before timing out a Read or a Write operation.
> - @param Parity If applicable, this is the EFI_PARITY_TYPE that is computed or checked
> - as each character is transmitted or received. If the device does not
> - support parity, the value is the default parity value.
> - @param DataBits The number of data bits in each character
> - @param StopBits If applicable, the EFI_STOP_BITS_TYPE number of stop bits per character.
> - If the device does not support stop bits, the value is the default stop
> - bit value.
> -
> - @retval EFI_SUCCESS All attributes were set correctly on the serial device.
> -
> -**/
> -EFI_STATUS
> -EFIAPI
> -SerialPortSetAttributes (
> - IN OUT UINT64 *BaudRate,
> - IN OUT UINT32 *ReceiveFifoDepth,
> - IN OUT UINT32 *Timeout,
> - IN OUT EFI_PARITY_TYPE *Parity,
> - IN OUT UINT8 *DataBits,
> - IN OUT EFI_STOP_BITS_TYPE *StopBits
> - )
> -{
> - DuartInitializePort (*BaudRate);
> -
> - return EFI_SUCCESS;
> -}
> diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> deleted file mode 100644
> index 7a2fa619b0..0000000000
> --- a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> +++ /dev/null
> @@ -1,34 +0,0 @@
> -# DUartPortLib.inf
> -#
> -# Component description file for DUartPortLib module
> -#
> -# Copyright (c) 2013, Freescale Ltd. All rights reserved.
> -# Copyright 2017 NXP
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -
> -[Defines]
> - INF_VERSION = 0x0001001A
> - BASE_NAME = DUartPortLib
> - FILE_GUID = c42dfe79-8de5-429e-a055-2d0a58591498
> - MODULE_TYPE = BASE
> - VERSION_STRING = 1.0
> - LIBRARY_CLASS = SerialPortLib
> -
> -[Sources.common]
> - DUartPortLib.c
> -
> -[LibraryClasses]
> - PcdLib
> - SocLib
> -
> -[Packages]
> - MdeModulePkg/MdeModulePkg.dec
> - MdePkg/MdePkg.dec
> - Silicon/NXP/NxpQoriqLs.dec
> -
> -[Pcd]
> - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
> - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
> - gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [edk2-devel] [PATCH 01/19] Silicon/NXP: Add I2c lib
2020-02-08 17:13 ` Leif Lindholm
@ 2020-02-09 11:49 ` Ard Biesheuvel
0 siblings, 0 replies; 49+ messages in thread
From: Ard Biesheuvel @ 2020-02-09 11:49 UTC (permalink / raw)
To: edk2-devel-groups-io, Leif Lindholm
Cc: Pankaj Bansal, Meenakshi Aggarwal, Michael D Kinney, Varun Sethi
On Sat, 8 Feb 2020 at 18:14, Leif Lindholm <leif@nuviainc.com> wrote:
>
> On Fri, Feb 07, 2020 at 18:13:10 +0530, Pankaj Bansal wrote:
> > I2c lib is going to be used in PrePeiCore sec module to get the
> > System clock information from devices connected to i2c (like fpga
> > or clcok generator)
> >
> > since we don't have support of DXE modules this early in boot stage,
> > move the i2c controller functionality in library.
> >
> > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> > ---
> > Platform/NXP/NxpQoriqLs.dsc.inc | 4 +-
> > Silicon/NXP/Include/Library/I2cLib.h | 99 ++++
> > Silicon/NXP/Library/I2cLib/I2cLib.c | 532 ++++++++++++++++++++
> > Silicon/NXP/Library/I2cLib/I2cLib.inf | 30 ++
> > Silicon/NXP/Library/I2cLib/I2cLibInternal.h | 95 ++++
> > Silicon/NXP/NxpQoriqLs.dec | 10 +-
> > 6 files changed, 768 insertions(+), 2 deletions(-)
> > create mode 100644 Silicon/NXP/Include/Library/I2cLib.h
> > create mode 100644 Silicon/NXP/Library/I2cLib/I2cLib.c
> > create mode 100644 Silicon/NXP/Library/I2cLib/I2cLib.inf
> > create mode 100644 Silicon/NXP/Library/I2cLib/I2cLibInternal.h
> >
> > diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc
> > index fa5f30dd39..b28e0615f7 100644
> > --- a/Platform/NXP/NxpQoriqLs.dsc.inc
> > +++ b/Platform/NXP/NxpQoriqLs.dsc.inc
...
> > + *
> > + * In case of duplicate SCL Divider value, the IBC value
> > + * with high MUL value has been selected.
> > + * A higher MUL value results in a lower sampling rate of the I2C signals.
> > + * This gives the I2C module greater immunity against glitches in the I2C signals.
> > + */
> > +STATIC I2C_CLOCK_DIVIDER_PAIR I2cClockDividerGlitchEnabled[] = {
>
> Module-scope global variables should have 'm' prefix.
>
These should be CONST as well afaict
> > + { 34, 0x0 }, { 36, 0x1 }, { 38, 0x2 }, { 40, 0x3 },
> > + { 42, 0x4 }, { 44, 0x8 }, { 48, 0x9 }, { 52, 0xA },
> > + { 54, 0x7 }, { 56, 0xB }, { 60, 0xC }, { 64, 0x10 },
> > + { 68, 0x40 }, { 72, 0x41 }, { 76, 0x42 }, { 80, 0x43 },
> > + { 84, 0x44 }, { 88, 0x48 }, { 96, 0x49 }, { 104, 0x4A },
> > + { 108, 0x47 }, { 112, 0x4B }, { 120, 0x4C }, { 128, 0x50 },
> > + { 136, 0x80 }, { 144, 0x81 }, { 152, 0x82 }, { 160, 0x83 },
> > + { 168, 0x84 }, { 176, 0x88 }, { 192, 0x89 }, { 208, 0x8A },
> > + { 216, 0x87 }, { 224, 0x8B }, { 240, 0x8C }, { 256, 0x90 },
> > + { 288, 0x91 }, { 320, 0x92 }, { 336, 0x8F }, { 352, 0x93 },
> > + { 384, 0x98 }, { 416, 0x95 }, { 448, 0x99 }, { 480, 0x96 },
> > + { 512, 0x9A }, { 576, 0x9B }, { 640, 0xA0 }, { 704, 0x9D },
> > + { 768, 0xA1 }, { 832, 0x9E }, { 896, 0xA2 }, { 960, 0x67 },
> > + { 1024, 0xA3 }, { 1152, 0xA4 }, { 1280, 0xA8 }, { 1536, 0xA9 },
> > + { 1792, 0xAA }, { 1920, 0xA7 }, { 2048, 0xAB }, { 2304, 0xAC },
> > + { 2560, 0xB0 }, { 3072, 0xB1 }, { 3584, 0xB2 }, { 3840, 0xAF },
> > + { 4096, 0xB3 }, { 4608, 0xB4 }, { 5120, 0xB8 }, { 6144, 0xB9 },
> > + { 7168, 0xBA }, { 7680, 0xB7 }, { 8192, 0xBB }, { 9216, 0xBC },
> > + { 10240, 0xBD }, { 12288, 0xBE }, { 15360, 0xBF }
> > +};
> > +
> > +/*
> > + * I2C divider and hold values when glitch filter is disabled
> > + * taken from table 21-13, LX2160ARM_RevE 01/2020
> > + *
> > + * In case of duplicate SCL Divider value, the IBC value
> > + * with high MUL value has been selected.
> > + * A higher MUL value results in a lower sampling rate of the I2C signals.
> > + * This gives the I2C module greater immunity against glitches in the I2C signals.
> > + */
> > +STATIC I2C_CLOCK_DIVIDER_PAIR I2cClockDividerGlitchDisabled[] = {
>
> Module-scope global variables should have 'm' prefix.
>
> > + { 20, 0x0 },{ 22, 0x1 },{ 24, 0x2 },{ 26, 0x3 },
> > + { 28, 0x8 },{ 30, 0x5 },{ 32, 0x9 },{ 34, 0x6 },
> > + { 36, 0x0A },{ 40, 0x40 },{ 44, 0x41 },{ 48, 0x42 },
> > + { 52, 0x43 },{ 56, 0x48 },{ 60, 0x45 },{ 64, 0x49 },
> > + { 68, 0x46 },{ 72, 0x4A },{ 80, 0x80 },{ 88, 0x81 },
> > + { 96, 0x82 },{ 104, 0x83 },{ 112, 0x88 },{ 120, 0x85 },
> > + { 128, 0x89 },{ 136, 0x86 },{ 144, 0x8A },{ 160, 0x8B },
> > + { 176, 0x8C },{ 192, 0x90 },{ 208, 0x56 },{ 224, 0x91 },
> > + { 240, 0x1F },{ 256, 0x92 },{ 272, 0x8F },{ 288, 0x93 },
> > + { 320, 0x98 },{ 352, 0x95 },{ 384, 0x99 },{ 416, 0x96 },
> > + { 448, 0x9A },{ 480, 0x5F },{ 512, 0x9B },{ 576, 0x9C },
> > + { 640, 0xA0 },{ 768, 0xA1 },{ 896, 0xA2 },{ 960, 0x9F },
> > + { 1024, 0xA3 },{ 1152, 0xA4 },{ 1280, 0xA8 },{ 1536, 0xA9 },
> > + { 1792, 0xAA },{ 1920, 0xA7 },{ 2048, 0xAB },{ 2304, 0xAC },
> > + { 2560, 0xAD },{ 3072, 0xB1 },{ 3584, 0xB2 },{ 3840, 0xAF },
> > + { 4096, 0xB3 },{ 4608, 0xB4 },{ 5120, 0xB8 },{ 6144, 0xB9 },
> > + { 7168, 0xBA },{ 7680, 0xB7 },{ 8192, 0xBB },{ 9216, 0xBC },
> > + { 10240, 0xBD },{ 12288, 0xBE },{ 15360, 0xBF }
> > +};
> > +
> > +/**
> > + ERR009203 : I2C may not work reliably with the default setting
>
> What erratum database does this ID refer to?
> I don't need access to it, but an explanation at the end of the file
> header comment would be helpful.
>
> > +
> > + Description : The clocking circuitry of I2C module may not work reliably due to the slow
> > + rise time of SCL signal.
>
> First line too long (wrap after 'due'). Second line weird indentation.
>
> > + Workaround : Enable the receiver digital filter by setting IBDBG[GLFLT_EN] to 1.
>
> Ideally, wrap this line after 'setting'.
>
> > +*/
> > +STATIC
> > +VOID
> > + I2cErratumA009203 (
>
> No indentation of function name.
> Explanation of where that A prefix of the erratum ID came from would
> also be appreciated.
>
> > + IN UINTN Base
> > + )
> > +{
> > + I2C_REGS *Regs;
> > +
> > + Regs = (I2C_REGS *)Base;
> > +
> > + MmioOr8 ( (UINTN)&Regs->Ibdbg, I2C_IBDBG_GLFLT_EN);
>
> No space before (UINTN).
>
> > +}
> > +
> > +/**
> > + Early init I2C for reading the sysclk from I2c slave device.
> > + I2c bus clock is determined from the clock input to I2c controller.
> > + The clock input to I2c controller is derived from the sysclk.
> > + sysclk is determined by clock generator, which is controller by i2c.
> > +
> > + So, it's a chicken-egg problem to read the sysclk from clock generator.
> > + To break this cycle (i.e. to read the sysclk), we setup the i2c bus clock to
> > + lowest value, in the hope that it won't be out of clock generator's supported
> > + i2c clock frequency. Once we have the correct sysclk, we can setup the correct
> > + i2c bus clock.
> > +
> > + @param[in] Base Base Address of I2c controller's registers
> > +
> > + @return EFI_SUCCESS successfuly setup the i2c bus for reading sysclk
> > +**/
> > +EFI_STATUS
> > +I2cEarlyInitialize (
> > + IN UINTN Base
> > + )
> > +{
> > + I2C_REGS *Regs;
> > + UINT8 Ibc;
>
> This is a CamelCase project.
> "Regs" is clear enough, but Ibc needs to be written out.
> I'm going to guess it stands for i2c bus clock.
>
> Since we're in a function where the name starts with I2c, we don't
> need to be explicit about that. And we don't seem to be having any
> other clocks to keep track of in this - so how about just calling it
> "Clock"?
>
> But then from the way it's used, should is be called MaxClock?
>
> > +
> > + Regs = (I2C_REGS *)Base;
> > + if (FeaturePcdGet (PcdI2cErratumA009203)) {
> > + I2cErratumA009203 (Base);
> > + }
> > +
> > + if (MmioRead8 ( (UINTN)&Regs->Ibdbg) & I2C_IBDBG_GLFLT_EN) {
>
> No space before (UINTN).
> In general, could you do a global search and replace for "( ("?
> I won't mention it again, but since it is used consistently, I expect
> to see much more of it in this set :)
>
> > + Ibc = I2cClockDividerGlitchEnabled[ARRAY_SIZE (I2cClockDividerGlitchEnabled) - 1].Ibc;
> > + } else {
> > + Ibc = I2cClockDividerGlitchDisabled[ARRAY_SIZE (I2cClockDividerGlitchDisabled) - 1].Ibc;
>
> This is way too hard to read.
> Can you add a preprocessor macro for
> X[ARRAY_SIZE (X) - 1] ?
> with a helpful name like ARRAY_LAST_ELEM or something?
>
> > + }
> > +
> > + MmioWrite8 ( (UINTN)&Regs->Ibfd, Ibc);
> > + // Reset Module
> > + MmioOr8 ( (UINTN)&Regs->Ibcr, I2C_IBCR_MDIS);
> > + MmioAnd8 ( (UINTN)&Regs->Ibcr, ~(I2C_IBCR_IBIE | I2C_IBCR_DMAEN));
> > + MmioAnd8 ( (UINTN)&Regs->Ibic, (UINT8)(~I2C_IBIC_BIIE));
> > +
> > + return EFI_SUCCESS;
> > +}
> > +
> > +/**
> > + Configure I2c bus to opearte at a given speed
>
> operate
>
> > +
> > + @param[in] Base Base Address of I2c controller's registers
> > + @param[in] I2cBusClock Input clock to I2c controller
> > + @param[in] Speed speed to be configured for I2c bus
>
> Align comments.
>
> > +**/
> > +EFI_STATUS
> > +I2cInitialize (
> > + IN UINTN Base,
> > + IN UINT64 I2cBusClock,
> > + IN UINT64 Speed
> > + )
> > +{
> > + I2C_REGS *Regs;
> > + UINT16 ClockDivider;
> > + UINT8 Ibc;
> > + I2C_CLOCK_DIVIDER_PAIR *ClockDividerPair;
> > + UINT32 ClockDividerPairSize;
> > + UINT32 Index;
> > +
> > + Regs = (I2C_REGS *)Base;
> > + if (FeaturePcdGet (PcdI2cErratumA009203)) {
> > + I2cErratumA009203 (Base);
> > + }
> > +
> > + Ibc = 0;
> > + ClockDivider = (I2cBusClock + Speed - 1) / Speed;
> > +
> > + if (MmioRead8 ( (UINTN)&Regs->Ibdbg) & I2C_IBDBG_GLFLT_EN) {
> > + ClockDividerPair = I2cClockDividerGlitchEnabled;
> > + ClockDividerPairSize = ARRAY_SIZE (I2cClockDividerGlitchEnabled);
> > + } else {
> > + ClockDividerPair = I2cClockDividerGlitchDisabled;
> > + ClockDividerPairSize = ARRAY_SIZE (I2cClockDividerGlitchDisabled);
> > + }
> > +
> > + if (ClockDivider > ClockDividerPair[ClockDividerPairSize - 1].Divider) {
> > + Ibc = ClockDividerPair[ClockDividerPairSize - 1].Ibc;
> > + } else {
> > + for (Index = 0; Index < ClockDividerPairSize; Index++) {
> > + if (ClockDividerPair[Index].Divider >= ClockDivider) {
> > + Ibc = ClockDividerPair[Index].Ibc;
> > + break;
> > + }
> > + }
> > + }
> > +
> > + MmioWrite8 ( (UINTN)&Regs->Ibfd, Ibc);
> > + // Reset Module
> > + MmioOr8 ( (UINTN)&Regs->Ibcr, I2C_IBCR_MDIS);
> > + MmioAnd8 ( (UINTN)&Regs->Ibcr, ~(I2C_IBCR_IBIE | I2C_IBCR_DMAEN));
> > + MmioAnd8 ( (UINTN)&Regs->Ibic, (UINT8)(~I2C_IBIC_BIIE));
> > +
> > + return EFI_SUCCESS;
> > +}
> > +
> > +STATIC
> > +EFI_STATUS
> > +I2cBusTestBusBusy (
> > + IN I2C_REGS *Regs,
> > + IN BOOLEAN TestBusy
> > + )
> > +{
> > + UINT8 Index;
> > + UINT8 Reg;
> > +
> > + for (Index = 0; Index < 500; Index++) {
>
> What does looping over something 500 times signify?
> Is there a time period we're waiting for or is it just arbitrary?
> If it's just arbitrary, put it in a #define and name it accordingly.
>
> > + Reg = MmioRead8 ( (UINTN)&Regs->Ibsr);
> > +
> > + if (Reg & I2C_IBSR_IBAL) {
> > + MmioWrite8 ( (UINTN)&Regs->Ibsr, Reg);
> > + return EFI_NOT_READY;
> > + }
> > +
> > + if (TestBusy && (Reg & I2C_IBSR_IBB)) {
> > + break;
> > + }
> > +
> > + if (!TestBusy && !(Reg & I2C_IBSR_IBB)) {
> > + break;
> > + }
> > +
> > + MicroSecondDelay (1);
>
> Do we need a delay or do we need a barrier? Or do we need both?
>
> > + }
> > +
> > + if (Index == 500) {
> > + return EFI_TIMEOUT;
> > + } else {
> > + return EFI_SUCCESS;
> > + }
> > +}
> > +
> > +STATIC
> > +EFI_STATUS
> > +I2cTransferComplete (
> > + IN I2C_REGS *Regs,
> > + IN BOOLEAN TestRxAck
> > +)
> > +{
> > + UINT8 Index;
> > + UINT8 Reg;
> > +
> > + for (Index = 0; Index < 500; Index++) {
>
> Same thing.
>
> > + Reg = MmioRead8 ( (UINTN)&Regs->Ibsr);
> > +
> > + if (Reg & I2C_IBSR_IBIF) {
> > + // Write 1 to clear the IBIF field
> > + MmioWrite8 ( (UINTN)&Regs->Ibsr, Reg);
> > + break;
> > + }
> > +
> > + MicroSecondDelay (1);
>
> Do we need a delay or do we need a barrier? Or do we need both?
>
> > + }
> > +
> > + if (Index == 500) {
> > + return EFI_TIMEOUT;
> > + }
> > +
> > + if (TestRxAck && (Reg & I2C_IBSR_RXAK)) {
> > + return EFI_NO_RESPONSE;
> > + }
> > +
> > + if (Reg & I2C_IBSR_TCF) {
> > + return EFI_SUCCESS;
> > + }
> > + return EFI_DEVICE_ERROR;
> > +}
> > +
> > +STATIC
> > +EFI_STATUS
> > +I2cRead (
> > + IN I2C_REGS *Regs,
> > + IN UINT32 SlaveAddress,
> > + IN EFI_I2C_OPERATION *Operation,
> > + IN BOOLEAN IsLastOperation
> > +)
> > +{
> > + EFI_STATUS Status;
> > + UINTN Index;
> > +
> > + // Write Slave Address
> > + MmioWrite8 ( (UINTN)&Regs->Ibdr, (SlaveAddress << BIT0) | BIT0);
> > + Status = I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > + // select Receive mode.
> > + MmioAnd8 ( (UINTN)&Regs->Ibcr, ~I2C_IBCR_TXRX);
> > + // Perform a dummy read to initiate the receive operation.
> > + MmioRead8 ( (UINTN)&Regs->Ibdr);
> > +
> > + for (Index = 0; Index < Operation->LengthInBytes; Index++) {
> > + Status = I2cTransferComplete (Regs, I2C_BUS_NO_TEST_RX_ACK);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > + if (Index == (Operation->LengthInBytes - 2)) {
> > + // Set No ACK = 1
> > + MmioOr8 ( (UINTN)&Regs->Ibcr, I2C_IBCR_NOACK);
> > + } else if (Index == (Operation->LengthInBytes - 1)) {
> > + if (!IsLastOperation) {
> > + // select Transmit mode (for repeat start)
> > + MmioOr8 ( (UINTN)&Regs->Ibcr, I2C_IBCR_TXRX);
> > + } else {
> > + // Generate Stop Signal
> > + MmioAnd8 ( (UINTN)&Regs->Ibcr, ~(I2C_IBCR_MSSL | I2C_IBCR_TXRX));
> > + Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > + }
> > + }
> > + Operation->Buffer[Index] = MmioRead8 ( (UINTN)&Regs->Ibdr);
> > + }
> > +
> > + return EFI_SUCCESS;
> > +}
> > +
> > +STATIC
> > +EFI_STATUS
> > +I2cWrite (
> > + IN I2C_REGS *Regs,
> > + IN UINT32 SlaveAddress,
> > + IN EFI_I2C_OPERATION *Operation
> > +)
> > +{
> > + EFI_STATUS Status;
> > + UINTN Index;
> > +
> > + // Write Slave Address
> > + MmioWrite8 ( (UINTN)&Regs->Ibdr, (SlaveAddress << BIT0) & (UINT8)(~BIT0));
> > + Status = I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > +
> > + // Write Data
> > + for (Index = 0; Index < Operation->LengthInBytes; Index++) {
> > + MmioWrite8 ( (UINTN)&Regs->Ibdr, Operation->Buffer[Index]);
> > + Status = I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > + }
> > + return EFI_SUCCESS;
> > +}
> > +
> > +STATIC
> > +EFI_STATUS
> > +I2cStop (
> > + IN I2C_REGS *Regs
> > + )
> > +{
> > + EFI_STATUS Status;
> > + UINT8 Reg;
> > +
> > + Reg = MmioRead8 ( (UINTN)&Regs->Ibsr);
> > + if (Reg & I2C_IBSR_IBB) {
> > + // Generate Stop Signal
> > + MmioAnd8 ( (UINTN)&Regs->Ibcr, ~(I2C_IBCR_MSSL | I2C_IBCR_TXRX));
> > + Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > + }
> > +
> > + // Disable I2c Controller
> > + MmioOr8 ( (UINTN)&Regs->Ibcr, I2C_IBCR_MDIS);
> > +
> > + return Status;
> > +}
> > +
> > +STATIC
> > +EFI_STATUS
> > +I2cStart (
> > + IN I2C_REGS *Regs
> > + )
> > +{
> > + EFI_STATUS Status;
> > +
> > + MmioOr8 ( (UINTN)&Regs->Ibsr, (I2C_IBSR_IBAL | I2C_IBSR_IBIF));
> > + MmioAnd8 ( (UINTN)&Regs->Ibcr, (UINT8)(~I2C_IBCR_MDIS));
> > +
> > + // Generate Start Signal
> > + MmioOr8 ( (UINTN)&Regs->Ibcr, I2C_IBCR_MSSL);
> > + Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_BUSY);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > + MmioOr8 ( (UINTN)&Regs->Ibcr, I2C_IBCR_TXRX | I2C_IBCR_NOACK);
> > + return Status;
> > +}
> > +
> > +/**
> > + Transfer data to/from I2c slave device
> > +
> > + @param[in] Base Base Address of I2c controller's registers
> > + @param[in] SlaveAddress Slave Address from which data is to be read
> > + @param[in] RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET structure
> > + describing the I2C transaction
> > +
> > + @return EFI_SUCCESS successfuly setup the i2c bus for reading sysclk
> > + @return EFI_DEVICE_ERROR There was an error while transferring data through I2c bus
> > + @return EFI_NO_RESPONSE There was no Ack from i2c device
> > + @return EFI_TIMEOUT I2c Bus is busy
> > + @return EFI_NOT_READY I2c Bus Arbitration lost
> > +**/
> > +EFI_STATUS
> > +I2cBusXfer (
> > + IN UINTN Base,
> > + IN UINT32 SlaveAddress,
> > + IN EFI_I2C_REQUEST_PACKET *RequestPacket
> > + )
> > +{
> > + UINTN Index;
> > + I2C_REGS *Regs;
> > + EFI_I2C_OPERATION *Operation;
> > + EFI_STATUS Status;
> > + BOOLEAN IsLastOperation;
> > +
> > + Regs = (I2C_REGS *)Base;
> > + IsLastOperation = FALSE;
> > +
> > + Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE);
> > + if (EFI_ERROR (Status)) {
> > + goto ErrorExit;
> > + }
> > +
> > + Status = I2cStart (Regs);
> > + if (EFI_ERROR (Status)) {
> > + goto ErrorExit;
> > + }
> > +
> > + for (Index = 0, Operation = RequestPacket->Operation;
> > + Index < RequestPacket->OperationCount;
> > + Index++, Operation++) {
> > + if (Index == (RequestPacket->OperationCount - 1)) {
> > + IsLastOperation = TRUE;
> > + }
> > + // Send repeat start after first transmit/recieve
> > + if (Index) {
> > + MmioOr8 ( (UINTN)&Regs->Ibcr, I2C_IBCR_RSTA);
> > + Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_BUSY);
> > + if (EFI_ERROR (Status)) {
> > + goto ErrorExit;
> > + }
> > + }
> > + // Read/write data
> > + if (Operation->Flags & I2C_FLAG_READ) {
> > + Status = I2cRead (Regs, SlaveAddress, Operation, IsLastOperation);
> > + } else {
> > + Status = I2cWrite (Regs, SlaveAddress, Operation);
> > + }
> > + if (EFI_ERROR (Status)) {
> > + goto ErrorExit;
> > + }
> > + }
> > +
> > +ErrorExit:
> > +
> > + I2cStop (Regs);
> > +
> > + return Status;
> > +}
> > +
> > +/**
> > + Read a register from I2c slave device. This API is wrapper around I2cBusXfer
> > +
> > + @param[in] Base Base Address of I2c controller's registers
> > + @param[in] SlaveAddress Slave Address from which register value is to be read
> > + @param[in] RegAddress Register Address in Slave's memory map
> > + @param[in] RegAddressWidthInBytes Number of bytes in RegAddress to send to I2c Slave
> > + for simple reads without any register, make this value = 0
> > + (RegAddress is don't care in that case)
> > + @param[out] RegValue Value to be read from I2c slave's regiser
> > + @param[in] RegValueNumBytes Number of bytes to read from I2c slave register
> > +
> > + @return EFI_SUCCESS successfuly setup the i2c bus for reading sysclk
> > + @return EFI_DEVICE_ERROR There was an error while transferring data through I2c bus
> > + @return EFI_NO_RESPONSE There was no Ack from i2c device
> > + @return EFI_TIMEOUT I2c Bus is busy
> > + @return EFI_NOT_READY I2c Bus Arbitration lost
>
> Align comments. And try to keep line lengths no longer than 80 characters.
>
> > +**/
> > +EFI_STATUS
> > +I2cBusReadReg (
> > + IN UINTN Base,
> > + IN UINT32 SlaveAddress,
> > + IN UINT64 RegAddress,
> > + IN UINT8 RegAddressWidthInBytes,
> > + OUT UINT8 *RegValue,
> > + IN UINT8 RegValueNumBytes
> > + )
> > +{
> > + EFI_I2C_OPERATION *Operations;
> > + I2C_REG_REQUEST RequestPacket;
> > + UINTN OperationCount;
> > + UINT8 Address[8];
>
> Create a well named #define for that 8.
>
> > + UINT8 *Ptr;
>
> The name Ptr does not convey information.
> Give it a name that describes what it points to.
>
> > + EFI_STATUS Status;
> > +
> > + ZeroMem (&RequestPacket, sizeof (RequestPacket));
> > + OperationCount = 0;
> > + Operations = RequestPacket.Operation;
> > + Ptr = Address;
> > +
> > + if (RegAddressWidthInBytes > ARRAY_SIZE (Address)) {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + if (RegAddressWidthInBytes != 0) {
> > + Operations[OperationCount].LengthInBytes = RegAddressWidthInBytes;
> > + Operations[OperationCount].Buffer = Ptr;
> > + while (RegAddressWidthInBytes--) {
> > + *Ptr++ = RegAddress >> (8 * RegAddressWidthInBytes);
> > + }
> > + OperationCount++;
> > + }
> > +
> > + Operations[OperationCount].LengthInBytes = RegValueNumBytes;
> > + Operations[OperationCount].Buffer = RegValue;
> > + Operations[OperationCount].Flags = I2C_FLAG_READ;
> > + OperationCount++;
> > +
> > + RequestPacket.OperationCount = OperationCount;
> > +
> > + Status = I2cBusXfer (Base, SlaveAddress, (EFI_I2C_REQUEST_PACKET *)&RequestPacket);
> > +
> > + return Status;
> > +}
> > +
> > diff --git a/Silicon/NXP/Library/I2cLib/I2cLib.inf b/Silicon/NXP/Library/I2cLib/I2cLib.inf
> > new file mode 100644
> > index 0000000000..9c8aae100b
> > --- /dev/null
> > +++ b/Silicon/NXP/Library/I2cLib/I2cLib.inf
> > @@ -0,0 +1,30 @@
> > +#/** @file
> > +#
> > +# Copyright 2020 NXP
> > +#
> > +# SPDX-License-Identifier: BSD-2-Clause
> > +#
> > +#**/
> > +
> > +[Defines]
> > + INF_VERSION = 1.27
> > + BASE_NAME = I2cLib
> > + FILE_GUID = f22393b1-98b6-4067-9ec2-6aa436321f03
> > + MODULE_TYPE = BASE
> > + VERSION_STRING = 1.0
> > + LIBRARY_CLASS = I2cLib
> > +
> > +[Packages]
> > + MdePkg/MdePkg.dec
> > + Silicon/NXP/NxpQoriqLs.dec
> > +
> > +[LibraryClasses]
> > + TimerLib
> > + IoLib
>
> Please sort library classes alphabetically.
>
> > +
> > +[Sources.common]
> > + I2cLib.c
> > +
> > +[FeaturePcd]
> > + gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203
> > +
> > diff --git a/Silicon/NXP/Library/I2cLib/I2cLibInternal.h b/Silicon/NXP/Library/I2cLib/I2cLibInternal.h
> > new file mode 100644
> > index 0000000000..14be9cb740
> > --- /dev/null
> > +++ b/Silicon/NXP/Library/I2cLib/I2cLibInternal.h
> > @@ -0,0 +1,95 @@
> > +/** @file
> > + I2c Lib to control I2c controller.
> > +
> > + Copyright 2020 NXP
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +
> > +#ifndef __I2C_LIB_INTERNAL_H__
> > +#define __I2C_LIB_INTERNAL_H__
>
> Please drop leading __ in header guards.
>
> > +
> > +#include <Pi/PiI2c.h>
> > +#include <Uefi.h>
> > +
> > +/* Module Disable
> > + * 0b - The module is enabled. You must clear this field before any other IBCR fields have any effect.
> > + * 1b - The module is reset and disabled. This is the power-on reset situation. When high, the
> > + * interface is held in reset, but registers can still be accessed. Status register fields (IBSR) are not
> > + * valid when the module is disabled.
>
> Please re-wrap lines at 80 characters throughout this file.
> ^
>
> > + */
> > +#define I2C_IBCR_MDIS BIT7
> > +// I2c Bus Interrupt Enable
> > +#define I2C_IBCR_IBIE BIT6
> > +/* Master / Slave Mode 0b - Slave mode 1b - Master mode
> > + * When you change this field from 0 to 1, the module generates a START signal on the bus and selects the
> > + * master mode. When you change this field from 1 to 0, the module generates a STOP signal and changes
> > + * the operation mode from master to slave. You should generate a STOP signal only if IBSR[IBIF]=1. The
> > + * module clears this field without generating a STOP signal when the master loses arbitration.
> > +*/
> > +#define I2C_IBCR_MSSL BIT5
> > +// 0b - Receive 1b - Transmit
> > +#define I2C_IBCR_TXRX BIT4
> > +/* Data acknowledge disable
> > + * Values written to this field are only used when the I2C module is a receiver, not a transmitter.
> > + * 0b - The module sends an acknowledge signal to the bus at the 9th clock bit after receiving one
> > + * byte of data.
> > + * 1b - The module does not send an acknowledge-signal response (that is, acknowledge bit = 1).
> > + */
> > +#define I2C_IBCR_NOACK BIT3
> > +/* Repeat START
> > + * If the I2C module is the current bus master, and you program RSTA=1, the I2C module generates a
> > + * repeated START condition. This field always reads as a 0. If you attempt a repeated START at the wrong
> > + * time—if the bus is owned by another master—the result is loss of arbitration.
> > + */
> > +#define I2C_IBCR_RSTA BIT2
> > +// DMA enable
> > +#define I2C_IBCR_DMAEN BIT1
> > +
> > +// Transfer Complete
> > +#define I2C_IBSR_TCF BIT7
> > +// I2C bus Busy. 0b - Bus is idle, 1b - Bus is busy
> > +#define I2C_IBSR_IBB BIT5
> > +// Arbitration Lost. software must clear this field by writing a one to it.
> > +#define I2C_IBSR_IBAL BIT4
> > +// I2C bus interrupt flag
> > +#define I2C_IBSR_IBIF BIT1
> > +// Received acknowledge 0b - Acknowledge received 1b - No acknowledge received
> > +#define I2C_IBSR_RXAK BIT0
> > +
> > +//Bus idle interrupt enable
> > +#define I2C_IBIC_BIIE BIT7
> > +
> > +// Glitch filter enable
> > +#define I2C_IBDBG_GLFLT_EN BIT3
> > +
> > +#define I2C_BUS_TEST_BUSY TRUE
> > +#define I2C_BUS_TEST_IDLE !I2C_BUS_TEST_BUSY
> > +#define I2C_BUS_TEST_RX_ACK TRUE
> > +#define I2C_BUS_NO_TEST_RX_ACK !I2C_BUS_TEST_RX_ACK
> > +
> > +typedef struct _I2C_REGS {
> > + UINT8 Ibad; // I2c Bus Address Register
> > + UINT8 Ibfd; // I2c Bus Frequency Dividor Register
> > + UINT8 Ibcr; // I2c Bus Control Register
> > + UINT8 Ibsr; // I2c Bus Status Register
> > + UINT8 Ibdr; // I2C Bus Data I/O Register
> > + UINT8 Ibic; // I2C Bus Interrupt Config Register
> > + UINT8 Ibdbg; // I2C Bus Debug Register
> > +} I2C_REGS;
> > +
> > +/*
> > + * sorted list of clock divider, register value pairs
> > + */
> > +typedef struct _I2C_CLOCK_DIVIDER_PAIR {
> > + UINT16 Divider;
> > + UINT16 Ibc;
>
> CamelCase - please expand Ibc.
>
> /
> Leif
>
> > +} I2C_CLOCK_DIVIDER_PAIR;
> > +
> > +typedef struct {
> > + UINTN OperationCount;
> > + EFI_I2C_OPERATION Operation[2];
> > +} I2C_REG_REQUEST;
> > +
> > +#endif // __I2C_LIB_INTERNAL_H__
> > +
> > diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> > index 764b9bb0e2..4a1cfb3e27 100644
> > --- a/Silicon/NXP/NxpQoriqLs.dec
> > +++ b/Silicon/NXP/NxpQoriqLs.dec
> > @@ -1,6 +1,6 @@
> > # @file.
> > #
> > -# Copyright 2017-2019 NXP
> > +# Copyright 2017-2020 NXP
> > #
> > # SPDX-License-Identifier: BSD-2-Clause-Patent
> > #
> > @@ -13,6 +13,10 @@
> > [Includes]
> > Include
> >
> > +[LibraryClasses]
> > + ## @libraryclass Provides services to read/write to I2c devices
> > + I2cLib|Include/Library/I2cLib.h
> > +
> > [Guids.common]
> > gNxpQoriqLsTokenSpaceGuid = {0x98657342, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
> > gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
> > @@ -101,3 +105,7 @@
> > gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000312
> > gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|FALSE|BOOLEAN|0x00000313
> > gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314
> > +
> > +[PcdsFeatureFlag]
> > + gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315
> > +
> > --
> > 2.17.1
> >
>
>
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 04/19] Silicon/NXP: Remove DuartLib and use BaseSerialPortLib16550
2020-02-08 17:46 ` Leif Lindholm
@ 2020-02-10 5:48 ` Pankaj Bansal
2020-02-12 23:27 ` Leif Lindholm
0 siblings, 1 reply; 49+ messages in thread
From: Pankaj Bansal @ 2020-02-10 5:48 UTC (permalink / raw)
To: Leif Lindholm
Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi,
devel@edk2.groups.io
> -----Original Message-----
> From: Leif Lindholm <leif@nuviainc.com>
> Sent: Saturday, February 8, 2020 11:16 PM
> To: Pankaj Bansal <pankaj.bansal@nxp.com>
> Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney
> <michael.d.kinney@intel.com>; Varun Sethi <V.Sethi@nxp.com>;
> devel@edk2.groups.io
> Subject: Re: [PATCH 04/19] Silicon/NXP: Remove DuartLib and use
> BaseSerialPortLib16550
>
> On Fri, Feb 07, 2020 at 18:13:13 +0530, Pankaj Bansal wrote:
> > UART in LS1043A conforms to ns16550 register set. so we can use the
> > SerialPortLib16550 from MdeModulePkg.
>
> 1) This patch adds a new library and deletes an existing one - those
> are two operationsand hence should be two patches.
OK. I can split the patch in two
>
> 2) That is irrelevant, because if you can use BaseSerialPortLib16550,
> then use BaseSerialPortLib16550. Copying an existing library in
> order to make some minor tweaks is not an option.
If you look at the [PATCH 05/19] NXP/BaseSerialPortLib16550: remove SerialPortInitalize functionality
(https://edk2.groups.io/g/devel/message/54011?p=,,,20,0,0,0::Created,,BaseSerialPortLib16550,20,2,0,71046325)
I have removed SerialPortInitalize functionality, which I am guessing would not work for each platform using BaseSerialPortLib16550
Which is why I have forked the BaseSerialPortLib16550 for NXP platforms.
>
> > We have removed the PCIe specific part from the library and also added
> > the APIs to get the UART clock from SOC lib instead of using the fixed
> > PCD.
>
> So, what you need to do is update BaseSerialPortLib16550 to be usable
> for you. This library is already used by several ARM platforms that
> don't actually implement PCIe.
Again, I can do that In the similar way we have done for PL011 (https://github.com/tianocore/edk2/commit/cbba5ca104fbc8baa0c613951e833e1a07bb34df)
But as I stated above, this is an unnecessary overhead which increases code size as well as execution time.
Both of which we want to avoid.
That is why we have forked BaseSerialPortLib16550 (and even PL011SerialPortLib for that matter for LX2160A) for NXP platforms.
>
> > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> > ---
> > Silicon/NXP/LS1043A/LS1043A.dsc.inc | 2 +-
> > .../BaseSerialPortLib16550.c | 804 ++++++++++++++++++
> > .../BaseSerialPortLib16550.inf | 39 +
> > .../BaseSerialPortLib16550.uni | 17 +
>
> Please don't leave out the --stat and --stat-graph-width when
> following the format-patch instructions at
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.co
> m%2Ftianocore%2Ftianocore.github.io%2Fwiki%2FLaszlo%2527s-unkempt-git-
> guide-for-edk2-contributors-and-
> maintainers&data=02%7C01%7Cpankaj.bansal%40nxp.com%7C696ddff166
> 5a4367502608d7acbed0e8%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C
> 0%7C637167807871085424&sdata=8tHGzseG00MNL1Hc62fFIxKGqcl0quW
> Rq%2Bc9W%2BQRFRU%3D&reserved=0
>
> /
> Leif
>
> > Silicon/NXP/Library/DUartPortLib/DUart.h | 122 ---
> > .../NXP/Library/DUartPortLib/DUartPortLib.c | 364 --------
> > .../NXP/Library/DUartPortLib/DUartPortLib.inf | 34 -
> > 7 files changed, 861 insertions(+), 521 deletions(-)
> > create mode 100644
> Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> > create mode 100644
> Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
> > create mode 100644
> Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.uni
> > delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUart.h
> > delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
> > delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> >
> > diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > index 8790db6ff8..754eff396a 100644
> > --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > @@ -9,7 +9,7 @@
> >
> > [LibraryClasses.common]
> > SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > - SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> > +
> SerialPortLib|Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib165
> 50.inf
> >
> >
> #################################################################
> ###############
> > #
> > diff --git
> a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> > new file mode 100644
> > index 0000000000..2c5c54ac7d
> > --- /dev/null
> > +++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> > @@ -0,0 +1,804 @@
> > +/** @file
> > + 16550 UART Serial Port library functions
> > +
> > + (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>
> > + Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> > + Copyright (c) 2018, AMD Incorporated. All rights reserved.<BR>
> > + Copyright 2020 NXP
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +
> > +#include <Base.h>
> > +#include <Library/SerialPortLib.h>
> > +#include <Library/PcdLib.h>
> > +#include <Library/IoLib.h>
> > +#include <Library/BaseLib.h>
> > +
> > +//
> > +// 16550 UART register offsets and bitfields
> > +//
> > +#define R_UART_RXBUF 0 // LCR_DLAB = 0
> > +#define R_UART_TXBUF 0 // LCR_DLAB = 0
> > +#define R_UART_BAUD_LOW 0 // LCR_DLAB = 1
> > +#define R_UART_BAUD_HIGH 1 // LCR_DLAB = 1
> > +#define R_UART_IER 1 // LCR_DLAB = 0
> > +#define R_UART_FCR 2
> > +#define B_UART_FCR_FIFOE BIT0
> > +#define B_UART_FCR_FIFO64 BIT5
> > +#define R_UART_LCR 3
> > +#define B_UART_LCR_DLAB BIT7
> > +#define R_UART_MCR 4
> > +#define B_UART_MCR_DTRC BIT0
> > +#define B_UART_MCR_RTS BIT1
> > +#define R_UART_LSR 5
> > +#define B_UART_LSR_RXRDY BIT0
> > +#define B_UART_LSR_TXRDY BIT5
> > +#define B_UART_LSR_TEMT BIT6
> > +#define R_UART_MSR 6
> > +#define B_UART_MSR_CTS BIT4
> > +#define B_UART_MSR_DSR BIT5
> > +#define B_UART_MSR_RI BIT6
> > +#define B_UART_MSR_DCD BIT7
> > +
> > +extern
> > +UINT64
> > +GetBusFrequency (
> > + VOID
> > + );
> > +
> > +/**
> > + Read an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is
> read from
> > + MMIO space. If PcdSerialUseMmio is FALSE, then the value is read from I/O
> space. The
> > + parameter Offset is added to the base address of the 16550 registers that is
> specified
> > + by PcdSerialRegisterBase. PcdSerialRegisterAccessWidth specifies the MMIO
> space access
> > + width and defaults to 8 bit access, and supports 8 or 32 bit access.
> > +
> > + @param Base The base address register of UART device.
> > + @param Offset The offset of the 16550 register to read.
> > +
> > + @return The value read from the 16550 register.
> > +
> > +**/
> > +UINT8
> > +SerialPortReadRegister (
> > + UINTN Base,
> > + UINTN Offset
> > + )
> > +{
> > + return MmioRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride));
> > +}
> > +
> > +/**
> > + Write an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value
> is written to
> > + MMIO space. If PcdSerialUseMmio is FALSE, then the value is written to I/O
> space. The
> > + parameter Offset is added to the base address of the 16550 registers that is
> specified
> > + by PcdSerialRegisterBase. PcdSerialRegisterAccessWidth specifies the MMIO
> space access
> > + width and defaults to 8 bit access, and supports 8 or 32 bit access.
> > +
> > + @param Base The base address register of UART device.
> > + @param Offset The offset of the 16550 register to write.
> > + @param Value The value to write to the 16550 register specified by Offset.
> > +
> > + @return The value written to the 16550 register.
> > +
> > +**/
> > +UINT8
> > +SerialPortWriteRegister (
> > + UINTN Base,
> > + UINTN Offset,
> > + UINT8 Value
> > + )
> > +{
> > + return MmioWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride),
> Value);
> > +}
> > +
> > +/**
> > + Retrieve the I/O or MMIO base address register for the PCI UART device.
> > +
> > + This function assumes Root Bus Numer is Zero, and enables I/O and MMIO
> in PCI UART
> > + Device if they are not already enabled.
> > +
> > + @return The base address register of the UART device.
> > +
> > +**/
> > +UINTN
> > +GetSerialRegisterBase (
> > + VOID
> > + )
> > +{
> > + return (UINTN)PcdGet64 (PcdSerialRegisterBase);
> > +}
> > +
> > +/**
> > + Return whether the hardware flow control signal allows writing.
> > +
> > + @param SerialRegisterBase The base address register of UART device.
> > +
> > + @retval TRUE The serial port is writable.
> > + @retval FALSE The serial port is not writable.
> > +**/
> > +BOOLEAN
> > +SerialPortWritable (
> > + UINTN SerialRegisterBase
> > + )
> > +{
> > + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
> > + if (PcdGetBool (PcdSerialDetectCable)) {
> > + //
> > + // Wait for both DSR and CTS to be set
> > + // DSR is set if a cable is connected.
> > + // CTS is set if it is ok to transmit data
> > + //
> > + // DSR CTS Description Action
> > + // === === ======================================== ========
> > + // 0 0 No cable connected. Wait
> > + // 0 1 No cable connected. Wait
> > + // 1 0 Cable connected, but not clear to send. Wait
> > + // 1 1 Cable connected, and clear to send. Transmit
> > + //
> > + return (BOOLEAN) ((SerialPortReadRegister (SerialRegisterBase,
> R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) ==
> (B_UART_MSR_DSR | B_UART_MSR_CTS));
> > + } else {
> > + //
> > + // Wait for both DSR and CTS to be set OR for DSR to be clear.
> > + // DSR is set if a cable is connected.
> > + // CTS is set if it is ok to transmit data
> > + //
> > + // DSR CTS Description Action
> > + // === === ======================================== ========
> > + // 0 0 No cable connected. Transmit
> > + // 0 1 No cable connected. Transmit
> > + // 1 0 Cable connected, but not clear to send. Wait
> > + // 1 1 Cable connected, and clar to send. Transmit
> > + //
> > + return (BOOLEAN) ((SerialPortReadRegister (SerialRegisterBase,
> R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) !=
> (B_UART_MSR_DSR));
> > + }
> > + }
> > +
> > + return TRUE;
> > +}
> > +
> > +/**
> > + Initialize the serial device hardware.
> > +
> > + If no initialization is required, then return RETURN_SUCCESS.
> > + If the serial device was successfully initialized, then return
> RETURN_SUCCESS.
> > + If the serial device could not be initialized, then return
> RETURN_DEVICE_ERROR.
> > +
> > + @retval RETURN_SUCCESS The serial device was initialized.
> > + @retval RETURN_DEVICE_ERROR The serial device could not be initialized.
> > +
> > +**/
> > +RETURN_STATUS
> > +EFIAPI
> > +SerialPortInitialize (
> > + VOID
> > + )
> > +{
> > + UINTN SerialRegisterBase;
> > + UINT32 Divisor;
> > + UINT32 CurrentDivisor;
> > + BOOLEAN Initialized;
> > + UINT64 SerialClock;
> > +
> > + //
> > + // Perform platform specific initialization required to enable use of the
> 16550 device
> > + // at the location specified by PcdSerialUseMmio and PcdSerialRegisterBase.
> > + //
> > + SerialClock = GetBusFrequency ();
> > + if (SerialClock == 0) {
> > + return EFI_DEVICE_ERROR;
> > + }
> > +
> > + //
> > + // Calculate divisor for baud generator
> > + // Ref_Clk_Rate / Baud_Rate / 16
> > + //
> > + Divisor = SerialClock / (PcdGet32 (PcdSerialBaudRate) * 16);
> > + if ((SerialClock % (PcdGet32 (PcdSerialBaudRate) * 16)) >= PcdGet32
> (PcdSerialBaudRate) * 8) {
> > + Divisor++;
> > + }
> > +
> > + //
> > + // Get the base address of the serial port in either I/O or MMIO space
> > + //
> > + SerialRegisterBase = GetSerialRegisterBase ();
> > + if (SerialRegisterBase == 0) {
> > + return RETURN_DEVICE_ERROR;
> > + }
> > +
> > + //
> > + // See if the serial port is already initialized
> > + //
> > + Initialized = TRUE;
> > + if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & 0x3F) !=
> (PcdGet8 (PcdSerialLineControl) & 0x3F)) {
> > + Initialized = FALSE;
> > + }
> > + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR,
> (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) |
> B_UART_LCR_DLAB));
> > + CurrentDivisor = SerialPortReadRegister (SerialRegisterBase,
> R_UART_BAUD_HIGH) << 8;
> > + CurrentDivisor |= (UINT32) SerialPortReadRegister (SerialRegisterBase,
> R_UART_BAUD_LOW);
> > + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR,
> (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) &
> ~B_UART_LCR_DLAB));
> > + if (CurrentDivisor != Divisor) {
> > + Initialized = FALSE;
> > + }
> > + if (Initialized) {
> > + return RETURN_SUCCESS;
> > + }
> > +
> > + //
> > + // Wait for the serial port to be ready.
> > + // Verify that both the transmit FIFO and the shift register are empty.
> > + //
> > + while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) &
> (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT |
> B_UART_LSR_TXRDY));
> > +
> > + //
> > + // Configure baud rate
> > + //
> > + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR,
> B_UART_LCR_DLAB);
> > + SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_HIGH, (UINT8)
> (Divisor >> 8));
> > + SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_LOW, (UINT8)
> (Divisor & 0xff));
> > +
> > + //
> > + // Clear DLAB and configure Data Bits, Parity, and Stop Bits.
> > + // Strip reserved bits from PcdSerialLineControl
> > + //
> > + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(PcdGet8
> (PcdSerialLineControl) & 0x3F));
> > +
> > + //
> > + // Enable and reset FIFOs
> > + // Strip reserved bits from PcdSerialFifoControl
> > + //
> > + SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, 0x00);
> > + SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8
> (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64)));
> > +
> > + //
> > + // Set FIFO Polled Mode by clearing IER after setting FCR
> > + //
> > + SerialPortWriteRegister (SerialRegisterBase, R_UART_IER, 0x00);
> > +
> > + //
> > + // Put Modem Control Register(MCR) into its reset state of 0x00.
> > + //
> > + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00);
> > +
> > + return RETURN_SUCCESS;
> > +}
> > +
> > +/**
> > + Write data from buffer to serial device.
> > +
> > + Writes NumberOfBytes data bytes from Buffer to the serial device.
> > + The number of bytes actually written to the serial device is returned.
> > + If the return value is less than NumberOfBytes, then the write operation
> failed.
> > +
> > + If Buffer is NULL, then ASSERT().
> > +
> > + If NumberOfBytes is zero, then return 0.
> > +
> > + @param Buffer Pointer to the data buffer to be written.
> > + @param NumberOfBytes Number of bytes to written to the serial device.
> > +
> > + @retval 0 NumberOfBytes is 0.
> > + @retval >0 The number of bytes written to the serial device.
> > + If this value is less than NumberOfBytes, then the write
> operation failed.
> > +
> > +**/
> > +UINTN
> > +EFIAPI
> > +SerialPortWrite (
> > + IN UINT8 *Buffer,
> > + IN UINTN NumberOfBytes
> > + )
> > +{
> > + UINTN SerialRegisterBase;
> > + UINTN Result;
> > + UINTN Index;
> > + UINTN FifoSize;
> > +
> > + if (Buffer == NULL) {
> > + return 0;
> > + }
> > +
> > + SerialRegisterBase = GetSerialRegisterBase ();
> > + if (SerialRegisterBase ==0) {
> > + return 0;
> > + }
> > +
> > + if (NumberOfBytes == 0) {
> > + //
> > + // Flush the hardware
> > + //
> > +
> > + //
> > + // Wait for both the transmit FIFO and shift register empty.
> > + //
> > + while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) &
> (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT |
> B_UART_LSR_TXRDY));
> > +
> > + //
> > + // Wait for the hardware flow control signal
> > + //
> > + while (!SerialPortWritable (SerialRegisterBase));
> > + return 0;
> > + }
> > +
> > + //
> > + // Compute the maximum size of the Tx FIFO
> > + //
> > + FifoSize = 1;
> > + if ((PcdGet8 (PcdSerialFifoControl) & B_UART_FCR_FIFOE) != 0) {
> > + if ((PcdGet8 (PcdSerialFifoControl) & B_UART_FCR_FIFO64) == 0) {
> > + FifoSize = 16;
> > + } else {
> > + FifoSize = PcdGet32 (PcdSerialExtendedTxFifoSize);
> > + }
> > + }
> > +
> > + Result = NumberOfBytes;
> > + while (NumberOfBytes != 0) {
> > + //
> > + // Wait for the serial port to be ready, to make sure both the transmit FIFO
> > + // and shift register empty.
> > + //
> > + while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) &
> (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT |
> B_UART_LSR_TXRDY));
> > +
> > + //
> > + // Fill then entire Tx FIFO
> > + //
> > + for (Index = 0; Index < FifoSize && NumberOfBytes != 0; Index++,
> NumberOfBytes--, Buffer++) {
> > + //
> > + // Wait for the hardware flow control signal
> > + //
> > + while (!SerialPortWritable (SerialRegisterBase));
> > +
> > + //
> > + // Write byte to the transmit buffer.
> > + //
> > + SerialPortWriteRegister (SerialRegisterBase, R_UART_TXBUF, *Buffer);
> > + }
> > + }
> > + return Result;
> > +}
> > +
> > +/**
> > + Reads data from a serial device into a buffer.
> > +
> > + @param Buffer Pointer to the data buffer to store the data read from
> the serial device.
> > + @param NumberOfBytes Number of bytes to read from the serial device.
> > +
> > + @retval 0 NumberOfBytes is 0.
> > + @retval >0 The number of bytes read from the serial device.
> > + If this value is less than NumberOfBytes, then the read
> operation failed.
> > +
> > +**/
> > +UINTN
> > +EFIAPI
> > +SerialPortRead (
> > + OUT UINT8 *Buffer,
> > + IN UINTN NumberOfBytes
> > + )
> > +{
> > + UINTN SerialRegisterBase;
> > + UINTN Result;
> > + UINT8 Mcr;
> > +
> > + if (NULL == Buffer) {
> > + return 0;
> > + }
> > +
> > + SerialRegisterBase = GetSerialRegisterBase ();
> > + if (SerialRegisterBase ==0) {
> > + return 0;
> > + }
> > +
> > + Mcr = (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) &
> ~B_UART_MCR_RTS);
> > +
> > + for (Result = 0; NumberOfBytes-- != 0; Result++, Buffer++) {
> > + //
> > + // Wait for the serial port to have some data.
> > + //
> > + while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) &
> B_UART_LSR_RXRDY) == 0) {
> > + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
> > + //
> > + // Set RTS to let the peer send some data
> > + //
> > + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(Mcr
> | B_UART_MCR_RTS));
> > + }
> > + }
> > + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
> > + //
> > + // Clear RTS to prevent peer from sending data
> > + //
> > + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, Mcr);
> > + }
> > +
> > + //
> > + // Read byte from the receive buffer.
> > + //
> > + *Buffer = SerialPortReadRegister (SerialRegisterBase, R_UART_RXBUF);
> > + }
> > +
> > + return Result;
> > +}
> > +
> > +
> > +/**
> > + Polls a serial device to see if there is any data waiting to be read.
> > +
> > + Polls aserial device to see if there is any data waiting to be read.
> > + If there is data waiting to be read from the serial device, then TRUE is
> returned.
> > + If there is no data waiting to be read from the serial device, then FALSE is
> returned.
> > +
> > + @retval TRUE Data is waiting to be read from the serial device.
> > + @retval FALSE There is no data waiting to be read from the serial
> device.
> > +
> > +**/
> > +BOOLEAN
> > +EFIAPI
> > +SerialPortPoll (
> > + VOID
> > + )
> > +{
> > + UINTN SerialRegisterBase;
> > +
> > + SerialRegisterBase = GetSerialRegisterBase ();
> > + if (SerialRegisterBase ==0) {
> > + return FALSE;
> > + }
> > +
> > + //
> > + // Read the serial port status
> > + //
> > + if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) &
> B_UART_LSR_RXRDY) != 0) {
> > + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
> > + //
> > + // Clear RTS to prevent peer from sending data
> > + //
> > + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR,
> (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) &
> ~B_UART_MCR_RTS));
> > + }
> > + return TRUE;
> > + }
> > +
> > + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
> > + //
> > + // Set RTS to let the peer send some data
> > + //
> > + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR,
> (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) |
> B_UART_MCR_RTS));
> > + }
> > +
> > + return FALSE;
> > +}
> > +
> > +/**
> > + Sets the control bits on a serial device.
> > +
> > + @param Control Sets the bits of Control that are settable.
> > +
> > + @retval RETURN_SUCCESS The new control bits were set on the serial
> device.
> > + @retval RETURN_UNSUPPORTED The serial device does not support this
> operation.
> > + @retval RETURN_DEVICE_ERROR The serial device is not functioning
> correctly.
> > +
> > +**/
> > +RETURN_STATUS
> > +EFIAPI
> > +SerialPortSetControl (
> > + IN UINT32 Control
> > + )
> > +{
> > + UINTN SerialRegisterBase;
> > + UINT8 Mcr;
> > +
> > + //
> > + // First determine the parameter is invalid.
> > + //
> > + if ((Control & (~(EFI_SERIAL_REQUEST_TO_SEND |
> EFI_SERIAL_DATA_TERMINAL_READY |
> > + EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE))) != 0) {
> > + return RETURN_UNSUPPORTED;
> > + }
> > +
> > + SerialRegisterBase = GetSerialRegisterBase ();
> > + if (SerialRegisterBase ==0) {
> > + return RETURN_UNSUPPORTED;
> > + }
> > +
> > + //
> > + // Read the Modem Control Register.
> > + //
> > + Mcr = SerialPortReadRegister (SerialRegisterBase, R_UART_MCR);
> > + Mcr &= (~(B_UART_MCR_DTRC | B_UART_MCR_RTS));
> > +
> > + if ((Control & EFI_SERIAL_DATA_TERMINAL_READY) ==
> EFI_SERIAL_DATA_TERMINAL_READY) {
> > + Mcr |= B_UART_MCR_DTRC;
> > + }
> > +
> > + if ((Control & EFI_SERIAL_REQUEST_TO_SEND) ==
> EFI_SERIAL_REQUEST_TO_SEND) {
> > + Mcr |= B_UART_MCR_RTS;
> > + }
> > +
> > + //
> > + // Write the Modem Control Register.
> > + //
> > + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, Mcr);
> > +
> > + return RETURN_SUCCESS;
> > +}
> > +
> > +/**
> > + Retrieve the status of the control bits on a serial device.
> > +
> > + @param Control A pointer to return the current control signals from
> the serial device.
> > +
> > + @retval RETURN_SUCCESS The control bits were read from the serial
> device.
> > + @retval RETURN_UNSUPPORTED The serial device does not support this
> operation.
> > + @retval RETURN_DEVICE_ERROR The serial device is not functioning
> correctly.
> > +
> > +**/
> > +RETURN_STATUS
> > +EFIAPI
> > +SerialPortGetControl (
> > + OUT UINT32 *Control
> > + )
> > +{
> > + UINTN SerialRegisterBase;
> > + UINT8 Msr;
> > + UINT8 Mcr;
> > + UINT8 Lsr;
> > +
> > + SerialRegisterBase = GetSerialRegisterBase ();
> > + if (SerialRegisterBase ==0) {
> > + return RETURN_UNSUPPORTED;
> > + }
> > +
> > + *Control = 0;
> > +
> > + //
> > + // Read the Modem Status Register.
> > + //
> > + Msr = SerialPortReadRegister (SerialRegisterBase, R_UART_MSR);
> > +
> > + if ((Msr & B_UART_MSR_CTS) == B_UART_MSR_CTS) {
> > + *Control |= EFI_SERIAL_CLEAR_TO_SEND;
> > + }
> > +
> > + if ((Msr & B_UART_MSR_DSR) == B_UART_MSR_DSR) {
> > + *Control |= EFI_SERIAL_DATA_SET_READY;
> > + }
> > +
> > + if ((Msr & B_UART_MSR_RI) == B_UART_MSR_RI) {
> > + *Control |= EFI_SERIAL_RING_INDICATE;
> > + }
> > +
> > + if ((Msr & B_UART_MSR_DCD) == B_UART_MSR_DCD) {
> > + *Control |= EFI_SERIAL_CARRIER_DETECT;
> > + }
> > +
> > + //
> > + // Read the Modem Control Register.
> > + //
> > + Mcr = SerialPortReadRegister (SerialRegisterBase, R_UART_MCR);
> > +
> > + if ((Mcr & B_UART_MCR_DTRC) == B_UART_MCR_DTRC) {
> > + *Control |= EFI_SERIAL_DATA_TERMINAL_READY;
> > + }
> > +
> > + if ((Mcr & B_UART_MCR_RTS) == B_UART_MCR_RTS) {
> > + *Control |= EFI_SERIAL_REQUEST_TO_SEND;
> > + }
> > +
> > + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
> > + *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
> > + }
> > +
> > + //
> > + // Read the Line Status Register.
> > + //
> > + Lsr = SerialPortReadRegister (SerialRegisterBase, R_UART_LSR);
> > +
> > + if ((Lsr & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) ==
> (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) {
> > + *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
> > + }
> > +
> > + if ((Lsr & B_UART_LSR_RXRDY) == 0) {
> > + *Control |= EFI_SERIAL_INPUT_BUFFER_EMPTY;
> > + }
> > +
> > + return RETURN_SUCCESS;
> > +}
> > +
> > +/**
> > + Sets the baud rate, receive FIFO depth, transmit/receice time out, parity,
> > + data bits, and stop bits on a serial device.
> > +
> > + @param BaudRate The requested baud rate. A BaudRate value of 0
> will use the
> > + device's default interface speed.
> > + On output, the value actually set.
> > + @param ReveiveFifoDepth The requested depth of the FIFO on the receive
> side of the
> > + serial interface. A ReceiveFifoDepth value of 0 will use
> > + the device's default FIFO depth.
> > + On output, the value actually set.
> > + @param Timeout The requested time out for a single character in
> microseconds.
> > + This timeout applies to both the transmit and receive side of
> the
> > + interface. A Timeout value of 0 will use the device's default
> time
> > + out value.
> > + On output, the value actually set.
> > + @param Parity The type of parity to use on this serial device. A Parity
> value of
> > + DefaultParity will use the device's default parity value.
> > + On output, the value actually set.
> > + @param DataBits The number of data bits to use on the serial device.
> A DataBits
> > + vaule of 0 will use the device's default data bit setting.
> > + On output, the value actually set.
> > + @param StopBits The number of stop bits to use on this serial device.
> A StopBits
> > + value of DefaultStopBits will use the device's default number
> of
> > + stop bits.
> > + On output, the value actually set.
> > +
> > + @retval RETURN_SUCCESS The new attributes were set on the serial
> device.
> > + @retval RETURN_UNSUPPORTED The serial device does not support this
> operation.
> > + @retval RETURN_INVALID_PARAMETER One or more of the attributes has
> an unsupported value.
> > + @retval RETURN_DEVICE_ERROR The serial device is not functioning
> correctly.
> > +
> > +**/
> > +RETURN_STATUS
> > +EFIAPI
> > +SerialPortSetAttributes (
> > + IN OUT UINT64 *BaudRate,
> > + IN OUT UINT32 *ReceiveFifoDepth,
> > + IN OUT UINT32 *Timeout,
> > + IN OUT EFI_PARITY_TYPE *Parity,
> > + IN OUT UINT8 *DataBits,
> > + IN OUT EFI_STOP_BITS_TYPE *StopBits
> > + )
> > +{
> > + UINTN SerialRegisterBase;
> > + UINT32 SerialBaudRate;
> > + UINTN Divisor;
> > + UINT8 Lcr;
> > + UINT8 LcrData;
> > + UINT8 LcrParity;
> > + UINT8 LcrStop;
> > + UINT64 SerialClock;
> > +
> > + SerialRegisterBase = GetSerialRegisterBase ();
> > + if (SerialRegisterBase ==0) {
> > + return RETURN_UNSUPPORTED;
> > + }
> > +
> > + SerialClock = GetBusFrequency ();
> > + if (SerialClock == 0) {
> > + return EFI_DEVICE_ERROR;
> > + }
> > +
> > + //
> > + // Check for default settings and fill in actual values.
> > + //
> > + if (*BaudRate == 0) {
> > + *BaudRate = PcdGet32 (PcdSerialBaudRate);
> > + }
> > + SerialBaudRate = (UINT32) *BaudRate;
> > +
> > + if (*DataBits == 0) {
> > + LcrData = (UINT8) (PcdGet8 (PcdSerialLineControl) & 0x3);
> > + *DataBits = LcrData + 5;
> > + } else {
> > + if ((*DataBits < 5) || (*DataBits > 8)) {
> > + return RETURN_INVALID_PARAMETER;
> > + }
> > + //
> > + // Map 5..8 to 0..3
> > + //
> > + LcrData = (UINT8) (*DataBits - (UINT8) 5);
> > + }
> > +
> > + if (*Parity == DefaultParity) {
> > + LcrParity = (UINT8) ((PcdGet8 (PcdSerialLineControl) >> 3) & 0x7);
> > + switch (LcrParity) {
> > + case 0:
> > + *Parity = NoParity;
> > + break;
> > +
> > + case 3:
> > + *Parity = EvenParity;
> > + break;
> > +
> > + case 1:
> > + *Parity = OddParity;
> > + break;
> > +
> > + case 7:
> > + *Parity = SpaceParity;
> > + break;
> > +
> > + case 5:
> > + *Parity = MarkParity;
> > + break;
> > +
> > + default:
> > + break;
> > + }
> > + } else {
> > + switch (*Parity) {
> > + case NoParity:
> > + LcrParity = 0;
> > + break;
> > +
> > + case EvenParity:
> > + LcrParity = 3;
> > + break;
> > +
> > + case OddParity:
> > + LcrParity = 1;
> > + break;
> > +
> > + case SpaceParity:
> > + LcrParity = 7;
> > + break;
> > +
> > + case MarkParity:
> > + LcrParity = 5;
> > + break;
> > +
> > + default:
> > + return RETURN_INVALID_PARAMETER;
> > + }
> > + }
> > +
> > + if (*StopBits == DefaultStopBits) {
> > + LcrStop = (UINT8) ((PcdGet8 (PcdSerialLineControl) >> 2) & 0x1);
> > + switch (LcrStop) {
> > + case 0:
> > + *StopBits = OneStopBit;
> > + break;
> > +
> > + case 1:
> > + if (*DataBits == 5) {
> > + *StopBits = OneFiveStopBits;
> > + } else {
> > + *StopBits = TwoStopBits;
> > + }
> > + break;
> > +
> > + default:
> > + break;
> > + }
> > + } else {
> > + switch (*StopBits) {
> > + case OneStopBit:
> > + LcrStop = 0;
> > + break;
> > +
> > + case OneFiveStopBits:
> > + case TwoStopBits:
> > + LcrStop = 1;
> > + break;
> > +
> > + default:
> > + return RETURN_INVALID_PARAMETER;
> > + }
> > + }
> > +
> > + //
> > + // Calculate divisor for baud generator
> > + // Ref_Clk_Rate / Baud_Rate / 16
> > + //
> > + Divisor = SerialClock / (SerialBaudRate * 16);
> > + if ((SerialClock % (SerialBaudRate * 16)) >= SerialBaudRate * 8) {
> > + Divisor++;
> > + }
> > +
> > + //
> > + // Configure baud rate
> > + //
> > + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR,
> B_UART_LCR_DLAB);
> > + SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_HIGH, (UINT8)
> (Divisor >> 8));
> > + SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_LOW, (UINT8)
> (Divisor & 0xff));
> > +
> > + //
> > + // Clear DLAB and configure Data Bits, Parity, and Stop Bits.
> > + // Strip reserved bits from line control value
> > + //
> > + Lcr = (UINT8) ((LcrParity << 3) | (LcrStop << 2) | LcrData);
> > + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8) (Lcr &
> 0x3F));
> > +
> > + return RETURN_SUCCESS;
> > +}
> > +
> > diff --git
> a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
> b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
> > new file mode 100644
> > index 0000000000..45ae9dc0af
> > --- /dev/null
> > +++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
> > @@ -0,0 +1,39 @@
> > +## @file
> > +# SerialPortLib instance for 16550 UART.
> > +#
> > +# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> > +# Copyright 2020 NXP
> > +# SPDX-License-Identifier: BSD-2-Clause-Patent
> > +#
> > +##
> > +
> > +[Defines]
> > + INF_VERSION = 0x00010005
> > + BASE_NAME = BaseSerialPortLib16550
> > + MODULE_UNI_FILE = BaseSerialPortLib16550.uni
> > + FILE_GUID = 9E7C00CF-355A-4d4e-BF60-0428CFF95540
> > + MODULE_TYPE = BASE
> > + VERSION_STRING = 1.1
> > + LIBRARY_CLASS = SerialPortLib
> > +
> > +[Packages]
> > + MdePkg/MdePkg.dec
> > + MdeModulePkg/MdeModulePkg.dec
> > +
> > +[LibraryClasses]
> > + PcdLib
> > + IoLib
> > + SocLib
> > +
> > +[Sources]
> > + BaseSerialPortLib16550.c
> > +
> > +[FixedPcd]
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl ##
> CONSUMES
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable ##
> SOMETIMES_CONSUMES
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ##
> CONSUMES
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ##
> CONSUMES
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl ##
> CONSUMES
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl ##
> CONSUMES
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize ##
> CONSUMES
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride ##
> CONSUMES
> > diff --git
> a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.uni
> b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.uni
> > new file mode 100644
> > index 0000000000..2fefe85cf8
> > --- /dev/null
> > +++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.uni
> > @@ -0,0 +1,17 @@
> > +// /** @file
> > +// SerialPortLib instance for 16550 UART.
> > +//
> > +// SerialPortLib instance for 16550 UART.
> > +//
> > +// Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> > +// Copyright 2020 NXP
> > +//
> > +// SPDX-License-Identifier: BSD-2-Clause-Patent
> > +//
> > +// **/
> > +
> > +
> > +#string STR_MODULE_ABSTRACT #language en-US "SerialPortLib
> instance for 16550 UART"
> > +
> > +#string STR_MODULE_DESCRIPTION #language en-US "SerialPortLib
> instance for 16550 UART."
> > +
> > diff --git a/Silicon/NXP/Library/DUartPortLib/DUart.h
> b/Silicon/NXP/Library/DUartPortLib/DUart.h
> > deleted file mode 100644
> > index c71e2ce55d..0000000000
> > --- a/Silicon/NXP/Library/DUartPortLib/DUart.h
> > +++ /dev/null
> > @@ -1,122 +0,0 @@
> > -/** DUart.h
> > -* Header defining the DUART constants (Base addresses, sizes, flags)
> > -*
> > -* Based on Serial I/O Port library headers available in PL011Uart.h
> > -*
> > -* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
> > -* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> > -* Copyright 2017 NXP
> > -*
> > -* SPDX-License-Identifier: BSD-2-Clause-Patent
> > -*
> > -**/
> > -
> > -#ifndef DUART_H_
> > -#define DUART_H_
> > -
> > -// FIFO Control Register
> > -#define DUART_FCR_FIFO_EN 0x01 /* Fifo enable */
> > -#define DUART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
> > -#define DUART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
> > -#define DUART_FCR_DMA_SELECT 0x08 /* For DMA applications */
> > -#define DUART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger
> range */
> > -#define DUART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
> > -#define DUART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
> > -#define DUART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
> > -#define DUART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
> > -#define DUART_FCR_RXSR 0x02 /* Receiver soft reset */
> > -#define DUART_FCR_TXSR 0x04 /* Transmitter soft reset */
> > -
> > -// Modem Control Register
> > -#define DUART_MCR_DTR 0x01 /* Reserved */
> > -#define DUART_MCR_RTS 0x02 /* RTS */
> > -#define DUART_MCR_OUT1 0x04 /* Reserved */
> > -#define DUART_MCR_OUT2 0x08 /* Reserved */
> > -#define DUART_MCR_LOOP 0x10 /* Enable loopback test mode */
> > -#define DUART_MCR_AFE 0x20 /* AFE (Auto Flow Control) */
> > -#define DUART_MCR_DMA_EN 0x04
> > -#define DUART_MCR_TX_DFR 0x08
> > -
> > -// Line Control Register
> > -/*
> > -* Note: if the word length is 5 bits (DUART_LCR_WLEN5), then setting
> > -* DUART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
> > -*/
> > -#define DUART_LCR_WLS_MSK 0x03 /* character length select mask */
> > -#define DUART_LCR_WLS_5 0x00 /* 5 bit character length */
> > -#define DUART_LCR_WLS_6 0x01 /* 6 bit character length */
> > -#define DUART_LCR_WLS_7 0x02 /* 7 bit character length */
> > -#define DUART_LCR_WLS_8 0x03 /* 8 bit character length */
> > -#define DUART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
> > -#define DUART_LCR_PEN 0x08 /* Parity eneble */
> > -#define DUART_LCR_EPS 0x10 /* Even Parity Select */
> > -#define DUART_LCR_STKP 0x20 /* Stick Parity */
> > -#define DUART_LCR_SBRK 0x40 /* Set Break */
> > -#define DUART_LCR_BKSE 0x80 /* Bank select enable */
> > -#define DUART_LCR_DLAB 0x80 /* Divisor latch access bit */
> > -
> > -// Line Status Register
> > -#define DUART_LSR_DR 0x01 /* Data ready */
> > -#define DUART_LSR_OE 0x02 /* Overrun */
> > -#define DUART_LSR_PE 0x04 /* Parity error */
> > -#define DUART_LSR_FE 0x08 /* Framing error */
> > -#define DUART_LSR_BI 0x10 /* Break */
> > -#define DUART_LSR_THRE 0x20 /* Xmit holding register empty */
> > -#define DUART_LSR_TEMT 0x40 /* Xmitter empty */
> > -#define DUART_LSR_ERR 0x80 /* Error */
> > -
> > -// Modem Status Register
> > -#define DUART_MSR_DCTS 0x01 /* Delta CTS */
> > -#define DUART_MSR_DDSR 0x02 /* Reserved */
> > -#define DUART_MSR_TERI 0x04 /* Reserved */
> > -#define DUART_MSR_DDCD 0x08 /* Reserved */
> > -#define DUART_MSR_CTS 0x10 /* Clear to Send */
> > -#define DUART_MSR_DSR 0x20 /* Reserved */
> > -#define DUART_MSR_RI 0x40 /* Reserved */
> > -#define DUART_MSR_DCD 0x80 /* Reserved */
> > -
> > -// Interrupt Identification Register
> > -#define DUART_IIR_NO_INT 0x01 /* No interrupts pending */
> > -#define DUART_IIR_ID 0x06 /* Mask for the interrupt ID */
> > -#define DUART_IIR_MSI 0x00 /* Modem status interrupt */
> > -#define DUART_IIR_THRI 0x02 /* Transmitter holding register empty */
> > -#define DUART_IIR_RDI 0x04 /* Receiver data interrupt */
> > -#define DUART_IIR_RLSI 0x06 /* Receiver line status interrupt */
> > -
> > -// Interrupt Enable Register
> > -#define DUART_IER_MSI 0x08 /* Enable Modem status interrupt */
> > -#define DUART_IER_RLSI 0x04 /* Enable receiver line status interrupt
> */
> > -#define DUART_IER_THRI 0x02 /* Enable Transmitter holding register
> int. */
> > -#define DUART_IER_RDI 0x01 /* Enable receiver data interrupt */
> > -
> > -// LCR defaults
> > -#define DUART_LCR_8N1 0x03
> > -#define DUART_LCRVAL DUART_LCR_8N1 /* 8 data, 1 stop, no
> parity */
> > -#define DUART_MCRVAL (DUART_MCR_DTR | \
> > - DUART_MCR_RTS) /* RTS/DTR */
> > -#define DUART_FCRVAL (DUART_FCR_FIFO_EN | \
> > - DUART_FCR_RXSR | \
> > - DUART_FCR_TXSR) /* Clear & enable FIFOs */
> > -
> > -#define URBR 0x0
> > -#define UTHR 0x0
> > -#define UDLB 0x0
> > -#define UDMB 0x1
> > -#define UIER 0x1
> > -#define UIIR 0x2
> > -#define UFCR 0x2
> > -#define UAFR 0x2
> > -#define ULCR 0x3
> > -#define UMCR 0x4
> > -#define ULSR 0x5
> > -#define UMSR 0x6
> > -#define USCR 0x7
> > -#define UDSR 0x10
> > -
> > -extern
> > -UINT64
> > -GetBusFrequency (
> > - VOID
> > - );
> > -
> > -#endif /* DUART_H_ */
> > diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
> b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
> > deleted file mode 100644
> > index c3c738d3cc..0000000000
> > --- a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
> > +++ /dev/null
> > @@ -1,364 +0,0 @@
> > -/** DuartPortLib.c
> > - DUART (NS16550) library functions
> > -
> > - Based on Serial I/O Port library functions available in PL011SerialPortLib.c
> > -
> > - Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
> > - Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.<BR>
> > - Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> > - Copyright 2017 NXP
> > -
> > - SPDX-License-Identifier: BSD-2-Clause-Patent
> > -
> > -**/
> > -
> > -#include <Base.h>
> > -#include <Library/IoLib.h>
> > -#include <Library/PcdLib.h>
> > -#include <Library/SerialPortLib.h>
> > -
> > -#include "DUart.h"
> > -
> > -STATIC CONST UINT32 mInvalidControlBits =
> (EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE | \
> > - EFI_SERIAL_DATA_TERMINAL_READY);
> > -
> > -/**
> > - Assert or deassert the control signals on a serial port.
> > - The following control signals are set according their bit settings :
> > - . Request to Send
> > - . Data Terminal Ready
> > -
> > - @param[in] Control The following bits are taken into account :
> > - . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the
> > - "Request To Send" control signal if this bit is
> > - equal to one/zero.
> > - . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert
> > - the "Data Terminal Ready" control signal if this
> > - bit is equal to one/zero.
> > - . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable
> > - the hardware loopback if this bit is equal to
> > - one/zero.
> > - . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.
> > - . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/
> > - disable the hardware flow control based on CTS (Clear
> > - To Send) and RTS (Ready To Send) control signals.
> > -
> > - @retval EFI_SUCCESS The new control bits were set on the device.
> > - @retval EFI_UNSUPPORTED The device does not support this operation.
> > -
> > -**/
> > -EFI_STATUS
> > -EFIAPI
> > -SerialPortSetControl (
> > - IN UINT32 Control
> > - )
> > -{
> > - UINT32 McrBits;
> > - UINTN UartBase;
> > -
> > - UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> > -
> > - if (Control & (mInvalidControlBits)) {
> > - return EFI_UNSUPPORTED;
> > - }
> > -
> > - McrBits = MmioRead8 (UartBase + UMCR);
> > -
> > - if (Control & EFI_SERIAL_REQUEST_TO_SEND) {
> > - McrBits |= DUART_MCR_RTS;
> > - } else {
> > - McrBits &= ~DUART_MCR_RTS;
> > - }
> > -
> > - if (Control & EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE) {
> > - McrBits |= DUART_MCR_LOOP;
> > - } else {
> > - McrBits &= ~DUART_MCR_LOOP;
> > - }
> > -
> > - if (Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) {
> > - McrBits |= DUART_MCR_AFE;
> > - } else {
> > - McrBits &= ~DUART_MCR_AFE;
> > - }
> > -
> > - MmioWrite32 (UartBase + UMCR, McrBits);
> > -
> > - return EFI_SUCCESS;
> > -}
> > -
> > -/**
> > - Retrieve the status of the control bits on a serial device.
> > -
> > - @param[out] Control Status of the control bits on a serial device :
> > -
> > - . EFI_SERIAL_DATA_CLEAR_TO_SEND,
> > - EFI_SERIAL_DATA_SET_READY,
> > - EFI_SERIAL_RING_INDICATE,
> > - EFI_SERIAL_CARRIER_DETECT,
> > - EFI_SERIAL_REQUEST_TO_SEND,
> > - EFI_SERIAL_DATA_TERMINAL_READY
> > - are all related to the DTE (Data Terminal Equipment)
> > - and DCE (Data Communication Equipment) modes of
> > - operation of the serial device.
> > - . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the
> > - receive buffer is empty, 0 otherwise.
> > - . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the
> > - transmit buffer is empty, 0 otherwise.
> > - . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if
> > - the hardware loopback is enabled (the ouput feeds the
> > - receive buffer), 0 otherwise.
> > - . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if
> > - a loopback is accomplished by software, 0 otherwise.
> > - . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to
> > - one if the hardware flow control based on CTS (Clear
> > - To Send) and RTS (Ready To Send) control signals is
> > - enabled, 0 otherwise.
> > -
> > - @retval EFI_SUCCESS The control bits were read from the serial device.
> > -
> > -**/
> > -EFI_STATUS
> > -EFIAPI
> > -SerialPortGetControl (
> > - OUT UINT32 *Control
> > - )
> > -{
> > - UINT32 MsrRegister;
> > - UINT32 McrRegister;
> > - UINT32 LsrRegister;
> > - UINTN UartBase;
> > -
> > - UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> > -
> > - MsrRegister = MmioRead8 (UartBase + UMSR);
> > - McrRegister = MmioRead8 (UartBase + UMCR);
> > - LsrRegister = MmioRead8 (UartBase + ULSR);
> > -
> > - *Control = 0;
> > -
> > - if ((MsrRegister & DUART_MSR_CTS) == DUART_MSR_CTS) {
> > - *Control |= EFI_SERIAL_CLEAR_TO_SEND;
> > - }
> > -
> > - if ((McrRegister & DUART_MCR_RTS) == DUART_MCR_RTS) {
> > - *Control |= EFI_SERIAL_REQUEST_TO_SEND;
> > - }
> > -
> > - if ((LsrRegister & DUART_LSR_TEMT) == DUART_LSR_TEMT) {
> > - *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
> > - }
> > -
> > - if ((McrRegister & DUART_MCR_AFE) == DUART_MCR_AFE) {
> > - *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
> > - }
> > -
> > - if ((McrRegister & DUART_MCR_LOOP) == DUART_MCR_LOOP) {
> > - *Control |= EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE;
> > - }
> > -
> > - return EFI_SUCCESS;
> > -}
> > -
> > -/*
> > - * Return Baud divisor on basis of Baudrate
> > - */
> > -UINT32
> > -CalculateBaudDivisor (
> > - IN UINT64 BaudRate
> > - )
> > -{
> > - UINTN DUartClk;
> > - UINTN FreqSystemBus;
> > -
> > - FreqSystemBus = GetBusFrequency ();
> > - DUartClk = FreqSystemBus/PcdGet32(PcdPlatformFreqDiv);
> > -
> > - return ((DUartClk)/(BaudRate * 16));
> > -}
> > -
> > -/*
> > - Initialise the serial port to the specified settings.
> > - All unspecified settings will be set to the default values.
> > -
> > - @return Always return EFI_SUCCESS or EFI_INVALID_PARAMETER.
> > -
> > - **/
> > -VOID
> > -EFIAPI
> > -DuartInitializePort (
> > - IN UINT64 BaudRate
> > - )
> > -{
> > - UINTN UartBase;
> > - UINT32 BaudDivisor;
> > -
> > - UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> > - BaudDivisor = CalculateBaudDivisor (BaudRate);
> > -
> > -
> > - while (!(MmioRead8 (UartBase + ULSR) & DUART_LSR_TEMT));
> > -
> > - //
> > - // Enable and assert interrupt when new data is available on
> > - // external device,
> > - // setup data format, setup baud divisor
> > - //
> > - MmioWrite8 (UartBase + UIER, 0x1);
> > - MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL);
> > - MmioWrite8 (UartBase + UDLB, 0);
> > - MmioWrite8 (UartBase + UDMB, 0);
> > - MmioWrite8 (UartBase + ULCR, DUART_LCRVAL);
> > - MmioWrite8 (UartBase + UMCR, DUART_MCRVAL);
> > - MmioWrite8 (UartBase + UFCR, DUART_FCRVAL);
> > - MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL);
> > - MmioWrite8 (UartBase + UDLB, BaudDivisor & 0xff);
> > - MmioWrite8 (UartBase + UDMB, (BaudDivisor >> 8) & 0xff);
> > - MmioWrite8 (UartBase + ULCR, DUART_LCRVAL);
> > -
> > - return;
> > -}
> > -
> > -/**
> > - Programmed hardware of Serial port.
> > -
> > - @return Always return EFI_SUCCESS.
> > -
> > -**/
> > -EFI_STATUS
> > -EFIAPI
> > -SerialPortInitialize (
> > - VOID
> > - )
> > -{
> > - UINT64 BaudRate;
> > - BaudRate = (UINTN)PcdGet64 (PcdUartDefaultBaudRate);
> > -
> > -
> > - DuartInitializePort (BaudRate);
> > -
> > - return EFI_SUCCESS;
> > -}
> > -
> > -/**
> > - Write data to serial device.
> > -
> > - @param Buffer Point of data buffer which need to be written.
> > - @param NumberOfBytes Number of output bytes which are cached in
> Buffer.
> > -
> > - @retval 0 Write data failed.
> > - @retval !0 Actual number of bytes written to serial device.
> > -
> > -**/
> > -UINTN
> > -EFIAPI
> > -SerialPortWrite (
> > - IN UINT8 *Buffer,
> > - IN UINTN NumberOfBytes
> > - )
> > -{
> > - UINT8 *Final;
> > - UINTN UartBase;
> > -
> > - Final = &Buffer[NumberOfBytes];
> > - UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> > -
> > - while (Buffer < Final) {
> > - while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_THRE) == 0);
> > - MmioWrite8 (UartBase + UTHR, *Buffer++);
> > - }
> > -
> > - return NumberOfBytes;
> > -}
> > -
> > -/**
> > - Read data from serial device and save the data in buffer.
> > -
> > - @param Buffer Point of data buffer which need to be written.
> > - @param NumberOfBytes Number of output bytes which are cached in
> Buffer.
> > -
> > - @retval 0 Read data failed.
> > - @retval !0 Actual number of bytes read from serial device.
> > -
> > -**/
> > -UINTN
> > -EFIAPI
> > -SerialPortRead (
> > - OUT UINT8 *Buffer,
> > - IN UINTN NumberOfBytes
> > - )
> > -{
> > - UINTN Count;
> > - UINTN UartBase;
> > -
> > - UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> > -
> > - for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
> > - // Loop while waiting for a new char(s) to arrive in the
> > - // RxFIFO
> > - while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) == 0);
> > -
> > - *Buffer = MmioRead8 (UartBase + URBR);
> > - }
> > -
> > - return NumberOfBytes;
> > -}
> > -
> > -/**
> > - Check to see if any data is available to be read from the debug device.
> > -
> > - @retval EFI_SUCCESS At least one byte of data is available to be read
> > - @retval EFI_NOT_READY No data is available to be read
> > - @retval EFI_DEVICE_ERROR The serial device is not functioning properly
> > -
> > -**/
> > -BOOLEAN
> > -EFIAPI
> > -SerialPortPoll (
> > - VOID
> > - )
> > -{
> > - UINTN UartBase;
> > -
> > - UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> > -
> > - return ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) != 0);
> > -}
> > -
> > -/**
> > - Set new attributes to LS1043a.
> > -
> > - @param BaudRate The baud rate of the serial device. If the baud
> rate is not supported,
> > - the speed will be reduced down to the nearest supported
> one and the
> > - variable's value will be updated accordingly.
> > - @param ReceiveFifoDepth The number of characters the device will
> buffer on input. If the specified
> > - value is not supported, the variable's value will be reduced
> down to the
> > - nearest supported one.
> > - @param Timeout If applicable, the number of microseconds the
> device will wait
> > - before timing out a Read or a Write operation.
> > - @param Parity If applicable, this is the EFI_PARITY_TYPE that is
> computed or checked
> > - as each character is transmitted or received. If the device
> does not
> > - support parity, the value is the default parity value.
> > - @param DataBits The number of data bits in each character
> > - @param StopBits If applicable, the EFI_STOP_BITS_TYPE number of
> stop bits per character.
> > - If the device does not support stop bits, the value is the
> default stop
> > - bit value.
> > -
> > - @retval EFI_SUCCESS All attributes were set correctly on the serial
> device.
> > -
> > -**/
> > -EFI_STATUS
> > -EFIAPI
> > -SerialPortSetAttributes (
> > - IN OUT UINT64 *BaudRate,
> > - IN OUT UINT32 *ReceiveFifoDepth,
> > - IN OUT UINT32 *Timeout,
> > - IN OUT EFI_PARITY_TYPE *Parity,
> > - IN OUT UINT8 *DataBits,
> > - IN OUT EFI_STOP_BITS_TYPE *StopBits
> > - )
> > -{
> > - DuartInitializePort (*BaudRate);
> > -
> > - return EFI_SUCCESS;
> > -}
> > diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> > deleted file mode 100644
> > index 7a2fa619b0..0000000000
> > --- a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> > +++ /dev/null
> > @@ -1,34 +0,0 @@
> > -# DUartPortLib.inf
> > -#
> > -# Component description file for DUartPortLib module
> > -#
> > -# Copyright (c) 2013, Freescale Ltd. All rights reserved.
> > -# Copyright 2017 NXP
> > -#
> > -# SPDX-License-Identifier: BSD-2-Clause-Patent
> > -#
> > -
> > -[Defines]
> > - INF_VERSION = 0x0001001A
> > - BASE_NAME = DUartPortLib
> > - FILE_GUID = c42dfe79-8de5-429e-a055-2d0a58591498
> > - MODULE_TYPE = BASE
> > - VERSION_STRING = 1.0
> > - LIBRARY_CLASS = SerialPortLib
> > -
> > -[Sources.common]
> > - DUartPortLib.c
> > -
> > -[LibraryClasses]
> > - PcdLib
> > - SocLib
> > -
> > -[Packages]
> > - MdeModulePkg/MdeModulePkg.dec
> > - MdePkg/MdePkg.dec
> > - Silicon/NXP/NxpQoriqLs.dec
> > -
> > -[Pcd]
> > - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
> > - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
> > - gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
> > --
> > 2.17.1
> >
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [EXTERNAL] [PATCH 06/19] Silicon/NXP: remove print information from Soc lib
2020-02-07 12:43 ` [PATCH 06/19] Silicon/NXP: remove print information from Soc lib Pankaj Bansal
@ 2020-02-10 17:09 ` Leif Lindholm
0 siblings, 0 replies; 49+ messages in thread
From: Leif Lindholm @ 2020-02-10 17:09 UTC (permalink / raw)
To: Pankaj Bansal; +Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi, devel
On Fri, Feb 07, 2020 at 18:13:15 +0530, Pankaj Bansal wrote:
> The Soc info being printed can be removed from SOC lib.
> We are in the process of implementing PEI Phase.
> After PEI phase impelmentation this info would be printed in
> common PEIM based on the information retrieved from PPIs.
> e.g. gArmMpCoreInfoPpiGuid can be used to print cluser and
> core info.
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
/
Leif
> ---
> Silicon/NXP/Include/Chassis2/LsSerDes.h | 62 ----
> Silicon/NXP/LS1043A/Include/SocSerDes.h | 51 ---
> Silicon/NXP/Library/SocLib/Chassis.c | 337 -------------------
> Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 8 -
> Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 -
> Silicon/NXP/Library/SocLib/SerDes.c | 268 ---------------
> 6 files changed, 727 deletions(-)
> delete mode 100644 Silicon/NXP/Include/Chassis2/LsSerDes.h
> delete mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h
> delete mode 100644 Silicon/NXP/Library/SocLib/SerDes.c
>
> diff --git a/Silicon/NXP/Include/Chassis2/LsSerDes.h b/Silicon/NXP/Include/Chassis2/LsSerDes.h
> deleted file mode 100644
> index 9afbc52239..0000000000
> --- a/Silicon/NXP/Include/Chassis2/LsSerDes.h
> +++ /dev/null
> @@ -1,62 +0,0 @@
> -/** LsSerDes.h
> - The Header file of SerDes Module for Chassis 2
> -
> - Copyright 2017-2019 NXP
> -
> - SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#ifndef LS_SERDES_H_
> -#define LS_SERDES_H_
> -
> -#include <Uefi/UefiBaseType.h>
> -
> -#define SRDS_MAX_LANES 4
> -
> -typedef enum {
> - None = 0,
> - Pcie1,
> - Pcie2,
> - Pcie3,
> - Sata,
> - SgmiiFm1Dtsec1,
> - SgmiiFm1Dtsec2,
> - SgmiiFm1Dtsec5,
> - SgmiiFm1Dtsec6,
> - SgmiiFm1Dtsec9,
> - SgmiiFm1Dtsec10,
> - QsgmiiFm1A,
> - XfiFm1Mac9,
> - XfiFm1Mac10,
> - Sgmii2500Fm1Dtsec2,
> - Sgmii2500Fm1Dtsec5,
> - Sgmii2500Fm1Dtsec9,
> - Sgmii2500Fm1Dtsec10,
> - SerdesPrtclCount
> -} SERDES_PROTOCOL;
> -
> -typedef enum {
> - Srds1 = 0,
> - Srds2,
> - SrdsMaxNum
> -} SERDES_NUMBER;
> -
> -typedef struct {
> - UINT16 Protocol;
> - UINT8 SrdsLane[SRDS_MAX_LANES];
> -} SERDES_CONFIG;
> -
> -typedef VOID
> -(*SERDES_PROBE_LANES_CALLBACK) (
> - IN SERDES_PROTOCOL LaneProtocol,
> - IN VOID *Arg
> - );
> -
> -VOID
> -SerDesProbeLanes(
> - IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
> - IN VOID *Arg
> - );
> -
> -#endif /* LS_SERDES_H_ */
> diff --git a/Silicon/NXP/LS1043A/Include/SocSerDes.h b/Silicon/NXP/LS1043A/Include/SocSerDes.h
> deleted file mode 100644
> index 2d1c6f10f9..0000000000
> --- a/Silicon/NXP/LS1043A/Include/SocSerDes.h
> +++ /dev/null
> @@ -1,51 +0,0 @@
> -/** @file
> - The Header file of SerDes Module for LS1043A
> -
> - Copyright 2017-2019 NXP
> -
> - SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#ifndef SOC_SERDES_H_
> -#define SOC_SERDES_H_
> -
> -#ifdef CHASSIS2
> -#include <Chassis2/LsSerDes.h>
> -#endif
> -
> -SERDES_CONFIG SerDes1ConfigTbl[] = {
> - /* SerDes 1 */
> - {0x1555, {XfiFm1Mac9, Pcie1, Pcie2, Pcie3 } },
> - {0x2555, {Sgmii2500Fm1Dtsec9, Pcie1, Pcie2, Pcie3 } },
> - {0x4555, {QsgmiiFm1A, Pcie1, Pcie2, Pcie3 } },
> - {0x4558, {QsgmiiFm1A, Pcie1, Pcie2, Sata } },
> - {0x1355, {XfiFm1Mac9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
> - {0x2355, {Sgmii2500Fm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
> - {0x3335, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, Pcie3 } },
> - {0x3355, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
> - {0x3358, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Sata } },
> - {0x3555, {SgmiiFm1Dtsec9, Pcie1, Pcie2, Pcie3 } },
> - {0x3558, {SgmiiFm1Dtsec9, Pcie1, Pcie2, Sata } },
> - {0x7000, {Pcie1, Pcie1, Pcie1, Pcie1 } },
> - {0x9998, {Pcie1, Pcie2, Pcie3, Sata } },
> - {0x6058, {Pcie1, Pcie1, Pcie2, Sata } },
> - {0x1455, {XfiFm1Mac9, QsgmiiFm1A, Pcie2, Pcie3 } },
> - {0x2455, {Sgmii2500Fm1Dtsec9, QsgmiiFm1A, Pcie2, Pcie3 } },
> - {0x2255, {Sgmii2500Fm1Dtsec9, Sgmii2500Fm1Dtsec2, Pcie2, Pcie3 } },
> - {0x3333, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 } },
> - {0x1460, {XfiFm1Mac9, QsgmiiFm1A, Pcie3, Pcie3 } },
> - {0x2460, {Sgmii2500Fm1Dtsec9, QsgmiiFm1A, Pcie3, Pcie3 } },
> - {0x3460, {SgmiiFm1Dtsec9, QsgmiiFm1A, Pcie3, Pcie3 } },
> - {0x3455, {SgmiiFm1Dtsec9, QsgmiiFm1A, Pcie2, Pcie3 } },
> - {0x9960, {Pcie1, Pcie2, Pcie3, Pcie3 } },
> - {0x2233, {Sgmii2500Fm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 }},
> - {0x2533, {Sgmii2500Fm1Dtsec9, Pcie1, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 } },
> - {}
> -};
> -
> -SERDES_CONFIG *SerDesConfigTbl[] = {
> - SerDes1ConfigTbl
> -};
> -
> -#endif /* SOC_SERDES_H_ */
> diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
> index b8a8118c5e..18a1f5e4e1 100644
> --- a/Silicon/NXP/Library/SocLib/Chassis.c
> +++ b/Silicon/NXP/Library/SocLib/Chassis.c
> @@ -25,16 +25,6 @@
> #include <DramInfo.h>
> #include "NxpChassis.h"
>
> -/*
> - * Structure to list available SOCs.
> - * Name, Soc Version, Number of Cores
> - */
> -STATIC CPU_TYPE mCpuTypeList[] = {
> - CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
> - CPU_TYPE_ENTRY (LS1046A, LS1046A, 4),
> - CPU_TYPE_ENTRY (LS2088A, LS2088A, 8),
> -};
> -
> UINT32
> EFIAPI
> GurRead (
> @@ -48,235 +38,6 @@ GurRead (
> }
> }
>
> -/*
> - * Return the type of initiator (core or hardware accelerator)
> - */
> -UINT32
> -InitiatorType (
> - IN UINT32 Cluster,
> - IN UINTN InitId
> - )
> -{
> - CCSR_GUR *GurBase;
> - UINT32 Idx;
> - UINT32 Type;
> -
> - GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> - Idx = (Cluster >> (InitId * 8)) & TP_CLUSTER_INIT_MASK;
> - Type = GurRead ((UINTN)&GurBase->TpItyp[Idx]);
> -
> - if (Type & TP_ITYP_AV_MASK) {
> - return Type;
> - }
> -
> - return 0;
> -}
> -
> -/*
> - * Return the mask for number of cores on this SOC.
> - */
> -UINT32
> -CpuMask (
> - VOID
> - )
> -{
> - CCSR_GUR *GurBase;
> - UINTN ClusterIndex;
> - UINTN Count;
> - UINT32 Cluster;
> - UINT32 Type;
> - UINT32 Mask;
> - UINTN InitiatorIndex;
> -
> - GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> - ClusterIndex = 0;
> - Count = 0;
> - Mask = 0;
> -
> - do {
> - Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
> - for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
> - Type = InitiatorType (Cluster, InitiatorIndex);
> - if (Type) {
> - if (TP_ITYP_TYPE_MASK (Type) == TP_ITYP_TYPE_ARM) {
> - Mask |= 1 << Count;
> - }
> - Count++;
> - }
> - }
> - ClusterIndex++;
> - } while (CHECK_CLUSTER (Cluster));
> -
> - return Mask;
> -}
> -
> -/*
> - * Return the number of cores on this SOC.
> - */
> -UINTN
> -CpuNumCores (
> - VOID
> - )
> -{
> - UINTN Count;
> - UINTN Num;
> -
> - Count = 0;
> - Num = CpuMask ();
> -
> - while (Num) {
> - Count += Num & 1;
> - Num >>= 1;
> - }
> -
> - return Count;
> -}
> -
> -/*
> - * Return core's cluster
> - */
> -INT32
> -QoriqCoreToCluster (
> - IN UINTN Core
> - )
> -{
> - CCSR_GUR *GurBase;
> - UINTN ClusterIndex;
> - UINTN Count;
> - UINT32 Cluster;
> - UINT32 Type;
> - UINTN InitiatorIndex;
> -
> - GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> - ClusterIndex = 0;
> - Count = 0;
> - do {
> - Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
> - for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
> - Type = InitiatorType (Cluster, InitiatorIndex);
> - if (Type) {
> - if (Count == Core) {
> - return ClusterIndex;
> - }
> - Count++;
> - }
> - }
> - ClusterIndex++;
> - } while (CHECK_CLUSTER (Cluster));
> -
> - return -1; // cannot identify the cluster
> -}
> -
> -/*
> - * Return the type of core i.e. A53, A57 etc of inputted
> - * core number.
> - */
> -UINTN
> -QoriqCoreToType (
> - IN UINTN Core
> - )
> -{
> - CCSR_GUR *GurBase;
> - UINTN ClusterIndex;
> - UINTN Count;
> - UINT32 Cluster;
> - UINT32 Type;
> - UINTN InitiatorIndex;
> -
> - GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> - ClusterIndex = 0;
> - Count = 0;
> -
> - do {
> - Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
> - for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
> - Type = InitiatorType (Cluster, InitiatorIndex);
> - if (Type) {
> - if (Count == Core) {
> - return Type;
> - }
> - Count++;
> - }
> - }
> - ClusterIndex++;
> - } while (CHECK_CLUSTER (Cluster));
> -
> - return EFI_NOT_FOUND; /* cannot identify the cluster */
> -}
> -
> -STATIC
> -UINTN
> -CpuMaskNext (
> - IN UINTN Cpu,
> - IN UINTN Mask
> - )
> -{
> - for (Cpu++; !((1 << Cpu) & Mask); Cpu++);
> -
> - return Cpu;
> -}
> -
> -/*
> - * Print CPU information
> - */
> -VOID
> -PrintCpuInfo (
> - VOID
> - )
> -{
> - SYS_INFO SysInfo;
> - UINTN CoreIndex;
> - UINTN Core;
> - UINT32 Type;
> - UINT32 NumCpus;
> - UINT32 Mask;
> - CHAR8 *CoreName;
> -
> - GetSysInfo (&SysInfo);
> - DEBUG ((DEBUG_INIT, "Clock Configuration:"));
> -
> - NumCpus = CpuNumCores ();
> - Mask = CpuMask ();
> -
> - for (CoreIndex = 0, Core = CpuMaskNext(-1, Mask);
> - CoreIndex < NumCpus;
> - CoreIndex++, Core = CpuMaskNext(Core, Mask))
> - {
> - if (!(CoreIndex % 3)) {
> - DEBUG ((DEBUG_INIT, "\n "));
> - }
> -
> - Type = TP_ITYP_VERSION (QoriqCoreToType (Core));
> - switch (Type) {
> - case TY_ITYP_VERSION_A7:
> - CoreName = "A7";
> - break;
> - case TY_ITYP_VERSION_A53:
> - CoreName = "A53";
> - break;
> - case TY_ITYP_VERSION_A57:
> - CoreName = "A57";
> - break;
> - case TY_ITYP_VERSION_A72:
> - CoreName = "A72";
> - break;
> - default:
> - CoreName = " Unknown Core ";
> - }
> - DEBUG ((DEBUG_INIT, "CPU%d(%a):%-4d MHz ",
> - Core, CoreName, SysInfo.FreqProcessor[Core] / MHZ));
> - }
> -
> - DEBUG ((DEBUG_INIT, "\n Bus: %-4d MHz ", SysInfo.FreqSystemBus / MHZ));
> - DEBUG ((DEBUG_INIT, "DDR: %-4d MT/s", SysInfo.FreqDdrBus / MHZ));
> -
> - if (SysInfo.FreqFman[0] != 0) {
> - DEBUG ((DEBUG_INIT, "\n FMAN: %-4d MHz ", SysInfo.FreqFman[0] / MHZ));
> - }
> -
> - DEBUG ((DEBUG_INIT, "\n"));
> -}
> -
> /*
> * Return system bus frequency
> */
> @@ -307,77 +68,6 @@ GetSdxcFrequency (
> return SocSysInfo.FreqSdhc;
> }
>
> -/*
> - * Print Soc information
> - */
> -VOID
> -PrintSoc (
> - VOID
> - )
> -{
> - CHAR8 Buf[20];
> - CCSR_GUR *GurBase;
> - UINTN Count;
> - //
> - // Svr : System Version Register
> - //
> - UINTN Svr;
> - UINTN Ver;
> -
> - GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> -
> - Svr = GurRead ((UINTN)&GurBase->Svr);
> - Ver = SVR_SOC_VER (Svr);
> -
> - for (Count = 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) {
> - if ((mCpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
> - AsciiStrCpyS (Buf, sizeof (Buf), mCpuTypeList[Count].Name);
> -
> - if (IS_E_PROCESSOR (Svr)) {
> - AsciiStrCatS (Buf, sizeof (Buf), "E");
> - }
> - break;
> - }
> - }
> -
> - DEBUG ((DEBUG_INFO, "SoC: %a (0x%x); Rev %d.%d\n",
> - Buf, Svr, SVR_MAJOR (Svr), SVR_MINOR (Svr)));
> -
> - return;
> -}
> -
> -/*
> - * Dump RCW (Reset Control Word) on console
> - */
> -VOID
> -PrintRCW (
> - VOID
> - )
> -{
> - CCSR_GUR *Base;
> - UINTN Count;
> -
> - Base = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> -
> - /*
> - * Display the RCW, so that no one gets confused as to what RCW
> - * we're actually using for this boot.
> - */
> -
> - DEBUG ((DEBUG_INIT, "Reset Configuration Word (RCW):"));
> - for (Count = 0; Count < ARRAY_SIZE (Base->RcwSr); Count++) {
> - UINT32 Rcw = SwapMmioRead32 ((UINTN)&Base->RcwSr[Count]);
> -
> - if ((Count % 4) == 0) {
> - DEBUG ((DEBUG_INIT, "\n %08x:", Count * 4));
> - }
> -
> - DEBUG ((DEBUG_INIT, " %08x", Rcw));
> - }
> -
> - DEBUG ((DEBUG_INIT, "\n"));
> -}
> -
> /*
> * Setup SMMU in bypass mode
> * and also set its pagesize
> @@ -400,33 +90,6 @@ SmmuInit (
> MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
> }
>
> -/*
> - * Return current Soc Name form mCpuTypeList
> - */
> -CHAR8 *
> -GetSocName (
> - VOID
> - )
> -{
> - UINT8 Count;
> - UINTN Svr;
> - UINTN Ver;
> - CCSR_GUR *GurBase;
> -
> - GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> -
> - Svr = GurRead ((UINTN)&GurBase->Svr);
> - Ver = SVR_SOC_VER (Svr);
> -
> - for (Count = 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) {
> - if ((mCpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
> - return (CHAR8 *)mCpuTypeList[Count].Name;
> - }
> - }
> -
> - return NULL;
> -}
> -
> UINTN
> GetDramSize (
> IN VOID
> diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> index 5a1a7376cd..3d803716c9 100644
> --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> @@ -171,13 +171,5 @@ SocInit (
> DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a on %a)\n",
> (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__));
>
> - PrintCpuInfo ();
> -
> - //
> - // Print Reset control Word
> - //
> - PrintRCW ();
> - PrintSoc ();
> -
> return;
> }
> diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> index 3334d4d4f1..fe77717337 100644
> --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> @@ -30,7 +30,6 @@
> [Sources.common]
> Chassis.c
> Chassis2/Soc.c
> - SerDes.c
>
> [BuildOptions]
> GCC:*_*_*_CC_FLAGS = -DCHASSIS2
> diff --git a/Silicon/NXP/Library/SocLib/SerDes.c b/Silicon/NXP/Library/SocLib/SerDes.c
> deleted file mode 100644
> index b9909d9221..0000000000
> --- a/Silicon/NXP/Library/SocLib/SerDes.c
> +++ /dev/null
> @@ -1,268 +0,0 @@
> -/** SerDes.c
> - Provides the basic interfaces for SerDes Module
> -
> - Copyright 2017-2019 NXP
> -
> - SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#ifdef CHASSIS2
> -#include <Chassis2/LsSerDes.h>
> -#include <Chassis2/NxpSoc.h>
> -#elif CHASSIS3
> -#include <Chassis3/LsSerDes.h>
> -#include <Chassis3/NxpSoc.h>
> -#endif
> -#include <Library/DebugLib.h>
> -#include <SocSerDes.h>
> -#include <Uefi.h>
> -
> -/**
> - Function to get serdes Lane protocol corresponding to
> - serdes protocol.
> -
> - @param SerDes Serdes number.
> - @param Cfg Serdes Protocol.
> - @param Lane Serdes Lane number.
> -
> - @return Serdes Lane protocol.
> -
> -**/
> -STATIC
> -SERDES_PROTOCOL
> -GetSerDesPrtcl (
> - IN INTN SerDes,
> - IN INTN Cfg,
> - IN INTN Lane
> - )
> -{
> - SERDES_CONFIG *Config;
> -
> - if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
> - return 0;
> - }
> -
> - Config = SerDesConfigTbl[SerDes];
> - while (Config->Protocol) {
> - if (Config->Protocol == Cfg) {
> - return Config->SrdsLane[Lane];
> - }
> - Config++;
> - }
> -
> - return EFI_SUCCESS;
> -}
> -
> -/**
> - Function to check if inputted protocol is a valid serdes protocol.
> -
> - @param SerDes Serdes number.
> - @param Prtcl Serdes Protocol to be verified.
> -
> - @return EFI_INVALID_PARAMETER Input parameter in invalid.
> - @return EFI_NOT_FOUND Serdes Protocol not a valid protocol.
> - @return EFI_SUCCESS Serdes Protocol is a valid protocol.
> -
> -**/
> -STATIC
> -EFI_STATUS
> -CheckSerDesPrtclValid (
> - IN INTN SerDes,
> - IN UINT32 Prtcl
> - )
> -{
> - SERDES_CONFIG *Config;
> - INTN Cnt;
> -
> - if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
> - return EFI_INVALID_PARAMETER;
> - }
> -
> - Config = SerDesConfigTbl[SerDes];
> - while (Config->Protocol) {
> - if (Config->Protocol == Prtcl) {
> - DEBUG ((DEBUG_INFO, "Protocol: %x Matched with the one in Table\n", Prtcl));
> - break;
> - }
> - Config++;
> - }
> -
> - if (!Config->Protocol) {
> - return EFI_NOT_FOUND;
> - }
> -
> - for (Cnt = 0; Cnt < SRDS_MAX_LANES; Cnt++) {
> - if (Config->SrdsLane[Cnt] != None) {
> - return EFI_SUCCESS;
> - }
> - }
> -
> - return EFI_NOT_FOUND;
> -}
> -
> -/**
> - Function to fill serdes map information.
> -
> - @param Srds Serdes number.
> - @param SerdesProtocolMask Serdes Protocol Mask.
> - @param SerdesProtocolShift Serdes Protocol shift value.
> - @param SerDesPrtclMap Pointer to Serdes Protocol map.
> -
> -**/
> -STATIC
> -VOID
> -LSSerDesMap (
> - IN UINT32 Srds,
> - IN UINT32 SerdesProtocolMask,
> - IN UINT32 SerdesProtocolShift,
> - OUT UINT64 *SerDesPrtclMap
> - )
> -{
> - CCSR_GUR *Gur;
> - UINT32 SrdsProt;
> - INTN Lane;
> - UINT32 Flag;
> -
> - Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> - *SerDesPrtclMap = 0x0;
> - Flag = 0;
> -
> - SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
> - SrdsProt >>= SerdesProtocolShift;
> -
> - DEBUG ((DEBUG_INFO, "Using SERDES%d Protocol: %d (0x%x)\n",
> - Srds + 1, SrdsProt, SrdsProt));
> -
> - if (EFI_SUCCESS != CheckSerDesPrtclValid (Srds, SrdsProt)) {
> - DEBUG ((DEBUG_ERROR, "SERDES%d[PRTCL] = 0x%x is not valid\n",
> - Srds + 1, SrdsProt));
> - Flag++;
> - }
> -
> - for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
> - SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
> - if (LanePrtcl >= SerdesPrtclCount) {
> - DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
> - Flag++;
> - } else {
> - *SerDesPrtclMap |= (1u << LanePrtcl);
> - }
> - }
> -
> - if (Flag) {
> - DEBUG ((DEBUG_ERROR, "Could not configure SerDes module!!\n"));
> - } else {
> - DEBUG ((DEBUG_INFO, "Successfully configured SerDes module!!\n"));
> - }
> -}
> -
> -/**
> - Get lane protocol on provided serdes lane and execute callback function.
> -
> - @param Srds Serdes number.
> - @param SerdesProtocolMask Mask to get Serdes Protocol for Srds
> - @param SerdesProtocolShift Shift value to get Serdes Protocol for Srds.
> - @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
> - @param Arg Pointer to Arguments to be passed to callback function.
> -
> -**/
> -STATIC
> -VOID
> -SerDesInstanceProbeLanes (
> - IN UINT32 Srds,
> - IN UINT32 SerdesProtocolMask,
> - IN UINT32 SerdesProtocolShift,
> - IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
> - IN VOID *Arg
> - )
> -{
> -
> - CCSR_GUR *Gur;
> - UINT32 SrdsProt;
> - INTN Lane;
> -
> - Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);;
> -
> - SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
> - SrdsProt >>= SerdesProtocolShift;
> -
> - /*
> - * Invoke callback for all lanes in the SerDes instance:
> - */
> - for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
> - SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
> - if ((LanePrtcl >= SerdesPrtclCount) || (LanePrtcl < None)) {
> - DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
> - } else if (LanePrtcl != None) {
> - SerDesLaneProbeCallback (LanePrtcl, Arg);
> - }
> - }
> -}
> -
> -/**
> - Probe all serdes lanes for lane protocol and execute provided callback function.
> -
> - @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
> - @param Arg Pointer to Arguments to be passed to callback function.
> -
> -**/
> -VOID
> -SerDesProbeLanes (
> - IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
> - IN VOID *Arg
> - )
> -{
> - SerDesInstanceProbeLanes (Srds1,
> - RCWSR_SRDS1_PRTCL_MASK,
> - RCWSR_SRDS1_PRTCL_SHIFT,
> - SerDesLaneProbeCallback,
> - Arg);
> -
> - if (PcdGetBool (PcdSerdes2Enabled)) {
> - SerDesInstanceProbeLanes (Srds2,
> - RCWSR_SRDS2_PRTCL_MASK,
> - RCWSR_SRDS2_PRTCL_SHIFT,
> - SerDesLaneProbeCallback,
> - Arg);
> - }
> -}
> -
> -/**
> - Function to return Serdes protocol map for all serdes available on board.
> -
> - @param SerDesPrtclMap Pointer to Serdes protocl map.
> -
> -**/
> -VOID
> -GetSerdesProtocolMaps (
> - OUT UINT64 *SerDesPrtclMap
> - )
> -{
> - LSSerDesMap (Srds1,
> - RCWSR_SRDS1_PRTCL_MASK,
> - RCWSR_SRDS1_PRTCL_SHIFT,
> - SerDesPrtclMap);
> -
> - if (PcdGetBool (PcdSerdes2Enabled)) {
> - LSSerDesMap (Srds2,
> - RCWSR_SRDS2_PRTCL_MASK,
> - RCWSR_SRDS2_PRTCL_SHIFT,
> - SerDesPrtclMap);
> - }
> -
> -}
> -
> -BOOLEAN
> -IsSerDesLaneProtocolConfigured (
> - IN UINT64 SerDesPrtclMap,
> - IN SERDES_PROTOCOL Device
> - )
> -{
> - if ((Device >= SerdesPrtclCount) || (Device < None)) {
> - ASSERT ((Device > None) && (Device < SerdesPrtclCount));
> - DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol Device %d\n", Device));
> - }
> -
> - return (SerDesPrtclMap & (1u << Device)) != 0 ;
> -}
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 07/19] Silicon/NXP: remove not needed components
2020-02-07 12:43 ` [PATCH 07/19] Silicon/NXP: remove not needed components Pankaj Bansal
@ 2020-02-10 17:11 ` Leif Lindholm
2020-02-11 7:24 ` Pankaj Bansal
0 siblings, 1 reply; 49+ messages in thread
From: Leif Lindholm @ 2020-02-10 17:11 UTC (permalink / raw)
To: Pankaj Bansal; +Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi, devel
On Fri, Feb 07, 2020 at 18:13:16 +0530, Pankaj Bansal wrote:
> We are changing the directory structure of code.
> After PEI phase impelmentation this info would be put back
> into appropriate location.
The message needs clarifying:
What is being deleted, why is this not a problem, and what is being
put back?
/
Leif
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> Silicon/NXP/Include/Chassis2/NxpSoc.h | 314 +---------------------
> Silicon/NXP/Library/SocLib/Chassis.c | 15 --
> Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 79 ------
> 3 files changed, 2 insertions(+), 406 deletions(-)
>
> diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> index f05a813750..74330b6205 100644
> --- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
> +++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> @@ -1,7 +1,7 @@
> /** Soc.h
> * Header defining the Base addresses, sizes, flags etc for chassis 1
> *
> -* Copyright 2017-2019 NXP
> +* Copyright 2017-2020 NXP
> *
> * SPDX-License-Identifier: BSD-2-Clause-Patent
> *
> @@ -10,22 +10,7 @@
> #ifndef NXP_SOC_H_
> #define NXP_SOC_H_
>
> -#define HWA_CGA_M1_CLK_SEL 0xe0000000
> -#define HWA_CGA_M1_CLK_SHIFT 29
> -
> -#define TP_CLUSTER_EOC_MASK 0xc0000000 /* end of clusters mask */
> -#define NUM_CC_PLLS 2
> #define CLK_FREQ 100000000
> -#define MAX_CPUS 4
> -#define NUM_FMAN 1
> -#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) == 0x0)
> -
> -/* RCW SERDES MACRO */
> -#define RCWSR_INDEX 4
> -#define RCWSR_SRDS1_PRTCL_MASK 0xffff0000
> -#define RCWSR_SRDS1_PRTCL_SHIFT 16
> -#define RCWSR_SRDS2_PRTCL_MASK 0x0000ffff
> -#define RCWSR_SRDS2_PRTCL_SHIFT 0
>
> /* SMMU Defintions */
> #define SMMU_BASE_ADDR 0x09000000
> @@ -41,312 +26,17 @@
> #define IDR1_PAGESIZE_MASK 0x80000000
>
> typedef struct {
> - UINTN FreqProcessor[MAX_CPUS];
> UINTN FreqSystemBus;
> - UINTN FreqDdrBus;
> - UINTN FreqLocalBus;
> - UINTN FreqSdhc;
> - UINTN FreqFman[NUM_FMAN];
> - UINTN FreqQman;
> } SYS_INFO;
>
> /* Device Configuration and Pin Control */
> typedef struct {
> - UINT32 PorSr1; /* POR status 1 */
> -#define CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
> - UINT32 PorSr2; /* POR status 2 */
> - UINT8 Res008[0x20-0x8];
> - UINT32 GppOrCr1; /* General-purpose POR configuration */
> - UINT32 GppOrCr2;
> - UINT32 DcfgFuseSr; /* Fuse status register */
> - UINT8 Res02c[0x70-0x2c];
> - UINT32 DevDisr; /* Device disable control */
> - UINT32 DevDisr2; /* Device disable control 2 */
> - UINT32 DevDisr3; /* Device disable control 3 */
> - UINT32 DevDisr4; /* Device disable control 4 */
> - UINT32 DevDisr5; /* Device disable control 5 */
> - UINT32 DevDisr6; /* Device disable control 6 */
> - UINT32 DevDisr7; /* Device disable control 7 */
> - UINT8 Res08c[0x94-0x8c];
> - UINT32 CoreDisrU; /* uppper portion for support of 64 cores */
> - UINT32 CoreDisrL; /* lower portion for support of 64 cores */
> - UINT8 Res09c[0xa0-0x9c];
> - UINT32 Pvr; /* Processor version */
> - UINT32 Svr; /* System version */
> - UINT32 Mvr; /* Manufacturing version */
> - UINT8 Res0ac[0xb0-0xac];
> - UINT32 RstCr; /* Reset control */
> - UINT32 RstRqPblSr; /* Reset request preboot loader status */
> - UINT8 Res0b8[0xc0-0xb8];
> - UINT32 RstRqMr1; /* Reset request mask */
> - UINT8 Res0c4[0xc8-0xc4];
> - UINT32 RstRqSr1; /* Reset request status */
> - UINT8 Res0cc[0xd4-0xcc];
> - UINT32 RstRqWdTmrL; /* Reset request WDT mask */
> - UINT8 Res0d8[0xdc-0xd8];
> - UINT32 RstRqWdtSrL; /* Reset request WDT status */
> - UINT8 Res0e0[0xe4-0xe0];
> - UINT32 BrrL; /* Boot release */
> - UINT8 Res0e8[0x100-0xe8];
> + UINT8 Res0[0x100-0x00];
> UINT32 RcwSr[16]; /* Reset control word status */
> #define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
> #define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
> -#define CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16
> -#define CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
> - UINT8 Res140[0x200-0x140];
> - UINT32 ScratchRw[4]; /* Scratch Read/Write */
> - UINT8 Res210[0x300-0x210];
> - UINT32 ScratcHw1R[4]; /* Scratch Read (Write once) */
> - UINT8 Res310[0x400-0x310];
> - UINT32 CrstSr[12];
> - UINT8 Res430[0x500-0x430];
> - /* PCI Express n Logical I/O Device Number register */
> - UINT32 DcfgCcsrPex1LiodNr;
> - UINT32 DcfgCcsrPex2LiodNr;
> - UINT32 DcfgCcsrPex3LiodNr;
> - UINT32 DcfgCcsrPex4LiodNr;
> - /* RIO n Logical I/O Device Number register */
> - UINT32 DcfgCcsrRio1LiodNr;
> - UINT32 DcfgCcsrRio2LiodNr;
> - UINT32 DcfgCcsrRio3LiodNr;
> - UINT32 DcfgCcsrRio4LiodNr;
> - /* USB Logical I/O Device Number register */
> - UINT32 DcfgCcsrUsb1LiodNr;
> - UINT32 DcfgCcsrUsb2LiodNr;
> - UINT32 DcfgCcsrUsb3LiodNr;
> - UINT32 DcfgCcsrUsb4LiodNr;
> - /* SD/MMC Logical I/O Device Number register */
> - UINT32 DcfgCcsrSdMmc1LiodNr;
> - UINT32 DcfgCcsrSdMmc2LiodNr;
> - UINT32 DcfgCcsrSdMmc3LiodNr;
> - UINT32 DcfgCcsrSdMmc4LiodNr;
> - /* RIO Message Unit Logical I/O Device Number register */
> - UINT32 DcfgCcsrRiomaintLiodNr;
> - UINT8 Res544[0x550-0x544];
> - UINT32 SataLiodNr[4];
> - UINT8 Res560[0x570-0x560];
> - UINT32 DcfgCcsrMisc1LiodNr;
> - UINT32 DcfgCcsrMisc2LiodNr;
> - UINT32 DcfgCcsrMisc3LiodNr;
> - UINT32 DcfgCcsrMisc4LiodNr;
> - UINT32 DcfgCcsrDma1LiodNr;
> - UINT32 DcfgCcsrDma2LiodNr;
> - UINT32 DcfgCcsrDma3LiodNr;
> - UINT32 DcfgCcsrDma4LiodNr;
> - UINT32 DcfgCcsrSpare1LiodNr;
> - UINT32 DcfgCcsrSpare2LiodNr;
> - UINT32 DcfgCcsrSpare3LiodNr;
> - UINT32 DcfgCcsrSpare4LiodNr;
> - UINT8 Res5a0[0x600-0x5a0];
> - UINT32 DcfgCcsrPblSr;
> - UINT32 PamuBypENr;
> - UINT32 DmaCr1;
> - UINT8 Res60c[0x610-0x60c];
> - UINT32 DcfgCcsrGenSr1;
> - UINT32 DcfgCcsrGenSr2;
> - UINT32 DcfgCcsrGenSr3;
> - UINT32 DcfgCcsrGenSr4;
> - UINT32 DcfgCcsrGenCr1;
> - UINT32 DcfgCcsrGenCr2;
> - UINT32 DcfgCcsrGenCr3;
> - UINT32 DcfgCcsrGenCr4;
> - UINT32 DcfgCcsrGenCr5;
> - UINT32 DcfgCcsrGenCr6;
> - UINT32 DcfgCcsrGenCr7;
> - UINT8 Res63c[0x658-0x63c];
> - UINT32 DcfgCcsrcGenSr1;
> - UINT32 DcfgCcsrcGenSr0;
> - UINT8 Res660[0x678-0x660];
> - UINT32 DcfgCcsrcGenCr1;
> - UINT32 DcfgCcsrcGenCr0;
> - UINT8 Res680[0x700-0x680];
> - UINT32 DcfgCcsrSrIoPstecr;
> - UINT32 DcfgCcsrDcsrCr;
> - UINT8 Res708[0x740-0x708]; /* add more registers when needed */
> - UINT32 TpItyp[64]; /* Topology Initiator Type Register */
> - struct {
> - UINT32 Upper;
> - UINT32 Lower;
> - } TpCluster[16];
> - UINT8 Res8c0[0xa00-0x8c0]; /* add more registers when needed */
> - UINT32 DcfgCcsrQmBmWarmRst;
> - UINT8 Resa04[0xa20-0xa04]; /* add more registers when needed */
> - UINT32 DcfgCcsrReserved0;
> - UINT32 DcfgCcsrReserved1;
> } CCSR_GUR;
>
> -/* Supplemental Configuration Unit */
> -typedef struct {
> - UINT8 Res000[0x070-0x000];
> - UINT32 Usb1Prm1Cr;
> - UINT32 Usb1Prm2Cr;
> - UINT32 Usb1Prm3Cr;
> - UINT32 Usb2Prm1Cr;
> - UINT32 Usb2Prm2Cr;
> - UINT32 Usb2Prm3Cr;
> - UINT32 Usb3Prm1Cr;
> - UINT32 Usb3Prm2Cr;
> - UINT32 Usb3Prm3Cr;
> - UINT8 Res094[0x100-0x094];
> - UINT32 Usb2Icid;
> - UINT32 Usb3Icid;
> - UINT8 Res108[0x114-0x108];
> - UINT32 DmaIcid;
> - UINT32 SataIcid;
> - UINT32 Usb1Icid;
> - UINT32 QeIcid;
> - UINT32 SdhcIcid;
> - UINT32 EdmaIcid;
> - UINT32 EtrIcid;
> - UINT32 Core0SftRst;
> - UINT32 Core1SftRst;
> - UINT32 Core2SftRst;
> - UINT32 Core3SftRst;
> - UINT8 Res140[0x158-0x140];
> - UINT32 AltCBar;
> - UINT32 QspiCfg;
> - UINT8 Res160[0x180-0x160];
> - UINT32 DmaMcr;
> - UINT8 Res184[0x188-0x184];
> - UINT32 GicAlign;
> - UINT32 DebugIcid;
> - UINT8 Res190[0x1a4-0x190];
> - UINT32 SnpCnfGcr;
> -#define CCSR_SCFG_SNPCNFGCR_SECRDSNP BIT31
> -#define CCSR_SCFG_SNPCNFGCR_SECWRSNP BIT30
> -#define CCSR_SCFG_SNPCNFGCR_SATARDSNP BIT23
> -#define CCSR_SCFG_SNPCNFGCR_SATAWRSNP BIT22
> -#define CCSR_SCFG_SNPCNFGCR_USB1RDSNP BIT21
> -#define CCSR_SCFG_SNPCNFGCR_USB1WRSNP BIT20
> -#define CCSR_SCFG_SNPCNFGCR_USB2RDSNP BIT15
> -#define CCSR_SCFG_SNPCNFGCR_USB2WRSNP BIT16
> -#define CCSR_SCFG_SNPCNFGCR_USB3RDSNP BIT13
> -#define CCSR_SCFG_SNPCNFGCR_USB3WRSNP BIT14
> - UINT8 Res1a8[0x1ac-0x1a8];
> - UINT32 IntpCr;
> - UINT8 Res1b0[0x204-0x1b0];
> - UINT32 CoreSrEnCr;
> - UINT8 Res208[0x220-0x208];
> - UINT32 RvBar00;
> - UINT32 RvBar01;
> - UINT32 RvBar10;
> - UINT32 RvBar11;
> - UINT32 RvBar20;
> - UINT32 RvBar21;
> - UINT32 RvBar30;
> - UINT32 RvBar31;
> - UINT32 LpmCsr;
> - UINT8 Res244[0x400-0x244];
> - UINT32 QspIdQScr;
> - UINT32 EcgTxcMcr;
> - UINT32 SdhcIoVSelCr;
> - UINT32 RcwPMuxCr0;
> - /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
> - *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
> - *Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS
> - Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS*/
> -#define CCSR_SCFG_RCWPMUXCRO_SELCR_USB 0x3333
> - /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
> - *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
> - *Setting RCW PinMux Register bits 25-27 to select IIC4_SCL
> - Setting RCW PinMux Register bits 29-31 to select IIC4_SDA*/
> -#define CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300
> - UINT32 UsbDrvVBusSelCr;
> -#define CCSR_SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
> -#define CCSR_SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
> -#define CCSR_SCFG_USBDRVVBUS_SELCR_USB3 0x00000003
> - UINT32 UsbPwrFaultSelCr;
> -#define CCSR_SCFG_USBPWRFAULT_INACTIVE 0x00000000
> -#define CCSR_SCFG_USBPWRFAULT_SHARED 0x00000001
> -#define CCSR_SCFG_USBPWRFAULT_DEDICATED 0x00000002
> -#define CCSR_SCFG_USBPWRFAULT_USB3_SHIFT 4
> -#define CCSR_SCFG_USBPWRFAULT_USB2_SHIFT 2
> -#define CCSR_SCFG_USBPWRFAULT_USB1_SHIFT 0
> - UINT32 UsbRefclkSelcr1;
> - UINT32 UsbRefclkSelcr2;
> - UINT32 UsbRefclkSelcr3;
> - UINT8 Res424[0x600-0x424];
> - UINT32 ScratchRw[4];
> - UINT8 Res610[0x680-0x610];
> - UINT32 CoreBCr;
> - UINT8 Res684[0x1000-0x684];
> - UINT32 Pex1MsiIr;
> - UINT32 Pex1MsiR;
> - UINT8 Res1008[0x2000-0x1008];
> - UINT32 Pex2;
> - UINT32 Pex2MsiR;
> - UINT8 Res2008[0x3000-0x2008];
> - UINT32 Pex3MsiIr;
> - UINT32 Pex3MsiR;
> -} CCSR_SCFG;
> -
> -#define USB_TXVREFTUNE 0x9
> -#define USB_SQRXTUNE 0xFC7FFFFF
> -#define USB_PCSTXSWINGFULL 0x47
> -#define USB_PHY_RX_EQ_VAL_1 0x0000
> -#define USB_PHY_RX_EQ_VAL_2 0x8000
> -#define USB_PHY_RX_EQ_VAL_3 0x8003
> -#define USB_PHY_RX_EQ_VAL_4 0x800b
> -
> -/*USB_PHY_SS memory map*/
> -typedef struct {
> - UINT16 IpIdcodeLo;
> - UINT16 SupIdcodeHi;
> - UINT8 Res4[0x0006-0x0004];
> - UINT16 RtuneDebug;
> - UINT16 RtuneStat;
> - UINT16 SupSsPhase;
> - UINT16 SsFreq;
> - UINT8 ResE[0x0020-0x000e];
> - UINT16 Ateovrd;
> - UINT16 MpllOvrdInLo;
> - UINT8 Res24[0x0026-0x0024];
> - UINT16 SscOvrdIn;
> - UINT8 Res28[0x002A-0x0028];
> - UINT16 LevelOvrdIn;
> - UINT8 Res2C[0x0044-0x002C];
> - UINT16 ScopeCount;
> - UINT8 Res46[0x0060-0x0046];
> - UINT16 MpllLoopCtl;
> - UINT8 Res62[0x006C-0x0062];
> - UINT16 SscClkCntrl;
> - UINT8 Res6E[0x2002-0x006E];
> - UINT16 Lane0TxOvrdInHi;
> - UINT16 Lane0TxOvrdDrvLo;
> - UINT8 Res2006[0x200C-0x2006];
> - UINT16 Lane0RxOvrdInHi;
> - UINT8 Res200E[0x2022-0x200E];
> - UINT16 Lane0TxCmWaitTimeOvrd;
> - UINT8 Res2024[0x202A-0x2024];
> - UINT16 Lane0TxLbertCtl;
> - UINT16 Lane0RxLbertCtl;
> - UINT16 Lane0RxLbertErr;
> - UINT8 Res2030[0x205A-0x2030];
> - UINT16 Lane0TxAltBlock;
> -} CCSR_USB_PHY;
> -
> -/* Clocking */
> -typedef struct {
> - struct {
> - UINT32 ClkCnCSr; /* core cluster n clock control status */
> - UINT8 Res004[0x0c];
> - UINT32 ClkcGHwAcSr; /* Clock generator n hardware accelerator */
> - UINT8 Res014[0x0c];
> - } ClkcSr[4];
> - UINT8 Res040[0x780]; /* 0x100 */
> - struct {
> - UINT32 PllCnGSr;
> - UINT8 Res804[0x1c];
> - } PllCgSr[NUM_CC_PLLS];
> - UINT8 Res840[0x1c0];
> - UINT32 ClkPCSr; /* 0xa00 Platform clock domain control/status */
> - UINT8 Resa04[0x1fc];
> - UINT32 PllPGSr; /* 0xc00 Platform PLL General Status */
> - UINT8 Resc04[0x1c];
> - UINT32 PllDGSr; /* 0xc20 DDR PLL General Status */
> - UINT8 Resc24[0x3dc];
> -} CCSR_CLOCK;
> -
> VOID
> GetSysInfo (
> OUT SYS_INFO *
> diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
> index 18a1f5e4e1..847331a631 100644
> --- a/Silicon/NXP/Library/SocLib/Chassis.c
> +++ b/Silicon/NXP/Library/SocLib/Chassis.c
> @@ -53,21 +53,6 @@ GetBusFrequency (
> return SocSysInfo.FreqSystemBus;
> }
>
> -/*
> - * Return SDXC bus frequency
> - */
> -UINT64
> -GetSdxcFrequency (
> - VOID
> - )
> -{
> - SYS_INFO SocSysInfo;
> -
> - GetSysInfo (&SocSysInfo);
> -
> - return SocSysInfo.FreqSdhc;
> -}
> -
> /*
> * Setup SMMU in bypass mode
> * and also set its pagesize
> diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> index 3d803716c9..9baeb17ecf 100644
> --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> @@ -32,38 +32,14 @@ GetSysInfo (
> )
> {
> CCSR_GUR *GurBase;
> - CCSR_CLOCK *ClkBase;
> - UINTN CpuIndex;
> - UINT32 TempRcw;
> - UINT32 CPllSel;
> - UINT32 CplxPll;
> - CONST UINT8 CoreCplxPll[8] = {
> - [0] = 0, /* CC1 PPL / 1 */
> - [1] = 0, /* CC1 PPL / 2 */
> - [4] = 1, /* CC2 PPL / 1 */
> - [5] = 1, /* CC2 PPL / 2 */
> - };
> -
> - CONST UINT8 CoreCplxPllDivisor[8] = {
> - [0] = 1, /* CC1 PPL / 1 */
> - [1] = 2, /* CC1 PPL / 2 */
> - [4] = 1, /* CC2 PPL / 1 */
> - [5] = 2, /* CC2 PPL / 2 */
> - };
> -
> - UINTN PllCount;
> - UINTN FreqCPll[NUM_CC_PLLS];
> - UINTN PllRatio[NUM_CC_PLLS];
> UINTN SysClk;
>
> GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> - ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
> SysClk = CLK_FREQ;
>
> SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
>
> PtrSysInfo->FreqSystemBus = SysClk;
> - PtrSysInfo->FreqDdrBus = SysClk;
>
> //
> // selects the platform clock:SYSCLK ratio and calculate
> @@ -72,61 +48,6 @@ GetSysInfo (
> PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
> CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
> CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
> - //
> - // selects the DDR PLL:SYSCLK Ratio and calculate DDR frequency
> - //
> - PtrSysInfo->FreqDdrBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
> - CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
> - CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
> -
> - for (PllCount = 0; PllCount < NUM_CC_PLLS; PllCount++) {
> - PllRatio[PllCount] = (GurRead ((UINTN)&ClkBase->PllCgSr[PllCount].PllCnGSr) >> 1) & 0xff;
> - if (PllRatio[PllCount] > 4) {
> - FreqCPll[PllCount] = SysClk * PllRatio[PllCount];
> - } else {
> - FreqCPll[PllCount] = PtrSysInfo->FreqSystemBus * PllRatio[PllCount];
> - }
> - }
> -
> - //
> - // Calculate Core frequency
> - //
> - for (CpuIndex = 0; CpuIndex < MAX_CPUS; CpuIndex++) {
> - CPllSel = (GurRead ((UINTN)&ClkBase->ClkcSr[CpuIndex].ClkCnCSr) >> 27) & 0xf;
> - CplxPll = CoreCplxPll[CPllSel];
> -
> - PtrSysInfo->FreqProcessor[CpuIndex] = FreqCPll[CplxPll] / CoreCplxPllDivisor[CPllSel];
> - }
> -
> - //
> - // Calculate FMAN frequency
> - //
> - TempRcw = GurRead ((UINTN)&GurBase->RcwSr[7]);
> - switch ((TempRcw & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
> - case 2:
> - PtrSysInfo->FreqFman[0] = FreqCPll[0] / 2;
> - break;
> - case 3:
> - PtrSysInfo->FreqFman[0] = FreqCPll[0] / 3;
> - break;
> - case 4:
> - PtrSysInfo->FreqFman[0] = FreqCPll[0] / 4;
> - break;
> - case 5:
> - PtrSysInfo->FreqFman[0] = PtrSysInfo->FreqSystemBus;
> - break;
> - case 6:
> - PtrSysInfo->FreqFman[0] = FreqCPll[1] / 2;
> - break;
> - case 7:
> - PtrSysInfo->FreqFman[0] = FreqCPll[1] / 3;
> - break;
> - default:
> - DEBUG ((DEBUG_WARN, "Error: Unknown FMan1 clock select!\n"));
> - break;
> - }
> - PtrSysInfo->FreqSdhc = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
> - PtrSysInfo->FreqQman = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
> }
>
> /**
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 08/19] Silicon/NXP: Remove unnecessary PCDs
2020-02-07 12:43 ` [PATCH 08/19] Silicon/NXP: Remove unnecessary PCDs Pankaj Bansal
@ 2020-02-10 17:32 ` Leif Lindholm
2020-02-11 8:45 ` Pankaj Bansal
0 siblings, 1 reply; 49+ messages in thread
From: Leif Lindholm @ 2020-02-10 17:32 UTC (permalink / raw)
To: Pankaj Bansal; +Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi, devel
On Fri, Feb 07, 2020 at 18:13:17 +0530, Pankaj Bansal wrote:
> There is no need to keep SOC specific PCDs defined for each SOC.
That sound like the definition of why we have SoC-specific Pcds, so I
don't follow.
> we can do away with these PCDs.
After looking through this patchset, it looks like:
1) Initial implementation defined a bunch of things as Pcds which
really cannot vary between different platforms using the same SoC.
2) This patch moves several things that can differ between platforms
into #defines, when they should be Pcds.
I am OK with the 1)s, but there are some you would need to convince me
are not 2:s.
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> .../Drivers/PlatformDxe/PlatformDxe.c | 15 +--
> .../Drivers/PlatformDxe/PlatformDxe.inf | 8 +-
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 1 -
> .../Library/PlatformLib/ArmPlatformLib.inf | 21 +---
> .../Library/PlatformLib/NxpQoriqLsMem.c | 103 +++++++++---------
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 6 -
> Silicon/NXP/Include/Chassis2/NxpSoc.h | 2 +
> Silicon/NXP/LS1043A/Include/Soc.h | 44 ++++++++
> Silicon/NXP/LS1043A/LS1043A.dsc.inc | 32 ------
> Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 2 +-
> Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 4 -
> Silicon/NXP/NxpQoriqLs.dec | 74 -------------
> 12 files changed, 108 insertions(+), 204 deletions(-)
> create mode 100644 Silicon/NXP/LS1043A/Include/Soc.h
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> index f89dcdeff3..62c400eb1a 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> +++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> @@ -1,7 +1,7 @@
> /** @file
> LS1043 DXE platform driver.
>
> - Copyright 2018-2019 NXP
> + Copyright 2018-2020 NXP
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -14,6 +14,7 @@
> #include <Library/PcdLib.h>
> #include <Library/UefiBootServicesTableLib.h>
> #include <Library/UefiLib.h>
> +#include <Soc.h>
>
> #include <Protocol/NonDiscoverableDevice.h>
>
> @@ -22,7 +23,7 @@ typedef struct {
> UINT8 EndDesc;
> } ADDRESS_SPACE_DESCRIPTOR;
>
> -STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[FixedPcdGet64 (PcdNumI2cController)];
> +STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[LS1043A_I2C_NUM_CONTROLLERS];
Sure, this one sounds like something not configurable in software or
board design.
>
> STATIC
> EFI_STATUS
> @@ -65,19 +66,19 @@ PopulateI2cInformation (
> {
> UINT32 Index;
>
> - for (Index = 0; Index < FixedPcdGet32 (PcdNumI2cController); Index++) {
> + for (Index = 0; Index < ARRAY_SIZE (mI2cDesc); Index++) {
> mI2cDesc[Index].StartDesc.Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
> mI2cDesc[Index].StartDesc.Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
> mI2cDesc[Index].StartDesc.ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
> mI2cDesc[Index].StartDesc.GenFlag = 0;
> mI2cDesc[Index].StartDesc.SpecificFlag = 0;
> mI2cDesc[Index].StartDesc.AddrSpaceGranularity = 32;
> - mI2cDesc[Index].StartDesc.AddrRangeMin = FixedPcdGet64 (PcdI2c0BaseAddr) +
> - (Index * FixedPcdGet32 (PcdI2cSize));
As does this.
> + mI2cDesc[Index].StartDesc.AddrRangeMin = LS1043A_I2C0_PHYS_ADDRESS +
> + (Index * LS1043A_I2C_SIZE);
> mI2cDesc[Index].StartDesc.AddrRangeMax = mI2cDesc[Index].StartDesc.AddrRangeMin +
> - FixedPcdGet32 (PcdI2cSize) - 1;
> + LS1043A_I2C_SIZE - 1;
> mI2cDesc[Index].StartDesc.AddrTranslationOffset = 0;
> - mI2cDesc[Index].StartDesc.AddrLen = FixedPcdGet32 (PcdI2cSize);
> + mI2cDesc[Index].StartDesc.AddrLen = LS1043A_I2C_SIZE;
>
> mI2cDesc[Index].EndDesc = ACPI_END_TAG_DESCRIPTOR;
> }
> diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> index d689cf4db5..126a1174fa 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> +++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> @@ -2,7 +2,7 @@
> #
> # Component description file for LS1043 DXE platform driver.
> #
> -# Copyright 2018-2019 NXP
> +# Copyright 2018-2020 NXP
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -25,6 +25,7 @@
> MdeModulePkg/MdeModulePkg.dec
> Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
> Silicon/NXP/NxpQoriqLs.dec
> + Silicon/NXP/LS1043A/LS1043A.dec
Please insert sorted alphabetically.
>
> [LibraryClasses]
> BaseLib
> @@ -43,10 +44,5 @@
> gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES
> gDs1307RealTimeClockLibI2cMasterProtocolGuid ## PRODUCES
>
> -[FixedPcd]
> - gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
> - gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
> - gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
Still good.
> -
> [Depex]
> TRUE
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> index 802cccdce6..74a1948fc6 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> @@ -42,7 +42,6 @@
> #
> # Board Specific Pcds
> #
> - gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
But this sounds exactly like the kind of thing that would be
configured differently for different boards. Can you please explain
why this should be removed?
> gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
>
> #
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> index f7ae74afc6..054dc4d003 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> @@ -1,7 +1,7 @@
> # @file
> #
> # Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> -# Copyright 2017, 2019 NXP
> +# Copyright 2017, 2019-2020 NXP
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -20,6 +20,7 @@
> EmbeddedPkg/EmbeddedPkg.dec
> MdePkg/MdePkg.dec
> Silicon/NXP/NxpQoriqLs.dec
> + Silicon/NXP/LS1043A/LS1043A.dec
Insert sorted.
>
> [LibraryClasses]
> ArmLib
> @@ -35,21 +36,3 @@
>
> [FixedPcd]
> gArmTokenSpaceGuid.PcdArmPrimaryCore
> - gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
> - gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
> - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr
> - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize
> - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr
> - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
> - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
> - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> index c6c256da07..3a72c8bdd8 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> @@ -6,7 +6,7 @@
> *
> * Copyright (c) 2011, ARM Limited. All rights reserved.
> * Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> -* Copyright 2017, 2019 NXP
> +* Copyright 2017, 2019-2020 NXP
> *
> * SPDX-License-Identifier: BSD-2-Clause-Patent
> *
> @@ -16,7 +16,7 @@
> #include <Library/DebugLib.h>
> #include <Library/PcdLib.h>
> #include <Library/MemoryAllocationLib.h>
> -#include <DramInfo.h>
> +#include <Soc.h>
>
> #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
>
> @@ -38,7 +38,6 @@ ArmPlatformGetVirtualMemoryMap (
> {
> UINTN Index;
> ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
> - DRAM_INFO DramInfo;
>
> Index = 0;
>
> @@ -51,25 +50,21 @@ ArmPlatformGetVirtualMemoryMap (
> return;
> }
>
> - if (GetDramBankInfo (&DramInfo)) {
> - DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n"));
> - return;
> - }
> + VirtualMemoryTable[Index].PhysicalBase = LS1043A_DRAM0_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LS1043A_DRAM0_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LS1043A_DRAM0_SIZE;
> + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
>
> -
> - for (Index = 0; Index < DramInfo.NumOfDrams; Index++) {
> - // DRAM1 (Must be 1st entry)
> - VirtualMemoryTable[Index].PhysicalBase = DramInfo.DramRegion[Index].BaseAddress;
> - VirtualMemoryTable[Index].VirtualBase = DramInfo.DramRegion[Index].BaseAddress;
> - VirtualMemoryTable[Index].Length = DramInfo.DramRegion[Index].Size;
> - VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> - }
> + VirtualMemoryTable[Index].PhysicalBase = LS1043A_DRAM1_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LS1043A_DRAM1_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LS1043A_DRAM1_SIZE;
> + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
No changes to this file so far appear to have anything to do with what
the commit message says the patch does.
>
> // CCSR Space
> - VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdCcsrBaseAddr);
> - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdCcsrBaseAddr);
> - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
> - VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> + VirtualMemoryTable[Index].PhysicalBase = LS1043A_CCSR_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LS1043A_CCSR_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LS1043A_CCSR_SIZE;
> + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
If these are not reconfigurable for different platforms, sure.
>
> // IFC region 1
> //
> @@ -85,60 +80,60 @@ ArmPlatformGetVirtualMemoryMap (
> // For write transactions from non-core masters (like system DMA), the address
> // should be 16 byte aligned and the data size should be multiple of 16 bytes.
> //
> - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
> - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
> - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion1Size);
> - VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> + VirtualMemoryTable[Index].PhysicalBase = LS1043A_IFC0_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LS1043A_IFC0_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LS1043A_IFC0_SIZE;
> + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
If these are not reconfigurable for different platforms, sure.
>
> // QMAN SWP
> - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
> - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
> - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQmanSwpSize);
> - VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> + VirtualMemoryTable[Index].PhysicalBase = LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LS1043A_QMAN_SW_PORTAL_SIZE;
> + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
>
If these are not reconfigurable for different platforms, sure.
> // BMAN SWP
> - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
> - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
> - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdBmanSwpSize);
> - VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> + VirtualMemoryTable[Index].PhysicalBase = LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LS1043A_QMAN_SW_PORTAL_SIZE;
> + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
>
If these are not reconfigurable for different platforms, sure.
> // IFC region 2
> - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
> - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
> - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion2Size);
> - VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> + VirtualMemoryTable[Index].PhysicalBase = LS1043A_IFC1_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LS1043A_IFC1_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LS1043A_IFC1_SIZE;
> + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>
If these are not reconfigurable for different platforms, sure.
> // PCIe1
> - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
> - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
> - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp1BaseSize);
> - VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> + VirtualMemoryTable[Index].PhysicalBase = LS1043A_PCI0_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI0_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
> + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>
If these are not reconfigurable for different platforms, sure.
> // PCIe2
> - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
> - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
> - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp2BaseSize);
> - VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> + VirtualMemoryTable[Index].PhysicalBase = LS1043A_PCI1_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI1_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
> + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>
If these are not reconfigurable for different platforms, sure.
> // PCIe3
> - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
> - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
> - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp3BaseSize);
> - VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> + VirtualMemoryTable[Index].PhysicalBase = LS1043A_PCI2_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI2_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
> + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
If these are not reconfigurable for different platforms, sure.
>
> // QSPI region
> - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
> - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
> - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegionSize);
> - VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> + VirtualMemoryTable[Index].PhysicalBase = LS1043A_QSPI_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LS1043A_QSPI_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LS1043A_QSPI_SIZE;
> + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
If these are not reconfigurable for different platforms, sure.
>
> // End of Table
> - VirtualMemoryTable[++Index].PhysicalBase = 0;
> + VirtualMemoryTable[Index].PhysicalBase = 0;
Move that ++ back where it belongs - there is no functional change
here.
> VirtualMemoryTable[Index].VirtualBase = 0;
> VirtualMemoryTable[Index].Length = 0;
> - VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
> + VirtualMemoryTable[Index++].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
Move that ++ back where it belongs - there is no functional change
here.
>
> - ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
> + ASSERT (Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
Drop that +1 = - there is no functional change here.
If you want to submit separate patches for coding style changes,
that's fine. But given that this set looks like it's making up for not
synchronising internal development with the (very long) upstreaming
effort so far, I am not interested in those until all functional
changes are in.
>
> *VirtualMemoryMap = VirtualMemoryTable;
> }
> diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> index 784139065f..fc4bb618fa 100644
> --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> @@ -49,11 +49,5 @@
> gEdkiiNonDiscoverableDeviceProtocolGuid ## TO_START
> gEfiI2cMasterProtocolGuid ## BY_START
>
> -[Pcd]
> - gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed
> - gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
> - gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
> - gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
> -
> [Depex]
> TRUE
> diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> index 74330b6205..6812beafe4 100644
> --- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
> +++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> @@ -12,6 +12,8 @@
>
> #define CLK_FREQ 100000000
>
> +#define CHASSIS2_DCFG_ADDRESS 0x1EE0000
> +
> /* SMMU Defintions */
> #define SMMU_BASE_ADDR 0x09000000
> #define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
> diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Include/Soc.h
> new file mode 100644
> index 0000000000..c1e00394af
> --- /dev/null
> +++ b/Silicon/NXP/LS1043A/Include/Soc.h
> @@ -0,0 +1,44 @@
> +/** @file
> +
> + Copyright 2020 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +#ifndef __SOC_H__
> +#define __SOC_H__
> +
> +/**
> + Soc Memory Map
> +**/
> +#define LS1043A_DRAM0_PHYS_ADDRESS 0x80000000
> +#define LS1043A_DRAM0_SIZE SIZE_2GB
> +#define LS1043A_DRAM1_PHYS_ADDRESS 0x880000000
> +#define LS1043A_DRAM1_SIZE 0x780000000 // 30 GB
> +
> +#define LS1043A_CCSR_PHYS_ADDRESS 0x1000000
> +#define LS1043A_CCSR_SIZE 0xF000000
> +
> +#define LS1043A_IFC0_PHYS_ADDRESS 0x60000000
> +#define LS1043A_IFC0_SIZE SIZE_512MB
> +#define LS1043A_IFC1_PHYS_ADDRESS 0x620000000
> +#define LS1043A_IFC1_SIZE 0xE0000000 // 3.5 GB
> +
> +#define LS1043A_QSPI_PHYS_ADDRESS 0x40000000
> +#define LS1043A_QSPI_SIZE SIZE_512MB
> +
> +#define LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS 0x500000000
> +#define LS1043A_QMAN_SW_PORTAL_SIZE SIZE_128MB
> +#define LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS 0x508000000
> +#define LS1043A_BMAN_SW_PORTAL_SIZE SIZE_128MB
> +
> +#define LS1043A_PCI0_PHYS_ADDRESS 0x4000000000
> +#define LS1043A_PCI1_PHYS_ADDRESS 0x4800000000
> +#define LS1043A_PCI2_PHYS_ADDRESS 0x5000000000
> +#define LS1043A_PCI_SIZE SIZE_32GB
> +
> +#define LS1043A_I2C0_PHYS_ADDRESS 0x2180000
> +#define LS1043A_I2C_SIZE 0x10000
> +#define LS1043A_I2C_NUM_CONTROLLERS 4
> +
> +#endif
> diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> index 754eff396a..7ebbb1a495 100644
> --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> @@ -26,40 +26,8 @@
> [PcdsFixedAtBuild.common]
> gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
>
> - #
> - # CCSR Address Space and other attached Memories
> - #
> - gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
> - gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
> - gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA
> - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000
> - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000
> - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000
> - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000
> - gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000
> - gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000
> - gNxpQoriqLsTokenSpaceGuid.PcdWatchdog1BaseAddr|0x02AD0000
> - gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000
> - gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000
> - gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
> - gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
> - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
> - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
> -
> #
> # Big Endian IPs
> #
> gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
> - gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|TRUE
> ##
> diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> index 9baeb17ecf..a3dabc93d1 100644
> --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> @@ -34,7 +34,7 @@ GetSysInfo (
> CCSR_GUR *GurBase;
> UINTN SysClk;
>
> - GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> + GurBase = (CCSR_GUR *)CHASSIS2_DCFG_ADDRESS;
> SysClk = CLK_FREQ;
>
> SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
> diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> index fe77717337..d8707927b7 100644
> --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> @@ -40,9 +40,5 @@
> gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
> gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
> gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> - gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
> gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
> - gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
> gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
> - gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr
> - gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index 4a1cfb3e27..b478560450 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -22,89 +22,15 @@
> gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
>
> [PcdsFixedAtBuild.common]
> - #
> - # Pcds for I2C Controller
> - #
> - gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000001
> - gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000002
> -
> - #
> - # Pcds for base address and size
> - #
> - gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x0|UINT64|0x00000100
> - gNxpQoriqLsTokenSpaceGuid.PcdPiFdSize|0x0|UINT32|0x00000101
> - gNxpQoriqLsTokenSpaceGuid.PcdPiFdBaseAddress|0x0|UINT64|0x00000102
> - gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x0|UINT64|0x00000103
> - gNxpQoriqLsTokenSpaceGuid.PcdWatchdog1BaseAddr|0x0|UINT64|0x00000104
> - gNxpQoriqLsTokenSpaceGuid.PcdDdrBaseAddr|0x0|UINT64|0x00000105
> - gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x0|UINT64|0x00000106
> - gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x0|UINT64|0x00000107
> - gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x0|UINT64|0x00000108
> - gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x0|UINT32|0x00000109
> - gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x0|UINT64|0x0000010A
> - gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0|UINT64|0x0000010B
> - gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x0000010C
> - gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x0000010D
> - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0|UINT64|0x0000010E
> - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0|UINT64|0x0000010F
> - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0|UINT64|0x00000110
> - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0|UINT64|0x00000111
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x0|UINT64|0x00000112
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x0|UINT64|0x00000113
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x0|UINT64|0x00000114
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x0|UINT64|0x00000115
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x0|UINT64|0x00000116
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x0|UINT64|0x00000117
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x0|UINT64|0x0000118
> - gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x0|UINT64|0x0000119
> - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x0|UINT64|0x0000011A
> - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x0|UINT64|0x0000011B
> - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x0|UINT64|0x0000011C
> - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x0|UINT64|0x0000011D
> - gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExBase|0x0|UINT64|0x0000011E
> - gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExSize|0x0|UINT64|0x0000011F
> - gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x0|UINT32|0x00000120
> - gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x0|UINT32|0x00000121
> - gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000122
> - gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000123
> -
> - #
> - # IFC PCDs
> - #
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x0|UINT64|0x00000190
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x0|UINT64|0x00000191
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0|UINT64|0x00000192
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x0|UINT64|0x00000193
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x0|UINT32|0x00000194
> - gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x0|UINT64|0x00000195
> - gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x0|UINT64|0x00000196
> -
> - #
> - # NV Pcd
> - #
> - gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase|0x0|UINT64|0x00000210
> - gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize|0x0|UINT64|0x00000211
Not able to be different between different platforms using the same SoC?
> -
> #
> # Platform PCDs
> #
> gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
> - gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251
> -
> - #
> - # Clock PCDs
> - #
> - gNxpQoriqLsTokenSpaceGuid.PcdSysClk|0x0|UINT64|0x000002A0
> - gNxpQoriqLsTokenSpaceGuid.PcdDdrClk|0x0|UINT64|0x000002A1
And clocks also sound very much like something that can change per platform?
/
Leif
>
> #
> # Pcds to support Big Endian IPs
> #
> - gNxpQoriqLsTokenSpaceGuid.PcdMmcBigEndian|FALSE|BOOLEAN|0x0000310
> gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311
> - gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000312
> - gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|FALSE|BOOLEAN|0x00000313
> - gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314
>
> [PcdsFeatureFlag]
> gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 07/19] Silicon/NXP: remove not needed components
2020-02-10 17:11 ` Leif Lindholm
@ 2020-02-11 7:24 ` Pankaj Bansal
2020-02-20 19:05 ` Leif Lindholm
0 siblings, 1 reply; 49+ messages in thread
From: Pankaj Bansal @ 2020-02-11 7:24 UTC (permalink / raw)
To: Leif Lindholm
Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi,
devel@edk2.groups.io
> -----Original Message-----
> From: Leif Lindholm <leif@nuviainc.com>
> Sent: Monday, February 10, 2020 10:42 PM
> To: Pankaj Bansal <pankaj.bansal@nxp.com>
> Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney
> <michael.d.kinney@intel.com>; Varun Sethi <V.Sethi@nxp.com>;
> devel@edk2.groups.io
> Subject: Re: [PATCH 07/19] Silicon/NXP: remove not needed components
>
> On Fri, Feb 07, 2020 at 18:13:16 +0530, Pankaj Bansal wrote:
> > We are changing the directory structure of code.
> > After PEI phase impelmentation this info would be put back into
> > appropriate location.
>
> The message needs clarifying:
> What is being deleted, why is this not a problem, and what is being put back?
The structures elements and functions that are not necessary for booting are being deleted.
Once the directory structure has been changed (i.e. we have clear distinction between
chassis code and header files and SOC code and header files), we will put back the code and
structure components back at their appropriate respective place. Also right now all the
elements are being defined in structures, which are not being used right now. So to simplify
the review, I have removed those for now. When we need to use those elements, we can define
those one by one.
>
> /
> Leif
>
> > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> > ---
> > Silicon/NXP/Include/Chassis2/NxpSoc.h | 314 +---------------------
> > Silicon/NXP/Library/SocLib/Chassis.c | 15 --
> > Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 79 ------
> > 3 files changed, 2 insertions(+), 406 deletions(-)
> >
> > diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h
> > b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> > index f05a813750..74330b6205 100644
> > --- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
> > +++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> > @@ -1,7 +1,7 @@
> > /** Soc.h
> > * Header defining the Base addresses, sizes, flags etc for chassis 1
> > *
> > -* Copyright 2017-2019 NXP
> > +* Copyright 2017-2020 NXP
> > *
> > * SPDX-License-Identifier: BSD-2-Clause-Patent
> > *
> > @@ -10,22 +10,7 @@
> > #ifndef NXP_SOC_H_
> > #define NXP_SOC_H_
> >
> > -#define HWA_CGA_M1_CLK_SEL 0xe0000000
> > -#define HWA_CGA_M1_CLK_SHIFT 29
> > -
> > -#define TP_CLUSTER_EOC_MASK 0xc0000000 /* end of clusters mask */
> > -#define NUM_CC_PLLS 2
> > #define CLK_FREQ 100000000
> > -#define MAX_CPUS 4
> > -#define NUM_FMAN 1
> > -#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) ==
> 0x0)
> > -
> > -/* RCW SERDES MACRO */
> > -#define RCWSR_INDEX 4
> > -#define RCWSR_SRDS1_PRTCL_MASK 0xffff0000
> > -#define RCWSR_SRDS1_PRTCL_SHIFT 16
> > -#define RCWSR_SRDS2_PRTCL_MASK 0x0000ffff
> > -#define RCWSR_SRDS2_PRTCL_SHIFT 0
> >
> > /* SMMU Defintions */
> > #define SMMU_BASE_ADDR 0x09000000
> > @@ -41,312 +26,17 @@
> > #define IDR1_PAGESIZE_MASK 0x80000000
> >
> > typedef struct {
> > - UINTN FreqProcessor[MAX_CPUS];
> > UINTN FreqSystemBus;
> > - UINTN FreqDdrBus;
> > - UINTN FreqLocalBus;
> > - UINTN FreqSdhc;
> > - UINTN FreqFman[NUM_FMAN];
> > - UINTN FreqQman;
> > } SYS_INFO;
> >
> > /* Device Configuration and Pin Control */ typedef struct {
> > - UINT32 PorSr1; /* POR status 1 */
> > -#define CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
> > - UINT32 PorSr2; /* POR status 2 */
> > - UINT8 Res008[0x20-0x8];
> > - UINT32 GppOrCr1; /* General-purpose POR configuration */
> > - UINT32 GppOrCr2;
> > - UINT32 DcfgFuseSr; /* Fuse status register */
> > - UINT8 Res02c[0x70-0x2c];
> > - UINT32 DevDisr; /* Device disable control */
> > - UINT32 DevDisr2; /* Device disable control 2 */
> > - UINT32 DevDisr3; /* Device disable control 3 */
> > - UINT32 DevDisr4; /* Device disable control 4 */
> > - UINT32 DevDisr5; /* Device disable control 5 */
> > - UINT32 DevDisr6; /* Device disable control 6 */
> > - UINT32 DevDisr7; /* Device disable control 7 */
> > - UINT8 Res08c[0x94-0x8c];
> > - UINT32 CoreDisrU; /* uppper portion for support of 64 cores */
> > - UINT32 CoreDisrL; /* lower portion for support of 64 cores */
> > - UINT8 Res09c[0xa0-0x9c];
> > - UINT32 Pvr; /* Processor version */
> > - UINT32 Svr; /* System version */
> > - UINT32 Mvr; /* Manufacturing version */
> > - UINT8 Res0ac[0xb0-0xac];
> > - UINT32 RstCr; /* Reset control */
> > - UINT32 RstRqPblSr; /* Reset request preboot loader status */
> > - UINT8 Res0b8[0xc0-0xb8];
> > - UINT32 RstRqMr1; /* Reset request mask */
> > - UINT8 Res0c4[0xc8-0xc4];
> > - UINT32 RstRqSr1; /* Reset request status */
> > - UINT8 Res0cc[0xd4-0xcc];
> > - UINT32 RstRqWdTmrL; /* Reset request WDT mask */
> > - UINT8 Res0d8[0xdc-0xd8];
> > - UINT32 RstRqWdtSrL; /* Reset request WDT status */
> > - UINT8 Res0e0[0xe4-0xe0];
> > - UINT32 BrrL; /* Boot release */
> > - UINT8 Res0e8[0x100-0xe8];
> > + UINT8 Res0[0x100-0x00];
> > UINT32 RcwSr[16]; /* Reset control word status */
> > #define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25 #define
> > CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f -#define
> > CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16 -#define
> > CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
> > - UINT8 Res140[0x200-0x140];
> > - UINT32 ScratchRw[4]; /* Scratch Read/Write */
> > - UINT8 Res210[0x300-0x210];
> > - UINT32 ScratcHw1R[4]; /* Scratch Read (Write once) */
> > - UINT8 Res310[0x400-0x310];
> > - UINT32 CrstSr[12];
> > - UINT8 Res430[0x500-0x430];
> > - /* PCI Express n Logical I/O Device Number register */
> > - UINT32 DcfgCcsrPex1LiodNr;
> > - UINT32 DcfgCcsrPex2LiodNr;
> > - UINT32 DcfgCcsrPex3LiodNr;
> > - UINT32 DcfgCcsrPex4LiodNr;
> > - /* RIO n Logical I/O Device Number register */
> > - UINT32 DcfgCcsrRio1LiodNr;
> > - UINT32 DcfgCcsrRio2LiodNr;
> > - UINT32 DcfgCcsrRio3LiodNr;
> > - UINT32 DcfgCcsrRio4LiodNr;
> > - /* USB Logical I/O Device Number register */
> > - UINT32 DcfgCcsrUsb1LiodNr;
> > - UINT32 DcfgCcsrUsb2LiodNr;
> > - UINT32 DcfgCcsrUsb3LiodNr;
> > - UINT32 DcfgCcsrUsb4LiodNr;
> > - /* SD/MMC Logical I/O Device Number register */
> > - UINT32 DcfgCcsrSdMmc1LiodNr;
> > - UINT32 DcfgCcsrSdMmc2LiodNr;
> > - UINT32 DcfgCcsrSdMmc3LiodNr;
> > - UINT32 DcfgCcsrSdMmc4LiodNr;
> > - /* RIO Message Unit Logical I/O Device Number register */
> > - UINT32 DcfgCcsrRiomaintLiodNr;
> > - UINT8 Res544[0x550-0x544];
> > - UINT32 SataLiodNr[4];
> > - UINT8 Res560[0x570-0x560];
> > - UINT32 DcfgCcsrMisc1LiodNr;
> > - UINT32 DcfgCcsrMisc2LiodNr;
> > - UINT32 DcfgCcsrMisc3LiodNr;
> > - UINT32 DcfgCcsrMisc4LiodNr;
> > - UINT32 DcfgCcsrDma1LiodNr;
> > - UINT32 DcfgCcsrDma2LiodNr;
> > - UINT32 DcfgCcsrDma3LiodNr;
> > - UINT32 DcfgCcsrDma4LiodNr;
> > - UINT32 DcfgCcsrSpare1LiodNr;
> > - UINT32 DcfgCcsrSpare2LiodNr;
> > - UINT32 DcfgCcsrSpare3LiodNr;
> > - UINT32 DcfgCcsrSpare4LiodNr;
> > - UINT8 Res5a0[0x600-0x5a0];
> > - UINT32 DcfgCcsrPblSr;
> > - UINT32 PamuBypENr;
> > - UINT32 DmaCr1;
> > - UINT8 Res60c[0x610-0x60c];
> > - UINT32 DcfgCcsrGenSr1;
> > - UINT32 DcfgCcsrGenSr2;
> > - UINT32 DcfgCcsrGenSr3;
> > - UINT32 DcfgCcsrGenSr4;
> > - UINT32 DcfgCcsrGenCr1;
> > - UINT32 DcfgCcsrGenCr2;
> > - UINT32 DcfgCcsrGenCr3;
> > - UINT32 DcfgCcsrGenCr4;
> > - UINT32 DcfgCcsrGenCr5;
> > - UINT32 DcfgCcsrGenCr6;
> > - UINT32 DcfgCcsrGenCr7;
> > - UINT8 Res63c[0x658-0x63c];
> > - UINT32 DcfgCcsrcGenSr1;
> > - UINT32 DcfgCcsrcGenSr0;
> > - UINT8 Res660[0x678-0x660];
> > - UINT32 DcfgCcsrcGenCr1;
> > - UINT32 DcfgCcsrcGenCr0;
> > - UINT8 Res680[0x700-0x680];
> > - UINT32 DcfgCcsrSrIoPstecr;
> > - UINT32 DcfgCcsrDcsrCr;
> > - UINT8 Res708[0x740-0x708]; /* add more registers when needed */
> > - UINT32 TpItyp[64]; /* Topology Initiator Type Register */
> > - struct {
> > - UINT32 Upper;
> > - UINT32 Lower;
> > - } TpCluster[16];
> > - UINT8 Res8c0[0xa00-0x8c0]; /* add more registers when needed */
> > - UINT32 DcfgCcsrQmBmWarmRst;
> > - UINT8 Resa04[0xa20-0xa04]; /* add more registers when needed */
> > - UINT32 DcfgCcsrReserved0;
> > - UINT32 DcfgCcsrReserved1;
> > } CCSR_GUR;
> >
> > -/* Supplemental Configuration Unit */ -typedef struct {
> > - UINT8 Res000[0x070-0x000];
> > - UINT32 Usb1Prm1Cr;
> > - UINT32 Usb1Prm2Cr;
> > - UINT32 Usb1Prm3Cr;
> > - UINT32 Usb2Prm1Cr;
> > - UINT32 Usb2Prm2Cr;
> > - UINT32 Usb2Prm3Cr;
> > - UINT32 Usb3Prm1Cr;
> > - UINT32 Usb3Prm2Cr;
> > - UINT32 Usb3Prm3Cr;
> > - UINT8 Res094[0x100-0x094];
> > - UINT32 Usb2Icid;
> > - UINT32 Usb3Icid;
> > - UINT8 Res108[0x114-0x108];
> > - UINT32 DmaIcid;
> > - UINT32 SataIcid;
> > - UINT32 Usb1Icid;
> > - UINT32 QeIcid;
> > - UINT32 SdhcIcid;
> > - UINT32 EdmaIcid;
> > - UINT32 EtrIcid;
> > - UINT32 Core0SftRst;
> > - UINT32 Core1SftRst;
> > - UINT32 Core2SftRst;
> > - UINT32 Core3SftRst;
> > - UINT8 Res140[0x158-0x140];
> > - UINT32 AltCBar;
> > - UINT32 QspiCfg;
> > - UINT8 Res160[0x180-0x160];
> > - UINT32 DmaMcr;
> > - UINT8 Res184[0x188-0x184];
> > - UINT32 GicAlign;
> > - UINT32 DebugIcid;
> > - UINT8 Res190[0x1a4-0x190];
> > - UINT32 SnpCnfGcr;
> > -#define CCSR_SCFG_SNPCNFGCR_SECRDSNP BIT31
> > -#define CCSR_SCFG_SNPCNFGCR_SECWRSNP BIT30
> > -#define CCSR_SCFG_SNPCNFGCR_SATARDSNP BIT23
> > -#define CCSR_SCFG_SNPCNFGCR_SATAWRSNP BIT22
> > -#define CCSR_SCFG_SNPCNFGCR_USB1RDSNP BIT21
> > -#define CCSR_SCFG_SNPCNFGCR_USB1WRSNP BIT20
> > -#define CCSR_SCFG_SNPCNFGCR_USB2RDSNP BIT15
> > -#define CCSR_SCFG_SNPCNFGCR_USB2WRSNP BIT16
> > -#define CCSR_SCFG_SNPCNFGCR_USB3RDSNP BIT13
> > -#define CCSR_SCFG_SNPCNFGCR_USB3WRSNP BIT14
> > - UINT8 Res1a8[0x1ac-0x1a8];
> > - UINT32 IntpCr;
> > - UINT8 Res1b0[0x204-0x1b0];
> > - UINT32 CoreSrEnCr;
> > - UINT8 Res208[0x220-0x208];
> > - UINT32 RvBar00;
> > - UINT32 RvBar01;
> > - UINT32 RvBar10;
> > - UINT32 RvBar11;
> > - UINT32 RvBar20;
> > - UINT32 RvBar21;
> > - UINT32 RvBar30;
> > - UINT32 RvBar31;
> > - UINT32 LpmCsr;
> > - UINT8 Res244[0x400-0x244];
> > - UINT32 QspIdQScr;
> > - UINT32 EcgTxcMcr;
> > - UINT32 SdhcIoVSelCr;
> > - UINT32 RcwPMuxCr0;
> > - /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
> > - *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
> > - *Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS
> > - Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS*/
> > -#define CCSR_SCFG_RCWPMUXCRO_SELCR_USB 0x3333
> > - /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
> > - *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
> > - *Setting RCW PinMux Register bits 25-27 to select IIC4_SCL
> > - Setting RCW PinMux Register bits 29-31 to select IIC4_SDA*/
> > -#define CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300
> > - UINT32 UsbDrvVBusSelCr;
> > -#define CCSR_SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
> > -#define CCSR_SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
> > -#define CCSR_SCFG_USBDRVVBUS_SELCR_USB3 0x00000003
> > - UINT32 UsbPwrFaultSelCr;
> > -#define CCSR_SCFG_USBPWRFAULT_INACTIVE 0x00000000
> > -#define CCSR_SCFG_USBPWRFAULT_SHARED 0x00000001
> > -#define CCSR_SCFG_USBPWRFAULT_DEDICATED 0x00000002
> > -#define CCSR_SCFG_USBPWRFAULT_USB3_SHIFT 4
> > -#define CCSR_SCFG_USBPWRFAULT_USB2_SHIFT 2
> > -#define CCSR_SCFG_USBPWRFAULT_USB1_SHIFT 0
> > - UINT32 UsbRefclkSelcr1;
> > - UINT32 UsbRefclkSelcr2;
> > - UINT32 UsbRefclkSelcr3;
> > - UINT8 Res424[0x600-0x424];
> > - UINT32 ScratchRw[4];
> > - UINT8 Res610[0x680-0x610];
> > - UINT32 CoreBCr;
> > - UINT8 Res684[0x1000-0x684];
> > - UINT32 Pex1MsiIr;
> > - UINT32 Pex1MsiR;
> > - UINT8 Res1008[0x2000-0x1008];
> > - UINT32 Pex2;
> > - UINT32 Pex2MsiR;
> > - UINT8 Res2008[0x3000-0x2008];
> > - UINT32 Pex3MsiIr;
> > - UINT32 Pex3MsiR;
> > -} CCSR_SCFG;
> > -
> > -#define USB_TXVREFTUNE 0x9
> > -#define USB_SQRXTUNE 0xFC7FFFFF
> > -#define USB_PCSTXSWINGFULL 0x47
> > -#define USB_PHY_RX_EQ_VAL_1 0x0000
> > -#define USB_PHY_RX_EQ_VAL_2 0x8000
> > -#define USB_PHY_RX_EQ_VAL_3 0x8003
> > -#define USB_PHY_RX_EQ_VAL_4 0x800b
> > -
> > -/*USB_PHY_SS memory map*/
> > -typedef struct {
> > - UINT16 IpIdcodeLo;
> > - UINT16 SupIdcodeHi;
> > - UINT8 Res4[0x0006-0x0004];
> > - UINT16 RtuneDebug;
> > - UINT16 RtuneStat;
> > - UINT16 SupSsPhase;
> > - UINT16 SsFreq;
> > - UINT8 ResE[0x0020-0x000e];
> > - UINT16 Ateovrd;
> > - UINT16 MpllOvrdInLo;
> > - UINT8 Res24[0x0026-0x0024];
> > - UINT16 SscOvrdIn;
> > - UINT8 Res28[0x002A-0x0028];
> > - UINT16 LevelOvrdIn;
> > - UINT8 Res2C[0x0044-0x002C];
> > - UINT16 ScopeCount;
> > - UINT8 Res46[0x0060-0x0046];
> > - UINT16 MpllLoopCtl;
> > - UINT8 Res62[0x006C-0x0062];
> > - UINT16 SscClkCntrl;
> > - UINT8 Res6E[0x2002-0x006E];
> > - UINT16 Lane0TxOvrdInHi;
> > - UINT16 Lane0TxOvrdDrvLo;
> > - UINT8 Res2006[0x200C-0x2006];
> > - UINT16 Lane0RxOvrdInHi;
> > - UINT8 Res200E[0x2022-0x200E];
> > - UINT16 Lane0TxCmWaitTimeOvrd;
> > - UINT8 Res2024[0x202A-0x2024];
> > - UINT16 Lane0TxLbertCtl;
> > - UINT16 Lane0RxLbertCtl;
> > - UINT16 Lane0RxLbertErr;
> > - UINT8 Res2030[0x205A-0x2030];
> > - UINT16 Lane0TxAltBlock;
> > -} CCSR_USB_PHY;
> > -
> > -/* Clocking */
> > -typedef struct {
> > - struct {
> > - UINT32 ClkCnCSr; /* core cluster n clock control status */
> > - UINT8 Res004[0x0c];
> > - UINT32 ClkcGHwAcSr; /* Clock generator n hardware accelerator */
> > - UINT8 Res014[0x0c];
> > - } ClkcSr[4];
> > - UINT8 Res040[0x780]; /* 0x100 */
> > - struct {
> > - UINT32 PllCnGSr;
> > - UINT8 Res804[0x1c];
> > - } PllCgSr[NUM_CC_PLLS];
> > - UINT8 Res840[0x1c0];
> > - UINT32 ClkPCSr; /* 0xa00 Platform clock domain control/status */
> > - UINT8 Resa04[0x1fc];
> > - UINT32 PllPGSr; /* 0xc00 Platform PLL General Status */
> > - UINT8 Resc04[0x1c];
> > - UINT32 PllDGSr; /* 0xc20 DDR PLL General Status */
> > - UINT8 Resc24[0x3dc];
> > -} CCSR_CLOCK;
> > -
> > VOID
> > GetSysInfo (
> > OUT SYS_INFO *
> > diff --git a/Silicon/NXP/Library/SocLib/Chassis.c
> > b/Silicon/NXP/Library/SocLib/Chassis.c
> > index 18a1f5e4e1..847331a631 100644
> > --- a/Silicon/NXP/Library/SocLib/Chassis.c
> > +++ b/Silicon/NXP/Library/SocLib/Chassis.c
> > @@ -53,21 +53,6 @@ GetBusFrequency (
> > return SocSysInfo.FreqSystemBus;
> > }
> >
> > -/*
> > - * Return SDXC bus frequency
> > - */
> > -UINT64
> > -GetSdxcFrequency (
> > - VOID
> > - )
> > -{
> > - SYS_INFO SocSysInfo;
> > -
> > - GetSysInfo (&SocSysInfo);
> > -
> > - return SocSysInfo.FreqSdhc;
> > -}
> > -
> > /*
> > * Setup SMMU in bypass mode
> > * and also set its pagesize
> > diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > index 3d803716c9..9baeb17ecf 100644
> > --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > @@ -32,38 +32,14 @@ GetSysInfo (
> > )
> > {
> > CCSR_GUR *GurBase;
> > - CCSR_CLOCK *ClkBase;
> > - UINTN CpuIndex;
> > - UINT32 TempRcw;
> > - UINT32 CPllSel;
> > - UINT32 CplxPll;
> > - CONST UINT8 CoreCplxPll[8] = {
> > - [0] = 0, /* CC1 PPL / 1 */
> > - [1] = 0, /* CC1 PPL / 2 */
> > - [4] = 1, /* CC2 PPL / 1 */
> > - [5] = 1, /* CC2 PPL / 2 */
> > - };
> > -
> > - CONST UINT8 CoreCplxPllDivisor[8] = {
> > - [0] = 1, /* CC1 PPL / 1 */
> > - [1] = 2, /* CC1 PPL / 2 */
> > - [4] = 1, /* CC2 PPL / 1 */
> > - [5] = 2, /* CC2 PPL / 2 */
> > - };
> > -
> > - UINTN PllCount;
> > - UINTN FreqCPll[NUM_CC_PLLS];
> > - UINTN PllRatio[NUM_CC_PLLS];
> > UINTN SysClk;
> >
> > GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> > - ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
> > SysClk = CLK_FREQ;
> >
> > SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
> >
> > PtrSysInfo->FreqSystemBus = SysClk;
> > - PtrSysInfo->FreqDdrBus = SysClk;
> >
> > //
> > // selects the platform clock:SYSCLK ratio and calculate @@ -72,61
> > +48,6 @@ GetSysInfo (
> > PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
> > CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
> > CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
> > - //
> > - // selects the DDR PLL:SYSCLK Ratio and calculate DDR frequency
> > - //
> > - PtrSysInfo->FreqDdrBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
> > - CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
> > - CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
> > -
> > - for (PllCount = 0; PllCount < NUM_CC_PLLS; PllCount++) {
> > - PllRatio[PllCount] = (GurRead ((UINTN)&ClkBase-
> >PllCgSr[PllCount].PllCnGSr) >> 1) & 0xff;
> > - if (PllRatio[PllCount] > 4) {
> > - FreqCPll[PllCount] = SysClk * PllRatio[PllCount];
> > - } else {
> > - FreqCPll[PllCount] = PtrSysInfo->FreqSystemBus * PllRatio[PllCount];
> > - }
> > - }
> > -
> > - //
> > - // Calculate Core frequency
> > - //
> > - for (CpuIndex = 0; CpuIndex < MAX_CPUS; CpuIndex++) {
> > - CPllSel = (GurRead ((UINTN)&ClkBase->ClkcSr[CpuIndex].ClkCnCSr) >> 27) &
> 0xf;
> > - CplxPll = CoreCplxPll[CPllSel];
> > -
> > - PtrSysInfo->FreqProcessor[CpuIndex] = FreqCPll[CplxPll] /
> CoreCplxPllDivisor[CPllSel];
> > - }
> > -
> > - //
> > - // Calculate FMAN frequency
> > - //
> > - TempRcw = GurRead ((UINTN)&GurBase->RcwSr[7]);
> > - switch ((TempRcw & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT)
> {
> > - case 2:
> > - PtrSysInfo->FreqFman[0] = FreqCPll[0] / 2;
> > - break;
> > - case 3:
> > - PtrSysInfo->FreqFman[0] = FreqCPll[0] / 3;
> > - break;
> > - case 4:
> > - PtrSysInfo->FreqFman[0] = FreqCPll[0] / 4;
> > - break;
> > - case 5:
> > - PtrSysInfo->FreqFman[0] = PtrSysInfo->FreqSystemBus;
> > - break;
> > - case 6:
> > - PtrSysInfo->FreqFman[0] = FreqCPll[1] / 2;
> > - break;
> > - case 7:
> > - PtrSysInfo->FreqFman[0] = FreqCPll[1] / 3;
> > - break;
> > - default:
> > - DEBUG ((DEBUG_WARN, "Error: Unknown FMan1 clock select!\n"));
> > - break;
> > - }
> > - PtrSysInfo->FreqSdhc = PtrSysInfo->FreqSystemBus/PcdGet32
> > (PcdPlatformFreqDiv);
> > - PtrSysInfo->FreqQman = PtrSysInfo->FreqSystemBus/PcdGet32
> > (PcdPlatformFreqDiv); }
> >
> > /**
> > --
> > 2.17.1
> >
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 08/19] Silicon/NXP: Remove unnecessary PCDs
2020-02-10 17:32 ` Leif Lindholm
@ 2020-02-11 8:45 ` Pankaj Bansal
2020-02-20 18:56 ` Leif Lindholm
0 siblings, 1 reply; 49+ messages in thread
From: Pankaj Bansal @ 2020-02-11 8:45 UTC (permalink / raw)
To: Leif Lindholm
Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi,
devel@edk2.groups.io
> -----Original Message-----
> From: Leif Lindholm <leif@nuviainc.com>
> Sent: Monday, February 10, 2020 11:02 PM
> To: Pankaj Bansal <pankaj.bansal@nxp.com>
> Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney
> <michael.d.kinney@intel.com>; Varun Sethi <V.Sethi@nxp.com>;
> devel@edk2.groups.io
> Subject: Re: [PATCH 08/19] Silicon/NXP: Remove unnecessary PCDs
>
> On Fri, Feb 07, 2020 at 18:13:17 +0530, Pankaj Bansal wrote:
> > There is no need to keep SOC specific PCDs defined for each SOC.
>
> That sound like the definition of why we have SoC-specific Pcds, so I don't
> follow.
>
> > we can do away with these PCDs.
>
> After looking through this patchset, it looks like:
> 1) Initial implementation defined a bunch of things as Pcds which
> really cannot vary between different platforms using the same SoC.
Yes.
> 2) This patch moves several things that can differ between platforms
> into #defines, when they should be Pcds.
>
> I am OK with the 1)s, but there are some you would need to convince me are not
> 2:s.
I have moved only those things to #define, which would be common for all platforms using the SOC.
I will explain more below.
>
> > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> > ---
> > .../Drivers/PlatformDxe/PlatformDxe.c | 15 +--
> > .../Drivers/PlatformDxe/PlatformDxe.inf | 8 +-
> > Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 1 -
> > .../Library/PlatformLib/ArmPlatformLib.inf | 21 +---
> > .../Library/PlatformLib/NxpQoriqLsMem.c | 103 +++++++++---------
> > Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 6 -
> > Silicon/NXP/Include/Chassis2/NxpSoc.h | 2 +
> > Silicon/NXP/LS1043A/Include/Soc.h | 44 ++++++++
> > Silicon/NXP/LS1043A/LS1043A.dsc.inc | 32 ------
> > Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 2 +-
> > Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 4 -
> > Silicon/NXP/NxpQoriqLs.dec | 74 -------------
> > 12 files changed, 108 insertions(+), 204 deletions(-) create mode
> > 100644 Silicon/NXP/LS1043A/Include/Soc.h
> >
> > diff --git
> > a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> > b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> > index f89dcdeff3..62c400eb1a 100644
> > --- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> > +++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> > @@ -1,7 +1,7 @@
> > /** @file
> > LS1043 DXE platform driver.
> >
> > - Copyright 2018-2019 NXP
> > + Copyright 2018-2020 NXP
> >
> > SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> > @@ -14,6 +14,7 @@
> > #include <Library/PcdLib.h>
> > #include <Library/UefiBootServicesTableLib.h>
> > #include <Library/UefiLib.h>
> > +#include <Soc.h>
> >
> > #include <Protocol/NonDiscoverableDevice.h>
> >
> > @@ -22,7 +23,7 @@ typedef struct {
> > UINT8 EndDesc;
> > } ADDRESS_SPACE_DESCRIPTOR;
> >
> > -STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[FixedPcdGet64
> > (PcdNumI2cController)];
> > +STATIC ADDRESS_SPACE_DESCRIPTOR
> > +mI2cDesc[LS1043A_I2C_NUM_CONTROLLERS];
>
> Sure, this one sounds like something not configurable in software or board
> design.
>
> >
> > STATIC
> > EFI_STATUS
> > @@ -65,19 +66,19 @@ PopulateI2cInformation ( {
> > UINT32 Index;
> >
> > - for (Index = 0; Index < FixedPcdGet32 (PcdNumI2cController);
> > Index++) {
> > + for (Index = 0; Index < ARRAY_SIZE (mI2cDesc); Index++) {
> > mI2cDesc[Index].StartDesc.Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
> > mI2cDesc[Index].StartDesc.Len = sizeof
> (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
> > mI2cDesc[Index].StartDesc.ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
> > mI2cDesc[Index].StartDesc.GenFlag = 0;
> > mI2cDesc[Index].StartDesc.SpecificFlag = 0;
> > mI2cDesc[Index].StartDesc.AddrSpaceGranularity = 32;
> > - mI2cDesc[Index].StartDesc.AddrRangeMin = FixedPcdGet64
> (PcdI2c0BaseAddr) +
> > - (Index * FixedPcdGet32 (PcdI2cSize));
>
> As does this.
>
> > + mI2cDesc[Index].StartDesc.AddrRangeMin =
> LS1043A_I2C0_PHYS_ADDRESS +
> > + (Index *
> > + LS1043A_I2C_SIZE);
> > mI2cDesc[Index].StartDesc.AddrRangeMax =
> mI2cDesc[Index].StartDesc.AddrRangeMin +
> > - FixedPcdGet32 (PcdI2cSize) - 1;
> > + LS1043A_I2C_SIZE - 1;
> > mI2cDesc[Index].StartDesc.AddrTranslationOffset = 0;
> > - mI2cDesc[Index].StartDesc.AddrLen = FixedPcdGet32 (PcdI2cSize);
> > + mI2cDesc[Index].StartDesc.AddrLen = LS1043A_I2C_SIZE;
> >
> > mI2cDesc[Index].EndDesc = ACPI_END_TAG_DESCRIPTOR;
> > }
> > diff --git
> > a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> > b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> > index d689cf4db5..126a1174fa 100644
> > --- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> > +++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> > @@ -2,7 +2,7 @@
> > #
> > # Component description file for LS1043 DXE platform driver.
> > #
> > -# Copyright 2018-2019 NXP
> > +# Copyright 2018-2020 NXP
> > #
> > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -25,6 +25,7 @@
> > MdeModulePkg/MdeModulePkg.dec
> > Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
> > Silicon/NXP/NxpQoriqLs.dec
> > + Silicon/NXP/LS1043A/LS1043A.dec
>
> Please insert sorted alphabetically.
>
> >
> > [LibraryClasses]
> > BaseLib
> > @@ -43,10 +44,5 @@
> > gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES
> > gDs1307RealTimeClockLibI2cMasterProtocolGuid ## PRODUCES
> >
> > -[FixedPcd]
> > - gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
> > - gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
> > - gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
>
> Still good.
>
> > -
> > [Depex]
> > TRUE
> > diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > index 802cccdce6..74a1948fc6 100644
> > --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > @@ -42,7 +42,6 @@
> > #
> > # Board Specific Pcds
> > #
> > - gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
>
> But this sounds exactly like the kind of thing that would be configured differently
> for different boards. Can you please explain why this should be removed?
This PCD was defined because LS1043A (Chassis2 based SOC) has one Serdes.
Other Soc based on Chassis2 LS1046A, has two Serdes. So this Pcd is false for LS1043A
and true for LS1046A. Serdes block in Layerscape SOCs control which devices are enabled
and which devices are disabled ? e.g. (hypothetical example) with Serdes protocol 5,
out of 8 MACs, only 3 and 6 and enabled.
Going forward the plan is to move the Serdes handling
to SOC specific code and NOT to Chassis specific code. This is because the serdes
protocols are SOC specific and not chassis specific. i.e. both LS1046A and LS1043A can have
serdes protocol 5. But their meaning can be different for both
For the time being we have removed Serdes related code (in PATCH 07/19). We will introduce
It after PEI phase changes are merged.
>
> > gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
> >
> > #
> > diff --git
> > a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> > b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> > index f7ae74afc6..054dc4d003 100644
> > ---
> > a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> > +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.in
> > +++ f
> > @@ -1,7 +1,7 @@
> > # @file
> > #
> > # Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> > -# Copyright 2017, 2019 NXP
> > +# Copyright 2017, 2019-2020 NXP
> > #
> > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -20,6 +20,7 @@
> > EmbeddedPkg/EmbeddedPkg.dec
> > MdePkg/MdePkg.dec
> > Silicon/NXP/NxpQoriqLs.dec
> > + Silicon/NXP/LS1043A/LS1043A.dec
>
> Insert sorted.
>
> >
> > [LibraryClasses]
> > ArmLib
> > @@ -35,21 +36,3 @@
> >
> > [FixedPcd]
> > gArmTokenSpaceGuid.PcdArmPrimaryCore
> > - gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
> > - gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
> > - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
> > - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
> > - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
> > - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
> > - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr
> > - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize
> > - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr
> > - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize
> > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
> > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
> > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
> > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
> > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
> > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
> > - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
> > - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
> > diff --git
> > a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> > b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> > index c6c256da07..3a72c8bdd8 100644
> > --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> > +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> > @@ -6,7 +6,7 @@
> > *
> > * Copyright (c) 2011, ARM Limited. All rights reserved.
> > * Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> > -* Copyright 2017, 2019 NXP
> > +* Copyright 2017, 2019-2020 NXP
> > *
> > * SPDX-License-Identifier: BSD-2-Clause-Patent
> > *
> > @@ -16,7 +16,7 @@
> > #include <Library/DebugLib.h>
> > #include <Library/PcdLib.h>
> > #include <Library/MemoryAllocationLib.h> -#include <DramInfo.h>
> > +#include <Soc.h>
> >
> > #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
> >
> > @@ -38,7 +38,6 @@ ArmPlatformGetVirtualMemoryMap ( {
> > UINTN Index;
> > ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
> > - DRAM_INFO DramInfo;
> >
> > Index = 0;
> >
> > @@ -51,25 +50,21 @@ ArmPlatformGetVirtualMemoryMap (
> > return;
> > }
> >
> > - if (GetDramBankInfo (&DramInfo)) {
> > - DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n"));
> > - return;
> > - }
> > + VirtualMemoryTable[Index].PhysicalBase =
> > + LS1043A_DRAM0_PHYS_ADDRESS; VirtualMemoryTable[Index].VirtualBase
> = LS1043A_DRAM0_PHYS_ADDRESS;
> > + VirtualMemoryTable[Index].Length = LS1043A_DRAM0_SIZE;
> > + VirtualMemoryTable[Index++].Attributes =
> ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> >
> > -
> > - for (Index = 0; Index < DramInfo.NumOfDrams; Index++) {
> > - // DRAM1 (Must be 1st entry)
> > - VirtualMemoryTable[Index].PhysicalBase =
> DramInfo.DramRegion[Index].BaseAddress;
> > - VirtualMemoryTable[Index].VirtualBase =
> DramInfo.DramRegion[Index].BaseAddress;
> > - VirtualMemoryTable[Index].Length = DramInfo.DramRegion[Index].Size;
> > - VirtualMemoryTable[Index].Attributes =
> ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> > - }
> > + VirtualMemoryTable[Index].PhysicalBase =
> > + LS1043A_DRAM1_PHYS_ADDRESS; VirtualMemoryTable[Index].VirtualBase
> = LS1043A_DRAM1_PHYS_ADDRESS;
> > + VirtualMemoryTable[Index].Length = LS1043A_DRAM1_SIZE;
> > + VirtualMemoryTable[Index++].Attributes =
> ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
>
> No changes to this file so far appear to have anything to do with what the
> commit message says the patch does.
>
> >
> > // CCSR Space
> > - VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64
> > (PcdCcsrBaseAddr);
> > - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdCcsrBaseAddr);
> > - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
> > - VirtualMemoryTable[Index].Attributes =
> ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> > + VirtualMemoryTable[Index].PhysicalBase = LS1043A_CCSR_PHYS_ADDRESS;
> > + VirtualMemoryTable[Index].VirtualBase = LS1043A_CCSR_PHYS_ADDRESS;
> > + VirtualMemoryTable[Index].Length = LS1043A_CCSR_SIZE;
> > + VirtualMemoryTable[Index++].Attributes =
> ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>
> If these are not reconfigurable for different platforms, sure.
Yes. The SOC memory map is fixed in hardware. It doesn't change with Platform using SOC.
>
> >
> > // IFC region 1
> > //
> > @@ -85,60 +80,60 @@ ArmPlatformGetVirtualMemoryMap (
> > // For write transactions from non-core masters (like system DMA),
> the address
> > // should be 16 byte aligned and the data size should be multiple of
> 16 bytes.
> > //
> > - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64
> > (PcdIfcRegion1BaseAddr);
> > - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64
> (PcdIfcRegion1BaseAddr);
> > - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion1Size);
> > - VirtualMemoryTable[Index].Attributes =
> ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> > + VirtualMemoryTable[Index].PhysicalBase = LS1043A_IFC0_PHYS_ADDRESS;
> > + VirtualMemoryTable[Index].VirtualBase = LS1043A_IFC0_PHYS_ADDRESS;
> > + VirtualMemoryTable[Index].Length = LS1043A_IFC0_SIZE;
> > + VirtualMemoryTable[Index++].Attributes =
> ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>
> If these are not reconfigurable for different platforms, sure.
>
> >
> > // QMAN SWP
> > - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64
> > (PcdQmanSwpBaseAddr);
> > - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64
> (PcdQmanSwpBaseAddr);
> > - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQmanSwpSize);
> > - VirtualMemoryTable[Index].Attributes =
> ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> > + VirtualMemoryTable[Index].PhysicalBase =
> > + LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS;
> > + VirtualMemoryTable[Index].VirtualBase =
> LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS;
> > + VirtualMemoryTable[Index].Length = LS1043A_QMAN_SW_PORTAL_SIZE;
> > + VirtualMemoryTable[Index++].Attributes =
> ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> >
>
> If these are not reconfigurable for different platforms, sure.
>
> > // BMAN SWP
> > - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64
> > (PcdBmanSwpBaseAddr);
> > - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64
> (PcdBmanSwpBaseAddr);
> > - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdBmanSwpSize);
> > - VirtualMemoryTable[Index].Attributes =
> ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> > + VirtualMemoryTable[Index].PhysicalBase =
> > + LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS;
> > + VirtualMemoryTable[Index].VirtualBase =
> LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS;
> > + VirtualMemoryTable[Index].Length = LS1043A_QMAN_SW_PORTAL_SIZE;
> > + VirtualMemoryTable[Index++].Attributes =
> ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> >
>
> If these are not reconfigurable for different platforms, sure.
>
> > // IFC region 2
> > - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64
> > (PcdIfcRegion2BaseAddr);
> > - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64
> (PcdIfcRegion2BaseAddr);
> > - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion2Size);
> > - VirtualMemoryTable[Index].Attributes =
> ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> > + VirtualMemoryTable[Index].PhysicalBase = LS1043A_IFC1_PHYS_ADDRESS;
> > + VirtualMemoryTable[Index].VirtualBase = LS1043A_IFC1_PHYS_ADDRESS;
> > + VirtualMemoryTable[Index].Length = LS1043A_IFC1_SIZE;
> > + VirtualMemoryTable[Index++].Attributes =
> ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> >
>
> If these are not reconfigurable for different platforms, sure.
>
> > // PCIe1
> > - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64
> > (PcdPciExp1BaseAddr);
> > - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64
> (PcdPciExp1BaseAddr);
> > - VirtualMemoryTable[Index].Length = FixedPcdGet64
> (PcdPciExp1BaseSize);
> > - VirtualMemoryTable[Index].Attributes =
> ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> > + VirtualMemoryTable[Index].PhysicalBase = LS1043A_PCI0_PHYS_ADDRESS;
> > + VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI0_PHYS_ADDRESS;
> > + VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
> > + VirtualMemoryTable[Index++].Attributes =
> ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> >
>
> If these are not reconfigurable for different platforms, sure.
>
> > // PCIe2
> > - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64
> > (PcdPciExp2BaseAddr);
> > - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64
> (PcdPciExp2BaseAddr);
> > - VirtualMemoryTable[Index].Length = FixedPcdGet64
> (PcdPciExp2BaseSize);
> > - VirtualMemoryTable[Index].Attributes =
> ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> > + VirtualMemoryTable[Index].PhysicalBase = LS1043A_PCI1_PHYS_ADDRESS;
> > + VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI1_PHYS_ADDRESS;
> > + VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
> > + VirtualMemoryTable[Index++].Attributes =
> ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> >
>
> If these are not reconfigurable for different platforms, sure.
>
> > // PCIe3
> > - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64
> > (PcdPciExp3BaseAddr);
> > - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64
> (PcdPciExp3BaseAddr);
> > - VirtualMemoryTable[Index].Length = FixedPcdGet64
> (PcdPciExp3BaseSize);
> > - VirtualMemoryTable[Index].Attributes =
> ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> > + VirtualMemoryTable[Index].PhysicalBase = LS1043A_PCI2_PHYS_ADDRESS;
> > + VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI2_PHYS_ADDRESS;
> > + VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
> > + VirtualMemoryTable[Index++].Attributes =
> ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>
> If these are not reconfigurable for different platforms, sure.
> >
> > // QSPI region
> > - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64
> > (PcdQspiRegionBaseAddr);
> > - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64
> (PcdQspiRegionBaseAddr);
> > - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegionSize);
> > - VirtualMemoryTable[Index].Attributes =
> ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> > + VirtualMemoryTable[Index].PhysicalBase = LS1043A_QSPI_PHYS_ADDRESS;
> > + VirtualMemoryTable[Index].VirtualBase = LS1043A_QSPI_PHYS_ADDRESS;
> > + VirtualMemoryTable[Index].Length = LS1043A_QSPI_SIZE;
> > + VirtualMemoryTable[Index++].Attributes =
> ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
>
> If these are not reconfigurable for different platforms, sure.
>
> >
> > // End of Table
> > - VirtualMemoryTable[++Index].PhysicalBase = 0;
> > + VirtualMemoryTable[Index].PhysicalBase = 0;
>
> Move that ++ back where it belongs - there is no functional change here.
I will remove this change and will keep functional changes only in this patch.
>
> > VirtualMemoryTable[Index].VirtualBase = 0;
> > VirtualMemoryTable[Index].Length = 0;
> > - VirtualMemoryTable[Index].Attributes =
> (ARM_MEMORY_REGION_ATTRIBUTES)0;
> > + VirtualMemoryTable[Index++].Attributes =
> (ARM_MEMORY_REGION_ATTRIBUTES)0;
>
> Move that ++ back where it belongs - there is no functional change here.
>
> >
> > - ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
> > + ASSERT (Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
>
> Drop that +1 = - there is no functional change here.
>
> If you want to submit separate patches for coding style changes, that's fine. But
> given that this set looks like it's making up for not synchronising internal
> development with the (very long) upstreaming effort so far, I am not interested
> in those until all functional changes are in.
I will remove this change and will keep functional changes only in this patch.
>
> >
> > *VirtualMemoryMap = VirtualMemoryTable; } diff --git
> > a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> > b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> > index 784139065f..fc4bb618fa 100644
> > --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> > +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> > @@ -49,11 +49,5 @@
> > gEdkiiNonDiscoverableDeviceProtocolGuid ## TO_START
> > gEfiI2cMasterProtocolGuid ## BY_START
> >
> > -[Pcd]
> > - gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed
> > - gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
> > - gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
> > - gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
> > -
> > [Depex]
> > TRUE
> > diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h
> > b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> > index 74330b6205..6812beafe4 100644
> > --- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
> > +++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> > @@ -12,6 +12,8 @@
> >
> > #define CLK_FREQ 100000000
> >
> > +#define CHASSIS2_DCFG_ADDRESS 0x1EE0000
> > +
> > /* SMMU Defintions */
> > #define SMMU_BASE_ADDR 0x09000000
> > #define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
> > diff --git a/Silicon/NXP/LS1043A/Include/Soc.h
> > b/Silicon/NXP/LS1043A/Include/Soc.h
> > new file mode 100644
> > index 0000000000..c1e00394af
> > --- /dev/null
> > +++ b/Silicon/NXP/LS1043A/Include/Soc.h
> > @@ -0,0 +1,44 @@
> > +/** @file
> > +
> > + Copyright 2020 NXP
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +#ifndef __SOC_H__
> > +#define __SOC_H__
> > +
> > +/**
> > + Soc Memory Map
> > +**/
> > +#define LS1043A_DRAM0_PHYS_ADDRESS 0x80000000
> > +#define LS1043A_DRAM0_SIZE SIZE_2GB
> > +#define LS1043A_DRAM1_PHYS_ADDRESS 0x880000000
> > +#define LS1043A_DRAM1_SIZE 0x780000000 // 30 GB
> > +
> > +#define LS1043A_CCSR_PHYS_ADDRESS 0x1000000
> > +#define LS1043A_CCSR_SIZE 0xF000000
> > +
> > +#define LS1043A_IFC0_PHYS_ADDRESS 0x60000000
> > +#define LS1043A_IFC0_SIZE SIZE_512MB
> > +#define LS1043A_IFC1_PHYS_ADDRESS 0x620000000
> > +#define LS1043A_IFC1_SIZE 0xE0000000 // 3.5 GB
> > +
> > +#define LS1043A_QSPI_PHYS_ADDRESS 0x40000000
> > +#define LS1043A_QSPI_SIZE SIZE_512MB
> > +
> > +#define LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS 0x500000000
> > +#define LS1043A_QMAN_SW_PORTAL_SIZE SIZE_128MB
> > +#define LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS 0x508000000
> > +#define LS1043A_BMAN_SW_PORTAL_SIZE SIZE_128MB
> > +
> > +#define LS1043A_PCI0_PHYS_ADDRESS 0x4000000000
> > +#define LS1043A_PCI1_PHYS_ADDRESS 0x4800000000
> > +#define LS1043A_PCI2_PHYS_ADDRESS 0x5000000000
> > +#define LS1043A_PCI_SIZE SIZE_32GB
> > +
> > +#define LS1043A_I2C0_PHYS_ADDRESS 0x2180000
> > +#define LS1043A_I2C_SIZE 0x10000
> > +#define LS1043A_I2C_NUM_CONTROLLERS 4
> > +
> > +#endif
> > diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > index 754eff396a..7ebbb1a495 100644
> > --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > @@ -26,40 +26,8 @@
> > [PcdsFixedAtBuild.common]
> > gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
> >
> > - #
> > - # CCSR Address Space and other attached Memories
> > - #
> > - gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
> > - gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
> > - gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000
> > - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000
> > - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000
> > - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000
> > - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000
> > - gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA
> > - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000
> > - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000
> > - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000
> > - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000
> > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000
> > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000
> > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000
> > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000
> > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000
> > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000
> > - gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000
> > - gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000
> > - gNxpQoriqLsTokenSpaceGuid.PcdWatchdog1BaseAddr|0x02AD0000
> > - gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000
> > - gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000
> > - gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
> > - gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
> > - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
> > - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
> > -
> > #
> > # Big Endian IPs
> > #
> > gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
> > - gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|TRUE
> > ##
> > diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > index 9baeb17ecf..a3dabc93d1 100644
> > --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > @@ -34,7 +34,7 @@ GetSysInfo (
> > CCSR_GUR *GurBase;
> > UINTN SysClk;
> >
> > - GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> > + GurBase = (CCSR_GUR *)CHASSIS2_DCFG_ADDRESS;
> > SysClk = CLK_FREQ;
> >
> > SetMem (PtrSysInfo, sizeof (SYS_INFO), 0); diff --git
> > a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > index fe77717337..d8707927b7 100644
> > --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > @@ -40,9 +40,5 @@
> > gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
> > gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
> > gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> > - gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
> > gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
> > - gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
> > gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
> > - gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr
> > - gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
> > diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> > index 4a1cfb3e27..b478560450 100644
> > --- a/Silicon/NXP/NxpQoriqLs.dec
> > +++ b/Silicon/NXP/NxpQoriqLs.dec
> > @@ -22,89 +22,15 @@
> > gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4,
> > {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
> >
> > [PcdsFixedAtBuild.common]
> > - #
> > - # Pcds for I2C Controller
> > - #
> > - gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000001
> > - gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000002
> > -
> > - #
> > - # Pcds for base address and size
> > - #
> > - gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x0|UINT64|0x00000100
> > - gNxpQoriqLsTokenSpaceGuid.PcdPiFdSize|0x0|UINT32|0x00000101
> > -
> gNxpQoriqLsTokenSpaceGuid.PcdPiFdBaseAddress|0x0|UINT64|0x00000102
> > - gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x0|UINT64|0x00000103
> > -
> >
> gNxpQoriqLsTokenSpaceGuid.PcdWatchdog1BaseAddr|0x0|UINT64|0x0000010
> 4
> > - gNxpQoriqLsTokenSpaceGuid.PcdDdrBaseAddr|0x0|UINT64|0x00000105
> > - gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x0|UINT64|0x00000106
> > - gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x0|UINT64|0x00000107
> > - gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x0|UINT64|0x00000108
> > - gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x0|UINT32|0x00000109
> > - gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x0|UINT64|0x0000010A
> > - gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0|UINT64|0x0000010B
> > - gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x0000010C
> > - gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x0000010D
> > -
> gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0|UINT64|0x0000010E
> > - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0|UINT64|0x0000010F
> > -
> gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0|UINT64|0x00000110
> > - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0|UINT64|0x00000111
> > -
> gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x0|UINT64|0x00000112
> > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x0|UINT64|0x00000113
> > -
> gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x0|UINT64|0x00000114
> > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x0|UINT64|0x00000115
> > -
> gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x0|UINT64|0x00000116
> > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x0|UINT64|0x00000117
> > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x0|UINT64|0x0000118
> > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x0|UINT64|0x0000119
> > -
> >
> gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x0|UINT64|0x0000011
> A
> > - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x0|UINT64|0x0000011B
> > -
> >
> gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x0|UINT64|0x000001
> 1C
> > -
> gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x0|UINT64|0x0000011D
> > -
> >
> gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExBase|0x0|UINT64|0x00000
> 11E
> > -
> >
> gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExSize|0x0|UINT64|0x000001
> 1F
> > - gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x0|UINT32|0x00000120
> > - gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x0|UINT32|0x00000121
> > - gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000122
> > - gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000123
> > -
> > - #
> > - # IFC PCDs
> > - #
> > -
> >
> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x0|UINT64|0x0000019
> 0
> > - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x0|UINT64|0x00000191
> > -
> >
> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0|UINT64|0x0000019
> 2
> > - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x0|UINT64|0x00000193
> > -
> >
> gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x0|UINT32|0x0000019
> 4
> > -
> >
> gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x0|UINT64|0x00000195
> > -
> >
> gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x0|UINT64|0x0
> 0
> > 000196
> > -
> > - #
> > - # NV Pcd
> > - #
> > - gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase|0x0|UINT64|0x00000210
> > - gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize|0x0|UINT64|0x00000211
>
> Not able to be different between different platforms using the same SoC?
This is a redundant Pcd. For Non Volatile Variables we already have PCDs like
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64
>
> > -
> > #
> > # Platform PCDs
> > #
> > gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
> > -
> >
> gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x0000025
> 1
> > -
> > - #
> > - # Clock PCDs
> > - #
> > - gNxpQoriqLsTokenSpaceGuid.PcdSysClk|0x0|UINT64|0x000002A0
> > - gNxpQoriqLsTokenSpaceGuid.PcdDdrClk|0x0|UINT64|0x000002A1
>
> And clocks also sound very much like something that can change per platform?
Yes Clocks can change. And also clocks are not fixed in all platforms. i.e. in most of the platforms based on the
switch settings, FPGA or Clock generator can be configured to provide different SYS clock / DDR Clock / SERDES clock etc.
Also we need the clock even when we don't have the support for PCD framework.
Which is why we have moved the clock functionality in ArmPlatformLib
Refer "NxpPlatformGetClock" in patch 14/19.
>
> /
> Leif
>
> >
> > #
> > # Pcds to support Big Endian IPs
> > #
> > -
> gNxpQoriqLsTokenSpaceGuid.PcdMmcBigEndian|FALSE|BOOLEAN|0x0000310
> >
> gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311
> > -
> >
> gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x0000031
> 2
> > -
> >
> gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|FALSE|BOOLEAN|0x0000
> 031
> > 3
> > -
> gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314
> >
> > [PcdsFeatureFlag]
> >
> >
> gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x0000
> 031
> > 5
> > --
> > 2.17.1
> >
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 09/19] Silicon/NXP: Move dsc file
2020-02-07 12:43 ` [PATCH 09/19] Silicon/NXP: Move dsc file Pankaj Bansal
@ 2020-02-11 11:35 ` Leif Lindholm
0 siblings, 0 replies; 49+ messages in thread
From: Leif Lindholm @ 2020-02-11 11:35 UTC (permalink / raw)
To: Pankaj Bansal; +Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi, devel
On Fri, Feb 07, 2020 at 18:13:18 +0530, Pankaj Bansal wrote:
> As per convention being followed in edk2-platforms, keep the dec
> file and dsc file together.
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
> ---
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 2 +-
> {Platform => Silicon}/NXP/NxpQoriqLs.dsc.inc | 0
> 2 files changed, 1 insertion(+), 1 deletion(-)
> rename {Platform => Silicon}/NXP/NxpQoriqLs.dsc.inc (100%)
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> index 74a1948fc6..7cffd09d7d 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> @@ -22,7 +22,7 @@
> OUTPUT_DIRECTORY = Build/LS1043aRdbPkg
> FLASH_DEFINITION = Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
>
> -!include Platform/NXP/NxpQoriqLs.dsc.inc
> +!include Silicon/NXP/NxpQoriqLs.dsc.inc
> !include Silicon/NXP/LS1043A/LS1043A.dsc.inc
>
> [LibraryClasses.common]
> diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
> similarity index 100%
> rename from Platform/NXP/NxpQoriqLs.dsc.inc
> rename to Silicon/NXP/NxpQoriqLs.dsc.inc
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 10/19] Platform/NXP: rename the ArmPlatformLib as per ArmPlatformPkg
2020-02-07 12:43 ` [PATCH 10/19] Platform/NXP: rename the ArmPlatformLib as per ArmPlatformPkg Pankaj Bansal
@ 2020-02-11 11:40 ` Leif Lindholm
0 siblings, 0 replies; 49+ messages in thread
From: Leif Lindholm @ 2020-02-11 11:40 UTC (permalink / raw)
To: Pankaj Bansal; +Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi, devel
On Fri, Feb 07, 2020 at 18:13:19 +0530, Pankaj Bansal wrote:
> Keep the names and location of files as mentioned in ArmPlatformPkg.
This isn't really a goal in itself, but the AArch64/ addition is good
cleanup, so I'm not objecting. But please mention that one explicitly.
> This helps in porting the common changes (if any in future) easily.
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 2 +-
> .../AArch64}/NxpQoriqLsHelper.S | 2 +-
> .../Library/{PlatformLib => ArmPlatformLib}/ArmPlatformLib.c | 2 +-
> .../{PlatformLib => ArmPlatformLib}/ArmPlatformLib.inf | 4 ++--
> .../NxpQoriqLsMem.c => ArmPlatformLib/ArmPlatformLibMem.c} | 0
> 5 files changed, 5 insertions(+), 5 deletions(-)
> rename Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib => ArmPlatformLib/AArch64}/NxpQoriqLsHelper.S (88%)
> rename Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib => ArmPlatformLib}/ArmPlatformLib.c (93%)
> rename Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib => ArmPlatformLib}/ArmPlatformLib.inf (89%)
> rename Platform/NXP/LS1043aRdbPkg/Library/{PlatformLib/NxpQoriqLsMem.c => ArmPlatformLib/ArmPlatformLibMem.c} (100%)
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> index 7cffd09d7d..bc6fa4f19d 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> @@ -26,7 +26,7 @@
> !include Silicon/NXP/LS1043A/LS1043A.dsc.inc
>
> [LibraryClasses.common]
> - ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> + ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
>
> [PcdsFixedAtBuild.common]
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/NxpQoriqLsHelper.S
> similarity index 88%
> rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/NxpQoriqLsHelper.S
> index 84ee8c9f97..dfbf73675a 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/NxpQoriqLsHelper.S
> @@ -1,7 +1,7 @@
> # @file
> #
> # Copyright (c) 2012-2013, ARM Limited. All rights reserved.
> -# Copyright 2017 NXP
> +# Copyright 2017, 2020 NXP
I don't think renaming a file qualifies for updating copyright on it.
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> similarity index 93%
> rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> index eac7d4aa4e..718c71bf02 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> @@ -6,7 +6,7 @@
> *
> * Copyright (c) 2011-2012, ARM Limited. All rights reserved.
> * Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> -* Copyright 2017 NXP
> +* Copyright 2017, 2020 NXP
Same again.
/
Leif
> * SPDX-License-Identifier: BSD-2-Clause-Patent
> *
> **/
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> similarity index 89%
> rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> index 054dc4d003..6396d2982b 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> @@ -27,8 +27,8 @@
> SocLib
>
> [Sources.common]
> - NxpQoriqLsHelper.S | GCC
> - NxpQoriqLsMem.c
> + AArch64/NxpQoriqLsHelper.S | GCC
> + ArmPlatformLibMem.c
> ArmPlatformLib.c
>
> [Ppis]
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
> similarity index 100%
> rename from Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> rename to Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 11/19] Silicon/NXP: Add Chassis Lib for Chassis2
2020-02-07 12:43 ` [PATCH 11/19] Silicon/NXP: Add Chassis Lib for Chassis2 Pankaj Bansal
@ 2020-02-11 12:28 ` Leif Lindholm
0 siblings, 0 replies; 49+ messages in thread
From: Leif Lindholm @ 2020-02-11 12:28 UTC (permalink / raw)
To: Pankaj Bansal; +Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi, devel
On Fri, Feb 07, 2020 at 18:13:20 +0530, Pankaj Bansal wrote:
> Add ChassisLib for Chassis2.
What is a Chassis2?
This adds a new package, a new library class - it needs more description.
Can we expect to see Silicon/NXP/Library/SocLib/Chassis.c broken out
into its own package in future?
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> Silicon/NXP/Chassis2/Chassis2.dec | 23 +++
> Silicon/NXP/Chassis2/Chassis2.dsc.inc | 10 +
> Silicon/NXP/Chassis2/Include/Chassis.h | 42 ++++
> .../Chassis2/Library/ChassisLib/ChassisLib.c | 186 ++++++++++++++++++
> .../Library/ChassisLib/ChassisLib.inf | 41 ++++
> Silicon/NXP/Include/Library/ChassisLib.h | 41 ++++
> Silicon/NXP/NxpQoriqLs.dec | 4 +
> 7 files changed, 347 insertions(+)
> create mode 100644 Silicon/NXP/Chassis2/Chassis2.dec
> create mode 100644 Silicon/NXP/Chassis2/Chassis2.dsc.inc
> create mode 100644 Silicon/NXP/Chassis2/Include/Chassis.h
> create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
> create mode 100644 Silicon/NXP/Include/Library/ChassisLib.h
>
> diff --git a/Silicon/NXP/Chassis2/Chassis2.dec b/Silicon/NXP/Chassis2/Chassis2.dec
> new file mode 100644
> index 0000000000..106b118188
> --- /dev/null
> +++ b/Silicon/NXP/Chassis2/Chassis2.dec
> @@ -0,0 +1,23 @@
> +#/** @file
> +# NXP Layerscape processor package.
> +#
> +# Copyright 2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#**/
> +
> +[Defines]
> + DEC_SPECIFICATION = 1.27
> + PACKAGE_VERSION = 0.1
> +
> +################################################################################
> +#
> +# Include Section - list of Include Paths that are provided by this package.
> +# Comments are used for Keywords and Module Types.
> +#
> +#
> +################################################################################
> +[Includes.common]
> + Include # Root include for the package
> +
> diff --git a/Silicon/NXP/Chassis2/Chassis2.dsc.inc b/Silicon/NXP/Chassis2/Chassis2.dsc.inc
> new file mode 100644
> index 0000000000..db8e5a92ea
> --- /dev/null
> +++ b/Silicon/NXP/Chassis2/Chassis2.dsc.inc
> @@ -0,0 +1,10 @@
> +# @file
> +#
> +# Copyright 2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +
> +[LibraryClasses.common]
> + ChassisLib|Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
> diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h b/Silicon/NXP/Chassis2/Include/Chassis.h
> new file mode 100644
> index 0000000000..48ba2e7bfb
> --- /dev/null
> +++ b/Silicon/NXP/Chassis2/Include/Chassis.h
> @@ -0,0 +1,42 @@
> +/** @file
> +
> + Copyright 2020 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +#ifndef __CHASSIS_H__
> +#define __CHASSIS_H__
Please drop leading __ from incude guards.
> +
> +#define NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS 0x1EE0000
> +
> +#define TP_CLUSTER_ITYPE_IDX 0x3f
> +#define TP_CLUSTER_EOC BIT31
> +#define TP_ITYPE_AVAILABLE BIT0
> +#define TP_ITYPE_TYPE(x) (((x) & 0x06) >> 1)
> +#define TP_ITYPE_ARM 0x0
> +#define TP_ITYPE_VERSION(x) (((x) & 0xe0) >> 5)
> +
> +#define TP_ITYPE_VERSION_A53 0x2
> +#define TP_ITYPE_VERSION_A72 0x4
> +
> +/**
> + The Device Configuration Unit provides general purpose configuration and status for the
> + device. These registers only support 32-bit accesses.
> +**/
> +#pragma pack(1)
> +typedef struct {
> + UINT8 Reserved0[0x100 - 0x0];
> + UINT32 RcwSr[16]; // Reset Control Word Status Register
> + UINT8 Reserved140[0x200 - 0x140];
> + UINT32 ScratchRw[16]; /// Scratch Read / Write Register
> + UINT8 Reserved240[0x740-0x240];
> + UINT32 TpItyp[65]; /// Topology Initiator Type Register
> + struct {
> + UINT32 Lower;
> + UINT32 Upper;
> + }TpCluster[8];
> +} NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG;
> +#pragma pack()
> +
> +#endif
> diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> new file mode 100644
> index 0000000000..fa6a36e96f
> --- /dev/null
> +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> @@ -0,0 +1,186 @@
> +/** @file
> + Chassis specific functions common to all SOCs based on a specific Chessis
> +
> + Copyright 2020 NXP
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Chassis.h>
> +#include <Uefi.h>
> +#include <Library/IoLib.h>
> +#include <Library/IoAccessLib.h>
Plese sort includes alphabetically.
> +#include <Library/PcdLib.h>
> +#include <Library/SerialPortLib.h>
> +#include <Ppi/ArmMpCoreInfo.h>
> +
> +UINT32
> +EFIAPI
> +DcfgRead32 (
OK, so after 3 years of review, I failed to spot the set I merged
doesn't actually make use of the GetMmioOperations* functions
introduced in IoAccessLib to get away from this needless code
duplication.
Ideally, I would like to see some patches that remedy this situation
in the alredy merged code.
But it certainly needs to be used for any new additions.
> + IN UINTN Address
> + )
> +{
> + if (FeaturePcdGet (PcdDcfgBigEndian)) {
> + return SwapMmioRead32 (Address);
> + } else {
> + return MmioRead32 (Address);
> + }
> +}
> +
> +UINT32
> +EFIAPI
> +DcfgWrite32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + )
> +{
> + if (FeaturePcdGet (PcdDcfgBigEndian)) {
> + return SwapMmioWrite32 (Address, Value);
> + } else {
> + return MmioWrite32 (Address, Value);
> + }
> +}
> +
> +/**
> + Get the type of core in cluster
> +
> + The core can be of type ARM or PowerPC or Hardware Accelerator.
> + If the core is enabled and of type ARM EFI_SUCCESS is returned and a code for type of ARM core is returned
Please wrap long lines.
> +
> + @param[in] TpItypeIdx Index of Core to be searched in TpItyp in Device Config Registers.
TpItype or TpItyp?
Neither Tp nor Itype are known abbreviations, so need to be explained
in file comment header, unless they can be given more generically
descriptive names.
> + @param[out] CoreType If the core is ARM core then the type of core i.e. A53/A72 etc.
> + These cores are identified based on their codes like TP_ITYPE_VERSION_A72
> +
> + @return EFI_NOT_FOUND No enabled ARM core found
> + @return EFI_SUCCESS An enabled ARM core found
> +**/
> +STATIC
> +EFI_STATUS
> +SocGetCoreType (
> + IN UINT8 TpItypeIdx,
> + OUT UINT8 *CoreType
> + )
> +{
> + NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG *Dcfg;
> + UINT32 TpItype;
> +
> + Dcfg = (NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG *)NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS;
> + TpItype = MmioRead32 ((UINTN)&Dcfg->TpItyp[TpItypeIdx]);
> + if (TpItype & TP_ITYPE_AVAILABLE) {
> + if (TP_ITYPE_TYPE (TpItype) == TP_ITYPE_ARM) {
> + *CoreType = TP_ITYPE_VERSION (TpItype);
> + } else {
> + return EFI_NOT_FOUND;
> + }
> + } else {
> + return EFI_NOT_FOUND;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Return the number of cores present in SOC
> +
> + This function returns the number of cores present in SOC.
> + and also their position (cluster number and core number) in the form of ARM_CORE_INFO array
Please wrap long lines.
> + and NxpCoreTable array.
> + NxpCoreTable array can be used to find out the type of core. it's values are of type
> + TP_ITYPE_VERSION_*.
> + The number of cores present in SOC can vary depending on which flavour of SOC is being used.
> + This function doesn't allocte any memory and must be provided memory for array of ARM_CORE_INFO
> + and NxpCoreTable for maximum number of cores the SOC can have.
> +
> + @param[out] NxpCoreTable array of UINT8 for maximum number of cores the SOC can have.
> + @param[out] ArmCoreTable array of ARM_CORE_INFO for maximum number of cores the SOC can have.
> + @param[in] ArmCoreTableSize Size of ArmCoreTable
> +
> + @return Actual number of cores present in SOC. After calling this function only the returned value number of
> + entries in ArmCoreTable are valid entries.
> +**/
> +UINTN
> +__attribute__((weak))
There is nothing *wrong* about using weak symbols, but it usually done
either for some specific workarouns, or as part of a defined usage
model to override things at different levels of software.
It is not clear to me what that usage model is here - could you
document it please?
> +SocGetMpCoreInfo (
> + OUT UINT8 *NxpCoreTable,
> + OUT ARM_CORE_INFO *ArmCoreTable,
> + IN UINTN CoreTableSize
> + )
> +{
> + NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG *Dcfg;
> + UINT32 TpClusterLower;
> + UINT8 TpClusterParser;
TpCusterLower/TpClusterParser are not generic terms - could they be
documented or renamed more generically.
> + UINT8 ClusterIndex;
> + UINT8 CoreIndex;
> + UINTN CoreCount;
> + UINT8 CoreType;
> + EFI_STATUS Status;
> +
> + Dcfg = (NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG *)NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS;
> + ClusterIndex = 0;
> + CoreCount = 0;
> + while (TRUE) {
> + TpClusterLower = MmioRead32 ((UINTN)&Dcfg->TpCluster[ClusterIndex].Lower);
> + for (CoreIndex = 0; CoreIndex < (sizeof (TpClusterLower) / sizeof (TpClusterParser)); CoreIndex++) {
I don't see a value in calculating sizeof(UINT32)/sizeof(UINT8).
A strategically placed #define would be more clear (and shorten the
line length).
> + TpClusterParser = (TpClusterLower >> (8 * CoreIndex));
And I would prefer to see that 8 replaced by another #define.
> + Status = SocGetCoreType (TpClusterParser & TP_CLUSTER_ITYPE_IDX, &CoreType);
> + if (Status != EFI_NOT_FOUND) {
> + ArmCoreTable[CoreCount].ClusterId = ClusterIndex;
> + ArmCoreTable[CoreCount].CoreId = CoreIndex;
> + ArmCoreTable[CoreCount].MailboxSetAddress = 0;
> + ArmCoreTable[CoreCount].MailboxGetAddress = 0;
> + ArmCoreTable[CoreCount].MailboxClearAddress = 0;
> + ArmCoreTable[CoreCount].MailboxClearValue = ~0;
> +
> + NxpCoreTable[CoreCount] = CoreType;
> + CoreCount++;
> + if (CoreCount == CoreTableSize) {
> + break;
> + }
> + }
> + }
> + if (TpClusterLower & TP_CLUSTER_EOC) {
> + break;
> + }
> + if (CoreCount == CoreTableSize) {
> + break;
> + }
> + ClusterIndex++;
> + }
> +
> + return CoreCount;
> +}
> +
> +/**
> + Function to initialize Chassis Specific functions
> + **/
> +VOID
> +ChassisInit (
> + VOID
> + )
> +{
> + UINT64 BaudRate;
> + UINT32 ReceiveFifoDepth;
> + EFI_PARITY_TYPE Parity;
> + UINT8 DataBits;
> + EFI_STOP_BITS_TYPE StopBits;
> + UINT32 Timeout;
> +
> + BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
> + ReceiveFifoDepth = FixedPcdGet16 (PcdUartDefaultReceiveFifoDepth); // Use default FIFO depth
> + Timeout = 0;
> + Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
> + DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
> + StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);
> +
> + //
> + // Early init serial Port to get board information.
> + //
> + SerialPortSetAttributes (
> + &BaudRate,
> + &ReceiveFifoDepth,
> + &Timeout,
> + &Parity,
> + &DataBits,
> + &StopBits
> + );
> +}
> diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
> new file mode 100644
> index 0000000000..4964bb4e82
> --- /dev/null
> +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
> @@ -0,0 +1,41 @@
> +#/** @file
> +#
> +# Copyright 2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause
> +#
> +#**/
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = Chassis2Lib
> + FILE_GUID = fae0d077-5fc2-494f-b8e1-c51a3023ee3e
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = ChassisLib
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + ArmPkg/ArmPkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> + Silicon/NXP/Chassis2/Chassis2.dec
Please sort packages alphabetically.
> +
> +[LibraryClasses]
> + IoLib
> + IoAccessLib
Please sort library classes alphabetically.
> + PcdLib
> + SerialPortLib
> +
> +[Sources.common]
> + ChassisLib.c
> +
> +[FeaturePcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian
> +
> +[FixedPcd]
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth
Please sort Pcds alphabetically (i.e. swap final two lines).
> +
> diff --git a/Silicon/NXP/Include/Library/ChassisLib.h b/Silicon/NXP/Include/Library/ChassisLib.h
> new file mode 100644
> index 0000000000..b51b024374
> --- /dev/null
> +++ b/Silicon/NXP/Include/Library/ChassisLib.h
> @@ -0,0 +1,41 @@
> +/** @file
> + I2c Lib to control I2c controller.
> +
> + Copyright 2020 NXP
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef __CHASSIS_LIB_H__
> +#define __CHASSIS_LIB_H__
Please drop leading __ from include guards.
> +
> +#include <Chassis.h>
Include files should only include those files needed for their own
definitions.
> +
> +/**
> + Read Dcfg register
> +**/
> +UINT32
> +EFIAPI
> +DcfgRead32 (
> + IN UINTN Address
> + );
> +
> +/**
> + Write Dcfg register
> +**/
> +UINT32
> +EFIAPI
> +DcfgWrite32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + );
> +
The above two prototypes can be deleted.
> +/**
> + Function to initialize Chassis Specific functions
> + **/
> +VOID
> +ChassisInit (
> + VOID
> + );
> +
> +#endif
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index b478560450..d8989657e6 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -14,6 +14,9 @@
> Include
>
> [LibraryClasses]
> + ## @libraryclass Provides Chassis specific functions to other modules
> + ChassisLib|Include/Library/ChassisLib.h
> +
> ## @libraryclass Provides services to read/write to I2c devices
> I2cLib|Include/Library/I2cLib.h
>
> @@ -34,4 +37,5 @@
>
> [PcdsFeatureFlag]
> gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315
> + gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000316
I would prefer for this flag to be added with the other *BigEndian
flags in the same file.
Looping back to a previous patch - looking at the Pcd tokens used, it
would be more convenient if PcdI2cErratumA009203 was kept as part of a
separate group and token 0x315 was given to PcdDcfgBigEndian.
/
Leif
>
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 12/19] Silicon/NXP/LS1043A: Add SocLib
2020-02-07 12:43 ` [PATCH 12/19] Silicon/NXP/LS1043A: Add SocLib Pankaj Bansal
@ 2020-02-11 12:38 ` Leif Lindholm
0 siblings, 0 replies; 49+ messages in thread
From: Leif Lindholm @ 2020-02-11 12:38 UTC (permalink / raw)
To: Pankaj Bansal; +Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi, devel
On Fri, Feb 07, 2020 at 18:13:21 +0530, Pankaj Bansal wrote:
> Add SocLib for LS1043A as per new directory structure
OK, now I'm confused again.
Separating the Chassis library from the SoC library seemed sensible.
But now we're merging them together again, only the other way around?
Can you explain why?
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> Silicon/NXP/Chassis2/LS1043A/Include/Soc.h | 56 +++++++++++++
> Silicon/NXP/Chassis2/LS1043A/LS1043A.dec | 23 ++++++
> Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc | 30 +++++++
> .../Chassis2/LS1043A/Library/SocLib/SocLib.c | 73 +++++++++++++++++
> .../LS1043A/Library/SocLib/SocLib.inf | 32 ++++++++
> Silicon/NXP/Include/Library/SocLib.h | 81 +++++++++++++++++++
> Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h | 47 +++++++++++
> Silicon/NXP/NxpQoriqLs.dec | 3 +
> 8 files changed, 345 insertions(+)
> create mode 100644 Silicon/NXP/Chassis2/LS1043A/Include/Soc.h
> create mode 100644 Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
> create mode 100644 Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
> create mode 100644 Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
> create mode 100644 Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> create mode 100644 Silicon/NXP/Include/Library/SocLib.h
> create mode 100644 Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h
>
> diff --git a/Silicon/NXP/Chassis2/LS1043A/Include/Soc.h b/Silicon/NXP/Chassis2/LS1043A/Include/Soc.h
> new file mode 100644
> index 0000000000..3b11b2b126
> --- /dev/null
> +++ b/Silicon/NXP/Chassis2/LS1043A/Include/Soc.h
> @@ -0,0 +1,56 @@
> +/** @file
> +
> + Copyright 2020 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +#ifndef __SOC_H__
> +#define __SOC_H__
Please drop leading __ from include guards.
> +
> +#include <Chassis.h>
> +
> +/**
> + Soc Memory Map
> +**/
> +#define LS1043A_DRAM0_PHYS_ADDRESS 0x80000000
> +#define LS1043A_DRAM0_SIZE SIZE_2GB
> +#define LS1043A_DRAM1_PHYS_ADDRESS 0x880000000
> +#define LS1043A_DRAM1_SIZE 0x780000000 // 30 GB
> +
> +#define LS1043A_CCSR_PHYS_ADDRESS 0x1000000
> +#define LS1043A_CCSR_SIZE 0xF000000
> +
> +#define LS1043A_IFC0_PHYS_ADDRESS 0x60000000
> +#define LS1043A_IFC0_SIZE SIZE_512MB
> +#define LS1043A_IFC1_PHYS_ADDRESS 0x620000000
> +#define LS1043A_IFC1_SIZE 0xE0000000 // 3.5 GB
> +
> +#define LS1043A_QSPI_PHYS_ADDRESS 0x40000000
> +#define LS1043A_QSPI_SIZE SIZE_512MB
> +
> +#define LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS 0x500000000
> +#define LS1043A_QMAN_SW_PORTAL_SIZE SIZE_128MB
> +#define LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS 0x508000000
> +#define LS1043A_BMAN_SW_PORTAL_SIZE SIZE_128MB
> +
> +#define LS1043A_PCI0_PHYS_ADDRESS 0x4000000000
> +#define LS1043A_PCI1_PHYS_ADDRESS 0x4800000000
> +#define LS1043A_PCI2_PHYS_ADDRESS 0x5000000000
> +#define LS1043A_PCI_SIZE SIZE_32GB
> +
> +#define LS1043A_I2C0_PHYS_ADDRESS 0x2180000
> +#define LS1043A_I2C_SIZE 0x10000
> +#define LS1043A_I2C_NUM_CONTROLLERS 4
> +
> +#define LS1043A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS
> +
> +/**
> + Reset Control Word (RCW) Bits
> +**/
> +#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6
RAT is an unknown term, what is it short for?
> +
> +typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1043A_DEVICE_CONFIG;
> +
> +#endif
> +
> diff --git a/Silicon/NXP/Chassis2/LS1043A/LS1043A.dec b/Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
> new file mode 100644
> index 0000000000..106b118188
> --- /dev/null
> +++ b/Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
> @@ -0,0 +1,23 @@
> +#/** @file
> +# NXP Layerscape processor package.
> +#
> +# Copyright 2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#**/
> +
> +[Defines]
> + DEC_SPECIFICATION = 1.27
> + PACKAGE_VERSION = 0.1
> +
> +################################################################################
> +#
> +# Include Section - list of Include Paths that are provided by this package.
> +# Comments are used for Keywords and Module Types.
> +#
> +#
> +################################################################################
> +[Includes.common]
> + Include # Root include for the package
*If* we are merging Soc and Chassis again - why do we need separate
include paths?
> +
> diff --git a/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
> new file mode 100644
> index 0000000000..4511203443
> --- /dev/null
> +++ b/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
> @@ -0,0 +1,30 @@
> +# @file
> +#
> +# Copyright 2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +
> +[LibraryClasses.common]
> + SocLib|Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> +
> +################################################################################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +################################################################################
> +[PcdsFeatureFlag.common]
> + gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|TRUE
> +
> +[PcdsFixedAtBuild.common]
> +## ns16550 Serial Terminal
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x21c0500
> + gArmPlatformTokenSpaceGuid.PcdCoreCount|4
> +
> +[PcdsDynamicDefault.common]
> + #
> + # ARM General Interrupt Controller
> + gArmTokenSpaceGuid.PcdGicDistributorBase|0x1401000
> + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x1402000
> +
> diff --git a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
> new file mode 100644
> index 0000000000..2a08ad87db
> --- /dev/null
> +++ b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
> @@ -0,0 +1,73 @@
> +/** @file
> +
> + Copyright 2017-2020 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> + **/
> +#include <Library/ChassisLib.h>
> +#include <Library/SocLib.h>
> +
> +/**
> + Return the input clock frequency to an IP Module.
> + This function reads the RCW bits and calculates the PLL multipler/divider values to be applied
> + to various IP modules.
> + If a module is disabled or doesn't exist on platform, then return zero.
> +
> + @param[in] BaseClock Base clock to which PLL multipler/divider values is to be applied.
> + @param[in] ClockType IP modules whose clock value is to be retrieved
> + @param[in] Args Variable Args lists that is parsed based on the ClockType
> + e.g. if there are multiple modules of same type then this value tells the
> + instance of module for which clock is to be retrieved.
> + (e.g. if there are four i2c controllers in SOC, then this value can be 1, 2, 3, 4)
> + for IP modules which have only single instance in SOC (e.g. one QSPI controller)
> + this value can be null (i.e. no arg)
Please wrap long lines (throughout).
> +
> + @return > 0 Return the input clock frequency to an IP Module
> + 0 either IP module doesn't exist in SOC
> + or IP module instance doesn't exist in SOC
> + or IP module instance is disabled. i.e. no input clock is provided to IP module instance.
> +**/
> +UINT64
> +SocGetClock (
> + IN UINT64 BaseClock,
> + IN UINT32 ClockType,
> + IN VA_LIST Args
> + )
> +{
> + LS1043A_DEVICE_CONFIG *Dcfg;
> + UINT32 RcwSr;
> + UINT64 ReturnValue;
> +
> + ReturnValue = 0;
> + Dcfg = (LS1043A_DEVICE_CONFIG *)LS1043A_DCFG_ADDRESS;
Extra space in cast.
> +
> + switch (ClockType) {
> + case NXP_UART_CLOCK:
> + case NXP_I2C_CLOCK:
> + RcwSr = DcfgRead32 ((UINTN)&Dcfg->RcwSr[0]);
> + ReturnValue = BaseClock * SYS_PLL_RAT (RcwSr);
> + break;
> + default:
> + break;
> + }
> +
> + return ReturnValue;
> +}
> +
> +/**
> + Function to initialize SoC specific constructs
> + CPU Info
> + SoC Personality
> + Board Personality
> + RCW prints
> + **/
> +VOID
> +SocInit (
> + VOID
> + )
> +{
> + ChassisInit ();
> +
> + return;
> +}
> +
> diff --git a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> new file mode 100644
> index 0000000000..c9a4fbc01f
> --- /dev/null
> +++ b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> @@ -0,0 +1,32 @@
> +#@file
> +#
> +# Component description file for SocLib module
> +#
> +# Copyright 2017-2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +
> +[Defines]
> + INF_VERSION = 0x0001000A
> + BASE_NAME = SocLib
> + FILE_GUID = 9b046753-2b4f-42d8-bfb3-468892fe17d4
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = SocLib
> +
> +[Sources.common]
> + SocLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> + Silicon/NXP/Chassis2/Chassis2.dec
> + Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
Please sort packages alphabetically.
> +
> +[LibraryClasses]
> + ChassisLib
> +
> diff --git a/Silicon/NXP/Include/Library/SocLib.h b/Silicon/NXP/Include/Library/SocLib.h
> new file mode 100644
> index 0000000000..3def396171
> --- /dev/null
> +++ b/Silicon/NXP/Include/Library/SocLib.h
> @@ -0,0 +1,81 @@
> +/** @file
> +
> + Copyright 2020 NXP
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef __SOC_LIB_H__
> +#define __SOC_LIB_H__
Please drop leading __ from header guards.
> +
> +#include <Soc.h>
> +#include <Uefi.h>
> +#include <Ppi/ArmMpCoreInfo.h>
> +#include <Ppi/NxpPlatformGetClock.h>
> +
> +/**
> + Return the number of cores present in SOC
> +
> + This function returns the number of cores present in SOC.
> + and also their position (cluster number and core number) in the form of ARM_CORE_INFO array
> + and NxpCoreTable array.
> + NxpCoreTable array can be used to find out the type of core. it's values are of type
> + TP_ITYPE_VERSION_*.
> + The number of cores present in SOC can vary depending on which flavour of SOC is being used.
> + This function doesn't allocte any memory and must be provided memory for array of ARM_CORE_INFO
> + and NxpCoreTable for maximum number of cores the SOC can have.
> +
> + @param[out] NxpCoreTable array of UINT8 for maximum number of cores the SOC can have.
> + @param[out] ArmCoreTable array of ARM_CORE_INFO for maximum number of cores the SOC can have.
> + @param[in] ArmCoreTableSize Size of ArmCoreTable
> +
> + @return Actual number of cores present in SOC. After calling this function only the returned value number of
> + entries in ArmCoreTable are valid entries.
> +**/
> +UINTN
> +SocGetMpCoreInfo (
> + OUT UINT8 *NxpCoreTable,
> + OUT ARM_CORE_INFO *ArmCoreTable,
> + IN UINTN ArmCoreTableSize
> + );
> +
> +/**
> + Return the input clock frequency to an IP Module.
> + This function reads the RCW bits and calculates the PLL multipler/divider values to be applied
> + to various IP modules.
> + If a module is disabled or doesn't exist on platform, then return zero.
> +
> + @param[in] BaseClock Base clock to which PLL multipler/divider values is to be applied.
> + @param[in] ClockType IP modules whose clock value is to be retrieved
> + @param[in] Args Variable Args lists that is parsed based on the ClockType
> + e.g. if there are multiple modules of same type then this value tells the
> + instance of module for which clock is to be retrieved.
> + (e.g. if there are four i2c controllers in SOC, then this value can be 1, 2, 3, 4)
> + for IP modules which have only single instance in SOC (e.g. one QSPI controller)
> + this value can be null (i.e. no arg)
> +
> + @return > 0 Return the input clock frequency to an IP Module
> + 0 either IP module doesn't exist in SOC
> + or IP module instance doesn't exist in SOC
> + or IP module instance is disabled. i.e. no input clock is provided to IP module instance.
> +**/
> +UINT64
> +SocGetClock (
> + IN UINT64 BaseClock,
> + IN UINT32 ClockType,
> + IN VA_LIST Args
> + );
> +
> +/**
> + Function to initialize SoC specific constructs
> + CPU Info
> + SoC Personality
> + Board Personality
> + RCW prints
> + **/
> +VOID
> +SocInit (
> + VOID
> + );
> +
> +#endif // __SOC_LIB_H__
> diff --git a/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h b/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h
> new file mode 100644
> index 0000000000..2c8c97987d
> --- /dev/null
> +++ b/Silicon/NXP/Include/Ppi/NxpPlatformGetClock.h
> @@ -0,0 +1,47 @@
> +/** @file
> +*
> +* Copyright 2020 NXP
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#ifndef __NXP_PLATFORM_PPI_H__
> +#define __NXP_PLATFORM_PPI_H__
Please drop leading __ from header guards.
> +
> +#include <Uefi.h>
> +
> +#define NXP_PLATFORM_GET_CLOCK_PPI_GUID \
> + { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }
> +
> +typedef enum _NXP_IP_CLOCK {
> + NXP_SYSTEM_CLOCK,
> + NXP_UART_CLOCK,
> + NXP_I2C_CLOCK
> +} NXP_IP_CLOCK;
> +
> +/**
> + Get the clocks supplied by Platform(Board) to NXP Layerscape SOC
> +
> + The core can be of type ARM or PowerPC or Hardware Accelerator.
> + If the core is enabled and of type ARM EFI_SUCCESS is returned and a code for type of ARM core is returned
> +
> + @param[in] ClockType Type of clock
> + @param[in] ... Variable argument list which is parsed based on ClockType
> +
> + @return Actual Clock Frequency. return value 0 should be interpreted as clock not provided by Board.
Funky alignment of argument/return descriptions.
/
Leif
> +**/
> +typedef
> +UINT64
> +(EFIAPI * NXP_PLATFORM_GET_CLOCK)(
> + IN UINT32 ClockType,
> + ...
> + );
> +
> +typedef struct {
> + NXP_PLATFORM_GET_CLOCK PlatformGetClock;
> +} NXP_PLATFORM_GET_CLOCK_PPI;
> +
> +extern EFI_GUID gNxpPlatformGetClockPpiGuid;
> +
> +#endif
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index d8989657e6..4f14cc9848 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -14,6 +14,9 @@
> Include
>
> [LibraryClasses]
> + ## @libraryclass Provides Soc specific functions to other modules
> + SocLib|Include/Library/SocLib.h
> +
> ## @libraryclass Provides Chassis specific functions to other modules
> ChassisLib|Include/Library/ChassisLib.h
>
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 13/19] Silicon/NXP: Move RAM retrieval from SocLib
2020-02-07 12:43 ` [PATCH 13/19] Silicon/NXP: Move RAM retrieval from SocLib Pankaj Bansal
@ 2020-02-11 13:28 ` Leif Lindholm
0 siblings, 0 replies; 49+ messages in thread
From: Leif Lindholm @ 2020-02-11 13:28 UTC (permalink / raw)
To: Pankaj Bansal; +Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi, devel
On Fri, Feb 07, 2020 at 18:13:22 +0530, Pankaj Bansal wrote:
> RAM retrieval using SMC commands is common to all Layerscape SOCs.
> Therefore, move it to commom MemoryInit Pei Lib.
>
> Also added provision to reserve a portion of RAM.
"Also" is an indicator of something that should be a separate patch.
That patch could explain the use case for the reservation function.
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> Silicon/NXP/Include/DramInfo.h | 38 ---
> .../Library/MemoryInitPei/MemoryInitPeiLib.c | 235 +++++++++++++++---
> .../Library/MemoryInitPei/MemoryInitPeiLib.h | 24 ++
> .../MemoryInitPei/MemoryInitPeiLib.inf | 8 +
> Silicon/NXP/Library/SocLib/Chassis.c | 67 -----
> Silicon/NXP/NxpQoriqLs.dec | 7 +-
> 6 files changed, 239 insertions(+), 140 deletions(-)
> delete mode 100644 Silicon/NXP/Include/DramInfo.h
> create mode 100644 Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
>
> diff --git a/Silicon/NXP/Include/DramInfo.h b/Silicon/NXP/Include/DramInfo.h
> deleted file mode 100644
> index a934aaeff1..0000000000
> --- a/Silicon/NXP/Include/DramInfo.h
> +++ /dev/null
> @@ -1,38 +0,0 @@
> -/** @file
> -* Header defining the structure for Dram Information
> -*
> -* Copyright 2019 NXP
> -*
> -* SPDX-License-Identifier: BSD-2-Clause-Patent
> -*
> -**/
> -
> -#ifndef DRAM_INFO_H_
> -#define DRAM_INFO_H_
> -
> -#include <Uefi/UefiBaseType.h>
> -
> -#define SMC_DRAM_BANK_INFO (0xC200FF12)
> -
> -typedef struct {
> - UINTN BaseAddress;
> - UINTN Size;
> -} DRAM_REGION_INFO;
> -
> -typedef struct {
> - UINT32 NumOfDrams;
> - UINT32 Reserved;
> - DRAM_REGION_INFO DramRegion[3];
> -} DRAM_INFO;
> -
> -EFI_STATUS
> -GetDramBankInfo (
> - IN OUT DRAM_INFO *DramInfo
> - );
> -
> -VOID
> -UpdateDpaaDram (
> - IN OUT DRAM_INFO *DramInfo
> - );
> -
> -#endif /* DRAM_INFO_H_ */
> diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
> index 3ea7736786..eb1983bdbc 100644
> --- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
> +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
> @@ -17,8 +17,10 @@
> #include <Library/HobLib.h>
> #include <Library/MemoryAllocationLib.h>
> #include <Library/PcdLib.h>
> +#include <Library/ArmSmcLib.h>
Please sort includes alphabetically.
> +
> +#include "MemoryInitPeiLib.h"
>
> -#include <DramInfo.h>
>
> VOID
> BuildMemoryTypeInformationHob (
> @@ -44,6 +46,85 @@ InitMmu (
> }
> }
>
> +STATIC
> +UINTN
> +CalculateReservedMemBase (
> + IN DRAM_REGION_INFO *DramRegions,
> + IN UINT32 NumRegions,
> + IN UINTN ReservedMemSize
> +)
> +{
> + UINTN ReservedMemAlignment;
> + INTN Index;
> + EFI_PHYSICAL_ADDRESS AlignmentMask;
> + UINTN RegionBaseAddress;
> + UINTN RegionSize;
> + UINTN ReservedBaseAddress;
> + INTN Index2;
> +
> + ReservedMemAlignment = FixedPcdGet64 (PcdReservedMemAlignment);
> + //
> + // Compute alignment bit mask
> + //
> + if (ReservedMemAlignment) {
> + AlignmentMask = LShiftU64 (1, LowBitSet64(ReservedMemAlignment)) - 1;
> + } else {
> + AlignmentMask = 0;
> + }
> + Index = NumRegions;
> + while (Index--) {
> + RegionBaseAddress = DramRegions[Index].BaseAddress;
> + RegionSize = DramRegions[Index].Size;
> +
> + if (ReservedMemSize > RegionSize) {
> + continue;
> + }
> +
> + ReservedBaseAddress = (RegionBaseAddress + RegionSize - ReservedMemSize) & (~AlignmentMask);
> + if (ReservedBaseAddress < RegionBaseAddress) {
> + continue;
> + }
> +
> + // found the region from which reserved mem is to be carved out
> + // Need to modify the region size and create/delete region if need be
> + RegionSize -= ReservedMemSize;
> + if (!RegionSize) {
> + for (Index2 = Index; Index2 < NumRegions; Index2++) {
> + CopyMem (&DramRegions[Index2], &DramRegions[Index2 + 1], sizeof (DRAM_REGION_INFO));
> + }
> + break;
> + }
> +
> + if (ReservedBaseAddress - RegionBaseAddress) {
> + DramRegions[Index].Size = ReservedBaseAddress - RegionBaseAddress;
> + RegionSize -= DramRegions[Index].Size;
> + } else {
> + DramRegions[Index].BaseAddress = ReservedBaseAddress + ReservedMemSize;
> + DramRegions[Index].Size = RegionSize;
> + RegionSize = 0;
> + }
> +
> + if (!RegionSize) {
> + break;
> + }
> +
> + for (Index2 = NumRegions; Index2 > (Index + 1); Index2--) {
> + CopyMem (&DramRegions[Index2], &DramRegions[Index2 - 1], sizeof (DRAM_REGION_INFO));
> + }
> + DramRegions[Index2].BaseAddress = ReservedBaseAddress + ReservedMemSize;
> + DramRegions[Index2].Size = RegionSize;
> + RegionSize = 0;
> +
> + break;
> + }
> +
> + if (Index == -1) {
> + return 0;
> + } else {
> + return ReservedBaseAddress;
> + }
> +}
> +
> /*++
>
> Routine Description:
> @@ -68,10 +149,19 @@ MemoryPeim (
> )
> {
> ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
> + ARM_SMC_ARGS ArmSmcArgs;
> + INT32 Index;
> + UINTN DramSize;
> + UINTN BaseAddress;
> + UINTN Size;
> + UINTN Top;
> + // Extra region gets created if we want to reserve a memory region and that creates a memory hole
> + // because of alignement requirements
> + DRAM_REGION_INFO DramRegions[MAX_DRAM_REGIONS + 1];
> EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
> - EFI_PEI_HOB_POINTERS NextHob;
> - BOOLEAN Found;
> - DRAM_INFO DramInfo;
> + UINTN FdBase;
> + UINTN FdTop;
> + BOOLEAN FoundSystemMem;
>
> // Get Virtual Memory Map from the Platform Library
> ArmPlatformGetVirtualMemoryMap (&MemoryTable);
> @@ -86,48 +176,127 @@ MemoryPeim (
> // Now, the permanent memory has been installed, we can call AllocatePages()
> //
> ResourceAttributes = (
> - EFI_RESOURCE_ATTRIBUTE_PRESENT |
> - EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
> - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
> - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
> - EFI_RESOURCE_ATTRIBUTE_TESTED
> + EFI_RESOURCE_ATTRIBUTE_PRESENT |
> + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
> + EFI_RESOURCE_ATTRIBUTE_TESTED
This unrelated indentation change is wrong.
> );
>
> - if (GetDramBankInfo (&DramInfo)) {
> - DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n"));
> - return EFI_UNSUPPORTED;
> - }
> + FoundSystemMem = FALSE;
> + ZeroMem (DramRegions, sizeof (DramRegions));
> +
> + Index = -1;
> + do {
> + ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
> + ArmSmcArgs.Arg1 = Index++;
This loop would be nicer in a helper function (which would also make
the diff more clear).
>
> - while (DramInfo.NumOfDrams--) {
> - //
> - // Check if the resource for the main system memory has been declared
> - //
> - Found = FALSE;
> - NextHob.Raw = GetHobList ();
> - while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) {
> - if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&
> - (DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress >= NextHob.ResourceDescriptor->PhysicalStart) &&
> - (NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength <=
> - DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress + DramInfo.DramRegion[DramInfo.NumOfDrams].Size))
> - {
> - Found = TRUE;
> - break;
> + ArmCallSmc (&ArmSmcArgs);
> + ASSERT (!(ArmSmcArgs.Arg0 && !Index));
> + if (!Index) {
> + DramSize = ArmSmcArgs.Arg1;
> + } else {
> + if (!ArmSmcArgs.Arg0) {
> + BaseAddress = ArmSmcArgs.Arg1;
> + Size = ArmSmcArgs.Arg2;
> + ASSERT (BaseAddress && Size);
> +
> + DramRegions[Index - 1].BaseAddress = BaseAddress;
> + DramRegions[Index - 1].Size = Size;
> + DramSize -= Size;
> +
> + DEBUG ((DEBUG_INFO, "bank[%d]: start 0x%lx, size 0x%lx\n", Index, BaseAddress, Size));
> }
> - NextHob.Raw = GET_NEXT_HOB (NextHob);
> + }
> + } while (DramSize && Index < MAX_DRAM_REGIONS);
> +
> + ASSERT (!DramSize);
> +
> + // Get the reserved memory size from non volatile storage
> + Size = FixedPcdGet64 (PcdReservedMemSize);
FixedPcd reads from non-volatile storage?
> + if (Size) {
> + BaseAddress = CalculateReservedMemBase (DramRegions, Index, Size);
> + if (BaseAddress) {
> + DEBUG ((DEBUG_INFO, "ReservedMem: start 0x%lx, size 0x%lx\n", BaseAddress, Size));
> + }
> + }
> +
> + FdBase = (UINTN)FixedPcdGet64 (PcdFdBaseAddress);
> + FdTop = FdBase + (UINTN)FixedPcdGet32 (PcdFdSize);
> +
> + // Declare memory regios to system
> + for (Index = MAX_DRAM_REGIONS; Index >= 0; Index--) {
> + if (!DramRegions[Index].Size) {
> + continue;
> }
>
> - if (!Found) {
> - // Reserved the memory space occupied by the firmware volume
> + BaseAddress = DramRegions[Index].BaseAddress;
> + Top = DramRegions[Index].BaseAddress + DramRegions[Index].Size;
> +
> + // EDK2 does not have the concept of boot firmware copied into DRAM. To avoid the DXE
Which boot firmware are we talking about here?
> + // core to overwrite this area we must create a memory allocation HOB for the region,
> + // but this only works if we split off the underlying resource descriptor as well.
> + if (FdBase >= BaseAddress && FdTop <= Top) {
> + // Update Size
> + Size = FdBase - BaseAddress;
> + if (Size) {
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_SYSTEM_MEMORY,
> + ResourceAttributes,
> + BaseAddress,
> + Size
> + );
> + }
> + // create the System Memory HOB for the firmware
> BuildResourceDescriptorHob (
> EFI_RESOURCE_SYSTEM_MEMORY,
> ResourceAttributes,
> - DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress,
> - DramInfo.DramRegion[DramInfo.NumOfDrams].Size
> + FdBase,
> + PcdGet32 (PcdFdSize)
> + );
> + // Create the System Memory HOB for the remaining region (top of the FD)s
> + Size = Top - FdTop;
> + if (Size) {
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_SYSTEM_MEMORY,
> + ResourceAttributes,
> + FdTop,
> + Size
> + );
> + };
> + // Mark the memory covering the Firmware Device as boot services data
> + BuildMemoryAllocationHob (FixedPcdGet64 (PcdFdBaseAddress),
> + FixedPcdGet32 (PcdFdSize),
> + EfiBootServicesData);
> + }else {
Space after }
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_SYSTEM_MEMORY,
Incorrect indentation.
> + ResourceAttributes,
> + DramRegions[Index].BaseAddress,
> + DramRegions[Index].Size
> );
> }
> +
> + if (FoundSystemMem) {
> + continue;
> + }
> +
> + BaseAddress = DramRegions[Index].BaseAddress;
> + Size = DramRegions[Index].Size;
> + Top = DramRegions[Index].BaseAddress + DramRegions[Index].Size;
> +
> + if (FdBase >= BaseAddress && FdTop <= Top) {
> + Size -= (UINTN)FixedPcdGet32 (PcdFdSize);
> + }
> +
> + if (Size >= FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)) {
> + FoundSystemMem = TRUE;
> + }
> }
>
> + ASSERT (FoundSystemMem);
> +
> // Build Memory Allocation Hob
> InitMmu (MemoryTable);
>
> diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
> new file mode 100644
> index 0000000000..e563b2ba8d
> --- /dev/null
> +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
> @@ -0,0 +1,24 @@
> +/** @file
> +*
> +* Copyright 2020 NXP
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#ifndef _MEMORY_INIT_PEI_LIB_H_
> +#define _MEMORY_INIT_PEI_LIB_H_
Please drop leading _ from include guards.
> +
> +#include <Uefi.h>
> +
> +// Specifies the Maximum regions onto which DDR memory can be mapped in a Platform
> +#define MAX_DRAM_REGIONS 3
> +#define SMC_DRAM_BANK_INFO (0xC200FF12)
> +
> +typedef struct {
> + UINTN BaseAddress;
> + UINTN Size;
> +} DRAM_REGION_INFO;
> +
> +#endif
> +
> diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
> index a5bd39415d..9adddcaf8c 100644
> --- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
> +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
> @@ -33,6 +33,7 @@
> DebugLib
> HobLib
> PcdLib
> + ArmSmcLib
Please sort library classes alphabetically.
>
> [Guids]
> gEfiMemoryTypeInformationGuid
> @@ -40,6 +41,13 @@
> [FeaturePcd]
> gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
>
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdFdBaseAddress
> + gArmTokenSpaceGuid.PcdFdSize
> + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize
Please sort fixedpcds alphabetically.
> + gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize
> + gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment
> +
> [Pcd]
> gArmTokenSpaceGuid.PcdSystemMemoryBase
> gArmTokenSpaceGuid.PcdSystemMemorySize
> diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
> index 847331a631..1ef99e8de2 100644
> --- a/Silicon/NXP/Library/SocLib/Chassis.c
> +++ b/Silicon/NXP/Library/SocLib/Chassis.c
> @@ -22,7 +22,6 @@
> #include <Library/PrintLib.h>
> #include <Library/SerialPortLib.h>
>
> -#include <DramInfo.h>
> #include "NxpChassis.h"
>
> UINT32
> @@ -75,69 +74,3 @@ SmmuInit (
> MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
> }
>
> -UINTN
> -GetDramSize (
> - IN VOID
> - )
> -{
> - ARM_SMC_ARGS ArmSmcArgs;
> -
> - ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
> - ArmSmcArgs.Arg1 = -1;
> -
> - ArmCallSmc (&ArmSmcArgs);
> -
> - if (ArmSmcArgs.Arg0) {
> - return 0;
> - } else {
> - return ArmSmcArgs.Arg1;
> - }
> -}
> -
> -EFI_STATUS
> -GetDramBankInfo (
> - IN OUT DRAM_INFO *DramInfo
> - )
> -{
> - ARM_SMC_ARGS ArmSmcArgs;
> - UINT32 I;
> - UINTN DramSize;
> -
> - DramSize = GetDramSize ();
> - DEBUG ((DEBUG_INFO, "DRAM Total Size 0x%lx \n", DramSize));
> -
> - // Ensure DramSize has been set
> - ASSERT (DramSize != 0);
> -
> - I = 0;
> -
> - do {
> - ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
> - ArmSmcArgs.Arg1 = I;
> -
> - ArmCallSmc (&ArmSmcArgs);
> - if (ArmSmcArgs.Arg0) {
> - if (I > 0) {
> - break;
> - } else {
> - ASSERT (ArmSmcArgs.Arg0 == 0);
> - }
> - }
> -
> - DramInfo->DramRegion[I].BaseAddress = ArmSmcArgs.Arg1;
> - DramInfo->DramRegion[I].Size = ArmSmcArgs.Arg2;
> -
> - DramSize -= DramInfo->DramRegion[I].Size;
> -
> - DEBUG ((DEBUG_INFO, "bank[%d]: start 0x%lx, size 0x%lx\n",
> - I, DramInfo->DramRegion[I].BaseAddress, DramInfo->DramRegion[I].Size));
> -
> - I++;
> - } while (DramSize);
> -
> - DramInfo->NumOfDrams = I;
> -
> - DEBUG ((DEBUG_INFO, "Number Of DRAM in system %d \n", DramInfo->NumOfDrams));
> -
> - return EFI_SUCCESS;
> -}
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index 4f14cc9848..c327e738cc 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -38,7 +38,10 @@
> #
> gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311
>
> + gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize|0x0|UINT64|0x00000315
> + gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment|0x0|UINT64|0x00000316
> +
> [PcdsFeatureFlag]
> - gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000315
> - gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000316
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000317
> + gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000318
And this hunk shows why it's a good idea to put your Pcds into groups
with gaps in between the tokens. The tokens should *not* be changing
throughout a single set, and only in unusual circumstances anyway.
/
Leif
>
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 14/19] Silicon/NXP/LS1043A: Replce SocLib
2020-02-07 12:43 ` [PATCH 14/19] Silicon/NXP/LS1043A: Replce SocLib Pankaj Bansal
@ 2020-02-11 13:35 ` Leif Lindholm
2020-02-12 9:37 ` Pankaj Bansal
0 siblings, 1 reply; 49+ messages in thread
From: Leif Lindholm @ 2020-02-11 13:35 UTC (permalink / raw)
To: Pankaj Bansal; +Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi, devel
On Fri, Feb 07, 2020 at 18:13:23 +0530, Pankaj Bansal wrote:
> Replace SocLib with new SocLib in which code structure has been
> changed.
I don't think there's much point to me reviewing this one until we've
discussed the ChassisLib/SocLib split and layout in more detail.
/
Leif
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> .../Drivers/PlatformDxe/PlatformDxe.inf | 3 +-
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 3 +-
> .../Library/ArmPlatformLib/ArmPlatformLib.c | 53 ++++++-
> .../Library/ArmPlatformLib/ArmPlatformLib.inf | 6 +-
> Silicon/NXP/Chassis2/Include/Chassis.h | 12 ++
> Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc | 1 +
> .../Chassis2/LS1043A/Library/SocLib/SocLib.c | 28 ++++
> .../LS1043A/Library/SocLib/SocLib.inf | 8 ++
> .../Chassis2/Library/ChassisLib/ChassisLib.c | 25 ++++
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 2 +-
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 7 +-
> Silicon/NXP/Include/Chassis2/NxpSoc.h | 53 -------
> Silicon/NXP/Include/Library/ChassisLib.h | 2 -
> Silicon/NXP/Include/Library/SocLib.h | 1 -
> Silicon/NXP/LS1043A/Include/Soc.h | 44 ------
> Silicon/NXP/LS1043A/LS1043A.dec | 16 ---
> Silicon/NXP/LS1043A/LS1043A.dsc.inc | 33 -----
> .../BaseSerialPortLib16550.c | 11 +-
> .../BaseSerialPortLib16550.inf | 3 +-
> Silicon/NXP/Library/SocLib/Chassis.c | 76 ----------
> Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 96 -------------
> Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 44 ------
> Silicon/NXP/Library/SocLib/NxpChassis.h | 136 ------------------
> 23 files changed, 142 insertions(+), 521 deletions(-)
> delete mode 100644 Silicon/NXP/Include/Chassis2/NxpSoc.h
> delete mode 100644 Silicon/NXP/LS1043A/Include/Soc.h
> delete mode 100644 Silicon/NXP/LS1043A/LS1043A.dec
> delete mode 100644 Silicon/NXP/LS1043A/LS1043A.dsc.inc
> delete mode 100644 Silicon/NXP/Library/SocLib/Chassis.c
> delete mode 100644 Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> delete mode 100644 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> delete mode 100644 Silicon/NXP/Library/SocLib/NxpChassis.h
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> index 126a1174fa..95f60b00f0 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> +++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> @@ -25,7 +25,8 @@
> MdeModulePkg/MdeModulePkg.dec
> Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
> Silicon/NXP/NxpQoriqLs.dec
> - Silicon/NXP/LS1043A/LS1043A.dec
> + Silicon/NXP/Chassis2/Chassis2.dec
> + Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
>
> [LibraryClasses]
> BaseLib
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> index bc6fa4f19d..4bc7f6ef97 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> @@ -23,7 +23,8 @@
> FLASH_DEFINITION = Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
>
> !include Silicon/NXP/NxpQoriqLs.dsc.inc
> -!include Silicon/NXP/LS1043A/LS1043A.dsc.inc
> +!include Silicon/NXP/Chassis2/Chassis2.dsc.inc
> +!include Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
>
> [LibraryClasses.common]
> ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> index 718c71bf02..821d413a3e 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> @@ -14,7 +14,10 @@
> #include <Library/ArmPlatformLib.h>
> #include <Ppi/ArmMpCoreInfo.h>
>
> -extern VOID SocInit (VOID);
> +#include <Library/DebugLib.h>
> +#include <Library/I2cLib.h>
> +#include <Library/SocLib.h>
> +#include <Ppi/NxpPlatformGetClock.h>
>
> /**
> Return the current Boot Mode
> @@ -30,6 +33,49 @@ ArmPlatformGetBootMode (
> return BOOT_WITH_FULL_CONFIGURATION;
> }
>
> +/**
> + Get the clocks supplied by Platform(Board) to NXP Layerscape SOC
> +
> + The core can be of type ARM or PowerPC or Hardware Accelerator.
> + If the core is enabled and of type ARM EFI_SUCCESS is returned and a code for type of ARM core is returned
> +
> + @param[in] ClockType Type of clock
> + @param[in] ... Variable argument list which is parsed based on ClockType
> +
> + @return Actual Clock Frequency. return value 0 should be interpreted as clock not provided by Board.
> +**/
> +UINT64
> +EFIAPI
> +NxpPlatformGetClock(
> + IN UINT32 ClockType,
> + ...
> + )
> +{
> + UINT64 Clock;
> + VA_LIST Args;
> +
> + Clock = 0;
> +
> + VA_START (Args, ClockType);
> +
> + switch (ClockType) {
> + case NXP_SYSTEM_CLOCK:
> + Clock = 100 * 1000 * 1000; // 100 MHz
> + break;
> + case NXP_I2C_CLOCK:
> + case NXP_UART_CLOCK:
> + Clock = NxpPlatformGetClock (NXP_SYSTEM_CLOCK);
> + Clock = SocGetClock (Clock, ClockType, Args);
> + break;
> + default:
> + break;
> + }
> +
> + VA_END (Args);
> +
> + return Clock;
> +}
> +
> /**
> Placeholder for Platform Initialization
> **/
> @@ -38,9 +84,9 @@ ArmPlatformInitialize (
> IN UINTN MpId
> )
> {
> - SocInit ();
> + SocInit ();
>
> - return EFI_SUCCESS;
> + return EFI_SUCCESS;
> }
>
> ARM_CORE_INFO LS1043aMpCoreInfoCTA53x4[] = {
> @@ -69,6 +115,7 @@ PrePeiCoreGetMpCoreInfo (
> }
>
> ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
> +NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi = { NxpPlatformGetClock };
>
> EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
> {
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> index 6396d2982b..8b79fd7490 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> @@ -20,11 +20,14 @@
> EmbeddedPkg/EmbeddedPkg.dec
> MdePkg/MdePkg.dec
> Silicon/NXP/NxpQoriqLs.dec
> - Silicon/NXP/LS1043A/LS1043A.dec
> + Silicon/NXP/Chassis2/Chassis2.dec
> + Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
>
> [LibraryClasses]
> ArmLib
> SocLib
> + I2cLib
> + DebugLib
>
> [Sources.common]
> AArch64/NxpQoriqLsHelper.S | GCC
> @@ -36,3 +39,4 @@
>
> [FixedPcd]
> gArmTokenSpaceGuid.PcdArmPrimaryCore
> + gArmPlatformTokenSpaceGuid.PcdCoreCount
> diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h b/Silicon/NXP/Chassis2/Include/Chassis.h
> index 48ba2e7bfb..8f26faf297 100644
> --- a/Silicon/NXP/Chassis2/Include/Chassis.h
> +++ b/Silicon/NXP/Chassis2/Include/Chassis.h
> @@ -20,6 +20,18 @@
> #define TP_ITYPE_VERSION_A53 0x2
> #define TP_ITYPE_VERSION_A72 0x4
>
> +/* SMMU Defintions */
> +#define SMMU_BASE_ADDR 0x09000000
> +#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
> +#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
> +#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
> +#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
> +#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
> +
> +#define SCR0_USFCFG_MASK 0x00000400
> +#define SCR0_CLIENTPD_MASK 0x00000001
> +#define SACR_PAGESIZE_MASK 0x00010000
> +
> /**
> The Device Configuration Unit provides general purpose configuration and status for the
> device. These registers only support 32-bit accesses.
> diff --git a/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
> index 4511203443..8440e5f0f3 100644
> --- a/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
> +++ b/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
> @@ -8,6 +8,7 @@
>
> [LibraryClasses.common]
> SocLib|Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> + SerialPortLib|Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
>
> ################################################################################
> #
> diff --git a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
> index 2a08ad87db..24241e9b02 100644
> --- a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
> +++ b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
> @@ -4,8 +4,10 @@
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
> **/
> +#include <Soc.h>
> #include <Library/ChassisLib.h>
> #include <Library/SocLib.h>
> +#include <Library/SerialPortLib.h>
>
> /**
> Return the input clock frequency to an IP Module.
> @@ -66,8 +68,34 @@ SocInit (
> VOID
> )
> {
> + UINT64 BaudRate;
> + UINT32 ReceiveFifoDepth;
> + EFI_PARITY_TYPE Parity;
> + UINT8 DataBits;
> + EFI_STOP_BITS_TYPE StopBits;
> + UINT32 Timeout;
> +
> + BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
> + ReceiveFifoDepth = FixedPcdGet16 (PcdUartDefaultReceiveFifoDepth); // Use default FIFO depth
> + Timeout = 0;
> + Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
> + DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
> + StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);
> +
> ChassisInit ();
>
> + //
> + // Early init serial Port to get board information.
> + //
> + SerialPortSetAttributes (
> + &BaudRate,
> + &ReceiveFifoDepth,
> + &Timeout,
> + &Parity,
> + &DataBits,
> + &StopBits
> + );
> +
> return;
> }
>
> diff --git a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> index c9a4fbc01f..fb39424bc5 100644
> --- a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> +++ b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> @@ -29,4 +29,12 @@
>
> [LibraryClasses]
> ChassisLib
> + PcdLib
> + SerialPortLib
>
> +[FixedPcd]
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth
> diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> index fa6a36e96f..e7573a0e06 100644
> --- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> @@ -150,6 +150,29 @@ SocGetMpCoreInfo (
> return CoreCount;
> }
>
> +/*
> + * Setup SMMU in bypass mode
> + * and also set its pagesize
> + */
> +STATIC
> +VOID
> +SmmuInit (
> + VOID
> + )
> +{
> + UINT32 Value;
> +
> + /* set pagesize as 64K and ssmu-500 in bypass mode */
> + Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
> + MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
> +
> + Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
> + MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
> +
> + Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
> + MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
> +}
> +
> /**
> Function to initialize Chassis Specific functions
> **/
> @@ -183,4 +206,6 @@ ChassisInit (
> &DataBits,
> &StopBits
> );
> +
> + SmmuInit();
> }
> diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> index 8e3a82efca..e79b106c8d 100644
> --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> @@ -50,7 +50,7 @@ SetBusFrequency (
>
> I2cBase = (UINTN)(I2c->Dev->Resources[0].AddrRangeMin);
>
> - I2cClock = GetBusFrequency ();
> + I2cClock = mPlatformGetClockPpi.PlatformGetClock (NXP_I2C_CLOCK, 0);
>
> I2cInitialize (I2cBase, I2cClock, *BusClockHertz);
>
> diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> index 88316f3133..f446f0d4f9 100644
> --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> @@ -13,6 +13,7 @@
> #include <Library/UefiLib.h>
> #include <Uefi.h>
>
> +#include <Ppi/NxpPlatformGetClock.h>
> #include <Protocol/I2cMaster.h>
> #include <Protocol/NonDiscoverableDevice.h>
>
> @@ -37,11 +38,7 @@ typedef struct {
> NON_DISCOVERABLE_DEVICE *Dev;
> } NXP_I2C_MASTER;
>
> -extern
> -UINT64
> -GetBusFrequency (
> - VOID
> - );
> +extern NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi;
>
> EFI_STATUS
> NxpI2cInit (
> diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> deleted file mode 100644
> index 6812beafe4..0000000000
> --- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
> +++ /dev/null
> @@ -1,53 +0,0 @@
> -/** Soc.h
> -* Header defining the Base addresses, sizes, flags etc for chassis 1
> -*
> -* Copyright 2017-2020 NXP
> -*
> -* SPDX-License-Identifier: BSD-2-Clause-Patent
> -*
> -**/
> -
> -#ifndef NXP_SOC_H_
> -#define NXP_SOC_H_
> -
> -#define CLK_FREQ 100000000
> -
> -#define CHASSIS2_DCFG_ADDRESS 0x1EE0000
> -
> -/* SMMU Defintions */
> -#define SMMU_BASE_ADDR 0x09000000
> -#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
> -#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
> -#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
> -#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
> -#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
> -
> -#define SCR0_USFCFG_MASK 0x00000400
> -#define SCR0_CLIENTPD_MASK 0x00000001
> -#define SACR_PAGESIZE_MASK 0x00010000
> -#define IDR1_PAGESIZE_MASK 0x80000000
> -
> -typedef struct {
> - UINTN FreqSystemBus;
> -} SYS_INFO;
> -
> -/* Device Configuration and Pin Control */
> -typedef struct {
> - UINT8 Res0[0x100-0x00];
> - UINT32 RcwSr[16]; /* Reset control word status */
> -#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
> -#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
> -} CCSR_GUR;
> -
> -VOID
> -GetSysInfo (
> - OUT SYS_INFO *
> - );
> -
> -UINT32
> -EFIAPI
> -GurRead (
> - IN UINTN Address
> - );
> -
> -#endif /* NXP_SOC_H_ */
> diff --git a/Silicon/NXP/Include/Library/ChassisLib.h b/Silicon/NXP/Include/Library/ChassisLib.h
> index b51b024374..d07c59b82d 100644
> --- a/Silicon/NXP/Include/Library/ChassisLib.h
> +++ b/Silicon/NXP/Include/Library/ChassisLib.h
> @@ -9,8 +9,6 @@
> #ifndef __CHASSIS_LIB_H__
> #define __CHASSIS_LIB_H__
>
> -#include <Chassis.h>
> -
> /**
> Read Dcfg register
> **/
> diff --git a/Silicon/NXP/Include/Library/SocLib.h b/Silicon/NXP/Include/Library/SocLib.h
> index 3def396171..700e877bdf 100644
> --- a/Silicon/NXP/Include/Library/SocLib.h
> +++ b/Silicon/NXP/Include/Library/SocLib.h
> @@ -8,7 +8,6 @@
> #ifndef __SOC_LIB_H__
> #define __SOC_LIB_H__
>
> -#include <Soc.h>
> #include <Uefi.h>
> #include <Ppi/ArmMpCoreInfo.h>
> #include <Ppi/NxpPlatformGetClock.h>
> diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Include/Soc.h
> deleted file mode 100644
> index c1e00394af..0000000000
> --- a/Silicon/NXP/LS1043A/Include/Soc.h
> +++ /dev/null
> @@ -1,44 +0,0 @@
> -/** @file
> -
> - Copyright 2020 NXP
> -
> - SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -#ifndef __SOC_H__
> -#define __SOC_H__
> -
> -/**
> - Soc Memory Map
> -**/
> -#define LS1043A_DRAM0_PHYS_ADDRESS 0x80000000
> -#define LS1043A_DRAM0_SIZE SIZE_2GB
> -#define LS1043A_DRAM1_PHYS_ADDRESS 0x880000000
> -#define LS1043A_DRAM1_SIZE 0x780000000 // 30 GB
> -
> -#define LS1043A_CCSR_PHYS_ADDRESS 0x1000000
> -#define LS1043A_CCSR_SIZE 0xF000000
> -
> -#define LS1043A_IFC0_PHYS_ADDRESS 0x60000000
> -#define LS1043A_IFC0_SIZE SIZE_512MB
> -#define LS1043A_IFC1_PHYS_ADDRESS 0x620000000
> -#define LS1043A_IFC1_SIZE 0xE0000000 // 3.5 GB
> -
> -#define LS1043A_QSPI_PHYS_ADDRESS 0x40000000
> -#define LS1043A_QSPI_SIZE SIZE_512MB
> -
> -#define LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS 0x500000000
> -#define LS1043A_QMAN_SW_PORTAL_SIZE SIZE_128MB
> -#define LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS 0x508000000
> -#define LS1043A_BMAN_SW_PORTAL_SIZE SIZE_128MB
> -
> -#define LS1043A_PCI0_PHYS_ADDRESS 0x4000000000
> -#define LS1043A_PCI1_PHYS_ADDRESS 0x4800000000
> -#define LS1043A_PCI2_PHYS_ADDRESS 0x5000000000
> -#define LS1043A_PCI_SIZE SIZE_32GB
> -
> -#define LS1043A_I2C0_PHYS_ADDRESS 0x2180000
> -#define LS1043A_I2C_SIZE 0x10000
> -#define LS1043A_I2C_NUM_CONTROLLERS 4
> -
> -#endif
> diff --git a/Silicon/NXP/LS1043A/LS1043A.dec b/Silicon/NXP/LS1043A/LS1043A.dec
> deleted file mode 100644
> index cd79949790..0000000000
> --- a/Silicon/NXP/LS1043A/LS1043A.dec
> +++ /dev/null
> @@ -1,16 +0,0 @@
> -# LS1043A.dec
> -#
> -# Copyright 2017-2019 NXP
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -#
> -
> -[Defines]
> - DEC_SPECIFICATION = 0x0001001A
> -
> -[Guids.common]
> - gNxpLs1043ATokenSpaceGuid = {0x6834fe45, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
> -
> -[Includes]
> - Include
> diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> deleted file mode 100644
> index 7ebbb1a495..0000000000
> --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> +++ /dev/null
> @@ -1,33 +0,0 @@
> -# LS1043A.dsc
> -# LS1043A Soc package.
> -#
> -# Copyright 2017-2020 NXP
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -#
> -
> -[LibraryClasses.common]
> - SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> - SerialPortLib|Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
> -
> -################################################################################
> -#
> -# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> -#
> -################################################################################
> -[PcdsDynamicDefault.common]
> -
> - #
> - # ARM General Interrupt Controller
> - gArmTokenSpaceGuid.PcdGicDistributorBase|0x01401000
> - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01402000
> -
> -[PcdsFixedAtBuild.common]
> - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
> -
> - #
> - # Big Endian IPs
> - #
> - gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
> -##
> diff --git a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> index 6b2aa46ff6..2e35f09d8f 100644
> --- a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> +++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> @@ -15,6 +15,9 @@
> #include <Library/PcdLib.h>
> #include <Library/IoLib.h>
> #include <Library/BaseLib.h>
> +#include <Ppi/NxpPlatformGetClock.h>
> +
> +extern NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi;
>
> //
> // 16550 UART register offsets and bitfields
> @@ -42,12 +45,6 @@
> #define B_UART_MSR_RI BIT6
> #define B_UART_MSR_DCD BIT7
>
> -extern
> -UINT64
> -GetBusFrequency (
> - VOID
> - );
> -
> /**
> Read an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is read from
> MMIO space. If PcdSerialUseMmio is FALSE, then the value is read from I/O space. The
> @@ -577,7 +574,7 @@ SerialPortSetAttributes (
> return RETURN_UNSUPPORTED;
> }
>
> - SerialClock = GetBusFrequency ();
> + SerialClock = mPlatformGetClockPpi.PlatformGetClock (NXP_UART_CLOCK, 0);
> if (SerialClock == 0) {
> return EFI_DEVICE_ERROR;
> }
> diff --git a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
> index 45ae9dc0af..7823bc5be5 100644
> --- a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
> +++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
> @@ -19,11 +19,12 @@
> [Packages]
> MdePkg/MdePkg.dec
> MdeModulePkg/MdeModulePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
>
> [LibraryClasses]
> PcdLib
> IoLib
> - SocLib
> + ArmPlatformLib
>
> [Sources]
> BaseSerialPortLib16550.c
> diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
> deleted file mode 100644
> index 1ef99e8de2..0000000000
> --- a/Silicon/NXP/Library/SocLib/Chassis.c
> +++ /dev/null
> @@ -1,76 +0,0 @@
> -/** @file
> - SoC specific Library containg functions to initialize various SoC components
> -
> - Copyright 2017-2020 NXP
> -
> - SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Base.h>
> -#ifdef CHASSIS2
> -#include <Chassis2/NxpSoc.h>
> -#elif CHASSIS3
> -#include <Chassis3/NxpSoc.h>
> -#endif
> -#include <Library/ArmSmcLib.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoAccessLib.h>
> -#include <Library/DebugLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/PrintLib.h>
> -#include <Library/SerialPortLib.h>
> -
> -#include "NxpChassis.h"
> -
> -UINT32
> -EFIAPI
> -GurRead (
> - IN UINTN Address
> - )
> -{
> - if (FixedPcdGetBool (PcdGurBigEndian)) {
> - return SwapMmioRead32 (Address);
> - } else {
> - return MmioRead32 (Address);
> - }
> -}
> -
> -/*
> - * Return system bus frequency
> - */
> -UINT64
> -GetBusFrequency (
> - VOID
> - )
> -{
> - SYS_INFO SocSysInfo;
> -
> - GetSysInfo (&SocSysInfo);
> -
> - return SocSysInfo.FreqSystemBus;
> -}
> -
> -/*
> - * Setup SMMU in bypass mode
> - * and also set its pagesize
> - */
> -VOID
> -SmmuInit (
> - VOID
> - )
> -{
> - UINT32 Value;
> -
> - /* set pagesize as 64K and ssmu-500 in bypass mode */
> - Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
> - MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
> -
> - Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
> - MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
> -
> - Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
> - MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
> -}
> -
> diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> deleted file mode 100644
> index a3dabc93d1..0000000000
> --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> +++ /dev/null
> @@ -1,96 +0,0 @@
> -/** @Soc.c
> - SoC specific Library containg functions to initialize various SoC components
> -
> - Copyright 2017-2020 NXP
> -
> - SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Base.h>
> -#include <NxpChassis.h>
> -#include <Chassis2/NxpSoc.h>
> -#include <Library/BaseLib.h>
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/DebugLib.h>
> -#include <Library/IoAccessLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/PrintLib.h>
> -#include <Library/SerialPortLib.h>
> -
> -/**
> - Calculate the frequency of various controllers and
> - populate the passed structure with frequuencies.
> -
> - @param PtrSysInfo Input structure to populate with
> - frequencies.
> -**/
> -VOID
> -GetSysInfo (
> - OUT SYS_INFO *PtrSysInfo
> - )
> -{
> - CCSR_GUR *GurBase;
> - UINTN SysClk;
> -
> - GurBase = (CCSR_GUR *)CHASSIS2_DCFG_ADDRESS;
> - SysClk = CLK_FREQ;
> -
> - SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
> -
> - PtrSysInfo->FreqSystemBus = SysClk;
> -
> - //
> - // selects the platform clock:SYSCLK ratio and calculate
> - // system frequency
> - //
> - PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
> - CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
> - CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
> -}
> -
> -/**
> - Function to initialize SoC specific constructs
> - CPU Info
> - SoC Personality
> - Board Personality
> - RCW prints
> - **/
> -VOID
> -SocInit (
> - VOID
> - )
> -{
> - UINT64 BaudRate;
> - UINT32 ReceiveFifoDepth;
> - EFI_PARITY_TYPE Parity;
> - UINT8 DataBits;
> - EFI_STOP_BITS_TYPE StopBits;
> - UINT32 Timeout;
> -
> - BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
> - ReceiveFifoDepth = 0; // Use default FIFO depth
> - Timeout = 0;
> - Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
> - DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
> - StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);
> -
> - SmmuInit ();
> -
> - //
> - // Early init serial Port to get board information.
> - //
> - SerialPortSetAttributes (
> - &BaudRate,
> - &ReceiveFifoDepth,
> - &Timeout,
> - &Parity,
> - &DataBits,
> - &StopBits
> - );
> - DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a on %a)\n",
> - (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__));
> -
> - return;
> -}
> diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> deleted file mode 100644
> index d8707927b7..0000000000
> --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> +++ /dev/null
> @@ -1,44 +0,0 @@
> -# @file
> -#
> -# Copyright 2017-2020 NXP
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -
> -[Defines]
> - INF_VERSION = 0x0001001A
> - BASE_NAME = SocLib
> - FILE_GUID = e868c5ca-9729-43ae-bff4-438c67de8c68
> - MODULE_TYPE = BASE
> - VERSION_STRING = 1.0
> - LIBRARY_CLASS = SocLib
> -
> -[Packages]
> - ArmPkg/ArmPkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - MdePkg/MdePkg.dec
> - Silicon/NXP/NxpQoriqLs.dec
> - Silicon/NXP/LS1043A/LS1043A.dec
> -
> -[LibraryClasses]
> - ArmSmcLib
> - BaseLib
> - DebugLib
> - IoAccessLib
> - SerialPortLib
> -
> -[Sources.common]
> - Chassis.c
> - Chassis2/Soc.c
> -
> -[BuildOptions]
> - GCC:*_*_*_CC_FLAGS = -DCHASSIS2
> -
> -[FixedPcd]
> - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
> - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
> - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
> - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
> - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> - gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
> - gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
> diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h b/Silicon/NXP/Library/SocLib/NxpChassis.h
> deleted file mode 100644
> index 99f6439d8f..0000000000
> --- a/Silicon/NXP/Library/SocLib/NxpChassis.h
> +++ /dev/null
> @@ -1,136 +0,0 @@
> -/** @file
> -* Header defining the Base addresses, sizes, flags etc for chassis 1
> -*
> -* Copyright 2017-2019 NXP
> -*
> -* SPDX-License-Identifier: BSD-2-Clause-Patent
> -*
> -**/
> -
> -#ifndef NXP_CHASSIS_H_
> -#define NXP_CHASSIS_H_
> -
> -#define TP_ITYP_AV_MASK 0x00000001 /* Initiator available */
> -#define TP_ITYP_TYPE_MASK(x) (((x) & 0x6) >> 1) /* Initiator Type */
> -#define TP_ITYP_TYPE_ARM 0x0
> -#define TP_ITYP_TYPE_PPC 0x1
> -#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
> -#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
> -#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
> -#define TP_ITYP_VERSION(x) (((x) & 0xe0) >> 5) /* Initiator Version */
> -#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
> -#define TP_INIT_PER_CLUSTER 4
> -
> -#define TY_ITYP_VERSION_A7 0x1
> -#define TY_ITYP_VERSION_A53 0x2
> -#define TY_ITYP_VERSION_A57 0x3
> -#define TY_ITYP_VERSION_A72 0x4
> -
> -#define CPU_TYPE_ENTRY(N, V, NC) { .Name = #N, .SocVer = SVR_##V, .NumCores = (NC)}
> -
> -#define SVR_WO_E 0xFFFFFE
> -#define SVR_LS1043A 0x879200
> -#define SVR_LS1046A 0x870700
> -#define SVR_LS2088A 0x870901
> -
> -#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
> -#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
> -#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
> -#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
> -
> -#define MHZ 1000000
> -
> -typedef struct {
> - CHAR8 *Name;
> - UINT32 SocVer;
> - UINT32 NumCores;
> -} CPU_TYPE;
> -
> -typedef struct {
> - UINTN CpuClk; /* CPU clock in Hz! */
> - UINTN BusClk;
> - UINTN MemClk;
> - UINTN PciClk;
> - UINTN SdhcClk;
> -} SOC_CLOCK_INFO;
> -
> -/*
> - * Print Soc information
> - */
> -VOID
> -PrintSoc (
> - VOID
> - );
> -
> -/*
> - * Initialize Clock structure
> - */
> -VOID
> -ClockInit (
> - VOID
> - );
> -
> -/*
> - * Setup SMMU in bypass mode
> - * and also set its pagesize
> - */
> -VOID
> -SmmuInit (
> - VOID
> - );
> -
> -/*
> - * Print CPU information
> - */
> -VOID
> -PrintCpuInfo (
> - VOID
> - );
> -
> -/*
> - * Dump RCW (Reset Control Word) on console
> - */
> -VOID
> -PrintRCW (
> - VOID
> - );
> -
> -UINT32
> -InitiatorType (
> - IN UINT32 Cluster,
> - IN UINTN InitId
> - );
> -
> -/*
> - * Return the mask for number of cores on this SOC.
> - */
> -UINT32
> -CpuMask (
> - VOID
> - );
> -
> -/*
> - * Return the number of cores on this SOC.
> - */
> -UINTN
> -CpuNumCores (
> - VOID
> - );
> -
> -/*
> - * Return the type of initiator for core/hardware accelerator for given core index.
> - */
> -UINTN
> -QoriqCoreToType (
> - IN UINTN Core
> - );
> -
> -/*
> - * Return the cluster of initiator for core/hardware accelerator for given core index.
> - */
> -INT32
> -QoriqCoreToCluster (
> - IN UINTN Core
> - );
> -
> -#endif /* NXP_CHASSIS_H_ */
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 14/19] Silicon/NXP/LS1043A: Replce SocLib
2020-02-11 13:35 ` Leif Lindholm
@ 2020-02-12 9:37 ` Pankaj Bansal
2020-02-12 22:50 ` Leif Lindholm
0 siblings, 1 reply; 49+ messages in thread
From: Pankaj Bansal @ 2020-02-12 9:37 UTC (permalink / raw)
To: Leif Lindholm
Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi,
devel@edk2.groups.io
> -----Original Message-----
> From: Leif Lindholm <leif@nuviainc.com>
> Sent: Tuesday, February 11, 2020 7:05 PM
> To: Pankaj Bansal <pankaj.bansal@nxp.com>
> Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney
> <michael.d.kinney@intel.com>; Varun Sethi <V.Sethi@nxp.com>;
> devel@edk2.groups.io
> Subject: Re: [PATCH 14/19] Silicon/NXP/LS1043A: Replce SocLib
>
> On Fri, Feb 07, 2020 at 18:13:23 +0530, Pankaj Bansal wrote:
> > Replace SocLib with new SocLib in which code structure has been
> > changed.
>
> I don't think there's much point to me reviewing this one until we've discussed
> the ChassisLib/SocLib split and layout in more detail.
Let me explain the code layout.
A Chassis is a base framework used for building SoCs.
All NXP Layerscape SOCs like LS1043A, LS1046A, LS2088A, LX2160A are part of some chassis.
e.g. LS1043A conforms to Chassis 2.x
LX2160A conforms to Chassis 3.2
We can think of Chassis/Soc/Platform(a.k.a Borad) in Oops terms.
Chassis is base. Soc Is derived from Chassis. Platform is derived from Soc.
We have kept the code also in such a way. Which is why we have made Soc Package part of Chassis Package.
SocLib provides services to PlatformLib. ChassisLib provides services to SocLib.
Which is why we have made SocGetMpCoreInfo as weak function and implemented it in ChassisLib (Patch 11/19)
This ensures that code can be reused for all SOCs belonging to same chassis.
If any future SOC implements this feature in different way, then this API can be overwritten in SocLib
SOCs belonging to same Chassis share many same traits.
e.g. the SOC memory map is usually common for all SOCs belonging to same Chassis.
>
> /
> Leif
>
> > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> > ---
> > .../Drivers/PlatformDxe/PlatformDxe.inf | 3 +-
> > Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 3 +-
> > .../Library/ArmPlatformLib/ArmPlatformLib.c | 53 ++++++-
> > .../Library/ArmPlatformLib/ArmPlatformLib.inf | 6 +-
> > Silicon/NXP/Chassis2/Include/Chassis.h | 12 ++
> > Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc | 1 +
> > .../Chassis2/LS1043A/Library/SocLib/SocLib.c | 28 ++++
> > .../LS1043A/Library/SocLib/SocLib.inf | 8 ++
> > .../Chassis2/Library/ChassisLib/ChassisLib.c | 25 ++++
> > Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 2 +-
> > Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 7 +-
> > Silicon/NXP/Include/Chassis2/NxpSoc.h | 53 -------
> > Silicon/NXP/Include/Library/ChassisLib.h | 2 -
> > Silicon/NXP/Include/Library/SocLib.h | 1 -
> > Silicon/NXP/LS1043A/Include/Soc.h | 44 ------
> > Silicon/NXP/LS1043A/LS1043A.dec | 16 ---
> > Silicon/NXP/LS1043A/LS1043A.dsc.inc | 33 -----
> > .../BaseSerialPortLib16550.c | 11 +-
> > .../BaseSerialPortLib16550.inf | 3 +-
> > Silicon/NXP/Library/SocLib/Chassis.c | 76 ----------
> > Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 96 -------------
> > Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 44 ------
> > Silicon/NXP/Library/SocLib/NxpChassis.h | 136 ------------------
> > 23 files changed, 142 insertions(+), 521 deletions(-) delete mode
> > 100644 Silicon/NXP/Include/Chassis2/NxpSoc.h
> > delete mode 100644 Silicon/NXP/LS1043A/Include/Soc.h delete mode
> > 100644 Silicon/NXP/LS1043A/LS1043A.dec delete mode 100644
> > Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > delete mode 100644 Silicon/NXP/Library/SocLib/Chassis.c
> > delete mode 100644 Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > delete mode 100644 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > delete mode 100644 Silicon/NXP/Library/SocLib/NxpChassis.h
> >
> > diff --git
> > a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> > b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> > index 126a1174fa..95f60b00f0 100644
> > --- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> > +++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> > @@ -25,7 +25,8 @@
> > MdeModulePkg/MdeModulePkg.dec
> > Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
> > Silicon/NXP/NxpQoriqLs.dec
> > - Silicon/NXP/LS1043A/LS1043A.dec
> > + Silicon/NXP/Chassis2/Chassis2.dec
> > + Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
> >
> > [LibraryClasses]
> > BaseLib
> > diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > index bc6fa4f19d..4bc7f6ef97 100644
> > --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > @@ -23,7 +23,8 @@
> > FLASH_DEFINITION =
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> >
> > !include Silicon/NXP/NxpQoriqLs.dsc.inc -!include
> > Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > +!include Silicon/NXP/Chassis2/Chassis2.dsc.inc
> > +!include Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
> >
> > [LibraryClasses.common]
> >
> > ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPl
> > atformLib.inf diff --git
> > a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> > b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> > index 718c71bf02..821d413a3e 100644
> > ---
> > a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> > +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib
> > +++ .c
> > @@ -14,7 +14,10 @@
> > #include <Library/ArmPlatformLib.h>
> > #include <Ppi/ArmMpCoreInfo.h>
> >
> > -extern VOID SocInit (VOID);
> > +#include <Library/DebugLib.h>
> > +#include <Library/I2cLib.h>
> > +#include <Library/SocLib.h>
> > +#include <Ppi/NxpPlatformGetClock.h>
> >
> > /**
> > Return the current Boot Mode
> > @@ -30,6 +33,49 @@ ArmPlatformGetBootMode (
> > return BOOT_WITH_FULL_CONFIGURATION; }
> >
> > +/**
> > + Get the clocks supplied by Platform(Board) to NXP Layerscape SOC
> > +
> > + The core can be of type ARM or PowerPC or Hardware Accelerator.
> > + If the core is enabled and of type ARM EFI_SUCCESS is returned and
> > + a code for type of ARM core is returned
> > +
> > + @param[in] ClockType Type of clock
> > + @param[in] ... Variable argument list which is parsed based on
> ClockType
> > +
> > + @return Actual Clock Frequency. return value 0 should be interpreted as
> clock not provided by Board.
> > +**/
> > +UINT64
> > +EFIAPI
> > +NxpPlatformGetClock(
> > + IN UINT32 ClockType,
> > + ...
> > + )
> > +{
> > + UINT64 Clock;
> > + VA_LIST Args;
> > +
> > + Clock = 0;
> > +
> > + VA_START (Args, ClockType);
> > +
> > + switch (ClockType) {
> > + case NXP_SYSTEM_CLOCK:
> > + Clock = 100 * 1000 * 1000; // 100 MHz
> > + break;
> > + case NXP_I2C_CLOCK:
> > + case NXP_UART_CLOCK:
> > + Clock = NxpPlatformGetClock (NXP_SYSTEM_CLOCK);
> > + Clock = SocGetClock (Clock, ClockType, Args);
> > + break;
> > + default:
> > + break;
> > + }
> > +
> > + VA_END (Args);
> > +
> > + return Clock;
> > +}
> > +
> > /**
> > Placeholder for Platform Initialization **/ @@ -38,9 +84,9 @@
> > ArmPlatformInitialize (
> > IN UINTN MpId
> > )
> > {
> > - SocInit ();
> > + SocInit ();
> >
> > - return EFI_SUCCESS;
> > + return EFI_SUCCESS;
> > }
> >
> > ARM_CORE_INFO LS1043aMpCoreInfoCTA53x4[] = { @@ -69,6 +115,7 @@
> > PrePeiCoreGetMpCoreInfo ( }
> >
> > ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
> > +NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi = {
> > +NxpPlatformGetClock };
> >
> > EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
> > {
> > diff --git
> > a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> > b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> > index 6396d2982b..8b79fd7490 100644
> > ---
> > a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> > +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib
> > +++ .inf
> > @@ -20,11 +20,14 @@
> > EmbeddedPkg/EmbeddedPkg.dec
> > MdePkg/MdePkg.dec
> > Silicon/NXP/NxpQoriqLs.dec
> > - Silicon/NXP/LS1043A/LS1043A.dec
> > + Silicon/NXP/Chassis2/Chassis2.dec
> > + Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
> >
> > [LibraryClasses]
> > ArmLib
> > SocLib
> > + I2cLib
> > + DebugLib
> >
> > [Sources.common]
> > AArch64/NxpQoriqLsHelper.S | GCC
> > @@ -36,3 +39,4 @@
> >
> > [FixedPcd]
> > gArmTokenSpaceGuid.PcdArmPrimaryCore
> > + gArmPlatformTokenSpaceGuid.PcdCoreCount
> > diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h
> > b/Silicon/NXP/Chassis2/Include/Chassis.h
> > index 48ba2e7bfb..8f26faf297 100644
> > --- a/Silicon/NXP/Chassis2/Include/Chassis.h
> > +++ b/Silicon/NXP/Chassis2/Include/Chassis.h
> > @@ -20,6 +20,18 @@
> > #define TP_ITYPE_VERSION_A53 0x2
> > #define TP_ITYPE_VERSION_A72 0x4
> >
> > +/* SMMU Defintions */
> > +#define SMMU_BASE_ADDR 0x09000000
> > +#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
> > +#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
> > +#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
> > +#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
> > +#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
> > +
> > +#define SCR0_USFCFG_MASK 0x00000400
> > +#define SCR0_CLIENTPD_MASK 0x00000001
> > +#define SACR_PAGESIZE_MASK 0x00010000
> > +
> > /**
> > The Device Configuration Unit provides general purpose configuration and
> status for the
> > device. These registers only support 32-bit accesses.
> > diff --git a/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
> > b/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
> > index 4511203443..8440e5f0f3 100644
> > --- a/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
> > +++ b/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
> > @@ -8,6 +8,7 @@
> >
> > [LibraryClasses.common]
> > SocLib|Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> > +
> > + SerialPortLib|Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialP
> > + ortLib16550.inf
> >
> >
> >
> #################################################################
> #####
> > ##########
> > #
> > diff --git a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
> > b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
> > index 2a08ad87db..24241e9b02 100644
> > --- a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
> > +++ b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
> > @@ -4,8 +4,10 @@
> >
> > SPDX-License-Identifier: BSD-2-Clause-Patent
> > **/
> > +#include <Soc.h>
> > #include <Library/ChassisLib.h>
> > #include <Library/SocLib.h>
> > +#include <Library/SerialPortLib.h>
> >
> > /**
> > Return the input clock frequency to an IP Module.
> > @@ -66,8 +68,34 @@ SocInit (
> > VOID
> > )
> > {
> > + UINT64 BaudRate;
> > + UINT32 ReceiveFifoDepth;
> > + EFI_PARITY_TYPE Parity;
> > + UINT8 DataBits;
> > + EFI_STOP_BITS_TYPE StopBits;
> > + UINT32 Timeout;
> > +
> > + BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
> > + ReceiveFifoDepth = FixedPcdGet16 (PcdUartDefaultReceiveFifoDepth);
> > + // Use default FIFO depth Timeout = 0; Parity =
> > + (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity); DataBits =
> > + FixedPcdGet8 (PcdUartDefaultDataBits); StopBits =
> > + (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);
> > +
> > ChassisInit ();
> >
> > + //
> > + // Early init serial Port to get board information.
> > + //
> > + SerialPortSetAttributes (
> > + &BaudRate,
> > + &ReceiveFifoDepth,
> > + &Timeout,
> > + &Parity,
> > + &DataBits,
> > + &StopBits
> > + );
> > +
> > return;
> > }
> >
> > diff --git a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> > b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> > index c9a4fbc01f..fb39424bc5 100644
> > --- a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> > +++ b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> > @@ -29,4 +29,12 @@
> >
> > [LibraryClasses]
> > ChassisLib
> > + PcdLib
> > + SerialPortLib
> >
> > +[FixedPcd]
> > + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
> > + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
> > + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
> > + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
> > + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth
> > diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> > b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> > index fa6a36e96f..e7573a0e06 100644
> > --- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> > +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> > @@ -150,6 +150,29 @@ SocGetMpCoreInfo (
> > return CoreCount;
> > }
> >
> > +/*
> > + * Setup SMMU in bypass mode
> > + * and also set its pagesize
> > + */
> > +STATIC
> > +VOID
> > +SmmuInit (
> > + VOID
> > + )
> > +{
> > + UINT32 Value;
> > +
> > + /* set pagesize as 64K and ssmu-500 in bypass mode */ Value =
> > + (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
> > + MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
> > +
> > + Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK)
> &
> > + ~SCR0_USFCFG_MASK;
> > + MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
> > +
> > + Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) |
> SCR0_CLIENTPD_MASK) &
> > +~SCR0_USFCFG_MASK;
> > + MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value); }
> > +
> > /**
> > Function to initialize Chassis Specific functions
> > **/
> > @@ -183,4 +206,6 @@ ChassisInit (
> > &DataBits,
> > &StopBits
> > );
> > +
> > + SmmuInit();
> > }
> > diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> > b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> > index 8e3a82efca..e79b106c8d 100644
> > --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> > +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> > @@ -50,7 +50,7 @@ SetBusFrequency (
> >
> > I2cBase = (UINTN)(I2c->Dev->Resources[0].AddrRangeMin);
> >
> > - I2cClock = GetBusFrequency ();
> > + I2cClock = mPlatformGetClockPpi.PlatformGetClock (NXP_I2C_CLOCK,
> > + 0);
> >
> > I2cInitialize (I2cBase, I2cClock, *BusClockHertz);
> >
> > diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> > b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> > index 88316f3133..f446f0d4f9 100644
> > --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> > +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> > @@ -13,6 +13,7 @@
> > #include <Library/UefiLib.h>
> > #include <Uefi.h>
> >
> > +#include <Ppi/NxpPlatformGetClock.h>
> > #include <Protocol/I2cMaster.h>
> > #include <Protocol/NonDiscoverableDevice.h>
> >
> > @@ -37,11 +38,7 @@ typedef struct {
> > NON_DISCOVERABLE_DEVICE *Dev;
> > } NXP_I2C_MASTER;
> >
> > -extern
> > -UINT64
> > -GetBusFrequency (
> > - VOID
> > - );
> > +extern NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi;
> >
> > EFI_STATUS
> > NxpI2cInit (
> > diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h
> > b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> > deleted file mode 100644
> > index 6812beafe4..0000000000
> > --- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
> > +++ /dev/null
> > @@ -1,53 +0,0 @@
> > -/** Soc.h
> > -* Header defining the Base addresses, sizes, flags etc for chassis 1
> > -*
> > -* Copyright 2017-2020 NXP
> > -*
> > -* SPDX-License-Identifier: BSD-2-Clause-Patent
> > -*
> > -**/
> > -
> > -#ifndef NXP_SOC_H_
> > -#define NXP_SOC_H_
> > -
> > -#define CLK_FREQ 100000000
> > -
> > -#define CHASSIS2_DCFG_ADDRESS 0x1EE0000
> > -
> > -/* SMMU Defintions */
> > -#define SMMU_BASE_ADDR 0x09000000
> > -#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
> > -#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
> > -#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
> > -#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
> > -#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
> > -
> > -#define SCR0_USFCFG_MASK 0x00000400
> > -#define SCR0_CLIENTPD_MASK 0x00000001
> > -#define SACR_PAGESIZE_MASK 0x00010000
> > -#define IDR1_PAGESIZE_MASK 0x80000000
> > -
> > -typedef struct {
> > - UINTN FreqSystemBus;
> > -} SYS_INFO;
> > -
> > -/* Device Configuration and Pin Control */ -typedef struct {
> > - UINT8 Res0[0x100-0x00];
> > - UINT32 RcwSr[16]; /* Reset control word status */
> > -#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25 -#define
> > CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f -} CCSR_GUR;
> > -
> > -VOID
> > -GetSysInfo (
> > - OUT SYS_INFO *
> > - );
> > -
> > -UINT32
> > -EFIAPI
> > -GurRead (
> > - IN UINTN Address
> > - );
> > -
> > -#endif /* NXP_SOC_H_ */
> > diff --git a/Silicon/NXP/Include/Library/ChassisLib.h
> > b/Silicon/NXP/Include/Library/ChassisLib.h
> > index b51b024374..d07c59b82d 100644
> > --- a/Silicon/NXP/Include/Library/ChassisLib.h
> > +++ b/Silicon/NXP/Include/Library/ChassisLib.h
> > @@ -9,8 +9,6 @@
> > #ifndef __CHASSIS_LIB_H__
> > #define __CHASSIS_LIB_H__
> >
> > -#include <Chassis.h>
> > -
> > /**
> > Read Dcfg register
> > **/
> > diff --git a/Silicon/NXP/Include/Library/SocLib.h
> > b/Silicon/NXP/Include/Library/SocLib.h
> > index 3def396171..700e877bdf 100644
> > --- a/Silicon/NXP/Include/Library/SocLib.h
> > +++ b/Silicon/NXP/Include/Library/SocLib.h
> > @@ -8,7 +8,6 @@
> > #ifndef __SOC_LIB_H__
> > #define __SOC_LIB_H__
> >
> > -#include <Soc.h>
> > #include <Uefi.h>
> > #include <Ppi/ArmMpCoreInfo.h>
> > #include <Ppi/NxpPlatformGetClock.h>
> > diff --git a/Silicon/NXP/LS1043A/Include/Soc.h
> > b/Silicon/NXP/LS1043A/Include/Soc.h
> > deleted file mode 100644
> > index c1e00394af..0000000000
> > --- a/Silicon/NXP/LS1043A/Include/Soc.h
> > +++ /dev/null
> > @@ -1,44 +0,0 @@
> > -/** @file
> > -
> > - Copyright 2020 NXP
> > -
> > - SPDX-License-Identifier: BSD-2-Clause-Patent
> > -
> > -**/
> > -#ifndef __SOC_H__
> > -#define __SOC_H__
> > -
> > -/**
> > - Soc Memory Map
> > -**/
> > -#define LS1043A_DRAM0_PHYS_ADDRESS 0x80000000
> > -#define LS1043A_DRAM0_SIZE SIZE_2GB
> > -#define LS1043A_DRAM1_PHYS_ADDRESS 0x880000000
> > -#define LS1043A_DRAM1_SIZE 0x780000000 // 30 GB
> > -
> > -#define LS1043A_CCSR_PHYS_ADDRESS 0x1000000
> > -#define LS1043A_CCSR_SIZE 0xF000000
> > -
> > -#define LS1043A_IFC0_PHYS_ADDRESS 0x60000000
> > -#define LS1043A_IFC0_SIZE SIZE_512MB
> > -#define LS1043A_IFC1_PHYS_ADDRESS 0x620000000
> > -#define LS1043A_IFC1_SIZE 0xE0000000 // 3.5 GB
> > -
> > -#define LS1043A_QSPI_PHYS_ADDRESS 0x40000000
> > -#define LS1043A_QSPI_SIZE SIZE_512MB
> > -
> > -#define LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS 0x500000000
> > -#define LS1043A_QMAN_SW_PORTAL_SIZE SIZE_128MB
> > -#define LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS 0x508000000
> > -#define LS1043A_BMAN_SW_PORTAL_SIZE SIZE_128MB
> > -
> > -#define LS1043A_PCI0_PHYS_ADDRESS 0x4000000000
> > -#define LS1043A_PCI1_PHYS_ADDRESS 0x4800000000
> > -#define LS1043A_PCI2_PHYS_ADDRESS 0x5000000000
> > -#define LS1043A_PCI_SIZE SIZE_32GB
> > -
> > -#define LS1043A_I2C0_PHYS_ADDRESS 0x2180000
> > -#define LS1043A_I2C_SIZE 0x10000
> > -#define LS1043A_I2C_NUM_CONTROLLERS 4
> > -
> > -#endif
> > diff --git a/Silicon/NXP/LS1043A/LS1043A.dec
> > b/Silicon/NXP/LS1043A/LS1043A.dec deleted file mode 100644 index
> > cd79949790..0000000000
> > --- a/Silicon/NXP/LS1043A/LS1043A.dec
> > +++ /dev/null
> > @@ -1,16 +0,0 @@
> > -# LS1043A.dec
> > -#
> > -# Copyright 2017-2019 NXP
> > -#
> > -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#
> > -
> > -[Defines]
> > - DEC_SPECIFICATION = 0x0001001A
> > -
> > -[Guids.common]
> > - gNxpLs1043ATokenSpaceGuid = {0x6834fe45, 0x4aee, 0x4fc6, {0xbc,
> 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
> > -
> > -[Includes]
> > - Include
> > diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > deleted file mode 100644
> > index 7ebbb1a495..0000000000
> > --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > +++ /dev/null
> > @@ -1,33 +0,0 @@
> > -# LS1043A.dsc
> > -# LS1043A Soc package.
> > -#
> > -# Copyright 2017-2020 NXP
> > -#
> > -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#
> > -
> > -[LibraryClasses.common]
> > - SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > -
> > SerialPortLib|Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPor
> > tLib16550.inf
> > -
> > -
> #################################################################
> ####
> > ###########
> > -#
> > -# Pcd Section - list of all EDK II PCD Entries defined by this
> > Platform -#
> > -
> #################################################################
> ####
> > ###########
> > -[PcdsDynamicDefault.common]
> > -
> > - #
> > - # ARM General Interrupt Controller
> > - gArmTokenSpaceGuid.PcdGicDistributorBase|0x01401000
> > - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01402000
> > -
> > -[PcdsFixedAtBuild.common]
> > - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
> > -
> > - #
> > - # Big Endian IPs
> > - #
> > - gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
> > -##
> > diff --git
> > a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> > b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> > index 6b2aa46ff6..2e35f09d8f 100644
> > ---
> > a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> > +++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib1655
> > +++ 0.c
> > @@ -15,6 +15,9 @@
> > #include <Library/PcdLib.h>
> > #include <Library/IoLib.h>
> > #include <Library/BaseLib.h>
> > +#include <Ppi/NxpPlatformGetClock.h>
> > +
> > +extern NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi;
> >
> > //
> > // 16550 UART register offsets and bitfields @@ -42,12 +45,6 @@
> > #define B_UART_MSR_RI BIT6
> > #define B_UART_MSR_DCD BIT7
> >
> > -extern
> > -UINT64
> > -GetBusFrequency (
> > - VOID
> > - );
> > -
> > /**
> > Read an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is
> read from
> > MMIO space. If PcdSerialUseMmio is FALSE, then the value is read
> > from I/O space. The @@ -577,7 +574,7 @@ SerialPortSetAttributes (
> > return RETURN_UNSUPPORTED;
> > }
> >
> > - SerialClock = GetBusFrequency ();
> > + SerialClock = mPlatformGetClockPpi.PlatformGetClock
> > + (NXP_UART_CLOCK, 0);
> > if (SerialClock == 0) {
> > return EFI_DEVICE_ERROR;
> > }
> > diff --git
> > a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.in
> > f
> > b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.in
> > f
> > index 45ae9dc0af..7823bc5be5 100644
> > ---
> > a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.in
> > f
> > +++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib1655
> > +++ 0.inf
> > @@ -19,11 +19,12 @@
> > [Packages]
> > MdePkg/MdePkg.dec
> > MdeModulePkg/MdeModulePkg.dec
> > + Silicon/NXP/NxpQoriqLs.dec
> >
> > [LibraryClasses]
> > PcdLib
> > IoLib
> > - SocLib
> > + ArmPlatformLib
> >
> > [Sources]
> > BaseSerialPortLib16550.c
> > diff --git a/Silicon/NXP/Library/SocLib/Chassis.c
> > b/Silicon/NXP/Library/SocLib/Chassis.c
> > deleted file mode 100644
> > index 1ef99e8de2..0000000000
> > --- a/Silicon/NXP/Library/SocLib/Chassis.c
> > +++ /dev/null
> > @@ -1,76 +0,0 @@
> > -/** @file
> > - SoC specific Library containg functions to initialize various SoC
> > components
> > -
> > - Copyright 2017-2020 NXP
> > -
> > - SPDX-License-Identifier: BSD-2-Clause-Patent
> > -
> > -**/
> > -
> > -#include <Base.h>
> > -#ifdef CHASSIS2
> > -#include <Chassis2/NxpSoc.h>
> > -#elif CHASSIS3
> > -#include <Chassis3/NxpSoc.h>
> > -#endif
> > -#include <Library/ArmSmcLib.h>
> > -#include <Library/BaseLib.h>
> > -#include <Library/IoAccessLib.h>
> > -#include <Library/DebugLib.h>
> > -#include <Library/IoLib.h>
> > -#include <Library/PcdLib.h>
> > -#include <Library/PrintLib.h>
> > -#include <Library/SerialPortLib.h>
> > -
> > -#include "NxpChassis.h"
> > -
> > -UINT32
> > -EFIAPI
> > -GurRead (
> > - IN UINTN Address
> > - )
> > -{
> > - if (FixedPcdGetBool (PcdGurBigEndian)) {
> > - return SwapMmioRead32 (Address);
> > - } else {
> > - return MmioRead32 (Address);
> > - }
> > -}
> > -
> > -/*
> > - * Return system bus frequency
> > - */
> > -UINT64
> > -GetBusFrequency (
> > - VOID
> > - )
> > -{
> > - SYS_INFO SocSysInfo;
> > -
> > - GetSysInfo (&SocSysInfo);
> > -
> > - return SocSysInfo.FreqSystemBus;
> > -}
> > -
> > -/*
> > - * Setup SMMU in bypass mode
> > - * and also set its pagesize
> > - */
> > -VOID
> > -SmmuInit (
> > - VOID
> > - )
> > -{
> > - UINT32 Value;
> > -
> > - /* set pagesize as 64K and ssmu-500 in bypass mode */
> > - Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
> > - MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
> > -
> > - Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK)
> &
> > ~SCR0_USFCFG_MASK;
> > - MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
> > -
> > - Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) |
> SCR0_CLIENTPD_MASK) &
> > ~SCR0_USFCFG_MASK;
> > - MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value); -}
> > -
> > diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > deleted file mode 100644
> > index a3dabc93d1..0000000000
> > --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > +++ /dev/null
> > @@ -1,96 +0,0 @@
> > -/** @Soc.c
> > - SoC specific Library containg functions to initialize various SoC
> > components
> > -
> > - Copyright 2017-2020 NXP
> > -
> > - SPDX-License-Identifier: BSD-2-Clause-Patent
> > -
> > -**/
> > -
> > -#include <Base.h>
> > -#include <NxpChassis.h>
> > -#include <Chassis2/NxpSoc.h>
> > -#include <Library/BaseLib.h>
> > -#include <Library/BaseMemoryLib.h>
> > -#include <Library/DebugLib.h>
> > -#include <Library/IoAccessLib.h>
> > -#include <Library/IoLib.h>
> > -#include <Library/PcdLib.h>
> > -#include <Library/PrintLib.h>
> > -#include <Library/SerialPortLib.h>
> > -
> > -/**
> > - Calculate the frequency of various controllers and
> > - populate the passed structure with frequuencies.
> > -
> > - @param PtrSysInfo Input structure to populate with
> > - frequencies.
> > -**/
> > -VOID
> > -GetSysInfo (
> > - OUT SYS_INFO *PtrSysInfo
> > - )
> > -{
> > - CCSR_GUR *GurBase;
> > - UINTN SysClk;
> > -
> > - GurBase = (CCSR_GUR *)CHASSIS2_DCFG_ADDRESS;
> > - SysClk = CLK_FREQ;
> > -
> > - SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
> > -
> > - PtrSysInfo->FreqSystemBus = SysClk;
> > -
> > - //
> > - // selects the platform clock:SYSCLK ratio and calculate
> > - // system frequency
> > - //
> > - PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
> > - CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
> > - CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
> > -}
> > -
> > -/**
> > - Function to initialize SoC specific constructs
> > - CPU Info
> > - SoC Personality
> > - Board Personality
> > - RCW prints
> > - **/
> > -VOID
> > -SocInit (
> > - VOID
> > - )
> > -{
> > - UINT64 BaudRate;
> > - UINT32 ReceiveFifoDepth;
> > - EFI_PARITY_TYPE Parity;
> > - UINT8 DataBits;
> > - EFI_STOP_BITS_TYPE StopBits;
> > - UINT32 Timeout;
> > -
> > - BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
> > - ReceiveFifoDepth = 0; // Use default FIFO depth
> > - Timeout = 0;
> > - Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
> > - DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
> > - StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8
> > (PcdUartDefaultStopBits);
> > -
> > - SmmuInit ();
> > -
> > - //
> > - // Early init serial Port to get board information.
> > - //
> > - SerialPortSetAttributes (
> > - &BaudRate,
> > - &ReceiveFifoDepth,
> > - &Timeout,
> > - &Parity,
> > - &DataBits,
> > - &StopBits
> > - );
> > - DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a on %a)\n",
> > - (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__,
> __DATE__));
> > -
> > - return;
> > -}
> > diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > deleted file mode 100644
> > index d8707927b7..0000000000
> > --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > +++ /dev/null
> > @@ -1,44 +0,0 @@
> > -# @file
> > -#
> > -# Copyright 2017-2020 NXP
> > -#
> > -# SPDX-License-Identifier: BSD-2-Clause-Patent -#
> > -
> > -[Defines]
> > - INF_VERSION = 0x0001001A
> > - BASE_NAME = SocLib
> > - FILE_GUID = e868c5ca-9729-43ae-bff4-438c67de8c68
> > - MODULE_TYPE = BASE
> > - VERSION_STRING = 1.0
> > - LIBRARY_CLASS = SocLib
> > -
> > -[Packages]
> > - ArmPkg/ArmPkg.dec
> > - MdeModulePkg/MdeModulePkg.dec
> > - MdePkg/MdePkg.dec
> > - Silicon/NXP/NxpQoriqLs.dec
> > - Silicon/NXP/LS1043A/LS1043A.dec
> > -
> > -[LibraryClasses]
> > - ArmSmcLib
> > - BaseLib
> > - DebugLib
> > - IoAccessLib
> > - SerialPortLib
> > -
> > -[Sources.common]
> > - Chassis.c
> > - Chassis2/Soc.c
> > -
> > -[BuildOptions]
> > - GCC:*_*_*_CC_FLAGS = -DCHASSIS2
> > -
> > -[FixedPcd]
> > - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
> > - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
> > - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
> > - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
> > - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> > - gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
> > - gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
> > diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h
> > b/Silicon/NXP/Library/SocLib/NxpChassis.h
> > deleted file mode 100644
> > index 99f6439d8f..0000000000
> > --- a/Silicon/NXP/Library/SocLib/NxpChassis.h
> > +++ /dev/null
> > @@ -1,136 +0,0 @@
> > -/** @file
> > -* Header defining the Base addresses, sizes, flags etc for chassis 1
> > -*
> > -* Copyright 2017-2019 NXP
> > -*
> > -* SPDX-License-Identifier: BSD-2-Clause-Patent
> > -*
> > -**/
> > -
> > -#ifndef NXP_CHASSIS_H_
> > -#define NXP_CHASSIS_H_
> > -
> > -#define TP_ITYP_AV_MASK 0x00000001 /* Initiator available */
> > -#define TP_ITYP_TYPE_MASK(x) (((x) & 0x6) >> 1) /* Initiator Type */
> > -#define TP_ITYP_TYPE_ARM 0x0
> > -#define TP_ITYP_TYPE_PPC 0x1
> > -#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
> > -#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
> > -#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
> > -#define TP_ITYP_VERSION(x) (((x) & 0xe0) >> 5) /* Initiator Version */
> > -#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
> > -#define TP_INIT_PER_CLUSTER 4
> > -
> > -#define TY_ITYP_VERSION_A7 0x1
> > -#define TY_ITYP_VERSION_A53 0x2
> > -#define TY_ITYP_VERSION_A57 0x3
> > -#define TY_ITYP_VERSION_A72 0x4
> > -
> > -#define CPU_TYPE_ENTRY(N, V, NC) { .Name = #N, .SocVer =
> SVR_##V, .NumCores = (NC)}
> > -
> > -#define SVR_WO_E 0xFFFFFE
> > -#define SVR_LS1043A 0x879200
> > -#define SVR_LS1046A 0x870700
> > -#define SVR_LS2088A 0x870901
> > -
> > -#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
> > -#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
> > -#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
> > -#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
> > -
> > -#define MHZ 1000000
> > -
> > -typedef struct {
> > - CHAR8 *Name;
> > - UINT32 SocVer;
> > - UINT32 NumCores;
> > -} CPU_TYPE;
> > -
> > -typedef struct {
> > - UINTN CpuClk; /* CPU clock in Hz! */
> > - UINTN BusClk;
> > - UINTN MemClk;
> > - UINTN PciClk;
> > - UINTN SdhcClk;
> > -} SOC_CLOCK_INFO;
> > -
> > -/*
> > - * Print Soc information
> > - */
> > -VOID
> > -PrintSoc (
> > - VOID
> > - );
> > -
> > -/*
> > - * Initialize Clock structure
> > - */
> > -VOID
> > -ClockInit (
> > - VOID
> > - );
> > -
> > -/*
> > - * Setup SMMU in bypass mode
> > - * and also set its pagesize
> > - */
> > -VOID
> > -SmmuInit (
> > - VOID
> > - );
> > -
> > -/*
> > - * Print CPU information
> > - */
> > -VOID
> > -PrintCpuInfo (
> > - VOID
> > - );
> > -
> > -/*
> > - * Dump RCW (Reset Control Word) on console
> > - */
> > -VOID
> > -PrintRCW (
> > - VOID
> > - );
> > -
> > -UINT32
> > -InitiatorType (
> > - IN UINT32 Cluster,
> > - IN UINTN InitId
> > - );
> > -
> > -/*
> > - * Return the mask for number of cores on this SOC.
> > - */
> > -UINT32
> > -CpuMask (
> > - VOID
> > - );
> > -
> > -/*
> > - * Return the number of cores on this SOC.
> > - */
> > -UINTN
> > -CpuNumCores (
> > - VOID
> > - );
> > -
> > -/*
> > - * Return the type of initiator for core/hardware accelerator for given core
> index.
> > - */
> > -UINTN
> > -QoriqCoreToType (
> > - IN UINTN Core
> > - );
> > -
> > -/*
> > - * Return the cluster of initiator for core/hardware accelerator for given core
> index.
> > - */
> > -INT32
> > -QoriqCoreToCluster (
> > - IN UINTN Core
> > - );
> > -
> > -#endif /* NXP_CHASSIS_H_ */
> > --
> > 2.17.1
> >
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 15/19] Platform/NXP/LS1043ARDB: introduce PEI Phase
2020-02-07 12:43 ` [PATCH 15/19] Platform/NXP/LS1043ARDB: introduce PEI Phase Pankaj Bansal
@ 2020-02-12 20:24 ` Leif Lindholm
0 siblings, 0 replies; 49+ messages in thread
From: Leif Lindholm @ 2020-02-12 20:24 UTC (permalink / raw)
To: Pankaj Bansal; +Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi, devel
On Fri, Feb 07, 2020 at 18:13:24 +0530, Pankaj Bansal wrote:
> Added PEI phase to LS1043ARDB.
Needs more detail.
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> Platform/NXP/FVRules.fdf.inc | 60 ++++---
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 13 --
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 19 ++-
> .../AArch64/ArmPlatformHelper.S | 46 +++++
> .../ArmPlatformLib/AArch64/NxpQoriqLsHelper.S | 31 ----
> .../Library/ArmPlatformLib/ArmPlatformLib.c | 86 +++++-----
> .../Library/ArmPlatformLib/ArmPlatformLib.inf | 19 ++-
> .../ArmPlatformLib/ArmPlatformLibMem.c | 27 ++-
> Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc | 91 ++++++++++
> .../MemoryInitPeiLib.c | 160 +++++++++---------
> .../MemoryInitPeiLib.h | 1 -
> .../MemoryInitPeiLib.inf | 24 +--
> .../Library/PlatformPeiLib/PlatformPeiLib.c | 30 ++++
> .../Library/PlatformPeiLib/PlatformPeiLib.inf | 50 ++++++
> Silicon/NXP/NxpQoriqLs.dec | 21 +--
> Silicon/NXP/NxpQoriqLs.dsc.inc | 67 +++++---
> 16 files changed, 481 insertions(+), 264 deletions(-)
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
> delete mode 100644 Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/NxpQoriqLsHelper.S
> create mode 100644 Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
> rename Silicon/NXP/Library/{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.c (82%)
> rename Silicon/NXP/Library/{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.h (94%)
> rename Silicon/NXP/Library/{MemoryInitPei => MemoryInitPeiLib}/MemoryInitPeiLib.inf (80%)
> create mode 100644 Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c
> create mode 100644 Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
>
> diff --git a/Platform/NXP/FVRules.fdf.inc b/Platform/NXP/FVRules.fdf.inc
> index c9fba65dae..598262e045 100644
> --- a/Platform/NXP/FVRules.fdf.inc
> +++ b/Platform/NXP/FVRules.fdf.inc
> @@ -1,8 +1,8 @@
> -# FvRules.fdf.inc
> #
> -# Rules for creating FD.
> -#
> -# Copyright 2017-2019 NXP
> +# Copyright (c) 2011-2015, ARM Limited. All rights reserved.
> +# Copyright (c) 2014-2016, Linaro Limited. All rights reserved.
> +# Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
> +# Copyright 2017-2020 NXP
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -16,40 +16,49 @@
> #
> ################################################################################
>
> +
> +############################################################################
> +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
> +############################################################################
> +#
> +#[Rule.Common.DXE_DRIVER]
> +# FILE DRIVER = $(NAMED_GUID) {
> +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> +# COMPRESS PI_STD {
> +# GUIDED {
> +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> +# UI STRING="$(MODULE_NAME)" Optional
> +# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> +# }
> +# }
> +# }
> +#
> +############################################################################
> +
> [Rule.Common.SEC]
> - FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
> - TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED {
> + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
> }
>
> [Rule.Common.PEI_CORE]
> - FILE PEI_CORE = $(NAMED_GUID) {
> - TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
> + FILE PEI_CORE = $(NAMED_GUID) FIXED {
> + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
> UI STRING ="$(MODULE_NAME)" Optional
> }
>
> [Rule.Common.PEIM]
> - FILE PEIM = $(NAMED_GUID) {
> + FILE PEIM = $(NAMED_GUID) FIXED {
> PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
> UI STRING="$(MODULE_NAME)" Optional
> }
>
> -[Rule.Common.PEIM.TIANOCOMPRESSED]
> - FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
> - PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> - GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
> - PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> - UI STRING="$(MODULE_NAME)" Optional
> - }
> - }
> -
> [Rule.Common.DXE_CORE]
> FILE DXE_CORE = $(NAMED_GUID) {
> PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> UI STRING="$(MODULE_NAME)" Optional
> }
>
> -
> [Rule.Common.UEFI_DRIVER]
> FILE DRIVER = $(NAMED_GUID) {
> DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> @@ -62,6 +71,8 @@
> DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> UI STRING="$(MODULE_NAME)" Optional
> + RAW ACPI Optional |.acpi
> + RAW ASL Optional |.aml
> }
>
> [Rule.Common.DXE_RUNTIME_DRIVER]
> @@ -73,7 +84,7 @@
>
> [Rule.Common.UEFI_APPLICATION]
> FILE APPLICATION = $(NAMED_GUID) {
> - UI STRING ="$(MODULE_NAME)" Optional
> + UI STRING ="$(MODULE_NAME)" Optional
> PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> }
>
> @@ -91,3 +102,10 @@
> UI STRING="$(MODULE_NAME)" Optional
> VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> }
> +
> +[Rule.Common.USER_DEFINED.ACPITABLE]
> + FILE FREEFORM = $(NAMED_GUID) {
> + RAW ACPI |.acpi
> + RAW ASL |.aml
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> index 4bc7f6ef97..c9f828668f 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> @@ -32,19 +32,6 @@
>
> [PcdsFixedAtBuild.common]
>
> - #
> - # LS1043a board Specific PCDs
> - # XX (DRAM - Region 1 2GB)
> - # (NOR - IFC Region 1 512MB)
> - gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
> - gArmTokenSpaceGuid.PcdSystemMemorySize|0x7BE00000
> - gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
> -
> - #
> - # Board Specific Pcds
> - #
> - gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
> -
> #
> # RTC Pcds
> #
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> index 8d66f36d74..22391899b7 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> @@ -3,7 +3,7 @@
> # FLASH layout file for LS1043a board.
> #
> # Copyright (c) 2016, Freescale Ltd. All rights reserved.
> -# Copyright 2017-2019 NXP
> +# Copyright 2017-2020 NXP
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -24,10 +24,10 @@
>
> [FD.LS1043ARDB_EFI]
> BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
> -Size = 0x000ED000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
> +Size = 0x00100000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
> ErasePolarity = 1
> BlockSize = 0x1
> -NumBlocks = 0xED000
> +NumBlocks = 0x100000
>
> ################################################################################
> #
> @@ -44,10 +44,11 @@ NumBlocks = 0xED000
> # RegionType <FV, DATA, or FILE>
> #
> ################################################################################
> -0x00000000|0x000ED000
> +0x00000000|0x00100000
> gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
> FV = FVMAIN_COMPACT
>
> +!include VarStore.fdf.inc
> !include Platform/NXP/FVRules.fdf.inc
> ################################################################################
> #
> @@ -158,7 +159,15 @@ READ_STATUS = TRUE
> READ_LOCK_CAP = TRUE
> READ_LOCK_STATUS = TRUE
>
> - INF ArmPlatformPkg/PrePi/PeiUniCore.inf
> + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
> + INF MdeModulePkg/Core/Pei/PeiMain.inf
> + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
> + INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
> + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
> + INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
> + INF ArmPkg/Drivers/CpuPei/CpuPei.inf
> + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
> + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
>
> FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
> SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
> new file mode 100644
> index 0000000000..d1b9f1debb
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
> @@ -0,0 +1,46 @@
> +//
> +// Copyright (c) 2012-2013, ARM Limited. All rights reserved.
> +//
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//
> +
> +#include <AsmMacroIoLibV8.h>
> +#include <Library/ArmLib.h>
> +
> +ASM_FUNC(ArmPlatformPeiBootAction)
> + ret
> +
> +//UINTN
> +//ArmPlatformGetCorePosition (
> +// IN UINTN MpId
> +// );
> +// With this function: CorePos = (ClusterId * 4) + CoreId
> +ASM_FUNC(ArmPlatformGetCorePosition)
> + and x1, x0, #ARM_CORE_MASK
> + and x0, x0, #ARM_CLUSTER_MASK
> + add x0, x1, x0, LSR #6
> + ret
> +
> +//UINTN
> +//ArmPlatformGetPrimaryCoreMpId (
> +// VOID
> +// );
> +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
> + MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore))
> + ret
> +
> +//UINTN
> +//ArmPlatformIsPrimaryCore (
> +// IN UINTN MpId
> +// );
> +ASM_FUNC(ArmPlatformIsPrimaryCore)
> + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
> + and x0, x0, x1
> + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore))
> + cmp w0, w1
> + mov x0, #1
> + mov x1, #0
> + csel x0, x0, x1, eq
> + ret
> +
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/NxpQoriqLsHelper.S b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/NxpQoriqLsHelper.S
> deleted file mode 100644
> index dfbf73675a..0000000000
> --- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/AArch64/NxpQoriqLsHelper.S
> +++ /dev/null
> @@ -1,31 +0,0 @@
> -# @file
> -#
> -# Copyright (c) 2012-2013, ARM Limited. All rights reserved.
> -# Copyright 2017, 2020 NXP
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -
> -#include <AsmMacroIoLibV8.h>
> -#include <AutoGen.h>
> -
> -.text
> -.align 2
> -
> -GCC_ASM_IMPORT(ArmReadMpidr)
> -
> -ASM_FUNC(ArmPlatformIsPrimaryCore)
> - tst x0, #3
> - cset x0, eq
> - ret
> -
> -ASM_FUNC(ArmPlatformPeiBootAction)
> -EL1_OR_EL2(x0)
> -1:
> -2:
> - ret
> -
> -ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
> - MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore))
> - ldrh w0, [x0]
> - ret
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> index 821d413a3e..f1d67d6c7d 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> @@ -1,8 +1,4 @@
> -/** ArmPlatformLib.c
> -*
> -* Contains board initialization functions.
> -*
> -* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
> +/** @file
> *
> * Copyright (c) 2011-2012, ARM Limited. All rights reserved.
> * Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> @@ -19,19 +15,18 @@
> #include <Library/SocLib.h>
> #include <Ppi/NxpPlatformGetClock.h>
>
> -/**
> - Return the current Boot Mode
> -
> - This function returns the boot reason on the platform
> +ARM_CORE_INFO mArmPlatformMpCoreInfoTable[] = {
> + {
> + // Cluster 0, Core 0
> + 0, 0,
>
> -**/
> -EFI_BOOT_MODE
> -ArmPlatformGetBootMode (
> - VOID
> - )
> -{
> - return BOOT_WITH_FULL_CONFIGURATION;
> -}
> + // MP Core MailBox Set/Get/Clear Addresses and Clear Value
> + (EFI_PHYSICAL_ADDRESS)0,
> + (EFI_PHYSICAL_ADDRESS)0,
> + (EFI_PHYSICAL_ADDRESS)0,
> + (UINT64)0xFFFFFFFF
> + },
> +};
>
> /**
> Get the clocks supplied by Platform(Board) to NXP Layerscape SOC
> @@ -77,11 +72,29 @@ NxpPlatformGetClock(
> }
>
> /**
> - Placeholder for Platform Initialization
> + Return the current Boot Mode
> +
> + This function returns the boot reason on the platform
> +
> **/
> -EFI_STATUS
> +EFI_BOOT_MODE
> +ArmPlatformGetBootMode (
> + VOID
> + )
> +{
> + return BOOT_WITH_FULL_CONFIGURATION;
> +}
> +
> +/**
> + Initialize controllers that must setup in the normal world
> +
> + This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
> + in the PEI phase.
> +
> +**/
> +RETURN_STATUS
> ArmPlatformInitialize (
> - IN UINTN MpId
> + IN UINTN MpId
Would prefer if formating changes were left until actually needed,
and/or broken out into separate patch.
> )
> {
> SocInit ();
> @@ -89,29 +102,19 @@ ArmPlatformInitialize (
> return EFI_SUCCESS;
> }
>
> -ARM_CORE_INFO LS1043aMpCoreInfoCTA53x4[] = {
> - {
> - // Cluster 0, Core 0
> - 0x0, 0x0,
> -
> - // MP Core MailBox Set/Get/Clear Addresses and Clear Value
> - (EFI_PHYSICAL_ADDRESS)0,
> - (EFI_PHYSICAL_ADDRESS)0,
> - (EFI_PHYSICAL_ADDRESS)0,
> - (UINT64)0xFFFFFFFF
> - },
> -};
> -
> EFI_STATUS
> PrePeiCoreGetMpCoreInfo (
> OUT UINTN *CoreCount,
> OUT ARM_CORE_INFO **ArmCoreTable
> )
> {
> - *CoreCount = sizeof (LS1043aMpCoreInfoCTA53x4) / sizeof (ARM_CORE_INFO);
> - *ArmCoreTable = LS1043aMpCoreInfoCTA53x4;
> -
> - return EFI_SUCCESS;
> + if (ArmIsMpCore()) {
> + *CoreCount = sizeof (mArmPlatformMpCoreInfoTable) / sizeof (ARM_CORE_INFO);
> + *ArmCoreTable = mArmPlatformMpCoreInfoTable;
> + return EFI_SUCCESS;
> + } else {
> + return EFI_UNSUPPORTED;
> + }
> }
>
> ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
> @@ -125,6 +128,7 @@ EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
> }
> };
>
> +
Spurious blank line addition.
> VOID
> ArmPlatformGetPlatformPpiList (
> OUT UINTN *PpiListSize,
> @@ -135,11 +139,3 @@ ArmPlatformGetPlatformPpiList (
> *PpiList = gPlatformPpiTable;
> }
>
> -
> -UINTN
> -ArmPlatformGetCorePosition (
> - IN UINTN MpId
> - )
> -{
> - return 1;
> -}
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> index 8b79fd7490..beb94fba64 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> @@ -1,24 +1,24 @@
> -# @file
> -#
> +#/* @file
I don't see the point of this change? For doxygen?
If so, shouldn't it be /** ?
Regardless, it does not form part of "added PEI for", so belongs in
a different patch.
> # Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> # Copyright 2017, 2019-2020 NXP
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> +#*/
>
> [Defines]
> INF_VERSION = 0x0001001A
> - BASE_NAME = PlatformLib
> + BASE_NAME = ArmPlatformLib
This does not look like the patch this hunk belongs in.
> FILE_GUID = 736343a0-1d96-11e0-aaaa-0002a5d5c51b
> MODULE_TYPE = BASE
> VERSION_STRING = 1.0
> LIBRARY_CLASS = ArmPlatformLib
>
> [Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
Please insert packages sorted alphabetically.
> ArmPkg/ArmPkg.dec
> ArmPlatformPkg/ArmPlatformPkg.dec
> - EmbeddedPkg/EmbeddedPkg.dec
> - MdePkg/MdePkg.dec
> Silicon/NXP/NxpQoriqLs.dec
> Silicon/NXP/Chassis2/Chassis2.dec
> Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
> @@ -30,13 +30,14 @@
> DebugLib
>
> [Sources.common]
> - AArch64/NxpQoriqLsHelper.S | GCC
> + AArch64/ArmPlatformHelper.S | GCC
> ArmPlatformLibMem.c
> ArmPlatformLib.c
>
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
> + gArmTokenSpaceGuid.PcdArmPrimaryCore
> +
> [Ppis]
> gArmMpCoreInfoPpiGuid
>
> -[FixedPcd]
> - gArmTokenSpaceGuid.PcdArmPrimaryCore
> - gArmPlatformTokenSpaceGuid.PcdCoreCount
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
> index 3a72c8bdd8..822afb2188 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
> @@ -1,8 +1,4 @@
> -/** NxpQoriqLsMem.c
> -*
> -* Board memory specific Library.
> -*
> -* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c
> +/** @file
> *
> * Copyright (c) 2011, ARM Limited. All rights reserved.
> * Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> @@ -14,10 +10,11 @@
>
> #include <Library/ArmPlatformLib.h>
> #include <Library/DebugLib.h>
> -#include <Library/PcdLib.h>
> +#include <Library/HobLib.h>
Please insert include files sorted alphabetically.
> #include <Library/MemoryAllocationLib.h>
> #include <Soc.h>
>
> +// Number of Virtual Memory Map Descriptors
This is not part of "added PEI for", belongs in a different patch.
> #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
>
> /**
> @@ -25,28 +22,28 @@
>
> This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
>
> - @param VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
> - Virtual Memory mapping. This array must be ended by a zero-filled
> - entry
> + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
> + Virtual Memory mapping. This array must be ended by a zero-filled
> + entry
Nor does this improvement.
>
> **/
> -
(Or this, but at least deleted lines don't confuse git blame/praise output.)
> VOID
> ArmPlatformGetVirtualMemoryMap (
> - IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap
> + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
Not this whitespace juggling.
> )
> {
> - UINTN Index;
> - ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
> + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
> + UINT32 Index;
Nor this one.
>
> Index = 0;
>
> ASSERT (VirtualMemoryMap != NULL);
>
> - VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (
> - EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
> + VirtualMemoryTable = AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) *
> + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
>
> if (VirtualMemoryTable == NULL) {
> + DEBUG ((DEBUG_ERROR, "%a: Error: Failed AllocatePool()\n", __FUNCTION__));
> return;
> }
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc b/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
> new file mode 100644
> index 0000000000..c6cb3339d9
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
Also confused over how this file addition forms part of "added PEI...".
> @@ -0,0 +1,91 @@
> +## @file
> +# FDF include file with FD definition that defines an empty variable store.
> +#
> +# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
> +# Copyright (C) 2014, Red Hat, Inc.
> +# Copyright (c) 2016, Linaro, Ltd. All rights reserved.
> +# Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
> +# Copyright 2017-2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[FD.LS1043ARDBNV_EFI]
> +BaseAddress = 0x60500000
> +Size = 0x000C0000
> +ErasePolarity = 1
> +BlockSize = 0x1
> +NumBlocks = 0xC0000
> +
> +#
> +# Place NV Storage just above Platform Data Base
> +#
> +DEFINE NVRAM_AREA_VARIABLE_BASE = 0x00000000
> +DEFINE NVRAM_AREA_VARIABLE_SIZE = 0x00040000
> +DEFINE FTW_WORKING_BASE = $(NVRAM_AREA_VARIABLE_BASE) + $(NVRAM_AREA_VARIABLE_SIZE)
> +DEFINE FTW_WORKING_SIZE = 0x00040000
> +DEFINE FTW_SPARE_BASE = $(FTW_WORKING_BASE) + $(FTW_WORKING_SIZE)
> +DEFINE FTW_SPARE_SIZE = 0x00040000
> +
> +#############################################################################
> +# LS1043ARDB NVRAM Area
> +# LS1043ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare
> +#############################################################################
> +
> +
> +$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> +#NV_VARIABLE_STORE
> +DATA = {
> + ## This is the EFI_FIRMWARE_VOLUME_HEADER
> + # ZeroVector []
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + # FileSystemGuid: gEfiSystemNvDataFvGuid =
> + # { 0xFFF12B8D, 0x7696, 0x4C8B,
> + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
> + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
> + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
> + # FvLength: Flash Size : 0x4000000
> + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
> + # Signature "_FVH" # Attributes
> + 0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
> + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
> + 0x48, 0x00, 0x08, 0xA6, 0x00, 0x00, 0x00, 0x02,
> + # Blockmap[0]: 0x4000 Blocks * 0x1000 Bytes / Block = SIZE_64MB
> + 0x00, 0x40, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
> + # Blockmap[1]: End
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + ## This is the VARIABLE_STORE_HEADER
> + # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
> + # Signature: gEfiVariableGuid =
> + # { 0xddcf3616, 0x3275, 0x4164,
> + # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
> + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
> + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
> + # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
> + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
> + # This can speed up the Variable Dispatch a bit.
> + 0xB8, 0xFF, 0x03, 0x00,
> + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
> + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> +}
> +
> +$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> +#NV_FTW_WORKING
> +DATA = {
> + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
> + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
> + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
> + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
> + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
> + 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
> + # WriteQueueSize: UINT64
> + 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
> +}
> +
> +$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> +#NV_FTW_SPARE
> diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
> similarity index 82%
> rename from Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
> rename to Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
> index eb1983bdbc..3d04e05283 100644
> --- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
> +++ b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.c
> @@ -1,7 +1,6 @@
> /** @file
> *
> * Copyright (c) 2011-2015, ARM Limited. All rights reserved.
> -*
Why?
> * Copyright 2019-2020 NXP
> *
> * SPDX-License-Identifier: BSD-2-Clause-Patent
> @@ -10,42 +9,18 @@
>
> #include <PiPei.h>
>
> +#include <Library/ArmSmcLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
Please insert include files alphabetically sorted.
> #include <Library/ArmMmuLib.h>
> #include <Library/ArmPlatformLib.h>
> -#include <Library/BaseMemoryLib.h>
> #include <Library/DebugLib.h>
> #include <Library/HobLib.h>
> #include <Library/MemoryAllocationLib.h>
> #include <Library/PcdLib.h>
> -#include <Library/ArmSmcLib.h>
>
> #include "MemoryInitPeiLib.h"
>
> -
> -VOID
> -BuildMemoryTypeInformationHob (
> - VOID
> - );
> -
> -VOID
> -InitMmu (
> - IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable
> - )
> -{
> -
> - VOID *TranslationTableBase;
> - UINTN TranslationTableSize;
> - RETURN_STATUS Status;
> -
> - //Note: Because we called PeiServicesInstallPeiMemory() before
> - //to call InitMmu() the MMU Page Table resides in DRAM
> - //(even at the top of DRAM as it is the first permanent memory allocation)
> - Status = ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);
> - if (EFI_ERROR (Status)) {
> - DEBUG ((DEBUG_ERROR, "Error: Failed to enable MMU\n"));
> - }
> -}
> -
> STATIC
> UINTN
> CalculateReservedMemBase (
> @@ -62,7 +37,7 @@ CalculateReservedMemBase (
> UINTN ReservedBaseAddress;
> INTN Index2;
>
> - ReservedMemAlignment = FixedPcdGet64 (PcdReservedMemAlignment);
> + ReservedMemAlignment = PcdGet64 (PcdReservedMemAlignment);
> //
> // Compute alignment bit mask
> //
> @@ -125,56 +100,26 @@ CalculateReservedMemBase (
> }
> }
>
> -/*++
> -
> -Routine Description:
> -
> -
> -
> -Arguments:
> -
> - FileHandle - Handle of the file being invoked.
> - PeiServices - Describes the list of possible PEI Services.
> -
> -Returns:
> -
> - Status - EFI_SUCCESS if the boot mode could be set
> -
> ---*/
> -EFI_STATUS
> +RETURN_STATUS
> EFIAPI
> -MemoryPeim (
> - IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
> - IN UINT64 UefiMemorySize
> +MemoryInitPeiLibConstructor (
> + VOID
> )
> {
> - ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
> - ARM_SMC_ARGS ArmSmcArgs;
> - INT32 Index;
> - UINTN DramSize;
> - UINTN BaseAddress;
> - UINTN Size;
> - UINTN Top;
> + ARM_SMC_ARGS ArmSmcArgs;
> + INT32 Index;
> + UINTN DramSize;
> + UINTN BaseAddress;
> + UINTN Size;
> + UINTN Top;
This block indentation change looks fairly superfluous.
> // Extra region gets created if we want to reserve a memory region and that creates a memory hole
> // because of alignement requirements
> - DRAM_REGION_INFO DramRegions[MAX_DRAM_REGIONS + 1];
> - EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
> - UINTN FdBase;
> - UINTN FdTop;
> - BOOLEAN FoundSystemMem;
> -
> - // Get Virtual Memory Map from the Platform Library
> - ArmPlatformGetVirtualMemoryMap (&MemoryTable);
> -
> - //
> - // Ensure MemoryTable[0].Length which is size of DRAM has been set
> - // by ArmPlatformGetVirtualMemoryMap ()
> - //
> - ASSERT (MemoryTable[0].Length != 0);
> + DRAM_REGION_INFO DramRegions[MAX_DRAM_REGIONS + 1];
> + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
> + UINTN FdBase;
> + UINTN FdTop;
> + BOOLEAN FoundSystemMem;
As does this block indentation change, which really messes with patch clarity.
>
> - //
> - // Now, the permanent memory has been installed, we can call AllocatePages()
> - //
> ResourceAttributes = (
> EFI_RESOURCE_ATTRIBUTE_PRESENT |
> EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> @@ -214,16 +159,17 @@ MemoryPeim (
> ASSERT (!DramSize);
>
> // Get the reserved memory size from non volatile storage
> - Size = FixedPcdGet64 (PcdReservedMemSize);
> + Size = PcdGet64 (PcdReservedMemSize);
> if (Size) {
> BaseAddress = CalculateReservedMemBase (DramRegions, Index, Size);
> if (BaseAddress) {
> DEBUG ((DEBUG_INFO, "ReservedMem: start 0x%lx, size 0x%lx\n", BaseAddress, Size));
> + PcdSet64S (PcdReservedMemBase, BaseAddress);
> }
> }
>
> - FdBase = (UINTN)FixedPcdGet64 (PcdFdBaseAddress);
> - FdTop = FdBase + (UINTN)FixedPcdGet32 (PcdFdSize);
> + FdBase = (UINTN)PcdGet64 (PcdFdBaseAddress);
> + FdTop = FdBase + (UINTN)PcdGet32 (PcdFdSize);
>
> // Declare memory regios to system
> for (Index = MAX_DRAM_REGIONS; Index >= 0; Index--) {
> @@ -266,8 +212,8 @@ MemoryPeim (
> );
> };
> // Mark the memory covering the Firmware Device as boot services data
> - BuildMemoryAllocationHob (FixedPcdGet64 (PcdFdBaseAddress),
> - FixedPcdGet32 (PcdFdSize),
> + BuildMemoryAllocationHob (PcdGet64 (PcdFdBaseAddress),
> + PcdGet32 (PcdFdSize),
> EfiBootServicesData);
> }else {
> BuildResourceDescriptorHob (
> @@ -287,16 +233,72 @@ MemoryPeim (
> Top = DramRegions[Index].BaseAddress + DramRegions[Index].Size;
>
> if (FdBase >= BaseAddress && FdTop <= Top) {
> - Size -= (UINTN)FixedPcdGet32 (PcdFdSize);
> + Size -= (UINTN)PcdGet32 (PcdFdSize);
> }
>
> if (Size >= FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)) {
> FoundSystemMem = TRUE;
> + PcdSet64S (PcdSystemMemoryBase, BaseAddress);
> + PcdSet64S (PcdSystemMemorySize, Size);
> }
> }
>
> ASSERT (FoundSystemMem);
>
> + return EFI_SUCCESS;
> +}
> +
> +VOID
> +BuildMemoryTypeInformationHob (
> + VOID
> + );
> +
Why has this prototype moved down here?
> +STATIC
> +VOID
> +InitMmu (
And this whole function definition?
> + IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable
> + )
> +{
> + VOID *TranslationTableBase;
> + UINTN TranslationTableSize;
> + RETURN_STATUS Status;
> +
> + //Note: Because we called PeiServicesInstallPeiMemory() before to call InitMmu() the MMU Page Table resides in
> + // DRAM (even at the top of DRAM as it is the first permanent memory allocation)
> + Status = ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "Error: Failed to enable MMU\n"));
> + }
> +}
> +
> +/*++
> +
> +Routine Description:
> +
> +
> +
> +Arguments:
> +
> + FileHandle - Handle of the file being invoked.
> + PeiServices - Describes the list of possible PEI Services.
> +
> +Returns:
> +
> + Status - EFI_SUCCESS if the boot mode could be set
> +
> +--*/
> +EFI_STATUS
> +EFIAPI
> +MemoryPeim (
> + IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
> + IN UINT64 UefiMemorySize
> + )
> +{
> + ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
> +
> + // Get Virtual Memory Map from the Platform Library
> + ArmPlatformGetVirtualMemoryMap (&MemoryTable);
> +
> // Build Memory Allocation Hob
> InitMmu (MemoryTable);
>
> diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.h
> similarity index 94%
> rename from Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
> rename to Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.h
> index e563b2ba8d..c3c42ed8a3 100644
> --- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.h
> +++ b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.h
> @@ -21,4 +21,3 @@ typedef struct {
> } DRAM_REGION_INFO;
>
> #endif
> -
Does not belong in this patch.
> diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
> similarity index 80%
> rename from Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
> rename to Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
> index 9adddcaf8c..4d932444a3 100644
> --- a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
> +++ b/Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
> @@ -8,32 +8,32 @@
> #**/
>
> [Defines]
> - INF_VERSION = 0x0001001A
> + INF_VERSION = 0x00010005
No.
> BASE_NAME = ArmMemoryInitPeiLib
> FILE_GUID = 55ddb6e0-70b5-11e0-b33e-0002a5d5c51b
> MODULE_TYPE = BASE
> VERSION_STRING = 1.0
> - LIBRARY_CLASS = MemoryInitPeiLib|SEC PEIM DXE_DRIVER
> + LIBRARY_CLASS = MemoryInitPeiLib|PEIM
> + CONSTRUCTOR = MemoryInitPeiLibConstructor
>
> [Sources]
> MemoryInitPeiLib.c
>
> -
> [Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + EmbeddedPkg/EmbeddedPkg.dec
Please insert packages sorted alphabetically.
> ArmPkg/ArmPkg.dec
> ArmPlatformPkg/ArmPlatformPkg.dec
> - EmbeddedPkg/EmbeddedPkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - MdePkg/MdePkg.dec
> Silicon/NXP/NxpQoriqLs.dec
>
> [LibraryClasses]
> - ArmMmuLib
> - ArmPlatformLib
> DebugLib
> HobLib
> - PcdLib
> + ArmMmuLib
> + ArmPlatformLib
Please insert library classes sorted alphabetically.
> ArmSmcLib
> + PcdLib
>
> [Guids]
> gEfiMemoryTypeInformationGuid
> @@ -44,13 +44,15 @@
> [FixedPcd]
> gArmTokenSpaceGuid.PcdFdBaseAddress
> gArmTokenSpaceGuid.PcdFdSize
> +
Why?
> gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize
> - gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize
> - gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment
>
> [Pcd]
> gArmTokenSpaceGuid.PcdSystemMemoryBase
> gArmTokenSpaceGuid.PcdSystemMemorySize
> + gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize
> + gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment
> + gNxpQoriqLsTokenSpaceGuid.PcdReservedMemBase
Please insert alphabetically sorted.
>
> [Depex]
> TRUE
> diff --git a/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c
> new file mode 100644
> index 0000000000..f64e564469
> --- /dev/null
> +++ b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.c
> @@ -0,0 +1,30 @@
> +/** @file
> +*
> +* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
> +* Copyright 2020 NXP
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#include <PiPei.h>
> +
> +#include <Library/HobLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
> +
> +#define XPRINT(x) PRINT(x)
> +#define PRINT(x) #x
?
> +
> +EFI_STATUS
> +EFIAPI
> +PlatformPeim (
> + VOID
> + )
> +{
> + BuildFvHob (PcdGet64 (PcdFvBaseAddress), PcdGet32 (PcdFvSize));
> + DEBUG ((DEBUG_INIT, "Edk2 version is %a\n", XPRINT (WORKSPACE_GIT_VERSION)));
> + DEBUG ((DEBUG_INIT, "Edk2 platforms version is %a\n", XPRINT (PACKAGES_PATH_GIT_VERSION)));
I am confused - what information are these trying to provide?
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
> new file mode 100644
> index 0000000000..b0481dece0
> --- /dev/null
> +++ b/Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
> @@ -0,0 +1,50 @@
> +#/** @file
> +#
> +# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
> +# Copyright 2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#**/
> +
> +[Defines]
> + INF_VERSION = 0x00010005
Please bump version.
> + BASE_NAME = ArmPlatformPeiLib
> + FILE_GUID = 49d37060-70b5-11e0-aa2d-0002a5d5c51b
GUIDs are supposed to be globally unique.
You can generate new ones from (for example)
https://www.guidgenerator.com/online-guid-generator.aspx
.
> + MODULE_TYPE = PEIM
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = PlatformPeiLib
> +
> +[BuildOptions]
> + GCC:*_*_*_CC_FLAGS = -DWORKSPACE_GIT_VERSION="$(WORKSPACE_GIT_VERSION)"
> + GCC:*_*_*_CC_FLAGS = -DPACKAGES_PATH_GIT_VERSION="$(PACKAGES_PATH_GIT_VERSION)"
> +
> +[Sources]
> + PlatformPeiLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + EmbeddedPkg/EmbeddedPkg.dec
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
Please insert packages sorted alphabetically.
> +
> +[LibraryClasses]
> + DebugLib
> + HobLib
> + PcdLib
> +
> +[Ppis]
> + gEfiPeiMasterBootModePpiGuid # PPI ALWAYS_PRODUCED
> + gEfiPeiBootInRecoveryModePpiGuid # PPI SOMETIMES_PRODUCED
Please insert Ppis sorted alphabetically.
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdFdBaseAddress
> + gArmTokenSpaceGuid.PcdFdSize
> +
> + gArmTokenSpaceGuid.PcdFvBaseAddress
> + gArmTokenSpaceGuid.PcdFvSize
> +
> +[depex]
> + TRUE
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index c327e738cc..0a90334c02 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -27,21 +27,12 @@
> gNxpQoriqLsTokenSpaceGuid = {0x98657342, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
> gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
>
> -[PcdsFixedAtBuild.common]
> - #
> - # Platform PCDs
> - #
> - gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
> -
> - #
> - # Pcds to support Big Endian IPs
> - #
> - gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311
> -
> - gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize|0x0|UINT64|0x00000315
> - gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment|0x0|UINT64|0x00000316
> +[PcdsDynamic,PcdsPatchableInModule]
> + gNxpQoriqLsTokenSpaceGuid.PcdReservedMemBase|0x0|UINT64|0x00000001
> + gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize|0x0|UINT64|0x00000002
> + gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment|0x0|UINT64|0x00000003
>
> [PcdsFeatureFlag]
> - gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000317
> - gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000318
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x00000004
> + gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian|FALSE|BOOLEAN|0x00000005
This reassigning of tokens should happen in a separate patch.
/
Leif
>
> diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
> index 94d3e53a04..9922686304 100644
> --- a/Silicon/NXP/NxpQoriqLs.dsc.inc
> +++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
> @@ -93,29 +93,35 @@
> CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
> NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
> ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
> + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
>
> I2cLib|Silicon/NXP/Library/I2cLib/I2cLib.inf
> ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
> IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
> + PlatformPeiLib|Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
> + MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
>
> [LibraryClasses.common.SEC]
> PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> - UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
> - ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
> - LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
> - PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> - HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
> - PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
> - MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
> - PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
> - PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
> - MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
>
> - # 1/123 faster than Stm or Vstm version
> - BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> + DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
> + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
> + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
> + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
> + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
> +
> +[LibraryClasses.common.PEI_CORE]
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
> + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
> + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
> + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
> + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
> + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
> + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
> + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
>
> - # Uncomment to turn on GDB stub in SEC.
> - #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
> + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
>
> [LibraryClasses.common.PEIM]
> PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> @@ -124,14 +130,16 @@
> PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
> HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
> MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
> + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
> + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
> ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
> + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
>
> [LibraryClasses.common.DXE_CORE]
> HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
> MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
> DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
> ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
> - UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
> DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
>
> @@ -139,7 +147,6 @@
> DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
> PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
> - MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
>
> [LibraryClasses.common.UEFI_APPLICATION]
> PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> @@ -204,6 +211,10 @@
> gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
> gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480
>
> + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x0
> + gArmTokenSpaceGuid.PcdSystemMemorySize|0x0
> + gNxpQoriqLsTokenSpaceGuid.PcdReservedMemBase|0x0
> +
> [PcdsDynamicHii.common.DEFAULT]
> gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10
>
> @@ -214,7 +225,6 @@
> gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800
> gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
> gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
> - gArmPlatformTokenSpaceGuid.PcdCoreCount|1 # Only one core
> gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
> gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|2000000
> gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
> @@ -224,6 +234,12 @@
> gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
> gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
>
> + ## Base of DRAM
> + ## since TFA puts Fd at 0x2000000 offset from DRAM base, we can use this space
> + ## for temporary ram
> + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x80000000
> + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
> +
> !if $(TARGET) == RELEASE
> gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
> gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000001
> @@ -281,13 +297,26 @@
> ################################################################################
> [Components.common]
> #
> - # SEC
> + # PEI Phase modules
> #
> - ArmPlatformPkg/PrePi/PeiUniCore.inf
> + ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
> +
> + MdeModulePkg/Core/Pei/PeiMain.inf
> MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
> <LibraryClasses>
> PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> }
> + MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
> + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
> +
> + ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
> + ArmPkg/Drivers/CpuPei/CpuPei.inf
> + ArmPlatformPkg/PlatformPei/PlatformPeim.inf
> +
> + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
> + <LibraryClasses>
> + NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
> + }
>
> #
> # DXE
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 16/19] Silicon/NXP: Add Pl011 Serial port lib
2020-02-07 12:43 ` [PATCH 16/19] Silicon/NXP: Add Pl011 Serial port lib Pankaj Bansal
@ 2020-02-12 20:26 ` Leif Lindholm
0 siblings, 0 replies; 49+ messages in thread
From: Leif Lindholm @ 2020-02-12 20:26 UTC (permalink / raw)
To: Pankaj Bansal; +Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi, devel
On Fri, Feb 07, 2020 at 18:13:25 +0530, Pankaj Bansal wrote:
> Use ArmPlatformPkg/PL011SerialPortLib with some changes:
> 1. add Get clock API to get the UART clock from ArmPlatformLib
> 2. remove SerialPortInitalize functionality
>
> This is same as being done in Silicon/NXP/Library/BaseSerialPortLib16550.
And just like for that one, any functionality changes need to be
introduced conditionally in the original - if there is no other way to
achieve the same effect.
/
Leif
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> .../PL011SerialPortLib/PL011SerialPortLib.c | 229 ++++++++++++++++++
> .../PL011SerialPortLib/PL011SerialPortLib.inf | 42 ++++
> Silicon/NXP/NxpQoriqLs.dsc.inc | 1 +
> 3 files changed, 272 insertions(+)
> create mode 100644 Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.c
> create mode 100644 Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.inf
>
> diff --git a/Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.c b/Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.c
> new file mode 100644
> index 0000000000..35cfe8e324
> --- /dev/null
> +++ b/Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.c
> @@ -0,0 +1,229 @@
> +/** @file
> + Serial I/O Port library functions with no library constructor/destructor
> +
> + Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
> + Copyright (c) 2012 - 2016, ARM Ltd. All rights reserved.<BR>
> + Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
> + Copyright 2020 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Base.h>
> +
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PL011UartClockLib.h>
> +#include <Library/PL011UartLib.h>
> +#include <Library/SerialPortLib.h>
> +#include <Ppi/NxpPlatformGetClock.h>
> +
> +extern NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi;
> +
> +/** Initialise the serial device hardware with default settings.
> +
> + @retval RETURN_SUCCESS The serial device was initialised.
> + @retval RETURN_INVALID_PARAMETER One or more of the default settings
> + has an unsupported value.
> + **/
> +RETURN_STATUS
> +EFIAPI
> +SerialPortInitialize (
> + VOID
> + )
> +{
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Write data to serial device.
> +
> + @param Buffer Point of data buffer which need to be written.
> + @param NumberOfBytes Number of output bytes which are cached in Buffer.
> +
> + @retval 0 Write data failed.
> + @retval !0 Actual number of bytes written to serial device.
> +
> +**/
> +UINTN
> +EFIAPI
> +SerialPortWrite (
> + IN UINT8 *Buffer,
> + IN UINTN NumberOfBytes
> + )
> +{
> + return PL011UartWrite ((UINTN)PcdGet64 (PcdSerialRegisterBase), Buffer, NumberOfBytes);
> +}
> +
> +/**
> + Read data from serial device and save the data in buffer.
> +
> + @param Buffer Point of data buffer which need to be written.
> + @param NumberOfBytes Number of output bytes which are cached in Buffer.
> +
> + @retval 0 Read data failed.
> + @retval !0 Actual number of bytes read from serial device.
> +
> +**/
> +UINTN
> +EFIAPI
> +SerialPortRead (
> + OUT UINT8 *Buffer,
> + IN UINTN NumberOfBytes
> +)
> +{
> + return PL011UartRead ((UINTN)PcdGet64 (PcdSerialRegisterBase), Buffer, NumberOfBytes);
> +}
> +
> +/**
> + Check to see if any data is available to be read from the debug device.
> +
> + @retval TRUE At least one byte of data is available to be read
> + @retval FALSE No data is available to be read
> +
> +**/
> +BOOLEAN
> +EFIAPI
> +SerialPortPoll (
> + VOID
> + )
> +{
> + return PL011UartPoll ((UINTN)PcdGet64 (PcdSerialRegisterBase));
> +}
> +/**
> + Set new attributes to PL011.
> +
> + @param BaudRate The baud rate of the serial device. If the
> + baud rate is not supported, the speed will
> + be reduced down to the nearest supported one
> + and the variable's value will be updated
> + accordingly.
> + @param ReceiveFifoDepth The number of characters the device will
> + buffer on input. If the specified value is
> + not supported, the variable's value will
> + be reduced down to the nearest supported one.
> + @param Timeout If applicable, the number of microseconds the
> + device will wait before timing out a Read or
> + a Write operation.
> + @param Parity If applicable, this is the EFI_PARITY_TYPE
> + that is computed or checked as each character
> + is transmitted or received. If the device
> + does not support parity, the value is the
> + default parity value.
> + @param DataBits The number of data bits in each character
> + @param StopBits If applicable, the EFI_STOP_BITS_TYPE number
> + of stop bits per character. If the device
> + does not support stop bits, the value is the
> + default stop bit value.
> +
> + @retval EFI_SUCCESS All attributes were set correctly.
> + @retval EFI_INVALID_PARAMETERS One or more attributes has an unsupported
> + value.
> + @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +SerialPortSetAttributes (
> + IN OUT UINT64 *BaudRate,
> + IN OUT UINT32 *ReceiveFifoDepth,
> + IN OUT UINT32 *Timeout,
> + IN OUT EFI_PARITY_TYPE *Parity,
> + IN OUT UINT8 *DataBits,
> + IN OUT EFI_STOP_BITS_TYPE *StopBits
> + )
> +{
> + UINT64 SerialClock;
> +
> + SerialClock = mPlatformGetClockPpi.PlatformGetClock (NXP_UART_CLOCK, 0);
> + if (SerialClock == 0) {
> + return EFI_DEVICE_ERROR;
> + }
> +
> + return PL011UartInitializePort (
> + (UINTN)PcdGet64 (PcdSerialRegisterBase),
> + SerialClock,
> + BaudRate,
> + ReceiveFifoDepth,
> + Parity,
> + DataBits,
> + StopBits
> + );
> +}
> +
> +/**
> +
> + Assert or deassert the control signals on a serial port.
> + The following control signals are set according their bit settings :
> + . Request to Send
> + . Data Terminal Ready
> +
> + @param[in] Control The following bits are taken into account :
> + . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the
> + "Request To Send" control signal if this bit is
> + equal to one/zero.
> + . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert
> + the "Data Terminal Ready" control signal if this
> + bit is equal to one/zero.
> + . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable
> + the hardware loopback if this bit is equal to
> + one/zero.
> + . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.
> + . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/
> + disable the hardware flow control based on CTS (Clear
> + To Send) and RTS (Ready To Send) control signals.
> +
> + @retval RETURN_SUCCESS The new control bits were set on the device.
> + @retval RETURN_UNSUPPORTED The device does not support this operation.
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +SerialPortSetControl (
> + IN UINT32 Control
> + )
> +{
> + return PL011UartSetControl ((UINTN)PcdGet64 (PcdSerialRegisterBase), Control);
> +}
> +
> +/**
> +
> + Retrieve the status of the control bits on a serial device.
> +
> + @param[out] Control Status of the control bits on a serial device :
> +
> + . EFI_SERIAL_DATA_CLEAR_TO_SEND,
> + EFI_SERIAL_DATA_SET_READY,
> + EFI_SERIAL_RING_INDICATE,
> + EFI_SERIAL_CARRIER_DETECT,
> + EFI_SERIAL_REQUEST_TO_SEND,
> + EFI_SERIAL_DATA_TERMINAL_READY
> + are all related to the DTE (Data Terminal Equipment)
> + and DCE (Data Communication Equipment) modes of
> + operation of the serial device.
> + . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the
> + receive buffer is empty, 0 otherwise.
> + . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the
> + transmit buffer is empty, 0 otherwise.
> + . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if
> + the hardware loopback is enabled (the output feeds
> + the receive buffer), 0 otherwise.
> + . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one
> + if a loopback is accomplished by software, else 0.
> + . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to
> + one if the hardware flow control based on CTS (Clear
> + To Send) and RTS (Ready To Send) control signals is
> + enabled, 0 otherwise.
> +
> + @retval RETURN_SUCCESS The control bits were read from the device.
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +SerialPortGetControl (
> + OUT UINT32 *Control
> + )
> +{
> + return PL011UartGetControl ((UINTN)PcdGet64 (PcdSerialRegisterBase), Control);
> +}
> diff --git a/Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.inf b/Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.inf
> new file mode 100644
> index 0000000000..29f234027f
> --- /dev/null
> +++ b/Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.inf
> @@ -0,0 +1,42 @@
> +#/** @file
> +#
> +# Component description file for PL011SerialPortLib module
> +#
> +# Copyright (c) 2011-2016, ARM Ltd. All rights reserved.<BR>
> +# Copyright 2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#**/
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = PL011SerialPortLib
> + FILE_GUID = 8ecefc8f-a2c4-4091-b80f-20f7aeb0567f
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = SerialPortLib
> +
> +[Sources.common]
> + PL011SerialPortLib.c
> +
> +[LibraryClasses]
> + PL011UartLib
> + PcdLib
> + ArmPlatformLib
> +
> +[Packages]
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[Pcd]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
> +
> +[FixedPcd]
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
> diff --git a/Silicon/NXP/NxpQoriqLs.dsc.inc b/Silicon/NXP/NxpQoriqLs.dsc.inc
> index 9922686304..2ab6ee1920 100644
> --- a/Silicon/NXP/NxpQoriqLs.dsc.inc
> +++ b/Silicon/NXP/NxpQoriqLs.dsc.inc
> @@ -100,6 +100,7 @@
> IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
> PlatformPeiLib|Silicon/NXP/Library/PlatformPeiLib/PlatformPeiLib.inf
> MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf
> + PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf
>
> [LibraryClasses.common.SEC]
> PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 17/19] Silicon/NXP: Add Chassis3V2
2020-02-07 12:43 ` [PATCH 17/19] Silicon/NXP: Add Chassis3V2 Pankaj Bansal
@ 2020-02-12 20:33 ` Leif Lindholm
0 siblings, 0 replies; 49+ messages in thread
From: Leif Lindholm @ 2020-02-12 20:33 UTC (permalink / raw)
To: Pankaj Bansal; +Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi, devel
On Fri, Feb 07, 2020 at 18:13:26 +0530, Pankaj Bansal wrote:
> Add Chassis3V2
Insufficient as a commit message.
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> Silicon/NXP/Chassis3V2/Chassis3V2.dec | 23 +++
> Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc | 10 +
> Silicon/NXP/Chassis3V2/Include/Chassis.h | 42 ++++
> .../Library/ChassisLib/ChassisLib.c | 186 ++++++++++++++++++
> .../Library/ChassisLib/ChassisLib.inf | 41 ++++
> 5 files changed, 302 insertions(+)
> create mode 100644 Silicon/NXP/Chassis3V2/Chassis3V2.dec
> create mode 100644 Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
> create mode 100644 Silicon/NXP/Chassis3V2/Include/Chassis.h
> create mode 100644 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
> create mode 100644 Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
>
> diff --git a/Silicon/NXP/Chassis3V2/Chassis3V2.dec b/Silicon/NXP/Chassis3V2/Chassis3V2.dec
> new file mode 100644
> index 0000000000..106b118188
> --- /dev/null
> +++ b/Silicon/NXP/Chassis3V2/Chassis3V2.dec
> @@ -0,0 +1,23 @@
> +#/** @file
> +# NXP Layerscape processor package.
> +#
> +# Copyright 2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#**/
> +
> +[Defines]
> + DEC_SPECIFICATION = 1.27
> + PACKAGE_VERSION = 0.1
> +
> +################################################################################
> +#
> +# Include Section - list of Include Paths that are provided by this package.
> +# Comments are used for Keywords and Module Types.
> +#
> +#
> +################################################################################
> +[Includes.common]
> + Include # Root include for the package
> +
Skip the blank line at EOF.
> diff --git a/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc b/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
> new file mode 100644
> index 0000000000..dabe2ae230
> --- /dev/null
> +++ b/Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
> @@ -0,0 +1,10 @@
> +# @file
> +#
> +# Copyright 2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +
> +[LibraryClasses.common]
> + ChassisLib|Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
> diff --git a/Silicon/NXP/Chassis3V2/Include/Chassis.h b/Silicon/NXP/Chassis3V2/Include/Chassis.h
> new file mode 100644
> index 0000000000..2771f26fe3
> --- /dev/null
> +++ b/Silicon/NXP/Chassis3V2/Include/Chassis.h
> @@ -0,0 +1,42 @@
> +/** @file
> +
> + Copyright 2020 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +#ifndef __CHASSIS_H__
> +#define __CHASSIS_H__
Please drop leading __ from include guards.
> +
> +#define NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS 0x1E00000
> +
> +#define TP_CLUSTER_ITYPE_IDX 0x3f
> +#define TP_CLUSTER_EOC BIT31
> +#define TP_ITYPE_AVAILABLE BIT0
> +#define TP_ITYPE_TYPE(x) (((x) & 0x06) >> 1)
> +#define TP_ITYPE_ARM 0x0
> +#define TP_ITYPE_VERSION(x) (((x) & 0xe0) >> 5)
> +
> +#define TP_ITYPE_VERSION_A53 0x2
> +#define TP_ITYPE_VERSION_A72 0x4
> +
> +/**
> + The Device Configuration Unit provides general purpose configuration and status for the
> + device. These registers only support 32-bit accesses.
> +**/
> +#pragma pack(1)
> +typedef struct {
> + UINT8 Reserved0[0x100 - 0x0];
> + UINT32 RcwSr[32]; // Reset Control Word Status Register
> + UINT8 Reserved180[0x200 - 0x180];
> + UINT32 ScratchRw[16]; /// Scratch Read / Write Register
> + UINT8 Reserved240[0x740-0x240];
> + UINT32 TpItyp[65]; /// Topology Initiator Type Register
> + struct {
> + UINT32 Lower;
> + UINT32 Upper;
> + }TpCluster[8];
> +} NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG;
> +#pragma pack()
> +
> +#endif
> diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
> new file mode 100644
> index 0000000000..99567bb76f
> --- /dev/null
> +++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.c
> @@ -0,0 +1,186 @@
> +/** @file
> + Chassis specific functions common to all SOCs based on a specific Chessis
> +
> + Copyright 2020 NXP
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Chassis.h>
> +#include <Uefi.h>
> +#include <Library/IoLib.h>
> +#include <Library/IoAccessLib.h>
Please flip above two lines, which will order the include files alphabetically.
> +#include <Library/PcdLib.h>
> +#include <Library/SerialPortLib.h>
> +#include <Ppi/ArmMpCoreInfo.h>
> +
> +UINT32
> +EFIAPI
> +DcfgRead32 (
> + IN UINTN Address
> + )
> +{
> + if (FeaturePcdGet (PcdDcfgBigEndian)) {
> + return SwapMmioRead32 (Address);
Same as for previous patches, please rewrite to use GetMmioOperations*.
> + } else {
> + return MmioRead32 (Address);
> + }
> +}
> +
> +UINT32
> +EFIAPI
> +DcfgWrite32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + )
> +{
> + if (FeaturePcdGet (PcdDcfgBigEndian)) {
> + return SwapMmioWrite32 (Address, Value);
> + } else {
> + return MmioWrite32 (Address, Value);
> + }
> +}
> +
> +/**
> + Get the type of core in cluster
> +
> + The core can be of type ARM or PowerPC or Hardware Accelerator.
> + If the core is enabled and of type ARM EFI_SUCCESS is returned and a code for type of ARM core is returned
Please wrap long lines, throughout.
> +
> + @param[in] TpItypeIdx Index of Core to be searched in TpItyp in Device Config Registers.
> + @param[out] CoreType If the core is ARM core then the type of core i.e. A53/A72 etc.
> + These cores are identified based on their codes like TP_ITYPE_VERSION_A72
> +
> + @return EFI_NOT_FOUND No enabled ARM core found
> + @return EFI_SUCCESS An enabled ARM core found
> +**/
> +STATIC
> +EFI_STATUS
> +SocGetCoreType (
> + IN UINT8 TpItypeIdx,
> + OUT UINT8 *CoreType
> + )
> +{
> + NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG *Dcfg;
> + UINT32 TpItype;
Same comment about TpItype as for previous chassis library.
> +
> + Dcfg = (NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG *)NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS;
> + TpItype = MmioRead32 ((UINTN)&Dcfg->TpItyp[TpItypeIdx]);
> + if (TpItype & TP_ITYPE_AVAILABLE) {
> + if (TP_ITYPE_TYPE (TpItype) == TP_ITYPE_ARM) {
> + *CoreType = TP_ITYPE_VERSION (TpItype);
> + } else {
> + return EFI_NOT_FOUND;
> + }
> + } else {
> + return EFI_NOT_FOUND;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Return the number of cores present in SOC
> +
> + This function returns the number of cores present in SOC.
> + and also their position (cluster number and core number) in the form of ARM_CORE_INFO array
> + and NxpCoreTable array.
> + NxpCoreTable array can be used to find out the type of core. it's values are of type
> + TP_ITYPE_VERSION_*.
> + The number of cores present in SOC can vary depending on which flavour of SOC is being used.
> + This function doesn't allocte any memory and must be provided memory for array of ARM_CORE_INFO
> + and NxpCoreTable for maximum number of cores the SOC can have.
> +
> + @param[out] NxpCoreTable array of UINT8 for maximum number of cores the SOC can have.
> + @param[out] ArmCoreTable array of ARM_CORE_INFO for maximum number of cores the SOC can have.
> + @param[in] ArmCoreTableSize Size of ArmCoreTable
> +
> + @return Actual number of cores present in SOC. After calling this function only the returned
> + value number of entries in ArmCoreTable are valid entries.
> +**/
> +UINTN
> +__attribute__((weak))
Same question about weak symbol linkage as for previous chassis library.
> +SocGetMpCoreInfo (
> + OUT UINT8 *NxpCoreTable,
> + OUT ARM_CORE_INFO *ArmCoreTable,
> + IN UINTN CoreTableSize
> + )
> +{
> + NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG *Dcfg;
> + UINT32 TpClusterLower;
> + UINT8 TpClusterParser;
Same ClusterLower/ClusterParser comments as for previous chassis library.
> + UINT8 ClusterIndex;
> + UINT8 CoreIndex;
> + UINTN CoreCount;
> + UINT8 CoreType;
> + EFI_STATUS Status;
> +
> + Dcfg = (NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG *)NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS;
> + ClusterIndex = 0;
> + CoreCount = 0;
> + while (TRUE) {
> + TpClusterLower = MmioRead32 ((UINTN)&Dcfg->TpCluster[ClusterIndex].Lower);
> + for (CoreIndex = 0; CoreIndex < (sizeof (TpClusterLower) / sizeof (TpClusterParser)); CoreIndex++) {
And here.
> + TpClusterParser = (TpClusterLower >> (8 * CoreIndex));
And here.
> + Status = SocGetCoreType (TpClusterParser & TP_CLUSTER_ITYPE_IDX, &CoreType);
> + if (Status != EFI_NOT_FOUND) {
> + ArmCoreTable[CoreCount].ClusterId = ClusterIndex;
> + ArmCoreTable[CoreCount].CoreId = CoreIndex;
> + ArmCoreTable[CoreCount].MailboxSetAddress = 0;
> + ArmCoreTable[CoreCount].MailboxGetAddress = 0;
> + ArmCoreTable[CoreCount].MailboxClearAddress = 0;
> + ArmCoreTable[CoreCount].MailboxClearValue = ~0;
> +
> + NxpCoreTable[CoreCount] = CoreType;
> + CoreCount++;
> + if (CoreCount == CoreTableSize) {
> + break;
> + }
> + }
> + }
> + if (TpClusterLower & TP_CLUSTER_EOC) {
> + break;
> + }
> + if (CoreCount == CoreTableSize) {
> + break;
> + }
> + ClusterIndex++;
> + }
> +
> + return CoreCount;
> +}
> +
> +/**
> + Function to initialize Chassis Specific functions
> + **/
> +VOID
> +ChassisInit (
> + VOID
> + )
> +{
> + UINT64 BaudRate;
> + UINT32 ReceiveFifoDepth;
> + EFI_PARITY_TYPE Parity;
> + UINT8 DataBits;
> + EFI_STOP_BITS_TYPE StopBits;
> + UINT32 Timeout;
> +
> + BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
> + ReceiveFifoDepth = FixedPcdGet16 (PcdUartDefaultReceiveFifoDepth);
> + Timeout = 0;
> + Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
> + DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
> + StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);
> +
> + //
> + // Early init serial Port to get board information.
> + //
> + SerialPortSetAttributes (
> + &BaudRate,
> + &ReceiveFifoDepth,
> + &Timeout,
> + &Parity,
> + &DataBits,
> + &StopBits
> + );
> +}
> diff --git a/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
> new file mode 100644
> index 0000000000..302296bf65
> --- /dev/null
> +++ b/Silicon/NXP/Chassis3V2/Library/ChassisLib/ChassisLib.inf
> @@ -0,0 +1,41 @@
> +#/** @file
> +#
> +# Copyright 2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause
> +#
> +#**/
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = Chassis3V2Lib
> + FILE_GUID = fae0d077-5fc2-494f-b8e1-c51a3023ee3e
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = ChassisLib
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + ArmPkg/ArmPkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> + Silicon/NXP/Chassis3V2/Chassis3V2.dec
Please sort packages alphabetically.
> +
> +[LibraryClasses]
> + IoLib
> + IoAccessLib
Please flip above two lines.
/
Leif
> + PcdLib
> + SerialPortLib
> +
> +[Sources.common]
> + ChassisLib.c
> +
> +[FeaturePcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian
> +
> +[FixedPcd]
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth
> +
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 19/19] Platform/NXP: Add LX2160ARDBPKG
2020-02-07 12:43 ` [PATCH 19/19] Platform/NXP: Add LX2160ARDBPKG Pankaj Bansal
@ 2020-02-12 21:36 ` Leif Lindholm
0 siblings, 0 replies; 49+ messages in thread
From: Leif Lindholm @ 2020-02-12 21:36 UTC (permalink / raw)
To: Pankaj Bansal; +Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi, devel
On Fri, Feb 07, 2020 at 18:13:28 +0530, Pankaj Bansal wrote:
> Add LX2160ARDBPKG
>
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> Platform/NXP/Include/Qixis.h | 40 ++++
> Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec | 23 +++
> Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc | 54 ++++++
> Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf | 172 ++++++++++++++++++
> .../AArch64/ArmPlatformHelper.S | 46 +++++
> .../Library/ArmPlatformLib/ArmPlatformLib.c | 168 +++++++++++++++++
> .../Library/ArmPlatformLib/ArmPlatformLib.inf | 45 +++++
> .../ArmPlatformLib/ArmPlatformLibInternal.h | 26 +++
> .../ArmPlatformLib/ArmPlatformLibMem.c | 80 ++++++++
> Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc | 90 +++++++++
> Platform/NXP/NxpQoriqLsPlatform.dec | 23 +++
> 11 files changed, 767 insertions(+)
> create mode 100644 Platform/NXP/Include/Qixis.h
> create mode 100644 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec
> create mode 100644 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc
> create mode 100644 Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
> create mode 100644 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
> create mode 100644 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> create mode 100644 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> create mode 100644 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibInternal.h
> create mode 100644 Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
> create mode 100644 Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc
> create mode 100644 Platform/NXP/NxpQoriqLsPlatform.dec
>
> diff --git a/Platform/NXP/Include/Qixis.h b/Platform/NXP/Include/Qixis.h
> new file mode 100644
> index 0000000000..116e4c1b30
> --- /dev/null
> +++ b/Platform/NXP/Include/Qixis.h
> @@ -0,0 +1,40 @@
> +/** @file
> + Qixis Layout.
> +
> + Copyright 2020 NXP
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef __QIXIS_H__
> +#define __QIXIS_H__
Please drop leading __ from include guards.
> +
> +#include <Uefi.h>
> +
> +typedef struct _QIXIS_MIN_LAYOUT {
> + UINT8 Id;
> + UINT8 Ver;
> + UINT8 Qver;
> + UINT8 Model;
> + UINT8 Minor;
> + UINT8 Ctl;
> + UINT8 Aux;
> + UINT8 Reserved007[0x040 - 0x007];
> + UINT8 ResetCtl;
> + UINT8 ResetStat;
> + UINT8 ResetReason;
> + UINT8 ResetForce[3];
> + UINT8 Reserved046[0x04B - 0x046];
> + UINT8 ResetMask[3];
> + UINT8 Reserved04E[0x050 - 0x04E];
> + UINT8 BoardConfig[16];
> + UINT8 DutConfig[16];
> + UINT8 Reserved070[0x090 - 0x070];
> + UINT8 IrqStat[4];
> + UINT8 IrqCtl[4];
> + UINT8 IrqDrv[8];
> + UINT8 Reserved0A0[0x0D8 - 0x0A0];
> +} QIXIS_MIN_LAYOUT;
> +
> +#endif
> +
> diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec
> new file mode 100644
> index 0000000000..192eabc5b3
> --- /dev/null
> +++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dec
> @@ -0,0 +1,23 @@
> +# LX2160aRdbPkg.dec
> +# LX2160a board package.
> +#
> +# Copyright 2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +[Defines]
> + PACKAGE_NAME = LX2160aRdbPkg
> + PACKAGE_GUID = 6eba6648-d853-4eb3-9761-528b82d5ab04
This GUID is cloned from LS1043aRdbPkg.dec, which is cloned from
BeagleBoardPkg.dec. Please generate a unique GUID for this one, and
provide a separate fix for LS1043aRdbPkg.dec.
> +
> +################################################################################
> +#
> +# Include Section - list of Include Paths that are provided by this package.
> +# Comments are used for Keywords and Module Types.
> +#
> +# Supported Module Types:
> +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
> +#
> +################################################################################
> +[Includes.common]
> + Include # Root include for the package
> diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc
> new file mode 100644
> index 0000000000..773b211b7d
> --- /dev/null
> +++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.dsc
> @@ -0,0 +1,54 @@
> +# LX2160aRdbPkg.dsc
> +#
> +# LX2160ARDB Board package.
> +#
> +# Copyright 2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +################################################################################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +################################################################################
> +[Defines]
> + #
> + # Defines for default states. These can be changed on the command line.
> + # -D FLAG=VALUE
> + #
> + PLATFORM_NAME = LX2160aRdbPkg
> + PLATFORM_GUID = 60169ec4-d2b4-44f8-825e-f8684fd42e4f
This GUID is cloned from LS1043aRdbPkg.dsc, please generate a unique one.
> + OUTPUT_DIRECTORY = Build/LX2160aRdbPkg
> + FLASH_DEFINITION = Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
> +
> +!include Silicon/NXP/NxpQoriqLs.dsc.inc
> +!include Silicon/NXP/Chassis3V2/Chassis3V2.dsc.inc
> +!include Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dsc.inc
> +
> +[LibraryClasses.common]
> + ArmPlatformLib|Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> + RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
> +
> +[PcdsFixedAtBuild.common]
> + #
> + # RTC Pcds
> + #
> +
> +################################################################################
> +#
> +# Components Section - list of all EDK II Modules needed by this Platform
> +#
> +################################################################################
> +[Components.common]
> + #
> + # Architectural Protocols
> + #
> + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
> + <PcdsFixedAtBuild>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
> + }
> +
> + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
> +
> + ##
> diff --git a/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
> new file mode 100644
> index 0000000000..ed7c39365c
> --- /dev/null
> +++ b/Platform/NXP/LX2160aRdbPkg/LX2160aRdbPkg.fdf
> @@ -0,0 +1,172 @@
> +# LX2160aRdbPkg.fdf
> +#
> +# FLASH layout file for LX2160aRdb board.
> +#
> +# Copyright 2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +################################################################################
> +#
> +# FD Section
> +# The [FD] Section is made up of the definition statements and a
> +# description of what goes into the Flash Device Image. Each FD section
> +# defines one flash "device" image. A flash device image may be one of
> +# the following: Removable media bootable image (like a boot floppy
> +# image,) an Option ROM image (that would be "flashed" into an add-in
> +# card,) a System "Flash" image (that would be burned into a system's
> +# flash) or an Update ("Capsule") image that will be used to update and
> +# existing system flash.
> +#
> +################################################################################
> +
> +[FD.LX2160ARDB_EFI]
> +BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
> +Size = 0x00100000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
> +ErasePolarity = 1
> +BlockSize = 0x1
> +NumBlocks = 0x100000
> +
> +################################################################################
> +#
> +# Following are lists of FD Region layout which correspond to the locations of different
> +# images within the flash device.
> +#
> +# Regions must be defined in ascending order and may not overlap.
> +#
> +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
> +# the pipe "|" character, followed by the size of the region, also in hex with the leading
> +# "0x" characters. Like:
> +# Offset|Size
> +# PcdOffsetCName|PcdSizeCName
> +# RegionType <FV, DATA, or FILE>
> +#
> +################################################################################
> +0x00000000|0x00100000
> +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
> +FV = FVMAIN_COMPACT
> +
> +!include VarStore.fdf.inc
> +!include Platform/NXP/FVRules.fdf.inc
> +################################################################################
> +#
> +# FV Section
> +#
> +# [FV] section is used to define what components or modules are placed within a flash
> +# device file. This section also defines order the components and modules are positioned
> +# within the image. The [FV] section consists of define statements, set statements and
> +# module statements.
> +#
> +################################################################################
> +
> +[FV.FvMain]
> +FvNameGuid = 1037c42b-8452-4c41-aac7-41e6c31468da
This is cloned from LS1043aRdbPkg.fdf.
> +BlockSize = 0x1
> +NumBlocks = 0 # This FV gets compressed so make it just big enough
> +FvAlignment = 8 # FV alignment and FV attributes setting.
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + INF MdeModulePkg/Core/Dxe/DxeMain.inf
> + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> +
> + #
> + # PI DXE Drivers producing Architectural Protocols (EFI Services)
> + #
> + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> +
> + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
> + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
> + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
> + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
> +
> + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
> +
> + #
> + # Multiple Console IO support
> + #
> + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
> + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> +
> + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
> + INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
> +
> + #
> + # FAT filesystem + GPT/MBR partitioning
> + #
> + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> + INF FatPkg/FatPei/FatPei.inf
> + INF FatPkg/EnhancedFatDxe/Fat.inf
> +
> + #
> + # UEFI application (Shell Embedded Boot Loader)
> + #
> + INF ShellPkg/Application/Shell/Shell.inf
> +
> + #
> + # Bds
> + #
> + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> + INF MdeModulePkg/Application/UiApp/UiApp.inf
> +
> +[FV.FVMAIN_COMPACT]
> +FvAlignment = 8
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
> + INF MdeModulePkg/Core/Pei/PeiMain.inf
> + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
> + INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
> + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
> + INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
> + INF ArmPkg/Drivers/CpuPei/CpuPei.inf
> + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
> + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> +
> + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
> + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
> + SECTION FV_IMAGE = FVMAIN
> + }
> + }
> diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
> new file mode 100644
> index 0000000000..d1b9f1debb
> --- /dev/null
> +++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S
> @@ -0,0 +1,46 @@
> +//
> +// Copyright (c) 2012-2013, ARM Limited. All rights reserved.
> +//
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +//
> +
> +#include <AsmMacroIoLibV8.h>
> +#include <Library/ArmLib.h>
> +
> +ASM_FUNC(ArmPlatformPeiBootAction)
> + ret
> +
> +//UINTN
> +//ArmPlatformGetCorePosition (
> +// IN UINTN MpId
> +// );
> +// With this function: CorePos = (ClusterId * 4) + CoreId
> +ASM_FUNC(ArmPlatformGetCorePosition)
> + and x1, x0, #ARM_CORE_MASK
> + and x0, x0, #ARM_CLUSTER_MASK
> + add x0, x1, x0, LSR #6
> + ret
> +
> +//UINTN
> +//ArmPlatformGetPrimaryCoreMpId (
> +// VOID
> +// );
> +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
> + MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore))
> + ret
> +
> +//UINTN
> +//ArmPlatformIsPrimaryCore (
> +// IN UINTN MpId
> +// );
> +ASM_FUNC(ArmPlatformIsPrimaryCore)
> + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
> + and x0, x0, x1
> + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore))
> + cmp w0, w1
> + mov x0, #1
> + mov x1, #0
> + csel x0, x0, x1, eq
> + ret
> +
> diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> new file mode 100644
> index 0000000000..adcc3315dd
> --- /dev/null
> +++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> @@ -0,0 +1,168 @@
> +/** @file
> +*
> +* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
> +* Copyright 2020 NXP
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +#include <Soc.h>
> +#include <Library/ArmPlatformLib.h>
> +#include <Ppi/ArmMpCoreInfo.h>
Please sort includes alphabetically (grouped with the below).
> +
> +#include <Library/DebugLib.h>
> +#include <Library/I2cLib.h>
> +#include <Library/SocLib.h>
> +#include <Ppi/NxpPlatformGetClock.h>
> +
> +#include "ArmPlatformLibInternal.h"
> +
> +ARM_CORE_INFO mArmPlatformMpCoreInfoTable[] = {
> + {
> + // Cluster 0, Core 0
> + 0, 0,
> +
> + // MP Core MailBox Set/Get/Clear Addresses and Clear Value
> + (EFI_PHYSICAL_ADDRESS)0,
> + (EFI_PHYSICAL_ADDRESS)0,
> + (EFI_PHYSICAL_ADDRESS)0,
> + (UINT64)0xFFFFFFFF
This defines only one core, right?
> + },
> +};
> +
> +/**
> + Get the clocks supplied by Platform(Board) to NXP Layerscape SOC
> +
> + The core can be of type ARM or PowerPC or Hardware Accelerator.
> + If the core is enabled and of type ARM EFI_SUCCESS is returned and a code for type of ARM core is returned
> +
> + @param[in] ClockType Type of clock
> + @param[in] ... Variable argument list which is parsed based on ClockType
> +
> + @return Actual Clock Frequency. return value 0 should be interpreted as clock not provided by Board.
> +**/
> +UINT64
> +EFIAPI
> +NxpPlatformGetClock(
> + IN UINT32 ClockType,
> + ...
> + )
> +{
> + UINT64 Clock;
> + EFI_STATUS Status;
> + VA_LIST Args;
> + UINT8 Reg;
> +
> + Clock = 0;
> +
> + VA_START (Args, ClockType);
> +
> + switch (ClockType) {
> + case NXP_SYSTEM_CLOCK:
> + Status = I2cBusReadReg (
> + LX2160A_I2C0_PHYS_ADDRESS, QIXIS_I2C_ADDRESS,
> + OFFSET_OF (QIXIS_LAYOUT, BoardConfig[1]),
> + 1, &Reg, sizeof (Reg)
> + );
> + ASSERT_EFI_ERROR (Status);
> + switch (Reg & 0x03) {
Need a #define for that 0x03.
> + case 0x00:
> + Clock = 100 * 1000 * 1000; // 100 MHz
> + break;
> + default:
> + ASSERT(0); // All other values are reserved
> + break;
> + }
> + break;
> + case NXP_I2C_CLOCK:
> + case NXP_UART_CLOCK:
> + Clock = NxpPlatformGetClock (NXP_SYSTEM_CLOCK);
> + Clock = SocGetClock (Clock, ClockType, Args);
> + break;
> + default:
> + break;
> + }
> +
> + VA_END (Args);
> +
> + return Clock;
> +}
> +
> +/**
> + Return the current Boot Mode
> +
> + This function returns the boot reason on the platform
> +
> +**/
> +EFI_BOOT_MODE
> +ArmPlatformGetBootMode (
> + VOID
> + )
> +{
> + return BOOT_WITH_FULL_CONFIGURATION;
> +}
> +
> +/**
> + Initialize controllers that must setup in the normal world
> +
> + This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
> + in the PEI phase.
> +
> +**/
> +RETURN_STATUS
> +ArmPlatformInitialize (
> + IN UINTN MpId
> + )
> +{
> + UINT64 Clock;
> +
> + TimerConstructor ();
> +
> + I2cEarlyInitialize (LX2160A_I2C0_PHYS_ADDRESS);
> +
> + Clock = NxpPlatformGetClock (NXP_I2C_CLOCK, 0);
> +
> + // Set I2c Clock 100 KHz
> + I2cInitialize (LX2160A_I2C0_PHYS_ADDRESS, Clock, 100 * 1000);
> +
> + SocInit ();
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +PrePeiCoreGetMpCoreInfo (
> + OUT UINTN *CoreCount,
> + OUT ARM_CORE_INFO **ArmCoreTable
> + )
> +{
> + if (ArmIsMpCore()) {
> + *CoreCount = sizeof (mArmPlatformMpCoreInfoTable) / sizeof (ARM_CORE_INFO);
Use ARRAY_SIZE macro.
> + *ArmCoreTable = mArmPlatformMpCoreInfoTable;
> + return EFI_SUCCESS;
> + } else {
> + return EFI_UNSUPPORTED;
> + }
> +}
> +
> +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
> +NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi = { NxpPlatformGetClock };
> +
> +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
> + {
> + EFI_PEI_PPI_DESCRIPTOR_PPI,
> + &gArmMpCoreInfoPpiGuid,
> + &mMpCoreInfoPpi
> + }
> +};
> +
> +VOID
> +ArmPlatformGetPlatformPpiList (
> + OUT UINTN *PpiListSize,
> + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
> + )
> +{
> + *PpiListSize = sizeof (gPlatformPpiTable);
> + *PpiList = gPlatformPpiTable;
> +}
> +
> diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> new file mode 100644
> index 0000000000..24258e1502
> --- /dev/null
> +++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> @@ -0,0 +1,45 @@
> +#/* @file
> +#
> +# Copyright 2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#*/
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = ArmPlatformLib
> + FILE_GUID = 736343a0-1d96-11e0-aaaa-0002a5d5c51b
Cloned from LS1043aRdbPkg, which is cloned from BeagleBoardPkg.
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = ArmPlatformLib
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> + Silicon/NXP/Chassis3V2/Chassis3V2.dec
> + Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec
> + Platform/NXP/NxpQoriqLsPlatform.dec
Sort alphabetically.
> +
> +[LibraryClasses]
> + ArmLib
> + SocLib
> + I2cLib
> + DebugLib
Sort alphabetically.
> +
> +[Sources.common]
> + ArmPlatformLib.c
> + ArmPlatformLibMem.c
> +
> +[Sources.AArch64]
> + AArch64/ArmPlatformHelper.S
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
> + gArmTokenSpaceGuid.PcdArmPrimaryCore
> +
> +[Ppis]
> + gArmMpCoreInfoPpiGuid
> diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibInternal.h b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibInternal.h
> new file mode 100644
> index 0000000000..fefbd273c8
> --- /dev/null
> +++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibInternal.h
> @@ -0,0 +1,26 @@
> +/** @file
> + Platform Specific data.
> +
> + Copyright 2020 NXP
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef __ARM_PLATFORM_LIB_INTERNAL_H__
> +#define __ARM_PLATFORM_LIB_INTERNAL_H__
Drop leading __.
> +
> +#include <Qixis.h>
This file does not appear to be used in this header, please move its
inclusion to files that actually use it.
/
Leif
> +
> +// This function should be better located into TimerLib implementation
> +RETURN_STATUS
> +EFIAPI
> +TimerConstructor (
> + VOID
> + );
> +
> +#define QIXIS_I2C_ADDRESS 0x66
> +
> +typedef QIXIS_MIN_LAYOUT QIXIS_LAYOUT;
> +
> +#endif
> +
> diff --git a/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
> new file mode 100644
> index 0000000000..85bd7e6307
> --- /dev/null
> +++ b/Platform/NXP/LX2160aRdbPkg/Library/ArmPlatformLib/ArmPlatformLibMem.c
> @@ -0,0 +1,80 @@
> +/** @file
> +*
> +* Copyright 2020 NXP
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#include <Library/ArmPlatformLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Soc.h>
> +
> +// Number of Virtual Memory Map Descriptors
> +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 10
> +
> +/**
> + Return the Virtual Memory Map of your platform
> +
> + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
> +
> + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
> + Virtual Memory mapping. This array must be ended by a zero-filled
> + entry
> +
> +**/
> +VOID
> +ArmPlatformGetVirtualMemoryMap (
> + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
> + )
> +{
> + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
> + UINT32 Index;
> +
> + ASSERT (VirtualMemoryMap != NULL);
> +
> + VirtualMemoryTable = AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) *
> + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
> +
> + if (VirtualMemoryTable == NULL) {
> + DEBUG ((DEBUG_ERROR, "%a: Error: Failed AllocatePool()\n", __FUNCTION__));
> + return;
> + }
> +
> + Index = 0;
> + // DRAM
> + VirtualMemoryTable[Index].PhysicalBase = LX2160A_DRAM0_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LX2160A_DRAM0_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LX2160A_DRAM0_SIZE;
> + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> +
> + VirtualMemoryTable[Index].PhysicalBase = LX2160A_DRAM1_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LX2160A_DRAM1_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LX2160A_DRAM1_SIZE;
> + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> +
> + // CCSR Space
> + VirtualMemoryTable[Index].PhysicalBase = LX2160A_CCSR_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LX2160A_CCSR_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LX2160A_CCSR_SIZE;
> + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // FlexSPI region
> + // TODO: check if we can change attributes for better performance
> + VirtualMemoryTable[Index].PhysicalBase = LX2160A_FLEXSPI_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].VirtualBase = LX2160A_FLEXSPI_PHYS_ADDRESS;
> + VirtualMemoryTable[Index].Length = LX2160A_FLEXSPI_SIZE;
> + VirtualMemoryTable[Index++].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // End of Table
> + VirtualMemoryTable[Index].PhysicalBase = 0;
> + VirtualMemoryTable[Index].VirtualBase = 0;
> + VirtualMemoryTable[Index].Length = 0;
> + VirtualMemoryTable[Index++].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
> +
> + ASSERT (Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
> +
> + *VirtualMemoryMap = VirtualMemoryTable;
> +}
> diff --git a/Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc b/Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc
> new file mode 100644
> index 0000000000..215d73dd8f
> --- /dev/null
> +++ b/Platform/NXP/LX2160aRdbPkg/VarStore.fdf.inc
> @@ -0,0 +1,90 @@
> +## @file
> +# FDF include file with FD definition that defines an empty variable store.
> +#
> +# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
> +# Copyright (C) 2014, Red Hat, Inc.
> +# Copyright (c) 2016, Linaro, Ltd. All rights reserved.
> +# Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
> +# Copyright 2017-2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +##
> +
> +[FD.LX2160ARDBNV_EFI]
> +
> +BaseAddress = 0x20500000
> +Size = 0x000C0000
> +ErasePolarity = 1
> +BlockSize = 0x1
> +NumBlocks = 0xC0000
> +
> +#
> +# Place NV Storage just above Platform Data Base
> +#
> +DEFINE NVRAM_AREA_VARIABLE_BASE = 0x00000000
> +DEFINE NVRAM_AREA_VARIABLE_SIZE = 0x00040000
> +DEFINE FTW_WORKING_BASE = $(NVRAM_AREA_VARIABLE_BASE) + $(NVRAM_AREA_VARIABLE_SIZE)
> +DEFINE FTW_WORKING_SIZE = 0x00040000
> +DEFINE FTW_SPARE_BASE = $(FTW_WORKING_BASE) + $(FTW_WORKING_SIZE)
> +DEFINE FTW_SPARE_SIZE = 0x00040000
> +
> +#############################################################################
> +# LX2160ARDB NVRAM Area
> +# LX2160ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare
> +#############################################################################
> +
> +$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> +#NV_VARIABLE_STORE
> +DATA = {
> + ## This is the EFI_FIRMWARE_VOLUME_HEADER
> + # ZeroVector []
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + # FileSystemGuid: gEfiSystemNvDataFvGuid =
> + # { 0xFFF12B8D, 0x7696, 0x4C8B,
> + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
> + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
> + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
> + # FvLength: Flash Size : 0x4000000
> + 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
> + # Signature "_FVH" # Attributes
> + 0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
> + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
> + 0x48, 0x00, 0x08, 0xA6, 0x00, 0x00, 0x00, 0x02,
> + # Blockmap[0]: 0x4000 Blocks * 0x1000 Bytes / Block = SIZE_64MB
> + 0x00, 0x40, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
> + # Blockmap[1]: End
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + ## This is the VARIABLE_STORE_HEADER
> + # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
> + # Signature: gEfiVariableGuid =
> + # { 0xddcf3616, 0x3275, 0x4164,
> + # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
> + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
> + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
> + # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
> + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
> + # This can speed up the Variable Dispatch a bit.
> + 0xB8, 0xFF, 0x03, 0x00,
> + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
> + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> +}
> +
> +$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> +#NV_FTW_WORKING
> +DATA = {
> + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
> + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
> + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
> + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
> + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
> + 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
> + # WriteQueueSize: UINT64
> + 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
> +}
> +
> +$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> +#NV_FTW_SPARE
> diff --git a/Platform/NXP/NxpQoriqLsPlatform.dec b/Platform/NXP/NxpQoriqLsPlatform.dec
> new file mode 100644
> index 0000000000..106b118188
> --- /dev/null
> +++ b/Platform/NXP/NxpQoriqLsPlatform.dec
> @@ -0,0 +1,23 @@
> +#/** @file
> +# NXP Layerscape processor package.
> +#
> +# Copyright 2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#**/
> +
> +[Defines]
> + DEC_SPECIFICATION = 1.27
> + PACKAGE_VERSION = 0.1
> +
> +################################################################################
> +#
> +# Include Section - list of Include Paths that are provided by this package.
> +# Comments are used for Keywords and Module Types.
> +#
> +#
> +################################################################################
> +[Includes.common]
> + Include # Root include for the package
> +
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 18/19] Silicon/NXP: Add LX2160A SocLib
2020-02-07 12:43 ` [PATCH 18/19] Silicon/NXP: Add LX2160A SocLib Pankaj Bansal
@ 2020-02-12 21:39 ` Leif Lindholm
0 siblings, 0 replies; 49+ messages in thread
From: Leif Lindholm @ 2020-02-12 21:39 UTC (permalink / raw)
To: Pankaj Bansal; +Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi, devel
On Fri, Feb 07, 2020 at 18:13:27 +0530, Pankaj Bansal wrote:
> Add LX2160A SocLib
Same soclib question as elsewhere.
Also, please add some more info to commit message.
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> Silicon/NXP/Chassis3V2/LX2160A/Include/Soc.h | 39 +++++++++
> Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec | 23 ++++++
> .../NXP/Chassis3V2/LX2160A/LX2160A.dsc.inc | 34 ++++++++
> .../LX2160A/Library/SocLib/SocLib.c | 79 +++++++++++++++++++
> .../LX2160A/Library/SocLib/SocLib.inf | 31 ++++++++
> 5 files changed, 206 insertions(+)
> create mode 100644 Silicon/NXP/Chassis3V2/LX2160A/Include/Soc.h
> create mode 100644 Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec
> create mode 100644 Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dsc.inc
> create mode 100644 Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.c
> create mode 100644 Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.inf
>
> diff --git a/Silicon/NXP/Chassis3V2/LX2160A/Include/Soc.h b/Silicon/NXP/Chassis3V2/LX2160A/Include/Soc.h
> new file mode 100644
> index 0000000000..cc1f91272d
> --- /dev/null
> +++ b/Silicon/NXP/Chassis3V2/LX2160A/Include/Soc.h
> @@ -0,0 +1,39 @@
> +/** @file
> +
> + Copyright 2020 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +#ifndef __SOC_H__
> +#define __SOC_H__
Please drop leading __.
> +
> +#include <Chassis.h>
> +
> +/**
> + Soc Memory Map
> +**/
> +#define LX2160A_CCSR_PHYS_ADDRESS 0x1000000
> +#define LX2160A_CCSR_SIZE 0xF000000
> +
> +#define LX2160A_FLEXSPI_PHYS_ADDRESS 0x20000000
> +#define LX2160A_FLEXSPI_SIZE SIZE_256MB
> +
> +#define LX2160A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS
> +
> +#define LX2160A_DRAM0_PHYS_ADDRESS 0x80000000
> +#define LX2160A_DRAM0_SIZE SIZE_2GB
> +#define LX2160A_DRAM1_PHYS_ADDRESS 0x2080000000
> +#define LX2160A_DRAM1_SIZE 0x1F80000000 // 128 GB
> +
> +#define LX2160A_I2C0_PHYS_ADDRESS 0x2000000
> +
> +/**
> + Reset Control Word (RCW) Bits
> +**/
> +#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 2-6
What is RAT?
> +
> +typedef NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG LX2160A_DEVICE_CONFIG;
> +
> +#endif
> +
> diff --git a/Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec b/Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec
> new file mode 100644
> index 0000000000..106b118188
> --- /dev/null
> +++ b/Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec
> @@ -0,0 +1,23 @@
> +#/** @file
> +# NXP Layerscape processor package.
> +#
> +# Copyright 2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#**/
> +
> +[Defines]
> + DEC_SPECIFICATION = 1.27
> + PACKAGE_VERSION = 0.1
> +
> +################################################################################
> +#
> +# Include Section - list of Include Paths that are provided by this package.
> +# Comments are used for Keywords and Module Types.
> +#
> +#
> +################################################################################
> +[Includes.common]
> + Include # Root include for the package
> +
> diff --git a/Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dsc.inc b/Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dsc.inc
> new file mode 100644
> index 0000000000..f786a57ebc
> --- /dev/null
> +++ b/Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dsc.inc
> @@ -0,0 +1,34 @@
> +# @file
> +#
> +# Copyright 2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +
> +[LibraryClasses.common]
> + SocLib|Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.inf
> + SerialPortLib|Silicon/NXP/Library/PL011SerialPortLib/PL011SerialPortLib.inf
> +
> +################################################################################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +################################################################################
> +[PcdsFeatureFlag.common]
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|TRUE
> +
> +[PcdsFixedAtBuild.common]
> +## PL011 Serial Terminal
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x21c0000
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
> + gArmPlatformTokenSpaceGuid.PcdCoreCount|16
> +
> +[PcdsDynamicDefault.common]
> + gNxpQoriqLsTokenSpaceGuid.PcdReservedMemSize|0x20000000
> + gNxpQoriqLsTokenSpaceGuid.PcdReservedMemAlignment|0x20000000
> + #
> + # ARM General Interrupt Controller
> + gArmTokenSpaceGuid.PcdGicDistributorBase|0x6000000
> + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x6200000
> + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x0c0c0000
> diff --git a/Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.c b/Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.c
> new file mode 100644
> index 0000000000..2c19c72b5f
> --- /dev/null
> +++ b/Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.c
> @@ -0,0 +1,79 @@
> +/** @file
> +
> + Copyright 2017-2020 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> + **/
> +#include <Soc.h>
> +#include <Library/ChassisLib.h>
> +#include <Library/SocLib.h>
> +
> +/**
> + Return the input clock frequency to an IP Module.
> + This function reads the RCW bits and calculates the PLL multipler/divider values to be applied
> + to various IP modules.
> + If a module is disabled or doesn't exist on platform, then return zero.
> +
> + @param[in] BaseClock Base clock to which PLL multipler/divider values is to be applied.
> + @param[in] ClockType IP modules whose clock value is to be retrieved
> + @param[in] Args Variable Args lists that is parsed based on the ClockType
> + e.g. if there are multiple modules of same type then this value tells the
> + instance of module for which clock is to be retrieved.
> + (e.g. if there are four i2c controllers in SOC, then this value can be 1, 2, 3, 4)
> + for IP modules which have only single instance in SOC (e.g. one QSPI controller)
> + this value can be null (i.e. no arg)
> +
> + @return > 0 Return the input clock frequency to an IP Module
> + 0 either IP module doesn't exist in SOC
> + or IP module instance doesn't exist in SOC
> + or IP module instance is disabled. i.e. no input clock is provided to IP module instance.
Please wrap long lines.
> +**/
> +UINT64
> +SocGetClock (
> + IN UINT64 BaseClock,
> + IN UINT32 ClockType,
> + IN VA_LIST Args
> + )
> +{
> + LX2160A_DEVICE_CONFIG *Dcfg;
> + UINT32 RcwSr;
> + UINT64 ReturnValue;
> +
> + ReturnValue = 0;
> + Dcfg = (LX2160A_DEVICE_CONFIG *)LX2160A_DCFG_ADDRESS;
> +
> + switch (ClockType) {
> + case NXP_UART_CLOCK:
> + RcwSr = DcfgRead32 ((UINTN)&Dcfg->RcwSr[0]);
> + ReturnValue = BaseClock * SYS_PLL_RAT (RcwSr);
> + ReturnValue >>= 3; // platform pll / 8
> + break;
> + case NXP_I2C_CLOCK:
> + RcwSr = DcfgRead32 ((UINTN)&Dcfg->RcwSr[0]);
> + ReturnValue = BaseClock * SYS_PLL_RAT (RcwSr);
> + ReturnValue >>= 4; // platform pll / 16
> + break;
> + default:
> + break;
> + }
> +
> + return ReturnValue;
> +}
> +
> +/**
> + Function to initialize SoC specific constructs
> + CPU Info
> + SoC Personality
> + Board Personality
> + RCW prints
> + **/
> +VOID
> +SocInit (
> + VOID
> + )
> +{
> + ChassisInit ();
> +
> + return;
> +}
> +
> diff --git a/Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.inf b/Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.inf
> new file mode 100644
> index 0000000000..ea9d45a021
> --- /dev/null
> +++ b/Silicon/NXP/Chassis3V2/LX2160A/Library/SocLib/SocLib.inf
> @@ -0,0 +1,31 @@
> +#@file
> +#
> +# Component description file for SocLib module
> +#
> +# Copyright 2017-2020 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +
> +[Defines]
> + INF_VERSION = 0x0001000A
> + BASE_NAME = SocLib
> + FILE_GUID = 9b046753-2b4f-42d8-bfb3-468892fe17d4
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = SocLib
> +
> +[Sources.common]
> + SocLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> + Silicon/NXP/Chassis3V2/Chassis3V2.dec
> + Silicon/NXP/Chassis3V2/LX2160A/LX2160A.dec
Please sort alphabetically.
/
Leif
> +
> +[LibraryClasses]
> + ChassisLib
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 14/19] Silicon/NXP/LS1043A: Replce SocLib
2020-02-12 9:37 ` Pankaj Bansal
@ 2020-02-12 22:50 ` Leif Lindholm
2020-02-13 11:00 ` Pankaj Bansal
0 siblings, 1 reply; 49+ messages in thread
From: Leif Lindholm @ 2020-02-12 22:50 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi,
devel@edk2.groups.io
On Wed, Feb 12, 2020 at 09:37:30 +0000, Pankaj Bansal wrote:
>
>
> > -----Original Message-----
> > From: Leif Lindholm <leif@nuviainc.com>
> > Sent: Tuesday, February 11, 2020 7:05 PM
> > To: Pankaj Bansal <pankaj.bansal@nxp.com>
> > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney
> > <michael.d.kinney@intel.com>; Varun Sethi <V.Sethi@nxp.com>;
> > devel@edk2.groups.io
> > Subject: Re: [PATCH 14/19] Silicon/NXP/LS1043A: Replce SocLib
> >
> > On Fri, Feb 07, 2020 at 18:13:23 +0530, Pankaj Bansal wrote:
> > > Replace SocLib with new SocLib in which code structure has been
> > > changed.
> >
> > I don't think there's much point to me reviewing this one until we've discussed
> > the ChassisLib/SocLib split and layout in more detail.
>
> Let me explain the code layout.
> A Chassis is a base framework used for building SoCs.
> All NXP Layerscape SOCs like LS1043A, LS1046A, LS2088A, LX2160A are part of some chassis.
> e.g. LS1043A conforms to Chassis 2.x
> LX2160A conforms to Chassis 3.2
>
> We can think of Chassis/Soc/Platform(a.k.a Borad) in Oops terms.
> Chassis is base. Soc Is derived from Chassis. Platform is derived from Soc.
Right. This is what confused me.
I was thinking "chassis" more along the lines of
https://en.wikipedia.org/wiki/Chassis_Management_Controller
You're talking about the ... bits that remain the same on migrating
the processors from PPC to ARM?
> We have kept the code also in such a way. Which is why we have made
> Soc Package part of Chassis Package.
>
> SocLib provides services to PlatformLib. ChassisLib provides
> services to SocLib.
> Which is why we have made SocGetMpCoreInfo as weak function and
> implemented it in ChassisLib (Patch 11/19)
> This ensures that code can be reused for all SOCs belonging to same
> chassis.
> If any future SOC implements this feature in different way, then
> this API can be overwritten in SocLib
>
> SOCs belonging to same Chassis share many same traits.
> e.g. the SOC memory map is usually common for all SOCs belonging to
> same Chassis.
OK, this sounds valid. But one follow-up question: why add the
hierarchy at all? From a (human) discoverability standpoint, if
someone is looking for the code for a specific SoC, they will be
looking for that SoC, not some abstraction of it.
So I agree it makes sense that chassis are not kept under SoC, but I
am asking if it would not make more sense to keep them on the same
level?
Any SoCs depending on Pcds defined by a specific chassis could access
those by importing the package fr that chassis.
Regards,
Leif
> >
> > /
> > Leif
> >
> > > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> > > ---
> > > .../Drivers/PlatformDxe/PlatformDxe.inf | 3 +-
> > > Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 3 +-
> > > .../Library/ArmPlatformLib/ArmPlatformLib.c | 53 ++++++-
> > > .../Library/ArmPlatformLib/ArmPlatformLib.inf | 6 +-
> > > Silicon/NXP/Chassis2/Include/Chassis.h | 12 ++
> > > Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc | 1 +
> > > .../Chassis2/LS1043A/Library/SocLib/SocLib.c | 28 ++++
> > > .../LS1043A/Library/SocLib/SocLib.inf | 8 ++
> > > .../Chassis2/Library/ChassisLib/ChassisLib.c | 25 ++++
> > > Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 2 +-
> > > Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 7 +-
> > > Silicon/NXP/Include/Chassis2/NxpSoc.h | 53 -------
> > > Silicon/NXP/Include/Library/ChassisLib.h | 2 -
> > > Silicon/NXP/Include/Library/SocLib.h | 1 -
> > > Silicon/NXP/LS1043A/Include/Soc.h | 44 ------
> > > Silicon/NXP/LS1043A/LS1043A.dec | 16 ---
> > > Silicon/NXP/LS1043A/LS1043A.dsc.inc | 33 -----
> > > .../BaseSerialPortLib16550.c | 11 +-
> > > .../BaseSerialPortLib16550.inf | 3 +-
> > > Silicon/NXP/Library/SocLib/Chassis.c | 76 ----------
> > > Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 96 -------------
> > > Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 44 ------
> > > Silicon/NXP/Library/SocLib/NxpChassis.h | 136 ------------------
> > > 23 files changed, 142 insertions(+), 521 deletions(-) delete mode
> > > 100644 Silicon/NXP/Include/Chassis2/NxpSoc.h
> > > delete mode 100644 Silicon/NXP/LS1043A/Include/Soc.h delete mode
> > > 100644 Silicon/NXP/LS1043A/LS1043A.dec delete mode 100644
> > > Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > > delete mode 100644 Silicon/NXP/Library/SocLib/Chassis.c
> > > delete mode 100644 Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > > delete mode 100644 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > > delete mode 100644 Silicon/NXP/Library/SocLib/NxpChassis.h
> > >
> > > diff --git
> > > a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> > > b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> > > index 126a1174fa..95f60b00f0 100644
> > > --- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> > > +++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> > > @@ -25,7 +25,8 @@
> > > MdeModulePkg/MdeModulePkg.dec
> > > Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
> > > Silicon/NXP/NxpQoriqLs.dec
> > > - Silicon/NXP/LS1043A/LS1043A.dec
> > > + Silicon/NXP/Chassis2/Chassis2.dec
> > > + Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
> > >
> > > [LibraryClasses]
> > > BaseLib
> > > diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > > b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > > index bc6fa4f19d..4bc7f6ef97 100644
> > > --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > > +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > > @@ -23,7 +23,8 @@
> > > FLASH_DEFINITION =
> > Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> > >
> > > !include Silicon/NXP/NxpQoriqLs.dsc.inc -!include
> > > Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > > +!include Silicon/NXP/Chassis2/Chassis2.dsc.inc
> > > +!include Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
> > >
> > > [LibraryClasses.common]
> > >
> > > ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPl
> > > atformLib.inf diff --git
> > > a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> > > b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> > > index 718c71bf02..821d413a3e 100644
> > > ---
> > > a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> > > +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib
> > > +++ .c
> > > @@ -14,7 +14,10 @@
> > > #include <Library/ArmPlatformLib.h>
> > > #include <Ppi/ArmMpCoreInfo.h>
> > >
> > > -extern VOID SocInit (VOID);
> > > +#include <Library/DebugLib.h>
> > > +#include <Library/I2cLib.h>
> > > +#include <Library/SocLib.h>
> > > +#include <Ppi/NxpPlatformGetClock.h>
> > >
> > > /**
> > > Return the current Boot Mode
> > > @@ -30,6 +33,49 @@ ArmPlatformGetBootMode (
> > > return BOOT_WITH_FULL_CONFIGURATION; }
> > >
> > > +/**
> > > + Get the clocks supplied by Platform(Board) to NXP Layerscape SOC
> > > +
> > > + The core can be of type ARM or PowerPC or Hardware Accelerator.
> > > + If the core is enabled and of type ARM EFI_SUCCESS is returned and
> > > + a code for type of ARM core is returned
> > > +
> > > + @param[in] ClockType Type of clock
> > > + @param[in] ... Variable argument list which is parsed based on
> > ClockType
> > > +
> > > + @return Actual Clock Frequency. return value 0 should be interpreted as
> > clock not provided by Board.
> > > +**/
> > > +UINT64
> > > +EFIAPI
> > > +NxpPlatformGetClock(
> > > + IN UINT32 ClockType,
> > > + ...
> > > + )
> > > +{
> > > + UINT64 Clock;
> > > + VA_LIST Args;
> > > +
> > > + Clock = 0;
> > > +
> > > + VA_START (Args, ClockType);
> > > +
> > > + switch (ClockType) {
> > > + case NXP_SYSTEM_CLOCK:
> > > + Clock = 100 * 1000 * 1000; // 100 MHz
> > > + break;
> > > + case NXP_I2C_CLOCK:
> > > + case NXP_UART_CLOCK:
> > > + Clock = NxpPlatformGetClock (NXP_SYSTEM_CLOCK);
> > > + Clock = SocGetClock (Clock, ClockType, Args);
> > > + break;
> > > + default:
> > > + break;
> > > + }
> > > +
> > > + VA_END (Args);
> > > +
> > > + return Clock;
> > > +}
> > > +
> > > /**
> > > Placeholder for Platform Initialization **/ @@ -38,9 +84,9 @@
> > > ArmPlatformInitialize (
> > > IN UINTN MpId
> > > )
> > > {
> > > - SocInit ();
> > > + SocInit ();
> > >
> > > - return EFI_SUCCESS;
> > > + return EFI_SUCCESS;
> > > }
> > >
> > > ARM_CORE_INFO LS1043aMpCoreInfoCTA53x4[] = { @@ -69,6 +115,7 @@
> > > PrePeiCoreGetMpCoreInfo ( }
> > >
> > > ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
> > > +NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi = {
> > > +NxpPlatformGetClock };
> > >
> > > EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
> > > {
> > > diff --git
> > > a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> > > b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> > > index 6396d2982b..8b79fd7490 100644
> > > ---
> > > a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> > > +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib
> > > +++ .inf
> > > @@ -20,11 +20,14 @@
> > > EmbeddedPkg/EmbeddedPkg.dec
> > > MdePkg/MdePkg.dec
> > > Silicon/NXP/NxpQoriqLs.dec
> > > - Silicon/NXP/LS1043A/LS1043A.dec
> > > + Silicon/NXP/Chassis2/Chassis2.dec
> > > + Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
> > >
> > > [LibraryClasses]
> > > ArmLib
> > > SocLib
> > > + I2cLib
> > > + DebugLib
> > >
> > > [Sources.common]
> > > AArch64/NxpQoriqLsHelper.S | GCC
> > > @@ -36,3 +39,4 @@
> > >
> > > [FixedPcd]
> > > gArmTokenSpaceGuid.PcdArmPrimaryCore
> > > + gArmPlatformTokenSpaceGuid.PcdCoreCount
> > > diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h
> > > b/Silicon/NXP/Chassis2/Include/Chassis.h
> > > index 48ba2e7bfb..8f26faf297 100644
> > > --- a/Silicon/NXP/Chassis2/Include/Chassis.h
> > > +++ b/Silicon/NXP/Chassis2/Include/Chassis.h
> > > @@ -20,6 +20,18 @@
> > > #define TP_ITYPE_VERSION_A53 0x2
> > > #define TP_ITYPE_VERSION_A72 0x4
> > >
> > > +/* SMMU Defintions */
> > > +#define SMMU_BASE_ADDR 0x09000000
> > > +#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
> > > +#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
> > > +#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
> > > +#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
> > > +#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
> > > +
> > > +#define SCR0_USFCFG_MASK 0x00000400
> > > +#define SCR0_CLIENTPD_MASK 0x00000001
> > > +#define SACR_PAGESIZE_MASK 0x00010000
> > > +
> > > /**
> > > The Device Configuration Unit provides general purpose configuration and
> > status for the
> > > device. These registers only support 32-bit accesses.
> > > diff --git a/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
> > > b/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
> > > index 4511203443..8440e5f0f3 100644
> > > --- a/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
> > > +++ b/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
> > > @@ -8,6 +8,7 @@
> > >
> > > [LibraryClasses.common]
> > > SocLib|Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> > > +
> > > + SerialPortLib|Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialP
> > > + ortLib16550.inf
> > >
> > >
> > >
> > #################################################################
> > #####
> > > ##########
> > > #
> > > diff --git a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
> > > b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
> > > index 2a08ad87db..24241e9b02 100644
> > > --- a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
> > > +++ b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
> > > @@ -4,8 +4,10 @@
> > >
> > > SPDX-License-Identifier: BSD-2-Clause-Patent
> > > **/
> > > +#include <Soc.h>
> > > #include <Library/ChassisLib.h>
> > > #include <Library/SocLib.h>
> > > +#include <Library/SerialPortLib.h>
> > >
> > > /**
> > > Return the input clock frequency to an IP Module.
> > > @@ -66,8 +68,34 @@ SocInit (
> > > VOID
> > > )
> > > {
> > > + UINT64 BaudRate;
> > > + UINT32 ReceiveFifoDepth;
> > > + EFI_PARITY_TYPE Parity;
> > > + UINT8 DataBits;
> > > + EFI_STOP_BITS_TYPE StopBits;
> > > + UINT32 Timeout;
> > > +
> > > + BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
> > > + ReceiveFifoDepth = FixedPcdGet16 (PcdUartDefaultReceiveFifoDepth);
> > > + // Use default FIFO depth Timeout = 0; Parity =
> > > + (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity); DataBits =
> > > + FixedPcdGet8 (PcdUartDefaultDataBits); StopBits =
> > > + (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);
> > > +
> > > ChassisInit ();
> > >
> > > + //
> > > + // Early init serial Port to get board information.
> > > + //
> > > + SerialPortSetAttributes (
> > > + &BaudRate,
> > > + &ReceiveFifoDepth,
> > > + &Timeout,
> > > + &Parity,
> > > + &DataBits,
> > > + &StopBits
> > > + );
> > > +
> > > return;
> > > }
> > >
> > > diff --git a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> > > b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> > > index c9a4fbc01f..fb39424bc5 100644
> > > --- a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> > > +++ b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> > > @@ -29,4 +29,12 @@
> > >
> > > [LibraryClasses]
> > > ChassisLib
> > > + PcdLib
> > > + SerialPortLib
> > >
> > > +[FixedPcd]
> > > + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
> > > + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
> > > + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
> > > + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
> > > + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth
> > > diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> > > b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> > > index fa6a36e96f..e7573a0e06 100644
> > > --- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> > > +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> > > @@ -150,6 +150,29 @@ SocGetMpCoreInfo (
> > > return CoreCount;
> > > }
> > >
> > > +/*
> > > + * Setup SMMU in bypass mode
> > > + * and also set its pagesize
> > > + */
> > > +STATIC
> > > +VOID
> > > +SmmuInit (
> > > + VOID
> > > + )
> > > +{
> > > + UINT32 Value;
> > > +
> > > + /* set pagesize as 64K and ssmu-500 in bypass mode */ Value =
> > > + (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
> > > + MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
> > > +
> > > + Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK)
> > &
> > > + ~SCR0_USFCFG_MASK;
> > > + MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
> > > +
> > > + Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) |
> > SCR0_CLIENTPD_MASK) &
> > > +~SCR0_USFCFG_MASK;
> > > + MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value); }
> > > +
> > > /**
> > > Function to initialize Chassis Specific functions
> > > **/
> > > @@ -183,4 +206,6 @@ ChassisInit (
> > > &DataBits,
> > > &StopBits
> > > );
> > > +
> > > + SmmuInit();
> > > }
> > > diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> > > b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> > > index 8e3a82efca..e79b106c8d 100644
> > > --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> > > +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> > > @@ -50,7 +50,7 @@ SetBusFrequency (
> > >
> > > I2cBase = (UINTN)(I2c->Dev->Resources[0].AddrRangeMin);
> > >
> > > - I2cClock = GetBusFrequency ();
> > > + I2cClock = mPlatformGetClockPpi.PlatformGetClock (NXP_I2C_CLOCK,
> > > + 0);
> > >
> > > I2cInitialize (I2cBase, I2cClock, *BusClockHertz);
> > >
> > > diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> > > b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> > > index 88316f3133..f446f0d4f9 100644
> > > --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> > > +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> > > @@ -13,6 +13,7 @@
> > > #include <Library/UefiLib.h>
> > > #include <Uefi.h>
> > >
> > > +#include <Ppi/NxpPlatformGetClock.h>
> > > #include <Protocol/I2cMaster.h>
> > > #include <Protocol/NonDiscoverableDevice.h>
> > >
> > > @@ -37,11 +38,7 @@ typedef struct {
> > > NON_DISCOVERABLE_DEVICE *Dev;
> > > } NXP_I2C_MASTER;
> > >
> > > -extern
> > > -UINT64
> > > -GetBusFrequency (
> > > - VOID
> > > - );
> > > +extern NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi;
> > >
> > > EFI_STATUS
> > > NxpI2cInit (
> > > diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h
> > > b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> > > deleted file mode 100644
> > > index 6812beafe4..0000000000
> > > --- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
> > > +++ /dev/null
> > > @@ -1,53 +0,0 @@
> > > -/** Soc.h
> > > -* Header defining the Base addresses, sizes, flags etc for chassis 1
> > > -*
> > > -* Copyright 2017-2020 NXP
> > > -*
> > > -* SPDX-License-Identifier: BSD-2-Clause-Patent
> > > -*
> > > -**/
> > > -
> > > -#ifndef NXP_SOC_H_
> > > -#define NXP_SOC_H_
> > > -
> > > -#define CLK_FREQ 100000000
> > > -
> > > -#define CHASSIS2_DCFG_ADDRESS 0x1EE0000
> > > -
> > > -/* SMMU Defintions */
> > > -#define SMMU_BASE_ADDR 0x09000000
> > > -#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
> > > -#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
> > > -#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
> > > -#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
> > > -#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
> > > -
> > > -#define SCR0_USFCFG_MASK 0x00000400
> > > -#define SCR0_CLIENTPD_MASK 0x00000001
> > > -#define SACR_PAGESIZE_MASK 0x00010000
> > > -#define IDR1_PAGESIZE_MASK 0x80000000
> > > -
> > > -typedef struct {
> > > - UINTN FreqSystemBus;
> > > -} SYS_INFO;
> > > -
> > > -/* Device Configuration and Pin Control */ -typedef struct {
> > > - UINT8 Res0[0x100-0x00];
> > > - UINT32 RcwSr[16]; /* Reset control word status */
> > > -#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25 -#define
> > > CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f -} CCSR_GUR;
> > > -
> > > -VOID
> > > -GetSysInfo (
> > > - OUT SYS_INFO *
> > > - );
> > > -
> > > -UINT32
> > > -EFIAPI
> > > -GurRead (
> > > - IN UINTN Address
> > > - );
> > > -
> > > -#endif /* NXP_SOC_H_ */
> > > diff --git a/Silicon/NXP/Include/Library/ChassisLib.h
> > > b/Silicon/NXP/Include/Library/ChassisLib.h
> > > index b51b024374..d07c59b82d 100644
> > > --- a/Silicon/NXP/Include/Library/ChassisLib.h
> > > +++ b/Silicon/NXP/Include/Library/ChassisLib.h
> > > @@ -9,8 +9,6 @@
> > > #ifndef __CHASSIS_LIB_H__
> > > #define __CHASSIS_LIB_H__
> > >
> > > -#include <Chassis.h>
> > > -
> > > /**
> > > Read Dcfg register
> > > **/
> > > diff --git a/Silicon/NXP/Include/Library/SocLib.h
> > > b/Silicon/NXP/Include/Library/SocLib.h
> > > index 3def396171..700e877bdf 100644
> > > --- a/Silicon/NXP/Include/Library/SocLib.h
> > > +++ b/Silicon/NXP/Include/Library/SocLib.h
> > > @@ -8,7 +8,6 @@
> > > #ifndef __SOC_LIB_H__
> > > #define __SOC_LIB_H__
> > >
> > > -#include <Soc.h>
> > > #include <Uefi.h>
> > > #include <Ppi/ArmMpCoreInfo.h>
> > > #include <Ppi/NxpPlatformGetClock.h>
> > > diff --git a/Silicon/NXP/LS1043A/Include/Soc.h
> > > b/Silicon/NXP/LS1043A/Include/Soc.h
> > > deleted file mode 100644
> > > index c1e00394af..0000000000
> > > --- a/Silicon/NXP/LS1043A/Include/Soc.h
> > > +++ /dev/null
> > > @@ -1,44 +0,0 @@
> > > -/** @file
> > > -
> > > - Copyright 2020 NXP
> > > -
> > > - SPDX-License-Identifier: BSD-2-Clause-Patent
> > > -
> > > -**/
> > > -#ifndef __SOC_H__
> > > -#define __SOC_H__
> > > -
> > > -/**
> > > - Soc Memory Map
> > > -**/
> > > -#define LS1043A_DRAM0_PHYS_ADDRESS 0x80000000
> > > -#define LS1043A_DRAM0_SIZE SIZE_2GB
> > > -#define LS1043A_DRAM1_PHYS_ADDRESS 0x880000000
> > > -#define LS1043A_DRAM1_SIZE 0x780000000 // 30 GB
> > > -
> > > -#define LS1043A_CCSR_PHYS_ADDRESS 0x1000000
> > > -#define LS1043A_CCSR_SIZE 0xF000000
> > > -
> > > -#define LS1043A_IFC0_PHYS_ADDRESS 0x60000000
> > > -#define LS1043A_IFC0_SIZE SIZE_512MB
> > > -#define LS1043A_IFC1_PHYS_ADDRESS 0x620000000
> > > -#define LS1043A_IFC1_SIZE 0xE0000000 // 3.5 GB
> > > -
> > > -#define LS1043A_QSPI_PHYS_ADDRESS 0x40000000
> > > -#define LS1043A_QSPI_SIZE SIZE_512MB
> > > -
> > > -#define LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS 0x500000000
> > > -#define LS1043A_QMAN_SW_PORTAL_SIZE SIZE_128MB
> > > -#define LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS 0x508000000
> > > -#define LS1043A_BMAN_SW_PORTAL_SIZE SIZE_128MB
> > > -
> > > -#define LS1043A_PCI0_PHYS_ADDRESS 0x4000000000
> > > -#define LS1043A_PCI1_PHYS_ADDRESS 0x4800000000
> > > -#define LS1043A_PCI2_PHYS_ADDRESS 0x5000000000
> > > -#define LS1043A_PCI_SIZE SIZE_32GB
> > > -
> > > -#define LS1043A_I2C0_PHYS_ADDRESS 0x2180000
> > > -#define LS1043A_I2C_SIZE 0x10000
> > > -#define LS1043A_I2C_NUM_CONTROLLERS 4
> > > -
> > > -#endif
> > > diff --git a/Silicon/NXP/LS1043A/LS1043A.dec
> > > b/Silicon/NXP/LS1043A/LS1043A.dec deleted file mode 100644 index
> > > cd79949790..0000000000
> > > --- a/Silicon/NXP/LS1043A/LS1043A.dec
> > > +++ /dev/null
> > > @@ -1,16 +0,0 @@
> > > -# LS1043A.dec
> > > -#
> > > -# Copyright 2017-2019 NXP
> > > -#
> > > -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#
> > > -
> > > -[Defines]
> > > - DEC_SPECIFICATION = 0x0001001A
> > > -
> > > -[Guids.common]
> > > - gNxpLs1043ATokenSpaceGuid = {0x6834fe45, 0x4aee, 0x4fc6, {0xbc,
> > 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
> > > -
> > > -[Includes]
> > > - Include
> > > diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > > b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > > deleted file mode 100644
> > > index 7ebbb1a495..0000000000
> > > --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > > +++ /dev/null
> > > @@ -1,33 +0,0 @@
> > > -# LS1043A.dsc
> > > -# LS1043A Soc package.
> > > -#
> > > -# Copyright 2017-2020 NXP
> > > -#
> > > -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#
> > > -
> > > -[LibraryClasses.common]
> > > - SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > > -
> > > SerialPortLib|Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPor
> > > tLib16550.inf
> > > -
> > > -
> > #################################################################
> > ####
> > > ###########
> > > -#
> > > -# Pcd Section - list of all EDK II PCD Entries defined by this
> > > Platform -#
> > > -
> > #################################################################
> > ####
> > > ###########
> > > -[PcdsDynamicDefault.common]
> > > -
> > > - #
> > > - # ARM General Interrupt Controller
> > > - gArmTokenSpaceGuid.PcdGicDistributorBase|0x01401000
> > > - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01402000
> > > -
> > > -[PcdsFixedAtBuild.common]
> > > - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
> > > -
> > > - #
> > > - # Big Endian IPs
> > > - #
> > > - gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
> > > -##
> > > diff --git
> > > a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> > > b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> > > index 6b2aa46ff6..2e35f09d8f 100644
> > > ---
> > > a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> > > +++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib1655
> > > +++ 0.c
> > > @@ -15,6 +15,9 @@
> > > #include <Library/PcdLib.h>
> > > #include <Library/IoLib.h>
> > > #include <Library/BaseLib.h>
> > > +#include <Ppi/NxpPlatformGetClock.h>
> > > +
> > > +extern NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi;
> > >
> > > //
> > > // 16550 UART register offsets and bitfields @@ -42,12 +45,6 @@
> > > #define B_UART_MSR_RI BIT6
> > > #define B_UART_MSR_DCD BIT7
> > >
> > > -extern
> > > -UINT64
> > > -GetBusFrequency (
> > > - VOID
> > > - );
> > > -
> > > /**
> > > Read an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is
> > read from
> > > MMIO space. If PcdSerialUseMmio is FALSE, then the value is read
> > > from I/O space. The @@ -577,7 +574,7 @@ SerialPortSetAttributes (
> > > return RETURN_UNSUPPORTED;
> > > }
> > >
> > > - SerialClock = GetBusFrequency ();
> > > + SerialClock = mPlatformGetClockPpi.PlatformGetClock
> > > + (NXP_UART_CLOCK, 0);
> > > if (SerialClock == 0) {
> > > return EFI_DEVICE_ERROR;
> > > }
> > > diff --git
> > > a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.in
> > > f
> > > b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.in
> > > f
> > > index 45ae9dc0af..7823bc5be5 100644
> > > ---
> > > a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.in
> > > f
> > > +++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib1655
> > > +++ 0.inf
> > > @@ -19,11 +19,12 @@
> > > [Packages]
> > > MdePkg/MdePkg.dec
> > > MdeModulePkg/MdeModulePkg.dec
> > > + Silicon/NXP/NxpQoriqLs.dec
> > >
> > > [LibraryClasses]
> > > PcdLib
> > > IoLib
> > > - SocLib
> > > + ArmPlatformLib
> > >
> > > [Sources]
> > > BaseSerialPortLib16550.c
> > > diff --git a/Silicon/NXP/Library/SocLib/Chassis.c
> > > b/Silicon/NXP/Library/SocLib/Chassis.c
> > > deleted file mode 100644
> > > index 1ef99e8de2..0000000000
> > > --- a/Silicon/NXP/Library/SocLib/Chassis.c
> > > +++ /dev/null
> > > @@ -1,76 +0,0 @@
> > > -/** @file
> > > - SoC specific Library containg functions to initialize various SoC
> > > components
> > > -
> > > - Copyright 2017-2020 NXP
> > > -
> > > - SPDX-License-Identifier: BSD-2-Clause-Patent
> > > -
> > > -**/
> > > -
> > > -#include <Base.h>
> > > -#ifdef CHASSIS2
> > > -#include <Chassis2/NxpSoc.h>
> > > -#elif CHASSIS3
> > > -#include <Chassis3/NxpSoc.h>
> > > -#endif
> > > -#include <Library/ArmSmcLib.h>
> > > -#include <Library/BaseLib.h>
> > > -#include <Library/IoAccessLib.h>
> > > -#include <Library/DebugLib.h>
> > > -#include <Library/IoLib.h>
> > > -#include <Library/PcdLib.h>
> > > -#include <Library/PrintLib.h>
> > > -#include <Library/SerialPortLib.h>
> > > -
> > > -#include "NxpChassis.h"
> > > -
> > > -UINT32
> > > -EFIAPI
> > > -GurRead (
> > > - IN UINTN Address
> > > - )
> > > -{
> > > - if (FixedPcdGetBool (PcdGurBigEndian)) {
> > > - return SwapMmioRead32 (Address);
> > > - } else {
> > > - return MmioRead32 (Address);
> > > - }
> > > -}
> > > -
> > > -/*
> > > - * Return system bus frequency
> > > - */
> > > -UINT64
> > > -GetBusFrequency (
> > > - VOID
> > > - )
> > > -{
> > > - SYS_INFO SocSysInfo;
> > > -
> > > - GetSysInfo (&SocSysInfo);
> > > -
> > > - return SocSysInfo.FreqSystemBus;
> > > -}
> > > -
> > > -/*
> > > - * Setup SMMU in bypass mode
> > > - * and also set its pagesize
> > > - */
> > > -VOID
> > > -SmmuInit (
> > > - VOID
> > > - )
> > > -{
> > > - UINT32 Value;
> > > -
> > > - /* set pagesize as 64K and ssmu-500 in bypass mode */
> > > - Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
> > > - MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
> > > -
> > > - Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK)
> > &
> > > ~SCR0_USFCFG_MASK;
> > > - MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
> > > -
> > > - Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) |
> > SCR0_CLIENTPD_MASK) &
> > > ~SCR0_USFCFG_MASK;
> > > - MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value); -}
> > > -
> > > diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > > b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > > deleted file mode 100644
> > > index a3dabc93d1..0000000000
> > > --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > > +++ /dev/null
> > > @@ -1,96 +0,0 @@
> > > -/** @Soc.c
> > > - SoC specific Library containg functions to initialize various SoC
> > > components
> > > -
> > > - Copyright 2017-2020 NXP
> > > -
> > > - SPDX-License-Identifier: BSD-2-Clause-Patent
> > > -
> > > -**/
> > > -
> > > -#include <Base.h>
> > > -#include <NxpChassis.h>
> > > -#include <Chassis2/NxpSoc.h>
> > > -#include <Library/BaseLib.h>
> > > -#include <Library/BaseMemoryLib.h>
> > > -#include <Library/DebugLib.h>
> > > -#include <Library/IoAccessLib.h>
> > > -#include <Library/IoLib.h>
> > > -#include <Library/PcdLib.h>
> > > -#include <Library/PrintLib.h>
> > > -#include <Library/SerialPortLib.h>
> > > -
> > > -/**
> > > - Calculate the frequency of various controllers and
> > > - populate the passed structure with frequuencies.
> > > -
> > > - @param PtrSysInfo Input structure to populate with
> > > - frequencies.
> > > -**/
> > > -VOID
> > > -GetSysInfo (
> > > - OUT SYS_INFO *PtrSysInfo
> > > - )
> > > -{
> > > - CCSR_GUR *GurBase;
> > > - UINTN SysClk;
> > > -
> > > - GurBase = (CCSR_GUR *)CHASSIS2_DCFG_ADDRESS;
> > > - SysClk = CLK_FREQ;
> > > -
> > > - SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
> > > -
> > > - PtrSysInfo->FreqSystemBus = SysClk;
> > > -
> > > - //
> > > - // selects the platform clock:SYSCLK ratio and calculate
> > > - // system frequency
> > > - //
> > > - PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
> > > - CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
> > > - CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
> > > -}
> > > -
> > > -/**
> > > - Function to initialize SoC specific constructs
> > > - CPU Info
> > > - SoC Personality
> > > - Board Personality
> > > - RCW prints
> > > - **/
> > > -VOID
> > > -SocInit (
> > > - VOID
> > > - )
> > > -{
> > > - UINT64 BaudRate;
> > > - UINT32 ReceiveFifoDepth;
> > > - EFI_PARITY_TYPE Parity;
> > > - UINT8 DataBits;
> > > - EFI_STOP_BITS_TYPE StopBits;
> > > - UINT32 Timeout;
> > > -
> > > - BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
> > > - ReceiveFifoDepth = 0; // Use default FIFO depth
> > > - Timeout = 0;
> > > - Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
> > > - DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
> > > - StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8
> > > (PcdUartDefaultStopBits);
> > > -
> > > - SmmuInit ();
> > > -
> > > - //
> > > - // Early init serial Port to get board information.
> > > - //
> > > - SerialPortSetAttributes (
> > > - &BaudRate,
> > > - &ReceiveFifoDepth,
> > > - &Timeout,
> > > - &Parity,
> > > - &DataBits,
> > > - &StopBits
> > > - );
> > > - DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a on %a)\n",
> > > - (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__,
> > __DATE__));
> > > -
> > > - return;
> > > -}
> > > diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > > b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > > deleted file mode 100644
> > > index d8707927b7..0000000000
> > > --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > > +++ /dev/null
> > > @@ -1,44 +0,0 @@
> > > -# @file
> > > -#
> > > -# Copyright 2017-2020 NXP
> > > -#
> > > -# SPDX-License-Identifier: BSD-2-Clause-Patent -#
> > > -
> > > -[Defines]
> > > - INF_VERSION = 0x0001001A
> > > - BASE_NAME = SocLib
> > > - FILE_GUID = e868c5ca-9729-43ae-bff4-438c67de8c68
> > > - MODULE_TYPE = BASE
> > > - VERSION_STRING = 1.0
> > > - LIBRARY_CLASS = SocLib
> > > -
> > > -[Packages]
> > > - ArmPkg/ArmPkg.dec
> > > - MdeModulePkg/MdeModulePkg.dec
> > > - MdePkg/MdePkg.dec
> > > - Silicon/NXP/NxpQoriqLs.dec
> > > - Silicon/NXP/LS1043A/LS1043A.dec
> > > -
> > > -[LibraryClasses]
> > > - ArmSmcLib
> > > - BaseLib
> > > - DebugLib
> > > - IoAccessLib
> > > - SerialPortLib
> > > -
> > > -[Sources.common]
> > > - Chassis.c
> > > - Chassis2/Soc.c
> > > -
> > > -[BuildOptions]
> > > - GCC:*_*_*_CC_FLAGS = -DCHASSIS2
> > > -
> > > -[FixedPcd]
> > > - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
> > > - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
> > > - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
> > > - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
> > > - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> > > - gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
> > > - gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
> > > diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h
> > > b/Silicon/NXP/Library/SocLib/NxpChassis.h
> > > deleted file mode 100644
> > > index 99f6439d8f..0000000000
> > > --- a/Silicon/NXP/Library/SocLib/NxpChassis.h
> > > +++ /dev/null
> > > @@ -1,136 +0,0 @@
> > > -/** @file
> > > -* Header defining the Base addresses, sizes, flags etc for chassis 1
> > > -*
> > > -* Copyright 2017-2019 NXP
> > > -*
> > > -* SPDX-License-Identifier: BSD-2-Clause-Patent
> > > -*
> > > -**/
> > > -
> > > -#ifndef NXP_CHASSIS_H_
> > > -#define NXP_CHASSIS_H_
> > > -
> > > -#define TP_ITYP_AV_MASK 0x00000001 /* Initiator available */
> > > -#define TP_ITYP_TYPE_MASK(x) (((x) & 0x6) >> 1) /* Initiator Type */
> > > -#define TP_ITYP_TYPE_ARM 0x0
> > > -#define TP_ITYP_TYPE_PPC 0x1
> > > -#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
> > > -#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
> > > -#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
> > > -#define TP_ITYP_VERSION(x) (((x) & 0xe0) >> 5) /* Initiator Version */
> > > -#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
> > > -#define TP_INIT_PER_CLUSTER 4
> > > -
> > > -#define TY_ITYP_VERSION_A7 0x1
> > > -#define TY_ITYP_VERSION_A53 0x2
> > > -#define TY_ITYP_VERSION_A57 0x3
> > > -#define TY_ITYP_VERSION_A72 0x4
> > > -
> > > -#define CPU_TYPE_ENTRY(N, V, NC) { .Name = #N, .SocVer =
> > SVR_##V, .NumCores = (NC)}
> > > -
> > > -#define SVR_WO_E 0xFFFFFE
> > > -#define SVR_LS1043A 0x879200
> > > -#define SVR_LS1046A 0x870700
> > > -#define SVR_LS2088A 0x870901
> > > -
> > > -#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
> > > -#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
> > > -#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
> > > -#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
> > > -
> > > -#define MHZ 1000000
> > > -
> > > -typedef struct {
> > > - CHAR8 *Name;
> > > - UINT32 SocVer;
> > > - UINT32 NumCores;
> > > -} CPU_TYPE;
> > > -
> > > -typedef struct {
> > > - UINTN CpuClk; /* CPU clock in Hz! */
> > > - UINTN BusClk;
> > > - UINTN MemClk;
> > > - UINTN PciClk;
> > > - UINTN SdhcClk;
> > > -} SOC_CLOCK_INFO;
> > > -
> > > -/*
> > > - * Print Soc information
> > > - */
> > > -VOID
> > > -PrintSoc (
> > > - VOID
> > > - );
> > > -
> > > -/*
> > > - * Initialize Clock structure
> > > - */
> > > -VOID
> > > -ClockInit (
> > > - VOID
> > > - );
> > > -
> > > -/*
> > > - * Setup SMMU in bypass mode
> > > - * and also set its pagesize
> > > - */
> > > -VOID
> > > -SmmuInit (
> > > - VOID
> > > - );
> > > -
> > > -/*
> > > - * Print CPU information
> > > - */
> > > -VOID
> > > -PrintCpuInfo (
> > > - VOID
> > > - );
> > > -
> > > -/*
> > > - * Dump RCW (Reset Control Word) on console
> > > - */
> > > -VOID
> > > -PrintRCW (
> > > - VOID
> > > - );
> > > -
> > > -UINT32
> > > -InitiatorType (
> > > - IN UINT32 Cluster,
> > > - IN UINTN InitId
> > > - );
> > > -
> > > -/*
> > > - * Return the mask for number of cores on this SOC.
> > > - */
> > > -UINT32
> > > -CpuMask (
> > > - VOID
> > > - );
> > > -
> > > -/*
> > > - * Return the number of cores on this SOC.
> > > - */
> > > -UINTN
> > > -CpuNumCores (
> > > - VOID
> > > - );
> > > -
> > > -/*
> > > - * Return the type of initiator for core/hardware accelerator for given core
> > index.
> > > - */
> > > -UINTN
> > > -QoriqCoreToType (
> > > - IN UINTN Core
> > > - );
> > > -
> > > -/*
> > > - * Return the cluster of initiator for core/hardware accelerator for given core
> > index.
> > > - */
> > > -INT32
> > > -QoriqCoreToCluster (
> > > - IN UINTN Core
> > > - );
> > > -
> > > -#endif /* NXP_CHASSIS_H_ */
> > > --
> > > 2.17.1
> > >
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 04/19] Silicon/NXP: Remove DuartLib and use BaseSerialPortLib16550
2020-02-10 5:48 ` Pankaj Bansal
@ 2020-02-12 23:27 ` Leif Lindholm
0 siblings, 0 replies; 49+ messages in thread
From: Leif Lindholm @ 2020-02-12 23:27 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi,
devel@edk2.groups.io
On Mon, Feb 10, 2020 at 05:48:47 +0000, Pankaj Bansal wrote:
>
>
> > -----Original Message-----
> > From: Leif Lindholm <leif@nuviainc.com>
> > Sent: Saturday, February 8, 2020 11:16 PM
> > To: Pankaj Bansal <pankaj.bansal@nxp.com>
> > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney
> > <michael.d.kinney@intel.com>; Varun Sethi <V.Sethi@nxp.com>;
> > devel@edk2.groups.io
> > Subject: Re: [PATCH 04/19] Silicon/NXP: Remove DuartLib and use
> > BaseSerialPortLib16550
> >
> > On Fri, Feb 07, 2020 at 18:13:13 +0530, Pankaj Bansal wrote:
> > > UART in LS1043A conforms to ns16550 register set. so we can use the
> > > SerialPortLib16550 from MdeModulePkg.
> >
> > 1) This patch adds a new library and deletes an existing one - those
> > are two operationsand hence should be two patches.
>
> OK. I can split the patch in two
>
> >
> > 2) That is irrelevant, because if you can use BaseSerialPortLib16550,
> > then use BaseSerialPortLib16550. Copying an existing library in
> > order to make some minor tweaks is not an option.
>
> If you look at the [PATCH 05/19] NXP/BaseSerialPortLib16550: remove SerialPortInitalize functionality
> (https://edk2.groups.io/g/devel/message/54011?p=,,,20,0,0,0::Created,,BaseSerialPortLib16550,20,2,0,71046325)
>
> I have removed SerialPortInitalize functionality, which I am
> guessing would not work for each platform using
> BaseSerialPortLib16550
> Which is why I have forked the BaseSerialPortLib16550 for NXP platforms.
Forking an existing driver in order to to change a few lines is not
maintainable and defeats the point of open source.
> >
> > > We have removed the PCIe specific part from the library and also added
> > > the APIs to get the UART clock from SOC lib instead of using the fixed
> > > PCD.
> >
> > So, what you need to do is update BaseSerialPortLib16550 to be usable
> > for you. This library is already used by several ARM platforms that
> > don't actually implement PCIe.
>
> Again, I can do that In the similar way we have done for PL011
> (https://github.com/tianocore/edk2/commit/cbba5ca104fbc8baa0c613951e833e1a07bb34df)
Yes, that sounds useful.
> But as I stated above, this is an unnecessary overhead which increases code size as well as execution time.
> Both of which we want to avoid.
> That is why we have forked BaseSerialPortLib16550 (and even PL011SerialPortLib for that matter for LX2160A) for NXP platforms.
I suggest we start with you submitting patches performing the
changes you need to make to the existing drivers, and we take it from
there dicussing how we can accomodate that without inconveniencing
other platforms.
Best Regards,
Leif
>
> >
> > > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> > > ---
> > > Silicon/NXP/LS1043A/LS1043A.dsc.inc | 2 +-
> > > .../BaseSerialPortLib16550.c | 804 ++++++++++++++++++
> > > .../BaseSerialPortLib16550.inf | 39 +
> > > .../BaseSerialPortLib16550.uni | 17 +
> >
> > Please don't leave out the --stat and --stat-graph-width when
> > following the format-patch instructions at
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.co
> > m%2Ftianocore%2Ftianocore.github.io%2Fwiki%2FLaszlo%2527s-unkempt-git-
> > guide-for-edk2-contributors-and-
> > maintainers&data=02%7C01%7Cpankaj.bansal%40nxp.com%7C696ddff166
> > 5a4367502608d7acbed0e8%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C
> > 0%7C637167807871085424&sdata=8tHGzseG00MNL1Hc62fFIxKGqcl0quW
> > Rq%2Bc9W%2BQRFRU%3D&reserved=0
> >
> > /
> > Leif
> >
> > > Silicon/NXP/Library/DUartPortLib/DUart.h | 122 ---
> > > .../NXP/Library/DUartPortLib/DUartPortLib.c | 364 --------
> > > .../NXP/Library/DUartPortLib/DUartPortLib.inf | 34 -
> > > 7 files changed, 861 insertions(+), 521 deletions(-)
> > > create mode 100644
> > Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> > > create mode 100644
> > Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
> > > create mode 100644
> > Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.uni
> > > delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUart.h
> > > delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
> > > delete mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> > >
> > > diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > > index 8790db6ff8..754eff396a 100644
> > > --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > > +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > > @@ -9,7 +9,7 @@
> > >
> > > [LibraryClasses.common]
> > > SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > > - SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> > > +
> > SerialPortLib|Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib165
> > 50.inf
> > >
> > >
> > #################################################################
> > ###############
> > > #
> > > diff --git
> > a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> > b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> > > new file mode 100644
> > > index 0000000000..2c5c54ac7d
> > > --- /dev/null
> > > +++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> > > @@ -0,0 +1,804 @@
> > > +/** @file
> > > + 16550 UART Serial Port library functions
> > > +
> > > + (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>
> > > + Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> > > + Copyright (c) 2018, AMD Incorporated. All rights reserved.<BR>
> > > + Copyright 2020 NXP
> > > +
> > > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > > +
> > > +**/
> > > +
> > > +#include <Base.h>
> > > +#include <Library/SerialPortLib.h>
> > > +#include <Library/PcdLib.h>
> > > +#include <Library/IoLib.h>
> > > +#include <Library/BaseLib.h>
> > > +
> > > +//
> > > +// 16550 UART register offsets and bitfields
> > > +//
> > > +#define R_UART_RXBUF 0 // LCR_DLAB = 0
> > > +#define R_UART_TXBUF 0 // LCR_DLAB = 0
> > > +#define R_UART_BAUD_LOW 0 // LCR_DLAB = 1
> > > +#define R_UART_BAUD_HIGH 1 // LCR_DLAB = 1
> > > +#define R_UART_IER 1 // LCR_DLAB = 0
> > > +#define R_UART_FCR 2
> > > +#define B_UART_FCR_FIFOE BIT0
> > > +#define B_UART_FCR_FIFO64 BIT5
> > > +#define R_UART_LCR 3
> > > +#define B_UART_LCR_DLAB BIT7
> > > +#define R_UART_MCR 4
> > > +#define B_UART_MCR_DTRC BIT0
> > > +#define B_UART_MCR_RTS BIT1
> > > +#define R_UART_LSR 5
> > > +#define B_UART_LSR_RXRDY BIT0
> > > +#define B_UART_LSR_TXRDY BIT5
> > > +#define B_UART_LSR_TEMT BIT6
> > > +#define R_UART_MSR 6
> > > +#define B_UART_MSR_CTS BIT4
> > > +#define B_UART_MSR_DSR BIT5
> > > +#define B_UART_MSR_RI BIT6
> > > +#define B_UART_MSR_DCD BIT7
> > > +
> > > +extern
> > > +UINT64
> > > +GetBusFrequency (
> > > + VOID
> > > + );
> > > +
> > > +/**
> > > + Read an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is
> > read from
> > > + MMIO space. If PcdSerialUseMmio is FALSE, then the value is read from I/O
> > space. The
> > > + parameter Offset is added to the base address of the 16550 registers that is
> > specified
> > > + by PcdSerialRegisterBase. PcdSerialRegisterAccessWidth specifies the MMIO
> > space access
> > > + width and defaults to 8 bit access, and supports 8 or 32 bit access.
> > > +
> > > + @param Base The base address register of UART device.
> > > + @param Offset The offset of the 16550 register to read.
> > > +
> > > + @return The value read from the 16550 register.
> > > +
> > > +**/
> > > +UINT8
> > > +SerialPortReadRegister (
> > > + UINTN Base,
> > > + UINTN Offset
> > > + )
> > > +{
> > > + return MmioRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride));
> > > +}
> > > +
> > > +/**
> > > + Write an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value
> > is written to
> > > + MMIO space. If PcdSerialUseMmio is FALSE, then the value is written to I/O
> > space. The
> > > + parameter Offset is added to the base address of the 16550 registers that is
> > specified
> > > + by PcdSerialRegisterBase. PcdSerialRegisterAccessWidth specifies the MMIO
> > space access
> > > + width and defaults to 8 bit access, and supports 8 or 32 bit access.
> > > +
> > > + @param Base The base address register of UART device.
> > > + @param Offset The offset of the 16550 register to write.
> > > + @param Value The value to write to the 16550 register specified by Offset.
> > > +
> > > + @return The value written to the 16550 register.
> > > +
> > > +**/
> > > +UINT8
> > > +SerialPortWriteRegister (
> > > + UINTN Base,
> > > + UINTN Offset,
> > > + UINT8 Value
> > > + )
> > > +{
> > > + return MmioWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride),
> > Value);
> > > +}
> > > +
> > > +/**
> > > + Retrieve the I/O or MMIO base address register for the PCI UART device.
> > > +
> > > + This function assumes Root Bus Numer is Zero, and enables I/O and MMIO
> > in PCI UART
> > > + Device if they are not already enabled.
> > > +
> > > + @return The base address register of the UART device.
> > > +
> > > +**/
> > > +UINTN
> > > +GetSerialRegisterBase (
> > > + VOID
> > > + )
> > > +{
> > > + return (UINTN)PcdGet64 (PcdSerialRegisterBase);
> > > +}
> > > +
> > > +/**
> > > + Return whether the hardware flow control signal allows writing.
> > > +
> > > + @param SerialRegisterBase The base address register of UART device.
> > > +
> > > + @retval TRUE The serial port is writable.
> > > + @retval FALSE The serial port is not writable.
> > > +**/
> > > +BOOLEAN
> > > +SerialPortWritable (
> > > + UINTN SerialRegisterBase
> > > + )
> > > +{
> > > + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
> > > + if (PcdGetBool (PcdSerialDetectCable)) {
> > > + //
> > > + // Wait for both DSR and CTS to be set
> > > + // DSR is set if a cable is connected.
> > > + // CTS is set if it is ok to transmit data
> > > + //
> > > + // DSR CTS Description Action
> > > + // === === ======================================== ========
> > > + // 0 0 No cable connected. Wait
> > > + // 0 1 No cable connected. Wait
> > > + // 1 0 Cable connected, but not clear to send. Wait
> > > + // 1 1 Cable connected, and clear to send. Transmit
> > > + //
> > > + return (BOOLEAN) ((SerialPortReadRegister (SerialRegisterBase,
> > R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) ==
> > (B_UART_MSR_DSR | B_UART_MSR_CTS));
> > > + } else {
> > > + //
> > > + // Wait for both DSR and CTS to be set OR for DSR to be clear.
> > > + // DSR is set if a cable is connected.
> > > + // CTS is set if it is ok to transmit data
> > > + //
> > > + // DSR CTS Description Action
> > > + // === === ======================================== ========
> > > + // 0 0 No cable connected. Transmit
> > > + // 0 1 No cable connected. Transmit
> > > + // 1 0 Cable connected, but not clear to send. Wait
> > > + // 1 1 Cable connected, and clar to send. Transmit
> > > + //
> > > + return (BOOLEAN) ((SerialPortReadRegister (SerialRegisterBase,
> > R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) !=
> > (B_UART_MSR_DSR));
> > > + }
> > > + }
> > > +
> > > + return TRUE;
> > > +}
> > > +
> > > +/**
> > > + Initialize the serial device hardware.
> > > +
> > > + If no initialization is required, then return RETURN_SUCCESS.
> > > + If the serial device was successfully initialized, then return
> > RETURN_SUCCESS.
> > > + If the serial device could not be initialized, then return
> > RETURN_DEVICE_ERROR.
> > > +
> > > + @retval RETURN_SUCCESS The serial device was initialized.
> > > + @retval RETURN_DEVICE_ERROR The serial device could not be initialized.
> > > +
> > > +**/
> > > +RETURN_STATUS
> > > +EFIAPI
> > > +SerialPortInitialize (
> > > + VOID
> > > + )
> > > +{
> > > + UINTN SerialRegisterBase;
> > > + UINT32 Divisor;
> > > + UINT32 CurrentDivisor;
> > > + BOOLEAN Initialized;
> > > + UINT64 SerialClock;
> > > +
> > > + //
> > > + // Perform platform specific initialization required to enable use of the
> > 16550 device
> > > + // at the location specified by PcdSerialUseMmio and PcdSerialRegisterBase.
> > > + //
> > > + SerialClock = GetBusFrequency ();
> > > + if (SerialClock == 0) {
> > > + return EFI_DEVICE_ERROR;
> > > + }
> > > +
> > > + //
> > > + // Calculate divisor for baud generator
> > > + // Ref_Clk_Rate / Baud_Rate / 16
> > > + //
> > > + Divisor = SerialClock / (PcdGet32 (PcdSerialBaudRate) * 16);
> > > + if ((SerialClock % (PcdGet32 (PcdSerialBaudRate) * 16)) >= PcdGet32
> > (PcdSerialBaudRate) * 8) {
> > > + Divisor++;
> > > + }
> > > +
> > > + //
> > > + // Get the base address of the serial port in either I/O or MMIO space
> > > + //
> > > + SerialRegisterBase = GetSerialRegisterBase ();
> > > + if (SerialRegisterBase == 0) {
> > > + return RETURN_DEVICE_ERROR;
> > > + }
> > > +
> > > + //
> > > + // See if the serial port is already initialized
> > > + //
> > > + Initialized = TRUE;
> > > + if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & 0x3F) !=
> > (PcdGet8 (PcdSerialLineControl) & 0x3F)) {
> > > + Initialized = FALSE;
> > > + }
> > > + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR,
> > (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) |
> > B_UART_LCR_DLAB));
> > > + CurrentDivisor = SerialPortReadRegister (SerialRegisterBase,
> > R_UART_BAUD_HIGH) << 8;
> > > + CurrentDivisor |= (UINT32) SerialPortReadRegister (SerialRegisterBase,
> > R_UART_BAUD_LOW);
> > > + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR,
> > (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) &
> > ~B_UART_LCR_DLAB));
> > > + if (CurrentDivisor != Divisor) {
> > > + Initialized = FALSE;
> > > + }
> > > + if (Initialized) {
> > > + return RETURN_SUCCESS;
> > > + }
> > > +
> > > + //
> > > + // Wait for the serial port to be ready.
> > > + // Verify that both the transmit FIFO and the shift register are empty.
> > > + //
> > > + while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) &
> > (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT |
> > B_UART_LSR_TXRDY));
> > > +
> > > + //
> > > + // Configure baud rate
> > > + //
> > > + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR,
> > B_UART_LCR_DLAB);
> > > + SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_HIGH, (UINT8)
> > (Divisor >> 8));
> > > + SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_LOW, (UINT8)
> > (Divisor & 0xff));
> > > +
> > > + //
> > > + // Clear DLAB and configure Data Bits, Parity, and Stop Bits.
> > > + // Strip reserved bits from PcdSerialLineControl
> > > + //
> > > + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(PcdGet8
> > (PcdSerialLineControl) & 0x3F));
> > > +
> > > + //
> > > + // Enable and reset FIFOs
> > > + // Strip reserved bits from PcdSerialFifoControl
> > > + //
> > > + SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, 0x00);
> > > + SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8
> > (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64)));
> > > +
> > > + //
> > > + // Set FIFO Polled Mode by clearing IER after setting FCR
> > > + //
> > > + SerialPortWriteRegister (SerialRegisterBase, R_UART_IER, 0x00);
> > > +
> > > + //
> > > + // Put Modem Control Register(MCR) into its reset state of 0x00.
> > > + //
> > > + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00);
> > > +
> > > + return RETURN_SUCCESS;
> > > +}
> > > +
> > > +/**
> > > + Write data from buffer to serial device.
> > > +
> > > + Writes NumberOfBytes data bytes from Buffer to the serial device.
> > > + The number of bytes actually written to the serial device is returned.
> > > + If the return value is less than NumberOfBytes, then the write operation
> > failed.
> > > +
> > > + If Buffer is NULL, then ASSERT().
> > > +
> > > + If NumberOfBytes is zero, then return 0.
> > > +
> > > + @param Buffer Pointer to the data buffer to be written.
> > > + @param NumberOfBytes Number of bytes to written to the serial device.
> > > +
> > > + @retval 0 NumberOfBytes is 0.
> > > + @retval >0 The number of bytes written to the serial device.
> > > + If this value is less than NumberOfBytes, then the write
> > operation failed.
> > > +
> > > +**/
> > > +UINTN
> > > +EFIAPI
> > > +SerialPortWrite (
> > > + IN UINT8 *Buffer,
> > > + IN UINTN NumberOfBytes
> > > + )
> > > +{
> > > + UINTN SerialRegisterBase;
> > > + UINTN Result;
> > > + UINTN Index;
> > > + UINTN FifoSize;
> > > +
> > > + if (Buffer == NULL) {
> > > + return 0;
> > > + }
> > > +
> > > + SerialRegisterBase = GetSerialRegisterBase ();
> > > + if (SerialRegisterBase ==0) {
> > > + return 0;
> > > + }
> > > +
> > > + if (NumberOfBytes == 0) {
> > > + //
> > > + // Flush the hardware
> > > + //
> > > +
> > > + //
> > > + // Wait for both the transmit FIFO and shift register empty.
> > > + //
> > > + while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) &
> > (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT |
> > B_UART_LSR_TXRDY));
> > > +
> > > + //
> > > + // Wait for the hardware flow control signal
> > > + //
> > > + while (!SerialPortWritable (SerialRegisterBase));
> > > + return 0;
> > > + }
> > > +
> > > + //
> > > + // Compute the maximum size of the Tx FIFO
> > > + //
> > > + FifoSize = 1;
> > > + if ((PcdGet8 (PcdSerialFifoControl) & B_UART_FCR_FIFOE) != 0) {
> > > + if ((PcdGet8 (PcdSerialFifoControl) & B_UART_FCR_FIFO64) == 0) {
> > > + FifoSize = 16;
> > > + } else {
> > > + FifoSize = PcdGet32 (PcdSerialExtendedTxFifoSize);
> > > + }
> > > + }
> > > +
> > > + Result = NumberOfBytes;
> > > + while (NumberOfBytes != 0) {
> > > + //
> > > + // Wait for the serial port to be ready, to make sure both the transmit FIFO
> > > + // and shift register empty.
> > > + //
> > > + while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) &
> > (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT |
> > B_UART_LSR_TXRDY));
> > > +
> > > + //
> > > + // Fill then entire Tx FIFO
> > > + //
> > > + for (Index = 0; Index < FifoSize && NumberOfBytes != 0; Index++,
> > NumberOfBytes--, Buffer++) {
> > > + //
> > > + // Wait for the hardware flow control signal
> > > + //
> > > + while (!SerialPortWritable (SerialRegisterBase));
> > > +
> > > + //
> > > + // Write byte to the transmit buffer.
> > > + //
> > > + SerialPortWriteRegister (SerialRegisterBase, R_UART_TXBUF, *Buffer);
> > > + }
> > > + }
> > > + return Result;
> > > +}
> > > +
> > > +/**
> > > + Reads data from a serial device into a buffer.
> > > +
> > > + @param Buffer Pointer to the data buffer to store the data read from
> > the serial device.
> > > + @param NumberOfBytes Number of bytes to read from the serial device.
> > > +
> > > + @retval 0 NumberOfBytes is 0.
> > > + @retval >0 The number of bytes read from the serial device.
> > > + If this value is less than NumberOfBytes, then the read
> > operation failed.
> > > +
> > > +**/
> > > +UINTN
> > > +EFIAPI
> > > +SerialPortRead (
> > > + OUT UINT8 *Buffer,
> > > + IN UINTN NumberOfBytes
> > > + )
> > > +{
> > > + UINTN SerialRegisterBase;
> > > + UINTN Result;
> > > + UINT8 Mcr;
> > > +
> > > + if (NULL == Buffer) {
> > > + return 0;
> > > + }
> > > +
> > > + SerialRegisterBase = GetSerialRegisterBase ();
> > > + if (SerialRegisterBase ==0) {
> > > + return 0;
> > > + }
> > > +
> > > + Mcr = (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) &
> > ~B_UART_MCR_RTS);
> > > +
> > > + for (Result = 0; NumberOfBytes-- != 0; Result++, Buffer++) {
> > > + //
> > > + // Wait for the serial port to have some data.
> > > + //
> > > + while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) &
> > B_UART_LSR_RXRDY) == 0) {
> > > + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
> > > + //
> > > + // Set RTS to let the peer send some data
> > > + //
> > > + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(Mcr
> > | B_UART_MCR_RTS));
> > > + }
> > > + }
> > > + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
> > > + //
> > > + // Clear RTS to prevent peer from sending data
> > > + //
> > > + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, Mcr);
> > > + }
> > > +
> > > + //
> > > + // Read byte from the receive buffer.
> > > + //
> > > + *Buffer = SerialPortReadRegister (SerialRegisterBase, R_UART_RXBUF);
> > > + }
> > > +
> > > + return Result;
> > > +}
> > > +
> > > +
> > > +/**
> > > + Polls a serial device to see if there is any data waiting to be read.
> > > +
> > > + Polls aserial device to see if there is any data waiting to be read.
> > > + If there is data waiting to be read from the serial device, then TRUE is
> > returned.
> > > + If there is no data waiting to be read from the serial device, then FALSE is
> > returned.
> > > +
> > > + @retval TRUE Data is waiting to be read from the serial device.
> > > + @retval FALSE There is no data waiting to be read from the serial
> > device.
> > > +
> > > +**/
> > > +BOOLEAN
> > > +EFIAPI
> > > +SerialPortPoll (
> > > + VOID
> > > + )
> > > +{
> > > + UINTN SerialRegisterBase;
> > > +
> > > + SerialRegisterBase = GetSerialRegisterBase ();
> > > + if (SerialRegisterBase ==0) {
> > > + return FALSE;
> > > + }
> > > +
> > > + //
> > > + // Read the serial port status
> > > + //
> > > + if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) &
> > B_UART_LSR_RXRDY) != 0) {
> > > + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
> > > + //
> > > + // Clear RTS to prevent peer from sending data
> > > + //
> > > + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR,
> > (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) &
> > ~B_UART_MCR_RTS));
> > > + }
> > > + return TRUE;
> > > + }
> > > +
> > > + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
> > > + //
> > > + // Set RTS to let the peer send some data
> > > + //
> > > + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR,
> > (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) |
> > B_UART_MCR_RTS));
> > > + }
> > > +
> > > + return FALSE;
> > > +}
> > > +
> > > +/**
> > > + Sets the control bits on a serial device.
> > > +
> > > + @param Control Sets the bits of Control that are settable.
> > > +
> > > + @retval RETURN_SUCCESS The new control bits were set on the serial
> > device.
> > > + @retval RETURN_UNSUPPORTED The serial device does not support this
> > operation.
> > > + @retval RETURN_DEVICE_ERROR The serial device is not functioning
> > correctly.
> > > +
> > > +**/
> > > +RETURN_STATUS
> > > +EFIAPI
> > > +SerialPortSetControl (
> > > + IN UINT32 Control
> > > + )
> > > +{
> > > + UINTN SerialRegisterBase;
> > > + UINT8 Mcr;
> > > +
> > > + //
> > > + // First determine the parameter is invalid.
> > > + //
> > > + if ((Control & (~(EFI_SERIAL_REQUEST_TO_SEND |
> > EFI_SERIAL_DATA_TERMINAL_READY |
> > > + EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE))) != 0) {
> > > + return RETURN_UNSUPPORTED;
> > > + }
> > > +
> > > + SerialRegisterBase = GetSerialRegisterBase ();
> > > + if (SerialRegisterBase ==0) {
> > > + return RETURN_UNSUPPORTED;
> > > + }
> > > +
> > > + //
> > > + // Read the Modem Control Register.
> > > + //
> > > + Mcr = SerialPortReadRegister (SerialRegisterBase, R_UART_MCR);
> > > + Mcr &= (~(B_UART_MCR_DTRC | B_UART_MCR_RTS));
> > > +
> > > + if ((Control & EFI_SERIAL_DATA_TERMINAL_READY) ==
> > EFI_SERIAL_DATA_TERMINAL_READY) {
> > > + Mcr |= B_UART_MCR_DTRC;
> > > + }
> > > +
> > > + if ((Control & EFI_SERIAL_REQUEST_TO_SEND) ==
> > EFI_SERIAL_REQUEST_TO_SEND) {
> > > + Mcr |= B_UART_MCR_RTS;
> > > + }
> > > +
> > > + //
> > > + // Write the Modem Control Register.
> > > + //
> > > + SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, Mcr);
> > > +
> > > + return RETURN_SUCCESS;
> > > +}
> > > +
> > > +/**
> > > + Retrieve the status of the control bits on a serial device.
> > > +
> > > + @param Control A pointer to return the current control signals from
> > the serial device.
> > > +
> > > + @retval RETURN_SUCCESS The control bits were read from the serial
> > device.
> > > + @retval RETURN_UNSUPPORTED The serial device does not support this
> > operation.
> > > + @retval RETURN_DEVICE_ERROR The serial device is not functioning
> > correctly.
> > > +
> > > +**/
> > > +RETURN_STATUS
> > > +EFIAPI
> > > +SerialPortGetControl (
> > > + OUT UINT32 *Control
> > > + )
> > > +{
> > > + UINTN SerialRegisterBase;
> > > + UINT8 Msr;
> > > + UINT8 Mcr;
> > > + UINT8 Lsr;
> > > +
> > > + SerialRegisterBase = GetSerialRegisterBase ();
> > > + if (SerialRegisterBase ==0) {
> > > + return RETURN_UNSUPPORTED;
> > > + }
> > > +
> > > + *Control = 0;
> > > +
> > > + //
> > > + // Read the Modem Status Register.
> > > + //
> > > + Msr = SerialPortReadRegister (SerialRegisterBase, R_UART_MSR);
> > > +
> > > + if ((Msr & B_UART_MSR_CTS) == B_UART_MSR_CTS) {
> > > + *Control |= EFI_SERIAL_CLEAR_TO_SEND;
> > > + }
> > > +
> > > + if ((Msr & B_UART_MSR_DSR) == B_UART_MSR_DSR) {
> > > + *Control |= EFI_SERIAL_DATA_SET_READY;
> > > + }
> > > +
> > > + if ((Msr & B_UART_MSR_RI) == B_UART_MSR_RI) {
> > > + *Control |= EFI_SERIAL_RING_INDICATE;
> > > + }
> > > +
> > > + if ((Msr & B_UART_MSR_DCD) == B_UART_MSR_DCD) {
> > > + *Control |= EFI_SERIAL_CARRIER_DETECT;
> > > + }
> > > +
> > > + //
> > > + // Read the Modem Control Register.
> > > + //
> > > + Mcr = SerialPortReadRegister (SerialRegisterBase, R_UART_MCR);
> > > +
> > > + if ((Mcr & B_UART_MCR_DTRC) == B_UART_MCR_DTRC) {
> > > + *Control |= EFI_SERIAL_DATA_TERMINAL_READY;
> > > + }
> > > +
> > > + if ((Mcr & B_UART_MCR_RTS) == B_UART_MCR_RTS) {
> > > + *Control |= EFI_SERIAL_REQUEST_TO_SEND;
> > > + }
> > > +
> > > + if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
> > > + *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
> > > + }
> > > +
> > > + //
> > > + // Read the Line Status Register.
> > > + //
> > > + Lsr = SerialPortReadRegister (SerialRegisterBase, R_UART_LSR);
> > > +
> > > + if ((Lsr & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) ==
> > (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) {
> > > + *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
> > > + }
> > > +
> > > + if ((Lsr & B_UART_LSR_RXRDY) == 0) {
> > > + *Control |= EFI_SERIAL_INPUT_BUFFER_EMPTY;
> > > + }
> > > +
> > > + return RETURN_SUCCESS;
> > > +}
> > > +
> > > +/**
> > > + Sets the baud rate, receive FIFO depth, transmit/receice time out, parity,
> > > + data bits, and stop bits on a serial device.
> > > +
> > > + @param BaudRate The requested baud rate. A BaudRate value of 0
> > will use the
> > > + device's default interface speed.
> > > + On output, the value actually set.
> > > + @param ReveiveFifoDepth The requested depth of the FIFO on the receive
> > side of the
> > > + serial interface. A ReceiveFifoDepth value of 0 will use
> > > + the device's default FIFO depth.
> > > + On output, the value actually set.
> > > + @param Timeout The requested time out for a single character in
> > microseconds.
> > > + This timeout applies to both the transmit and receive side of
> > the
> > > + interface. A Timeout value of 0 will use the device's default
> > time
> > > + out value.
> > > + On output, the value actually set.
> > > + @param Parity The type of parity to use on this serial device. A Parity
> > value of
> > > + DefaultParity will use the device's default parity value.
> > > + On output, the value actually set.
> > > + @param DataBits The number of data bits to use on the serial device.
> > A DataBits
> > > + vaule of 0 will use the device's default data bit setting.
> > > + On output, the value actually set.
> > > + @param StopBits The number of stop bits to use on this serial device.
> > A StopBits
> > > + value of DefaultStopBits will use the device's default number
> > of
> > > + stop bits.
> > > + On output, the value actually set.
> > > +
> > > + @retval RETURN_SUCCESS The new attributes were set on the serial
> > device.
> > > + @retval RETURN_UNSUPPORTED The serial device does not support this
> > operation.
> > > + @retval RETURN_INVALID_PARAMETER One or more of the attributes has
> > an unsupported value.
> > > + @retval RETURN_DEVICE_ERROR The serial device is not functioning
> > correctly.
> > > +
> > > +**/
> > > +RETURN_STATUS
> > > +EFIAPI
> > > +SerialPortSetAttributes (
> > > + IN OUT UINT64 *BaudRate,
> > > + IN OUT UINT32 *ReceiveFifoDepth,
> > > + IN OUT UINT32 *Timeout,
> > > + IN OUT EFI_PARITY_TYPE *Parity,
> > > + IN OUT UINT8 *DataBits,
> > > + IN OUT EFI_STOP_BITS_TYPE *StopBits
> > > + )
> > > +{
> > > + UINTN SerialRegisterBase;
> > > + UINT32 SerialBaudRate;
> > > + UINTN Divisor;
> > > + UINT8 Lcr;
> > > + UINT8 LcrData;
> > > + UINT8 LcrParity;
> > > + UINT8 LcrStop;
> > > + UINT64 SerialClock;
> > > +
> > > + SerialRegisterBase = GetSerialRegisterBase ();
> > > + if (SerialRegisterBase ==0) {
> > > + return RETURN_UNSUPPORTED;
> > > + }
> > > +
> > > + SerialClock = GetBusFrequency ();
> > > + if (SerialClock == 0) {
> > > + return EFI_DEVICE_ERROR;
> > > + }
> > > +
> > > + //
> > > + // Check for default settings and fill in actual values.
> > > + //
> > > + if (*BaudRate == 0) {
> > > + *BaudRate = PcdGet32 (PcdSerialBaudRate);
> > > + }
> > > + SerialBaudRate = (UINT32) *BaudRate;
> > > +
> > > + if (*DataBits == 0) {
> > > + LcrData = (UINT8) (PcdGet8 (PcdSerialLineControl) & 0x3);
> > > + *DataBits = LcrData + 5;
> > > + } else {
> > > + if ((*DataBits < 5) || (*DataBits > 8)) {
> > > + return RETURN_INVALID_PARAMETER;
> > > + }
> > > + //
> > > + // Map 5..8 to 0..3
> > > + //
> > > + LcrData = (UINT8) (*DataBits - (UINT8) 5);
> > > + }
> > > +
> > > + if (*Parity == DefaultParity) {
> > > + LcrParity = (UINT8) ((PcdGet8 (PcdSerialLineControl) >> 3) & 0x7);
> > > + switch (LcrParity) {
> > > + case 0:
> > > + *Parity = NoParity;
> > > + break;
> > > +
> > > + case 3:
> > > + *Parity = EvenParity;
> > > + break;
> > > +
> > > + case 1:
> > > + *Parity = OddParity;
> > > + break;
> > > +
> > > + case 7:
> > > + *Parity = SpaceParity;
> > > + break;
> > > +
> > > + case 5:
> > > + *Parity = MarkParity;
> > > + break;
> > > +
> > > + default:
> > > + break;
> > > + }
> > > + } else {
> > > + switch (*Parity) {
> > > + case NoParity:
> > > + LcrParity = 0;
> > > + break;
> > > +
> > > + case EvenParity:
> > > + LcrParity = 3;
> > > + break;
> > > +
> > > + case OddParity:
> > > + LcrParity = 1;
> > > + break;
> > > +
> > > + case SpaceParity:
> > > + LcrParity = 7;
> > > + break;
> > > +
> > > + case MarkParity:
> > > + LcrParity = 5;
> > > + break;
> > > +
> > > + default:
> > > + return RETURN_INVALID_PARAMETER;
> > > + }
> > > + }
> > > +
> > > + if (*StopBits == DefaultStopBits) {
> > > + LcrStop = (UINT8) ((PcdGet8 (PcdSerialLineControl) >> 2) & 0x1);
> > > + switch (LcrStop) {
> > > + case 0:
> > > + *StopBits = OneStopBit;
> > > + break;
> > > +
> > > + case 1:
> > > + if (*DataBits == 5) {
> > > + *StopBits = OneFiveStopBits;
> > > + } else {
> > > + *StopBits = TwoStopBits;
> > > + }
> > > + break;
> > > +
> > > + default:
> > > + break;
> > > + }
> > > + } else {
> > > + switch (*StopBits) {
> > > + case OneStopBit:
> > > + LcrStop = 0;
> > > + break;
> > > +
> > > + case OneFiveStopBits:
> > > + case TwoStopBits:
> > > + LcrStop = 1;
> > > + break;
> > > +
> > > + default:
> > > + return RETURN_INVALID_PARAMETER;
> > > + }
> > > + }
> > > +
> > > + //
> > > + // Calculate divisor for baud generator
> > > + // Ref_Clk_Rate / Baud_Rate / 16
> > > + //
> > > + Divisor = SerialClock / (SerialBaudRate * 16);
> > > + if ((SerialClock % (SerialBaudRate * 16)) >= SerialBaudRate * 8) {
> > > + Divisor++;
> > > + }
> > > +
> > > + //
> > > + // Configure baud rate
> > > + //
> > > + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR,
> > B_UART_LCR_DLAB);
> > > + SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_HIGH, (UINT8)
> > (Divisor >> 8));
> > > + SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_LOW, (UINT8)
> > (Divisor & 0xff));
> > > +
> > > + //
> > > + // Clear DLAB and configure Data Bits, Parity, and Stop Bits.
> > > + // Strip reserved bits from line control value
> > > + //
> > > + Lcr = (UINT8) ((LcrParity << 3) | (LcrStop << 2) | LcrData);
> > > + SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8) (Lcr &
> > 0x3F));
> > > +
> > > + return RETURN_SUCCESS;
> > > +}
> > > +
> > > diff --git
> > a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
> > b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
> > > new file mode 100644
> > > index 0000000000..45ae9dc0af
> > > --- /dev/null
> > > +++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
> > > @@ -0,0 +1,39 @@
> > > +## @file
> > > +# SerialPortLib instance for 16550 UART.
> > > +#
> > > +# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> > > +# Copyright 2020 NXP
> > > +# SPDX-License-Identifier: BSD-2-Clause-Patent
> > > +#
> > > +##
> > > +
> > > +[Defines]
> > > + INF_VERSION = 0x00010005
> > > + BASE_NAME = BaseSerialPortLib16550
> > > + MODULE_UNI_FILE = BaseSerialPortLib16550.uni
> > > + FILE_GUID = 9E7C00CF-355A-4d4e-BF60-0428CFF95540
> > > + MODULE_TYPE = BASE
> > > + VERSION_STRING = 1.1
> > > + LIBRARY_CLASS = SerialPortLib
> > > +
> > > +[Packages]
> > > + MdePkg/MdePkg.dec
> > > + MdeModulePkg/MdeModulePkg.dec
> > > +
> > > +[LibraryClasses]
> > > + PcdLib
> > > + IoLib
> > > + SocLib
> > > +
> > > +[Sources]
> > > + BaseSerialPortLib16550.c
> > > +
> > > +[FixedPcd]
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl ##
> > CONSUMES
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable ##
> > SOMETIMES_CONSUMES
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ##
> > CONSUMES
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ##
> > CONSUMES
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl ##
> > CONSUMES
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl ##
> > CONSUMES
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize ##
> > CONSUMES
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride ##
> > CONSUMES
> > > diff --git
> > a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.uni
> > b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.uni
> > > new file mode 100644
> > > index 0000000000..2fefe85cf8
> > > --- /dev/null
> > > +++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.uni
> > > @@ -0,0 +1,17 @@
> > > +// /** @file
> > > +// SerialPortLib instance for 16550 UART.
> > > +//
> > > +// SerialPortLib instance for 16550 UART.
> > > +//
> > > +// Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> > > +// Copyright 2020 NXP
> > > +//
> > > +// SPDX-License-Identifier: BSD-2-Clause-Patent
> > > +//
> > > +// **/
> > > +
> > > +
> > > +#string STR_MODULE_ABSTRACT #language en-US "SerialPortLib
> > instance for 16550 UART"
> > > +
> > > +#string STR_MODULE_DESCRIPTION #language en-US "SerialPortLib
> > instance for 16550 UART."
> > > +
> > > diff --git a/Silicon/NXP/Library/DUartPortLib/DUart.h
> > b/Silicon/NXP/Library/DUartPortLib/DUart.h
> > > deleted file mode 100644
> > > index c71e2ce55d..0000000000
> > > --- a/Silicon/NXP/Library/DUartPortLib/DUart.h
> > > +++ /dev/null
> > > @@ -1,122 +0,0 @@
> > > -/** DUart.h
> > > -* Header defining the DUART constants (Base addresses, sizes, flags)
> > > -*
> > > -* Based on Serial I/O Port library headers available in PL011Uart.h
> > > -*
> > > -* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
> > > -* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> > > -* Copyright 2017 NXP
> > > -*
> > > -* SPDX-License-Identifier: BSD-2-Clause-Patent
> > > -*
> > > -**/
> > > -
> > > -#ifndef DUART_H_
> > > -#define DUART_H_
> > > -
> > > -// FIFO Control Register
> > > -#define DUART_FCR_FIFO_EN 0x01 /* Fifo enable */
> > > -#define DUART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
> > > -#define DUART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
> > > -#define DUART_FCR_DMA_SELECT 0x08 /* For DMA applications */
> > > -#define DUART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger
> > range */
> > > -#define DUART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
> > > -#define DUART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
> > > -#define DUART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
> > > -#define DUART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
> > > -#define DUART_FCR_RXSR 0x02 /* Receiver soft reset */
> > > -#define DUART_FCR_TXSR 0x04 /* Transmitter soft reset */
> > > -
> > > -// Modem Control Register
> > > -#define DUART_MCR_DTR 0x01 /* Reserved */
> > > -#define DUART_MCR_RTS 0x02 /* RTS */
> > > -#define DUART_MCR_OUT1 0x04 /* Reserved */
> > > -#define DUART_MCR_OUT2 0x08 /* Reserved */
> > > -#define DUART_MCR_LOOP 0x10 /* Enable loopback test mode */
> > > -#define DUART_MCR_AFE 0x20 /* AFE (Auto Flow Control) */
> > > -#define DUART_MCR_DMA_EN 0x04
> > > -#define DUART_MCR_TX_DFR 0x08
> > > -
> > > -// Line Control Register
> > > -/*
> > > -* Note: if the word length is 5 bits (DUART_LCR_WLEN5), then setting
> > > -* DUART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
> > > -*/
> > > -#define DUART_LCR_WLS_MSK 0x03 /* character length select mask */
> > > -#define DUART_LCR_WLS_5 0x00 /* 5 bit character length */
> > > -#define DUART_LCR_WLS_6 0x01 /* 6 bit character length */
> > > -#define DUART_LCR_WLS_7 0x02 /* 7 bit character length */
> > > -#define DUART_LCR_WLS_8 0x03 /* 8 bit character length */
> > > -#define DUART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
> > > -#define DUART_LCR_PEN 0x08 /* Parity eneble */
> > > -#define DUART_LCR_EPS 0x10 /* Even Parity Select */
> > > -#define DUART_LCR_STKP 0x20 /* Stick Parity */
> > > -#define DUART_LCR_SBRK 0x40 /* Set Break */
> > > -#define DUART_LCR_BKSE 0x80 /* Bank select enable */
> > > -#define DUART_LCR_DLAB 0x80 /* Divisor latch access bit */
> > > -
> > > -// Line Status Register
> > > -#define DUART_LSR_DR 0x01 /* Data ready */
> > > -#define DUART_LSR_OE 0x02 /* Overrun */
> > > -#define DUART_LSR_PE 0x04 /* Parity error */
> > > -#define DUART_LSR_FE 0x08 /* Framing error */
> > > -#define DUART_LSR_BI 0x10 /* Break */
> > > -#define DUART_LSR_THRE 0x20 /* Xmit holding register empty */
> > > -#define DUART_LSR_TEMT 0x40 /* Xmitter empty */
> > > -#define DUART_LSR_ERR 0x80 /* Error */
> > > -
> > > -// Modem Status Register
> > > -#define DUART_MSR_DCTS 0x01 /* Delta CTS */
> > > -#define DUART_MSR_DDSR 0x02 /* Reserved */
> > > -#define DUART_MSR_TERI 0x04 /* Reserved */
> > > -#define DUART_MSR_DDCD 0x08 /* Reserved */
> > > -#define DUART_MSR_CTS 0x10 /* Clear to Send */
> > > -#define DUART_MSR_DSR 0x20 /* Reserved */
> > > -#define DUART_MSR_RI 0x40 /* Reserved */
> > > -#define DUART_MSR_DCD 0x80 /* Reserved */
> > > -
> > > -// Interrupt Identification Register
> > > -#define DUART_IIR_NO_INT 0x01 /* No interrupts pending */
> > > -#define DUART_IIR_ID 0x06 /* Mask for the interrupt ID */
> > > -#define DUART_IIR_MSI 0x00 /* Modem status interrupt */
> > > -#define DUART_IIR_THRI 0x02 /* Transmitter holding register empty */
> > > -#define DUART_IIR_RDI 0x04 /* Receiver data interrupt */
> > > -#define DUART_IIR_RLSI 0x06 /* Receiver line status interrupt */
> > > -
> > > -// Interrupt Enable Register
> > > -#define DUART_IER_MSI 0x08 /* Enable Modem status interrupt */
> > > -#define DUART_IER_RLSI 0x04 /* Enable receiver line status interrupt
> > */
> > > -#define DUART_IER_THRI 0x02 /* Enable Transmitter holding register
> > int. */
> > > -#define DUART_IER_RDI 0x01 /* Enable receiver data interrupt */
> > > -
> > > -// LCR defaults
> > > -#define DUART_LCR_8N1 0x03
> > > -#define DUART_LCRVAL DUART_LCR_8N1 /* 8 data, 1 stop, no
> > parity */
> > > -#define DUART_MCRVAL (DUART_MCR_DTR | \
> > > - DUART_MCR_RTS) /* RTS/DTR */
> > > -#define DUART_FCRVAL (DUART_FCR_FIFO_EN | \
> > > - DUART_FCR_RXSR | \
> > > - DUART_FCR_TXSR) /* Clear & enable FIFOs */
> > > -
> > > -#define URBR 0x0
> > > -#define UTHR 0x0
> > > -#define UDLB 0x0
> > > -#define UDMB 0x1
> > > -#define UIER 0x1
> > > -#define UIIR 0x2
> > > -#define UFCR 0x2
> > > -#define UAFR 0x2
> > > -#define ULCR 0x3
> > > -#define UMCR 0x4
> > > -#define ULSR 0x5
> > > -#define UMSR 0x6
> > > -#define USCR 0x7
> > > -#define UDSR 0x10
> > > -
> > > -extern
> > > -UINT64
> > > -GetBusFrequency (
> > > - VOID
> > > - );
> > > -
> > > -#endif /* DUART_H_ */
> > > diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
> > b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
> > > deleted file mode 100644
> > > index c3c738d3cc..0000000000
> > > --- a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
> > > +++ /dev/null
> > > @@ -1,364 +0,0 @@
> > > -/** DuartPortLib.c
> > > - DUART (NS16550) library functions
> > > -
> > > - Based on Serial I/O Port library functions available in PL011SerialPortLib.c
> > > -
> > > - Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
> > > - Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.<BR>
> > > - Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> > > - Copyright 2017 NXP
> > > -
> > > - SPDX-License-Identifier: BSD-2-Clause-Patent
> > > -
> > > -**/
> > > -
> > > -#include <Base.h>
> > > -#include <Library/IoLib.h>
> > > -#include <Library/PcdLib.h>
> > > -#include <Library/SerialPortLib.h>
> > > -
> > > -#include "DUart.h"
> > > -
> > > -STATIC CONST UINT32 mInvalidControlBits =
> > (EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE | \
> > > - EFI_SERIAL_DATA_TERMINAL_READY);
> > > -
> > > -/**
> > > - Assert or deassert the control signals on a serial port.
> > > - The following control signals are set according their bit settings :
> > > - . Request to Send
> > > - . Data Terminal Ready
> > > -
> > > - @param[in] Control The following bits are taken into account :
> > > - . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the
> > > - "Request To Send" control signal if this bit is
> > > - equal to one/zero.
> > > - . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert
> > > - the "Data Terminal Ready" control signal if this
> > > - bit is equal to one/zero.
> > > - . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable
> > > - the hardware loopback if this bit is equal to
> > > - one/zero.
> > > - . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.
> > > - . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/
> > > - disable the hardware flow control based on CTS (Clear
> > > - To Send) and RTS (Ready To Send) control signals.
> > > -
> > > - @retval EFI_SUCCESS The new control bits were set on the device.
> > > - @retval EFI_UNSUPPORTED The device does not support this operation.
> > > -
> > > -**/
> > > -EFI_STATUS
> > > -EFIAPI
> > > -SerialPortSetControl (
> > > - IN UINT32 Control
> > > - )
> > > -{
> > > - UINT32 McrBits;
> > > - UINTN UartBase;
> > > -
> > > - UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> > > -
> > > - if (Control & (mInvalidControlBits)) {
> > > - return EFI_UNSUPPORTED;
> > > - }
> > > -
> > > - McrBits = MmioRead8 (UartBase + UMCR);
> > > -
> > > - if (Control & EFI_SERIAL_REQUEST_TO_SEND) {
> > > - McrBits |= DUART_MCR_RTS;
> > > - } else {
> > > - McrBits &= ~DUART_MCR_RTS;
> > > - }
> > > -
> > > - if (Control & EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE) {
> > > - McrBits |= DUART_MCR_LOOP;
> > > - } else {
> > > - McrBits &= ~DUART_MCR_LOOP;
> > > - }
> > > -
> > > - if (Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) {
> > > - McrBits |= DUART_MCR_AFE;
> > > - } else {
> > > - McrBits &= ~DUART_MCR_AFE;
> > > - }
> > > -
> > > - MmioWrite32 (UartBase + UMCR, McrBits);
> > > -
> > > - return EFI_SUCCESS;
> > > -}
> > > -
> > > -/**
> > > - Retrieve the status of the control bits on a serial device.
> > > -
> > > - @param[out] Control Status of the control bits on a serial device :
> > > -
> > > - . EFI_SERIAL_DATA_CLEAR_TO_SEND,
> > > - EFI_SERIAL_DATA_SET_READY,
> > > - EFI_SERIAL_RING_INDICATE,
> > > - EFI_SERIAL_CARRIER_DETECT,
> > > - EFI_SERIAL_REQUEST_TO_SEND,
> > > - EFI_SERIAL_DATA_TERMINAL_READY
> > > - are all related to the DTE (Data Terminal Equipment)
> > > - and DCE (Data Communication Equipment) modes of
> > > - operation of the serial device.
> > > - . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the
> > > - receive buffer is empty, 0 otherwise.
> > > - . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the
> > > - transmit buffer is empty, 0 otherwise.
> > > - . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if
> > > - the hardware loopback is enabled (the ouput feeds the
> > > - receive buffer), 0 otherwise.
> > > - . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if
> > > - a loopback is accomplished by software, 0 otherwise.
> > > - . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to
> > > - one if the hardware flow control based on CTS (Clear
> > > - To Send) and RTS (Ready To Send) control signals is
> > > - enabled, 0 otherwise.
> > > -
> > > - @retval EFI_SUCCESS The control bits were read from the serial device.
> > > -
> > > -**/
> > > -EFI_STATUS
> > > -EFIAPI
> > > -SerialPortGetControl (
> > > - OUT UINT32 *Control
> > > - )
> > > -{
> > > - UINT32 MsrRegister;
> > > - UINT32 McrRegister;
> > > - UINT32 LsrRegister;
> > > - UINTN UartBase;
> > > -
> > > - UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> > > -
> > > - MsrRegister = MmioRead8 (UartBase + UMSR);
> > > - McrRegister = MmioRead8 (UartBase + UMCR);
> > > - LsrRegister = MmioRead8 (UartBase + ULSR);
> > > -
> > > - *Control = 0;
> > > -
> > > - if ((MsrRegister & DUART_MSR_CTS) == DUART_MSR_CTS) {
> > > - *Control |= EFI_SERIAL_CLEAR_TO_SEND;
> > > - }
> > > -
> > > - if ((McrRegister & DUART_MCR_RTS) == DUART_MCR_RTS) {
> > > - *Control |= EFI_SERIAL_REQUEST_TO_SEND;
> > > - }
> > > -
> > > - if ((LsrRegister & DUART_LSR_TEMT) == DUART_LSR_TEMT) {
> > > - *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
> > > - }
> > > -
> > > - if ((McrRegister & DUART_MCR_AFE) == DUART_MCR_AFE) {
> > > - *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
> > > - }
> > > -
> > > - if ((McrRegister & DUART_MCR_LOOP) == DUART_MCR_LOOP) {
> > > - *Control |= EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE;
> > > - }
> > > -
> > > - return EFI_SUCCESS;
> > > -}
> > > -
> > > -/*
> > > - * Return Baud divisor on basis of Baudrate
> > > - */
> > > -UINT32
> > > -CalculateBaudDivisor (
> > > - IN UINT64 BaudRate
> > > - )
> > > -{
> > > - UINTN DUartClk;
> > > - UINTN FreqSystemBus;
> > > -
> > > - FreqSystemBus = GetBusFrequency ();
> > > - DUartClk = FreqSystemBus/PcdGet32(PcdPlatformFreqDiv);
> > > -
> > > - return ((DUartClk)/(BaudRate * 16));
> > > -}
> > > -
> > > -/*
> > > - Initialise the serial port to the specified settings.
> > > - All unspecified settings will be set to the default values.
> > > -
> > > - @return Always return EFI_SUCCESS or EFI_INVALID_PARAMETER.
> > > -
> > > - **/
> > > -VOID
> > > -EFIAPI
> > > -DuartInitializePort (
> > > - IN UINT64 BaudRate
> > > - )
> > > -{
> > > - UINTN UartBase;
> > > - UINT32 BaudDivisor;
> > > -
> > > - UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> > > - BaudDivisor = CalculateBaudDivisor (BaudRate);
> > > -
> > > -
> > > - while (!(MmioRead8 (UartBase + ULSR) & DUART_LSR_TEMT));
> > > -
> > > - //
> > > - // Enable and assert interrupt when new data is available on
> > > - // external device,
> > > - // setup data format, setup baud divisor
> > > - //
> > > - MmioWrite8 (UartBase + UIER, 0x1);
> > > - MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL);
> > > - MmioWrite8 (UartBase + UDLB, 0);
> > > - MmioWrite8 (UartBase + UDMB, 0);
> > > - MmioWrite8 (UartBase + ULCR, DUART_LCRVAL);
> > > - MmioWrite8 (UartBase + UMCR, DUART_MCRVAL);
> > > - MmioWrite8 (UartBase + UFCR, DUART_FCRVAL);
> > > - MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL);
> > > - MmioWrite8 (UartBase + UDLB, BaudDivisor & 0xff);
> > > - MmioWrite8 (UartBase + UDMB, (BaudDivisor >> 8) & 0xff);
> > > - MmioWrite8 (UartBase + ULCR, DUART_LCRVAL);
> > > -
> > > - return;
> > > -}
> > > -
> > > -/**
> > > - Programmed hardware of Serial port.
> > > -
> > > - @return Always return EFI_SUCCESS.
> > > -
> > > -**/
> > > -EFI_STATUS
> > > -EFIAPI
> > > -SerialPortInitialize (
> > > - VOID
> > > - )
> > > -{
> > > - UINT64 BaudRate;
> > > - BaudRate = (UINTN)PcdGet64 (PcdUartDefaultBaudRate);
> > > -
> > > -
> > > - DuartInitializePort (BaudRate);
> > > -
> > > - return EFI_SUCCESS;
> > > -}
> > > -
> > > -/**
> > > - Write data to serial device.
> > > -
> > > - @param Buffer Point of data buffer which need to be written.
> > > - @param NumberOfBytes Number of output bytes which are cached in
> > Buffer.
> > > -
> > > - @retval 0 Write data failed.
> > > - @retval !0 Actual number of bytes written to serial device.
> > > -
> > > -**/
> > > -UINTN
> > > -EFIAPI
> > > -SerialPortWrite (
> > > - IN UINT8 *Buffer,
> > > - IN UINTN NumberOfBytes
> > > - )
> > > -{
> > > - UINT8 *Final;
> > > - UINTN UartBase;
> > > -
> > > - Final = &Buffer[NumberOfBytes];
> > > - UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> > > -
> > > - while (Buffer < Final) {
> > > - while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_THRE) == 0);
> > > - MmioWrite8 (UartBase + UTHR, *Buffer++);
> > > - }
> > > -
> > > - return NumberOfBytes;
> > > -}
> > > -
> > > -/**
> > > - Read data from serial device and save the data in buffer.
> > > -
> > > - @param Buffer Point of data buffer which need to be written.
> > > - @param NumberOfBytes Number of output bytes which are cached in
> > Buffer.
> > > -
> > > - @retval 0 Read data failed.
> > > - @retval !0 Actual number of bytes read from serial device.
> > > -
> > > -**/
> > > -UINTN
> > > -EFIAPI
> > > -SerialPortRead (
> > > - OUT UINT8 *Buffer,
> > > - IN UINTN NumberOfBytes
> > > - )
> > > -{
> > > - UINTN Count;
> > > - UINTN UartBase;
> > > -
> > > - UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> > > -
> > > - for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
> > > - // Loop while waiting for a new char(s) to arrive in the
> > > - // RxFIFO
> > > - while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) == 0);
> > > -
> > > - *Buffer = MmioRead8 (UartBase + URBR);
> > > - }
> > > -
> > > - return NumberOfBytes;
> > > -}
> > > -
> > > -/**
> > > - Check to see if any data is available to be read from the debug device.
> > > -
> > > - @retval EFI_SUCCESS At least one byte of data is available to be read
> > > - @retval EFI_NOT_READY No data is available to be read
> > > - @retval EFI_DEVICE_ERROR The serial device is not functioning properly
> > > -
> > > -**/
> > > -BOOLEAN
> > > -EFIAPI
> > > -SerialPortPoll (
> > > - VOID
> > > - )
> > > -{
> > > - UINTN UartBase;
> > > -
> > > - UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> > > -
> > > - return ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) != 0);
> > > -}
> > > -
> > > -/**
> > > - Set new attributes to LS1043a.
> > > -
> > > - @param BaudRate The baud rate of the serial device. If the baud
> > rate is not supported,
> > > - the speed will be reduced down to the nearest supported
> > one and the
> > > - variable's value will be updated accordingly.
> > > - @param ReceiveFifoDepth The number of characters the device will
> > buffer on input. If the specified
> > > - value is not supported, the variable's value will be reduced
> > down to the
> > > - nearest supported one.
> > > - @param Timeout If applicable, the number of microseconds the
> > device will wait
> > > - before timing out a Read or a Write operation.
> > > - @param Parity If applicable, this is the EFI_PARITY_TYPE that is
> > computed or checked
> > > - as each character is transmitted or received. If the device
> > does not
> > > - support parity, the value is the default parity value.
> > > - @param DataBits The number of data bits in each character
> > > - @param StopBits If applicable, the EFI_STOP_BITS_TYPE number of
> > stop bits per character.
> > > - If the device does not support stop bits, the value is the
> > default stop
> > > - bit value.
> > > -
> > > - @retval EFI_SUCCESS All attributes were set correctly on the serial
> > device.
> > > -
> > > -**/
> > > -EFI_STATUS
> > > -EFIAPI
> > > -SerialPortSetAttributes (
> > > - IN OUT UINT64 *BaudRate,
> > > - IN OUT UINT32 *ReceiveFifoDepth,
> > > - IN OUT UINT32 *Timeout,
> > > - IN OUT EFI_PARITY_TYPE *Parity,
> > > - IN OUT UINT8 *DataBits,
> > > - IN OUT EFI_STOP_BITS_TYPE *StopBits
> > > - )
> > > -{
> > > - DuartInitializePort (*BaudRate);
> > > -
> > > - return EFI_SUCCESS;
> > > -}
> > > diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> > b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> > > deleted file mode 100644
> > > index 7a2fa619b0..0000000000
> > > --- a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> > > +++ /dev/null
> > > @@ -1,34 +0,0 @@
> > > -# DUartPortLib.inf
> > > -#
> > > -# Component description file for DUartPortLib module
> > > -#
> > > -# Copyright (c) 2013, Freescale Ltd. All rights reserved.
> > > -# Copyright 2017 NXP
> > > -#
> > > -# SPDX-License-Identifier: BSD-2-Clause-Patent
> > > -#
> > > -
> > > -[Defines]
> > > - INF_VERSION = 0x0001001A
> > > - BASE_NAME = DUartPortLib
> > > - FILE_GUID = c42dfe79-8de5-429e-a055-2d0a58591498
> > > - MODULE_TYPE = BASE
> > > - VERSION_STRING = 1.0
> > > - LIBRARY_CLASS = SerialPortLib
> > > -
> > > -[Sources.common]
> > > - DUartPortLib.c
> > > -
> > > -[LibraryClasses]
> > > - PcdLib
> > > - SocLib
> > > -
> > > -[Packages]
> > > - MdeModulePkg/MdeModulePkg.dec
> > > - MdePkg/MdePkg.dec
> > > - Silicon/NXP/NxpQoriqLs.dec
> > > -
> > > -[Pcd]
> > > - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
> > > - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
> > > - gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
> > > --
> > > 2.17.1
> > >
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 14/19] Silicon/NXP/LS1043A: Replce SocLib
2020-02-12 22:50 ` Leif Lindholm
@ 2020-02-13 11:00 ` Pankaj Bansal
2020-02-20 18:45 ` Leif Lindholm
0 siblings, 1 reply; 49+ messages in thread
From: Pankaj Bansal @ 2020-02-13 11:00 UTC (permalink / raw)
To: Leif Lindholm
Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi,
devel@edk2.groups.io
> -----Original Message-----
> From: Leif Lindholm <leif@nuviainc.com>
> Sent: Thursday, February 13, 2020 4:20 AM
> To: Pankaj Bansal <pankaj.bansal@nxp.com>
> Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney
> <michael.d.kinney@intel.com>; Varun Sethi <V.Sethi@nxp.com>;
> devel@edk2.groups.io
> Subject: Re: [PATCH 14/19] Silicon/NXP/LS1043A: Replce SocLib
>
> On Wed, Feb 12, 2020 at 09:37:30 +0000, Pankaj Bansal wrote:
> >
> >
> > > -----Original Message-----
> > > From: Leif Lindholm <leif@nuviainc.com>
> > > Sent: Tuesday, February 11, 2020 7:05 PM
> > > To: Pankaj Bansal <pankaj.bansal@nxp.com>
> > > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D
> > > Kinney <michael.d.kinney@intel.com>; Varun Sethi <V.Sethi@nxp.com>;
> > > devel@edk2.groups.io
> > > Subject: Re: [PATCH 14/19] Silicon/NXP/LS1043A: Replce SocLib
> > >
> > > On Fri, Feb 07, 2020 at 18:13:23 +0530, Pankaj Bansal wrote:
> > > > Replace SocLib with new SocLib in which code structure has been
> > > > changed.
> > >
> > > I don't think there's much point to me reviewing this one until
> > > we've discussed the ChassisLib/SocLib split and layout in more detail.
> >
> > Let me explain the code layout.
> > A Chassis is a base framework used for building SoCs.
> > All NXP Layerscape SOCs like LS1043A, LS1046A, LS2088A, LX2160A are part of
> some chassis.
> > e.g. LS1043A conforms to Chassis 2.x
> > LX2160A conforms to Chassis 3.2
> >
> > We can think of Chassis/Soc/Platform(a.k.a Borad) in Oops terms.
> > Chassis is base. Soc Is derived from Chassis. Platform is derived from Soc.
>
> Right. This is what confused me.
> I was thinking "chassis" more along the lines of
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fen.wikip
> edia.org%2Fwiki%2FChassis_Management_Controller&data=02%7C01%7C
> pankaj.bansal%40nxp.com%7C40f5669720214fb025c708d7b00df071%7C686ea
> 1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637171446229288672&sda
> ta=QJfj0eslQDGR8Jwflda%2BdmgnYa3f87iJelHGA37SpVk%3D&reserved=0
>
> You're talking about the ... bits that remain the same on migrating the
> processors from PPC to ARM?
I am not sure if the concept of Chassis was there in PPC or not?
It's just the way the SOCs are designed. SOCs that are designed around same chassis, reuse most of the components.
It cuts down on s/w development time, because most of the s/w can be reused.
>
> > We have kept the code also in such a way. Which is why we have made
> > Soc Package part of Chassis Package.
> >
> > SocLib provides services to PlatformLib. ChassisLib provides services
> > to SocLib.
> > Which is why we have made SocGetMpCoreInfo as weak function and
> > implemented it in ChassisLib (Patch 11/19) This ensures that code can
> > be reused for all SOCs belonging to same chassis.
> > If any future SOC implements this feature in different way, then this
> > API can be overwritten in SocLib
> >
> > SOCs belonging to same Chassis share many same traits.
> > e.g. the SOC memory map is usually common for all SOCs belonging to
> > same Chassis.
>
> OK, this sounds valid. But one follow-up question: why add the hierarchy at all?
> From a (human) discoverability standpoint, if someone is looking for the code
> for a specific SoC, they will be looking for that SoC, not some abstraction of it.
>
> So I agree it makes sense that chassis are not kept under SoC, but I am asking if
> it would not make more sense to keep them on the same level?
> Any SoCs depending on Pcds defined by a specific chassis could access those by
> importing the package fr that chassis.
>
Hmm. This can be done. We can make Silicon/NXP/Chassis2 and Silicon/NXP/LS1043A.
> Regards,
>
> Leif
>
> > >
> > > /
> > > Leif
> > >
> > > > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> > > > ---
> > > > .../Drivers/PlatformDxe/PlatformDxe.inf | 3 +-
> > > > Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 3 +-
> > > > .../Library/ArmPlatformLib/ArmPlatformLib.c | 53 ++++++-
> > > > .../Library/ArmPlatformLib/ArmPlatformLib.inf | 6 +-
> > > > Silicon/NXP/Chassis2/Include/Chassis.h | 12 ++
> > > > Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc | 1 +
> > > > .../Chassis2/LS1043A/Library/SocLib/SocLib.c | 28 ++++
> > > > .../LS1043A/Library/SocLib/SocLib.inf | 8 ++
> > > > .../Chassis2/Library/ChassisLib/ChassisLib.c | 25 ++++
> > > > Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 2 +-
> > > > Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 7 +-
> > > > Silicon/NXP/Include/Chassis2/NxpSoc.h | 53 -------
> > > > Silicon/NXP/Include/Library/ChassisLib.h | 2 -
> > > > Silicon/NXP/Include/Library/SocLib.h | 1 -
> > > > Silicon/NXP/LS1043A/Include/Soc.h | 44 ------
> > > > Silicon/NXP/LS1043A/LS1043A.dec | 16 ---
> > > > Silicon/NXP/LS1043A/LS1043A.dsc.inc | 33 -----
> > > > .../BaseSerialPortLib16550.c | 11 +-
> > > > .../BaseSerialPortLib16550.inf | 3 +-
> > > > Silicon/NXP/Library/SocLib/Chassis.c | 76 ----------
> > > > Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 96 -------------
> > > > Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 44 ------
> > > > Silicon/NXP/Library/SocLib/NxpChassis.h | 136 ------------------
> > > > 23 files changed, 142 insertions(+), 521 deletions(-) delete
> > > > mode
> > > > 100644 Silicon/NXP/Include/Chassis2/NxpSoc.h
> > > > delete mode 100644 Silicon/NXP/LS1043A/Include/Soc.h delete mode
> > > > 100644 Silicon/NXP/LS1043A/LS1043A.dec delete mode 100644
> > > > Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > > > delete mode 100644 Silicon/NXP/Library/SocLib/Chassis.c
> > > > delete mode 100644 Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > > > delete mode 100644 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > > > delete mode 100644 Silicon/NXP/Library/SocLib/NxpChassis.h
> > > >
> > > > diff --git
> > > > a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> > > > b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> > > > index 126a1174fa..95f60b00f0 100644
> > > > ---
> > > > a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> > > > +++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.i
> > > > +++ nf
> > > > @@ -25,7 +25,8 @@
> > > > MdeModulePkg/MdeModulePkg.dec
> > > > Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
> > > > Silicon/NXP/NxpQoriqLs.dec
> > > > - Silicon/NXP/LS1043A/LS1043A.dec
> > > > + Silicon/NXP/Chassis2/Chassis2.dec
> > > > + Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
> > > >
> > > > [LibraryClasses]
> > > > BaseLib
> > > > diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > > > b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > > > index bc6fa4f19d..4bc7f6ef97 100644
> > > > --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > > > +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > > > @@ -23,7 +23,8 @@
> > > > FLASH_DEFINITION =
> > > Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> > > >
> > > > !include Silicon/NXP/NxpQoriqLs.dsc.inc -!include
> > > > Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > > > +!include Silicon/NXP/Chassis2/Chassis2.dsc.inc
> > > > +!include Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
> > > >
> > > > [LibraryClasses.common]
> > > >
> > > > ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/A
> > > > ArmPlatformLib|rmPl
> > > > atformLib.inf diff --git
> > > > a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib
> > > > .c
> > > > b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib
> > > > .c index 718c71bf02..821d413a3e 100644
> > > > ---
> > > > a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib
> > > > .c
> > > > +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatfor
> > > > +++ mLib
> > > > +++ .c
> > > > @@ -14,7 +14,10 @@
> > > > #include <Library/ArmPlatformLib.h> #include
> > > > <Ppi/ArmMpCoreInfo.h>
> > > >
> > > > -extern VOID SocInit (VOID);
> > > > +#include <Library/DebugLib.h>
> > > > +#include <Library/I2cLib.h>
> > > > +#include <Library/SocLib.h>
> > > > +#include <Ppi/NxpPlatformGetClock.h>
> > > >
> > > > /**
> > > > Return the current Boot Mode
> > > > @@ -30,6 +33,49 @@ ArmPlatformGetBootMode (
> > > > return BOOT_WITH_FULL_CONFIGURATION; }
> > > >
> > > > +/**
> > > > + Get the clocks supplied by Platform(Board) to NXP Layerscape
> > > > +SOC
> > > > +
> > > > + The core can be of type ARM or PowerPC or Hardware Accelerator.
> > > > + If the core is enabled and of type ARM EFI_SUCCESS is returned
> > > > + and a code for type of ARM core is returned
> > > > +
> > > > + @param[in] ClockType Type of clock
> > > > + @param[in] ... Variable argument list which is parsed based on
> > > ClockType
> > > > +
> > > > + @return Actual Clock Frequency. return value 0 should be
> interpreted as
> > > clock not provided by Board.
> > > > +**/
> > > > +UINT64
> > > > +EFIAPI
> > > > +NxpPlatformGetClock(
> > > > + IN UINT32 ClockType,
> > > > + ...
> > > > + )
> > > > +{
> > > > + UINT64 Clock;
> > > > + VA_LIST Args;
> > > > +
> > > > + Clock = 0;
> > > > +
> > > > + VA_START (Args, ClockType);
> > > > +
> > > > + switch (ClockType) {
> > > > + case NXP_SYSTEM_CLOCK:
> > > > + Clock = 100 * 1000 * 1000; // 100 MHz
> > > > + break;
> > > > + case NXP_I2C_CLOCK:
> > > > + case NXP_UART_CLOCK:
> > > > + Clock = NxpPlatformGetClock (NXP_SYSTEM_CLOCK);
> > > > + Clock = SocGetClock (Clock, ClockType, Args);
> > > > + break;
> > > > + default:
> > > > + break;
> > > > + }
> > > > +
> > > > + VA_END (Args);
> > > > +
> > > > + return Clock;
> > > > +}
> > > > +
> > > > /**
> > > > Placeholder for Platform Initialization **/ @@ -38,9 +84,9 @@
> > > > ArmPlatformInitialize (
> > > > IN UINTN MpId
> > > > )
> > > > {
> > > > - SocInit ();
> > > > + SocInit ();
> > > >
> > > > - return EFI_SUCCESS;
> > > > + return EFI_SUCCESS;
> > > > }
> > > >
> > > > ARM_CORE_INFO LS1043aMpCoreInfoCTA53x4[] = { @@ -69,6 +115,7
> @@
> > > > PrePeiCoreGetMpCoreInfo ( }
> > > >
> > > > ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =
> { PrePeiCoreGetMpCoreInfo
> > > > };
> > > > +NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi = {
> > > > +NxpPlatformGetClock };
> > > >
> > > > EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
> > > > {
> > > > diff --git
> > > > a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib
> > > > .inf
> > > > b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib
> > > > .inf index 6396d2982b..8b79fd7490 100644
> > > > ---
> > > > a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib
> > > > .inf
> > > > +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatfor
> > > > +++ mLib
> > > > +++ .inf
> > > > @@ -20,11 +20,14 @@
> > > > EmbeddedPkg/EmbeddedPkg.dec
> > > > MdePkg/MdePkg.dec
> > > > Silicon/NXP/NxpQoriqLs.dec
> > > > - Silicon/NXP/LS1043A/LS1043A.dec
> > > > + Silicon/NXP/Chassis2/Chassis2.dec
> > > > + Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
> > > >
> > > > [LibraryClasses]
> > > > ArmLib
> > > > SocLib
> > > > + I2cLib
> > > > + DebugLib
> > > >
> > > > [Sources.common]
> > > > AArch64/NxpQoriqLsHelper.S | GCC
> > > > @@ -36,3 +39,4 @@
> > > >
> > > > [FixedPcd]
> > > > gArmTokenSpaceGuid.PcdArmPrimaryCore
> > > > + gArmPlatformTokenSpaceGuid.PcdCoreCount
> > > > diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h
> > > > b/Silicon/NXP/Chassis2/Include/Chassis.h
> > > > index 48ba2e7bfb..8f26faf297 100644
> > > > --- a/Silicon/NXP/Chassis2/Include/Chassis.h
> > > > +++ b/Silicon/NXP/Chassis2/Include/Chassis.h
> > > > @@ -20,6 +20,18 @@
> > > > #define TP_ITYPE_VERSION_A53 0x2
> > > > #define TP_ITYPE_VERSION_A72 0x4
> > > >
> > > > +/* SMMU Defintions */
> > > > +#define SMMU_BASE_ADDR 0x09000000
> > > > +#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
> > > > +#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
> > > > +#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
> > > > +#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
> > > > +#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
> > > > +
> > > > +#define SCR0_USFCFG_MASK 0x00000400
> > > > +#define SCR0_CLIENTPD_MASK 0x00000001
> > > > +#define SACR_PAGESIZE_MASK 0x00010000
> > > > +
> > > > /**
> > > > The Device Configuration Unit provides general purpose
> > > > configuration and
> > > status for the
> > > > device. These registers only support 32-bit accesses.
> > > > diff --git a/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
> > > > b/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
> > > > index 4511203443..8440e5f0f3 100644
> > > > --- a/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
> > > > +++ b/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
> > > > @@ -8,6 +8,7 @@
> > > >
> > > > [LibraryClasses.common]
> > > > SocLib|Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> > > > +
> > > > + SerialPortLib|Silicon/NXP/Library/BaseSerialPortLib16550/BaseSer
> > > > + SerialPortLib|ialP
> > > > + ortLib16550.inf
> > > >
> > > >
> > > >
> > >
> #################################################################
> > > #####
> > > > ##########
> > > > #
> > > > diff --git a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
> > > > b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
> > > > index 2a08ad87db..24241e9b02 100644
> > > > --- a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
> > > > +++ b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
> > > > @@ -4,8 +4,10 @@
> > > >
> > > > SPDX-License-Identifier: BSD-2-Clause-Patent
> > > > **/
> > > > +#include <Soc.h>
> > > > #include <Library/ChassisLib.h>
> > > > #include <Library/SocLib.h>
> > > > +#include <Library/SerialPortLib.h>
> > > >
> > > > /**
> > > > Return the input clock frequency to an IP Module.
> > > > @@ -66,8 +68,34 @@ SocInit (
> > > > VOID
> > > > )
> > > > {
> > > > + UINT64 BaudRate;
> > > > + UINT32 ReceiveFifoDepth;
> > > > + EFI_PARITY_TYPE Parity;
> > > > + UINT8 DataBits;
> > > > + EFI_STOP_BITS_TYPE StopBits;
> > > > + UINT32 Timeout;
> > > > +
> > > > + BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
> > > > + ReceiveFifoDepth = FixedPcdGet16
> > > > + (PcdUartDefaultReceiveFifoDepth); // Use default FIFO depth
> > > > + Timeout = 0; Parity =
> > > > + (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity); DataBits
> > > > + =
> > > > + FixedPcdGet8 (PcdUartDefaultDataBits); StopBits =
> > > > + (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);
> > > > +
> > > > ChassisInit ();
> > > >
> > > > + //
> > > > + // Early init serial Port to get board information.
> > > > + //
> > > > + SerialPortSetAttributes (
> > > > + &BaudRate,
> > > > + &ReceiveFifoDepth,
> > > > + &Timeout,
> > > > + &Parity,
> > > > + &DataBits,
> > > > + &StopBits
> > > > + );
> > > > +
> > > > return;
> > > > }
> > > >
> > > > diff --git
> > > > a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> > > > b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> > > > index c9a4fbc01f..fb39424bc5 100644
> > > > --- a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> > > > +++ b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> > > > @@ -29,4 +29,12 @@
> > > >
> > > > [LibraryClasses]
> > > > ChassisLib
> > > > + PcdLib
> > > > + SerialPortLib
> > > >
> > > > +[FixedPcd]
> > > > + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
> > > > + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
> > > > + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
> > > > + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
> > > > + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth
> > > > diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> > > > b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> > > > index fa6a36e96f..e7573a0e06 100644
> > > > --- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> > > > +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> > > > @@ -150,6 +150,29 @@ SocGetMpCoreInfo (
> > > > return CoreCount;
> > > > }
> > > >
> > > > +/*
> > > > + * Setup SMMU in bypass mode
> > > > + * and also set its pagesize
> > > > + */
> > > > +STATIC
> > > > +VOID
> > > > +SmmuInit (
> > > > + VOID
> > > > + )
> > > > +{
> > > > + UINT32 Value;
> > > > +
> > > > + /* set pagesize as 64K and ssmu-500 in bypass mode */ Value =
> > > > + (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
> > > > + MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
> > > > +
> > > > + Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) |
> > > > + SCR0_CLIENTPD_MASK)
> > > &
> > > > + ~SCR0_USFCFG_MASK;
> > > > + MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
> > > > +
> > > > + Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) |
> > > SCR0_CLIENTPD_MASK) &
> > > > +~SCR0_USFCFG_MASK;
> > > > + MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value); }
> > > > +
> > > > /**
> > > > Function to initialize Chassis Specific functions
> > > > **/
> > > > @@ -183,4 +206,6 @@ ChassisInit (
> > > > &DataBits,
> > > > &StopBits
> > > > );
> > > > +
> > > > + SmmuInit();
> > > > }
> > > > diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> > > > b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> > > > index 8e3a82efca..e79b106c8d 100644
> > > > --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> > > > +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> > > > @@ -50,7 +50,7 @@ SetBusFrequency (
> > > >
> > > > I2cBase = (UINTN)(I2c->Dev->Resources[0].AddrRangeMin);
> > > >
> > > > - I2cClock = GetBusFrequency ();
> > > > + I2cClock = mPlatformGetClockPpi.PlatformGetClock
> > > > + (NXP_I2C_CLOCK, 0);
> > > >
> > > > I2cInitialize (I2cBase, I2cClock, *BusClockHertz);
> > > >
> > > > diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> > > > b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> > > > index 88316f3133..f446f0d4f9 100644
> > > > --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> > > > +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> > > > @@ -13,6 +13,7 @@
> > > > #include <Library/UefiLib.h>
> > > > #include <Uefi.h>
> > > >
> > > > +#include <Ppi/NxpPlatformGetClock.h>
> > > > #include <Protocol/I2cMaster.h>
> > > > #include <Protocol/NonDiscoverableDevice.h>
> > > >
> > > > @@ -37,11 +38,7 @@ typedef struct {
> > > > NON_DISCOVERABLE_DEVICE *Dev;
> > > > } NXP_I2C_MASTER;
> > > >
> > > > -extern
> > > > -UINT64
> > > > -GetBusFrequency (
> > > > - VOID
> > > > - );
> > > > +extern NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi;
> > > >
> > > > EFI_STATUS
> > > > NxpI2cInit (
> > > > diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h
> > > > b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> > > > deleted file mode 100644
> > > > index 6812beafe4..0000000000
> > > > --- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
> > > > +++ /dev/null
> > > > @@ -1,53 +0,0 @@
> > > > -/** Soc.h
> > > > -* Header defining the Base addresses, sizes, flags etc for
> > > > chassis 1
> > > > -*
> > > > -* Copyright 2017-2020 NXP
> > > > -*
> > > > -* SPDX-License-Identifier: BSD-2-Clause-Patent
> > > > -*
> > > > -**/
> > > > -
> > > > -#ifndef NXP_SOC_H_
> > > > -#define NXP_SOC_H_
> > > > -
> > > > -#define CLK_FREQ 100000000
> > > > -
> > > > -#define CHASSIS2_DCFG_ADDRESS 0x1EE0000
> > > > -
> > > > -/* SMMU Defintions */
> > > > -#define SMMU_BASE_ADDR 0x09000000
> > > > -#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
> > > > -#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
> > > > -#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
> > > > -#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
> > > > -#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
> > > > -
> > > > -#define SCR0_USFCFG_MASK 0x00000400
> > > > -#define SCR0_CLIENTPD_MASK 0x00000001
> > > > -#define SACR_PAGESIZE_MASK 0x00010000
> > > > -#define IDR1_PAGESIZE_MASK 0x80000000
> > > > -
> > > > -typedef struct {
> > > > - UINTN FreqSystemBus;
> > > > -} SYS_INFO;
> > > > -
> > > > -/* Device Configuration and Pin Control */ -typedef struct {
> > > > - UINT8 Res0[0x100-0x00];
> > > > - UINT32 RcwSr[16]; /* Reset control word status */
> > > > -#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25 -#define
> > > > CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f -} CCSR_GUR;
> > > > -
> > > > -VOID
> > > > -GetSysInfo (
> > > > - OUT SYS_INFO *
> > > > - );
> > > > -
> > > > -UINT32
> > > > -EFIAPI
> > > > -GurRead (
> > > > - IN UINTN Address
> > > > - );
> > > > -
> > > > -#endif /* NXP_SOC_H_ */
> > > > diff --git a/Silicon/NXP/Include/Library/ChassisLib.h
> > > > b/Silicon/NXP/Include/Library/ChassisLib.h
> > > > index b51b024374..d07c59b82d 100644
> > > > --- a/Silicon/NXP/Include/Library/ChassisLib.h
> > > > +++ b/Silicon/NXP/Include/Library/ChassisLib.h
> > > > @@ -9,8 +9,6 @@
> > > > #ifndef __CHASSIS_LIB_H__
> > > > #define __CHASSIS_LIB_H__
> > > >
> > > > -#include <Chassis.h>
> > > > -
> > > > /**
> > > > Read Dcfg register
> > > > **/
> > > > diff --git a/Silicon/NXP/Include/Library/SocLib.h
> > > > b/Silicon/NXP/Include/Library/SocLib.h
> > > > index 3def396171..700e877bdf 100644
> > > > --- a/Silicon/NXP/Include/Library/SocLib.h
> > > > +++ b/Silicon/NXP/Include/Library/SocLib.h
> > > > @@ -8,7 +8,6 @@
> > > > #ifndef __SOC_LIB_H__
> > > > #define __SOC_LIB_H__
> > > >
> > > > -#include <Soc.h>
> > > > #include <Uefi.h>
> > > > #include <Ppi/ArmMpCoreInfo.h>
> > > > #include <Ppi/NxpPlatformGetClock.h> diff --git
> > > > a/Silicon/NXP/LS1043A/Include/Soc.h
> > > > b/Silicon/NXP/LS1043A/Include/Soc.h
> > > > deleted file mode 100644
> > > > index c1e00394af..0000000000
> > > > --- a/Silicon/NXP/LS1043A/Include/Soc.h
> > > > +++ /dev/null
> > > > @@ -1,44 +0,0 @@
> > > > -/** @file
> > > > -
> > > > - Copyright 2020 NXP
> > > > -
> > > > - SPDX-License-Identifier: BSD-2-Clause-Patent
> > > > -
> > > > -**/
> > > > -#ifndef __SOC_H__
> > > > -#define __SOC_H__
> > > > -
> > > > -/**
> > > > - Soc Memory Map
> > > > -**/
> > > > -#define LS1043A_DRAM0_PHYS_ADDRESS 0x80000000
> > > > -#define LS1043A_DRAM0_SIZE SIZE_2GB
> > > > -#define LS1043A_DRAM1_PHYS_ADDRESS 0x880000000
> > > > -#define LS1043A_DRAM1_SIZE 0x780000000 // 30 GB
> > > > -
> > > > -#define LS1043A_CCSR_PHYS_ADDRESS 0x1000000
> > > > -#define LS1043A_CCSR_SIZE 0xF000000
> > > > -
> > > > -#define LS1043A_IFC0_PHYS_ADDRESS 0x60000000
> > > > -#define LS1043A_IFC0_SIZE SIZE_512MB
> > > > -#define LS1043A_IFC1_PHYS_ADDRESS 0x620000000
> > > > -#define LS1043A_IFC1_SIZE 0xE0000000 // 3.5 GB
> > > > -
> > > > -#define LS1043A_QSPI_PHYS_ADDRESS 0x40000000
> > > > -#define LS1043A_QSPI_SIZE SIZE_512MB
> > > > -
> > > > -#define LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS 0x500000000
> > > > -#define LS1043A_QMAN_SW_PORTAL_SIZE SIZE_128MB
> > > > -#define LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS 0x508000000
> > > > -#define LS1043A_BMAN_SW_PORTAL_SIZE SIZE_128MB
> > > > -
> > > > -#define LS1043A_PCI0_PHYS_ADDRESS 0x4000000000
> > > > -#define LS1043A_PCI1_PHYS_ADDRESS 0x4800000000
> > > > -#define LS1043A_PCI2_PHYS_ADDRESS 0x5000000000
> > > > -#define LS1043A_PCI_SIZE SIZE_32GB
> > > > -
> > > > -#define LS1043A_I2C0_PHYS_ADDRESS 0x2180000
> > > > -#define LS1043A_I2C_SIZE 0x10000
> > > > -#define LS1043A_I2C_NUM_CONTROLLERS 4
> > > > -
> > > > -#endif
> > > > diff --git a/Silicon/NXP/LS1043A/LS1043A.dec
> > > > b/Silicon/NXP/LS1043A/LS1043A.dec deleted file mode 100644 index
> > > > cd79949790..0000000000
> > > > --- a/Silicon/NXP/LS1043A/LS1043A.dec
> > > > +++ /dev/null
> > > > @@ -1,16 +0,0 @@
> > > > -# LS1043A.dec
> > > > -#
> > > > -# Copyright 2017-2019 NXP
> > > > -#
> > > > -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#
> > > > -
> > > > -[Defines]
> > > > - DEC_SPECIFICATION = 0x0001001A
> > > > -
> > > > -[Guids.common]
> > > > - gNxpLs1043ATokenSpaceGuid = {0x6834fe45, 0x4aee, 0x4fc6, {0xbc,
> > > 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
> > > > -
> > > > -[Includes]
> > > > - Include
> > > > diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > > > b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > > > deleted file mode 100644
> > > > index 7ebbb1a495..0000000000
> > > > --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > > > +++ /dev/null
> > > > @@ -1,33 +0,0 @@
> > > > -# LS1043A.dsc
> > > > -# LS1043A Soc package.
> > > > -#
> > > > -# Copyright 2017-2020 NXP
> > > > -#
> > > > -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -#
> > > > -
> > > > -[LibraryClasses.common]
> > > > - SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > > > -
> > > > SerialPortLib|Silicon/NXP/Library/BaseSerialPortLib16550/BaseSeria
> > > > SerialPortLib|lPor
> > > > tLib16550.inf
> > > > -
> > > > -
> > >
> #################################################################
> > > ####
> > > > ###########
> > > > -#
> > > > -# Pcd Section - list of all EDK II PCD Entries defined by this
> > > > Platform -#
> > > > -
> > >
> #################################################################
> > > ####
> > > > ###########
> > > > -[PcdsDynamicDefault.common]
> > > > -
> > > > - #
> > > > - # ARM General Interrupt Controller
> > > > - gArmTokenSpaceGuid.PcdGicDistributorBase|0x01401000
> > > > - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01402000
> > > > -
> > > > -[PcdsFixedAtBuild.common]
> > > > - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
> > > > -
> > > > - #
> > > > - # Big Endian IPs
> > > > - #
> > > > - gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
> > > > -##
> > > > diff --git
> > > > a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib1655
> > > > 0.c
> > > > b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib1655
> > > > 0.c index 6b2aa46ff6..2e35f09d8f 100644
> > > > ---
> > > > a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib1655
> > > > 0.c
> > > > +++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib
> > > > +++ 1655
> > > > +++ 0.c
> > > > @@ -15,6 +15,9 @@
> > > > #include <Library/PcdLib.h>
> > > > #include <Library/IoLib.h>
> > > > #include <Library/BaseLib.h>
> > > > +#include <Ppi/NxpPlatformGetClock.h>
> > > > +
> > > > +extern NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi;
> > > >
> > > > //
> > > > // 16550 UART register offsets and bitfields @@ -42,12 +45,6 @@
> > > > #define B_UART_MSR_RI BIT6
> > > > #define B_UART_MSR_DCD BIT7
> > > >
> > > > -extern
> > > > -UINT64
> > > > -GetBusFrequency (
> > > > - VOID
> > > > - );
> > > > -
> > > > /**
> > > > Read an 8-bit 16550 register. If PcdSerialUseMmio is TRUE,
> > > > then the value is
> > > read from
> > > > MMIO space. If PcdSerialUseMmio is FALSE, then the value is
> > > > read from I/O space. The @@ -577,7 +574,7 @@ SerialPortSetAttributes (
> > > > return RETURN_UNSUPPORTED;
> > > > }
> > > >
> > > > - SerialClock = GetBusFrequency ();
> > > > + SerialClock = mPlatformGetClockPpi.PlatformGetClock
> > > > + (NXP_UART_CLOCK, 0);
> > > > if (SerialClock == 0) {
> > > > return EFI_DEVICE_ERROR;
> > > > }
> > > > diff --git
> > > > a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib1655
> > > > 0.in
> > > > f
> > > > b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib1655
> > > > 0.in
> > > > f
> > > > index 45ae9dc0af..7823bc5be5 100644
> > > > ---
> > > > a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib1655
> > > > 0.in
> > > > f
> > > > +++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib
> > > > +++ 1655
> > > > +++ 0.inf
> > > > @@ -19,11 +19,12 @@
> > > > [Packages]
> > > > MdePkg/MdePkg.dec
> > > > MdeModulePkg/MdeModulePkg.dec
> > > > + Silicon/NXP/NxpQoriqLs.dec
> > > >
> > > > [LibraryClasses]
> > > > PcdLib
> > > > IoLib
> > > > - SocLib
> > > > + ArmPlatformLib
> > > >
> > > > [Sources]
> > > > BaseSerialPortLib16550.c
> > > > diff --git a/Silicon/NXP/Library/SocLib/Chassis.c
> > > > b/Silicon/NXP/Library/SocLib/Chassis.c
> > > > deleted file mode 100644
> > > > index 1ef99e8de2..0000000000
> > > > --- a/Silicon/NXP/Library/SocLib/Chassis.c
> > > > +++ /dev/null
> > > > @@ -1,76 +0,0 @@
> > > > -/** @file
> > > > - SoC specific Library containg functions to initialize various
> > > > SoC components
> > > > -
> > > > - Copyright 2017-2020 NXP
> > > > -
> > > > - SPDX-License-Identifier: BSD-2-Clause-Patent
> > > > -
> > > > -**/
> > > > -
> > > > -#include <Base.h>
> > > > -#ifdef CHASSIS2
> > > > -#include <Chassis2/NxpSoc.h>
> > > > -#elif CHASSIS3
> > > > -#include <Chassis3/NxpSoc.h>
> > > > -#endif
> > > > -#include <Library/ArmSmcLib.h>
> > > > -#include <Library/BaseLib.h>
> > > > -#include <Library/IoAccessLib.h>
> > > > -#include <Library/DebugLib.h>
> > > > -#include <Library/IoLib.h>
> > > > -#include <Library/PcdLib.h>
> > > > -#include <Library/PrintLib.h>
> > > > -#include <Library/SerialPortLib.h>
> > > > -
> > > > -#include "NxpChassis.h"
> > > > -
> > > > -UINT32
> > > > -EFIAPI
> > > > -GurRead (
> > > > - IN UINTN Address
> > > > - )
> > > > -{
> > > > - if (FixedPcdGetBool (PcdGurBigEndian)) {
> > > > - return SwapMmioRead32 (Address);
> > > > - } else {
> > > > - return MmioRead32 (Address);
> > > > - }
> > > > -}
> > > > -
> > > > -/*
> > > > - * Return system bus frequency
> > > > - */
> > > > -UINT64
> > > > -GetBusFrequency (
> > > > - VOID
> > > > - )
> > > > -{
> > > > - SYS_INFO SocSysInfo;
> > > > -
> > > > - GetSysInfo (&SocSysInfo);
> > > > -
> > > > - return SocSysInfo.FreqSystemBus; -}
> > > > -
> > > > -/*
> > > > - * Setup SMMU in bypass mode
> > > > - * and also set its pagesize
> > > > - */
> > > > -VOID
> > > > -SmmuInit (
> > > > - VOID
> > > > - )
> > > > -{
> > > > - UINT32 Value;
> > > > -
> > > > - /* set pagesize as 64K and ssmu-500 in bypass mode */
> > > > - Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) |
> > > > SACR_PAGESIZE_MASK);
> > > > - MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
> > > > -
> > > > - Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) |
> > > > SCR0_CLIENTPD_MASK)
> > > &
> > > > ~SCR0_USFCFG_MASK;
> > > > - MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
> > > > -
> > > > - Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) |
> > > SCR0_CLIENTPD_MASK) &
> > > > ~SCR0_USFCFG_MASK;
> > > > - MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value); -}
> > > > -
> > > > diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > > > b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > > > deleted file mode 100644
> > > > index a3dabc93d1..0000000000
> > > > --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > > > +++ /dev/null
> > > > @@ -1,96 +0,0 @@
> > > > -/** @Soc.c
> > > > - SoC specific Library containg functions to initialize various
> > > > SoC components
> > > > -
> > > > - Copyright 2017-2020 NXP
> > > > -
> > > > - SPDX-License-Identifier: BSD-2-Clause-Patent
> > > > -
> > > > -**/
> > > > -
> > > > -#include <Base.h>
> > > > -#include <NxpChassis.h>
> > > > -#include <Chassis2/NxpSoc.h>
> > > > -#include <Library/BaseLib.h>
> > > > -#include <Library/BaseMemoryLib.h> -#include <Library/DebugLib.h>
> > > > -#include <Library/IoAccessLib.h> -#include <Library/IoLib.h>
> > > > -#include <Library/PcdLib.h> -#include <Library/PrintLib.h>
> > > > -#include <Library/SerialPortLib.h>
> > > > -
> > > > -/**
> > > > - Calculate the frequency of various controllers and
> > > > - populate the passed structure with frequuencies.
> > > > -
> > > > - @param PtrSysInfo Input structure to populate with
> > > > - frequencies.
> > > > -**/
> > > > -VOID
> > > > -GetSysInfo (
> > > > - OUT SYS_INFO *PtrSysInfo
> > > > - )
> > > > -{
> > > > - CCSR_GUR *GurBase;
> > > > - UINTN SysClk;
> > > > -
> > > > - GurBase = (CCSR_GUR *)CHASSIS2_DCFG_ADDRESS;
> > > > - SysClk = CLK_FREQ;
> > > > -
> > > > - SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
> > > > -
> > > > - PtrSysInfo->FreqSystemBus = SysClk;
> > > > -
> > > > - //
> > > > - // selects the platform clock:SYSCLK ratio and calculate
> > > > - // system frequency
> > > > - //
> > > > - PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
> > > > - CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
> > > > - CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
> > > > -}
> > > > -
> > > > -/**
> > > > - Function to initialize SoC specific constructs
> > > > - CPU Info
> > > > - SoC Personality
> > > > - Board Personality
> > > > - RCW prints
> > > > - **/
> > > > -VOID
> > > > -SocInit (
> > > > - VOID
> > > > - )
> > > > -{
> > > > - UINT64 BaudRate;
> > > > - UINT32 ReceiveFifoDepth;
> > > > - EFI_PARITY_TYPE Parity;
> > > > - UINT8 DataBits;
> > > > - EFI_STOP_BITS_TYPE StopBits;
> > > > - UINT32 Timeout;
> > > > -
> > > > - BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
> > > > - ReceiveFifoDepth = 0; // Use default FIFO depth
> > > > - Timeout = 0;
> > > > - Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
> > > > - DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
> > > > - StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8
> > > > (PcdUartDefaultStopBits);
> > > > -
> > > > - SmmuInit ();
> > > > -
> > > > - //
> > > > - // Early init serial Port to get board information.
> > > > - //
> > > > - SerialPortSetAttributes (
> > > > - &BaudRate,
> > > > - &ReceiveFifoDepth,
> > > > - &Timeout,
> > > > - &Parity,
> > > > - &DataBits,
> > > > - &StopBits
> > > > - );
> > > > - DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a
> on %a)\n",
> > > > - (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__,
> > > __DATE__));
> > > > -
> > > > - return;
> > > > -}
> > > > diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > > > b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > > > deleted file mode 100644
> > > > index d8707927b7..0000000000
> > > > --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > > > +++ /dev/null
> > > > @@ -1,44 +0,0 @@
> > > > -# @file
> > > > -#
> > > > -# Copyright 2017-2020 NXP
> > > > -#
> > > > -# SPDX-License-Identifier: BSD-2-Clause-Patent -#
> > > > -
> > > > -[Defines]
> > > > - INF_VERSION = 0x0001001A
> > > > - BASE_NAME = SocLib
> > > > - FILE_GUID = e868c5ca-9729-43ae-bff4-438c67de8c68
> > > > - MODULE_TYPE = BASE
> > > > - VERSION_STRING = 1.0
> > > > - LIBRARY_CLASS = SocLib
> > > > -
> > > > -[Packages]
> > > > - ArmPkg/ArmPkg.dec
> > > > - MdeModulePkg/MdeModulePkg.dec
> > > > - MdePkg/MdePkg.dec
> > > > - Silicon/NXP/NxpQoriqLs.dec
> > > > - Silicon/NXP/LS1043A/LS1043A.dec
> > > > -
> > > > -[LibraryClasses]
> > > > - ArmSmcLib
> > > > - BaseLib
> > > > - DebugLib
> > > > - IoAccessLib
> > > > - SerialPortLib
> > > > -
> > > > -[Sources.common]
> > > > - Chassis.c
> > > > - Chassis2/Soc.c
> > > > -
> > > > -[BuildOptions]
> > > > - GCC:*_*_*_CC_FLAGS = -DCHASSIS2
> > > > -
> > > > -[FixedPcd]
> > > > - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
> > > > - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
> > > > - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
> > > > - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
> > > > - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> > > > - gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
> > > > - gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
> > > > diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h
> > > > b/Silicon/NXP/Library/SocLib/NxpChassis.h
> > > > deleted file mode 100644
> > > > index 99f6439d8f..0000000000
> > > > --- a/Silicon/NXP/Library/SocLib/NxpChassis.h
> > > > +++ /dev/null
> > > > @@ -1,136 +0,0 @@
> > > > -/** @file
> > > > -* Header defining the Base addresses, sizes, flags etc for
> > > > chassis 1
> > > > -*
> > > > -* Copyright 2017-2019 NXP
> > > > -*
> > > > -* SPDX-License-Identifier: BSD-2-Clause-Patent
> > > > -*
> > > > -**/
> > > > -
> > > > -#ifndef NXP_CHASSIS_H_
> > > > -#define NXP_CHASSIS_H_
> > > > -
> > > > -#define TP_ITYP_AV_MASK 0x00000001 /* Initiator available */
> > > > -#define TP_ITYP_TYPE_MASK(x) (((x) & 0x6) >> 1) /* Initiator Type */
> > > > -#define TP_ITYP_TYPE_ARM 0x0
> > > > -#define TP_ITYP_TYPE_PPC 0x1
> > > > -#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
> > > > -#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
> > > > -#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
> > > > -#define TP_ITYP_VERSION(x) (((x) & 0xe0) >> 5) /* Initiator Version */
> > > > -#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
> > > > -#define TP_INIT_PER_CLUSTER 4
> > > > -
> > > > -#define TY_ITYP_VERSION_A7 0x1
> > > > -#define TY_ITYP_VERSION_A53 0x2
> > > > -#define TY_ITYP_VERSION_A57 0x3
> > > > -#define TY_ITYP_VERSION_A72 0x4
> > > > -
> > > > -#define CPU_TYPE_ENTRY(N, V, NC) { .Name = #N, .SocVer =
> > > SVR_##V, .NumCores = (NC)}
> > > > -
> > > > -#define SVR_WO_E 0xFFFFFE
> > > > -#define SVR_LS1043A 0x879200
> > > > -#define SVR_LS1046A 0x870700
> > > > -#define SVR_LS2088A 0x870901
> > > > -
> > > > -#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
> > > > -#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
> > > > -#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
> > > > -#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
> > > > -
> > > > -#define MHZ 1000000
> > > > -
> > > > -typedef struct {
> > > > - CHAR8 *Name;
> > > > - UINT32 SocVer;
> > > > - UINT32 NumCores;
> > > > -} CPU_TYPE;
> > > > -
> > > > -typedef struct {
> > > > - UINTN CpuClk; /* CPU clock in Hz! */
> > > > - UINTN BusClk;
> > > > - UINTN MemClk;
> > > > - UINTN PciClk;
> > > > - UINTN SdhcClk;
> > > > -} SOC_CLOCK_INFO;
> > > > -
> > > > -/*
> > > > - * Print Soc information
> > > > - */
> > > > -VOID
> > > > -PrintSoc (
> > > > - VOID
> > > > - );
> > > > -
> > > > -/*
> > > > - * Initialize Clock structure
> > > > - */
> > > > -VOID
> > > > -ClockInit (
> > > > - VOID
> > > > - );
> > > > -
> > > > -/*
> > > > - * Setup SMMU in bypass mode
> > > > - * and also set its pagesize
> > > > - */
> > > > -VOID
> > > > -SmmuInit (
> > > > - VOID
> > > > - );
> > > > -
> > > > -/*
> > > > - * Print CPU information
> > > > - */
> > > > -VOID
> > > > -PrintCpuInfo (
> > > > - VOID
> > > > - );
> > > > -
> > > > -/*
> > > > - * Dump RCW (Reset Control Word) on console
> > > > - */
> > > > -VOID
> > > > -PrintRCW (
> > > > - VOID
> > > > - );
> > > > -
> > > > -UINT32
> > > > -InitiatorType (
> > > > - IN UINT32 Cluster,
> > > > - IN UINTN InitId
> > > > - );
> > > > -
> > > > -/*
> > > > - * Return the mask for number of cores on this SOC.
> > > > - */
> > > > -UINT32
> > > > -CpuMask (
> > > > - VOID
> > > > - );
> > > > -
> > > > -/*
> > > > - * Return the number of cores on this SOC.
> > > > - */
> > > > -UINTN
> > > > -CpuNumCores (
> > > > - VOID
> > > > - );
> > > > -
> > > > -/*
> > > > - * Return the type of initiator for core/hardware accelerator for
> > > > given core
> > > index.
> > > > - */
> > > > -UINTN
> > > > -QoriqCoreToType (
> > > > - IN UINTN Core
> > > > - );
> > > > -
> > > > -/*
> > > > - * Return the cluster of initiator for core/hardware accelerator
> > > > for given core
> > > index.
> > > > - */
> > > > -INT32
> > > > -QoriqCoreToCluster (
> > > > - IN UINTN Core
> > > > - );
> > > > -
> > > > -#endif /* NXP_CHASSIS_H_ */
> > > > --
> > > > 2.17.1
> > > >
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 14/19] Silicon/NXP/LS1043A: Replce SocLib
2020-02-13 11:00 ` Pankaj Bansal
@ 2020-02-20 18:45 ` Leif Lindholm
0 siblings, 0 replies; 49+ messages in thread
From: Leif Lindholm @ 2020-02-20 18:45 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi,
devel@edk2.groups.io
On Thu, Feb 13, 2020 at 11:00:10 +0000, Pankaj Bansal wrote:
> > You're talking about the ... bits that remain the same on migrating the
> > processors from PPC to ARM?
>
> I am not sure if the concept of Chassis was there in PPC or not?
> It's just the way the SOCs are designed. SOCs that are designed
> around same chassis, reuse most of the components.
> It cuts down on s/w development time, because most of the s/w can be
> reused.
Sure, I'm just trying to determine whether this is something I sort of
already understand (like QUICC -> PowerQUICC), or something more internal.
> > > We have kept the code also in such a way. Which is why we have made
> > > Soc Package part of Chassis Package.
> > >
> > > SocLib provides services to PlatformLib. ChassisLib provides services
> > > to SocLib.
> > > Which is why we have made SocGetMpCoreInfo as weak function and
> > > implemented it in ChassisLib (Patch 11/19) This ensures that code can
> > > be reused for all SOCs belonging to same chassis.
> > > If any future SOC implements this feature in different way, then this
> > > API can be overwritten in SocLib
> > >
> > > SOCs belonging to same Chassis share many same traits.
> > > e.g. the SOC memory map is usually common for all SOCs belonging to
> > > same Chassis.
> >
> > OK, this sounds valid. But one follow-up question: why add the hierarchy at all?
> > From a (human) discoverability standpoint, if someone is looking for the code
> > for a specific SoC, they will be looking for that SoC, not some abstraction of it.
> >
> > So I agree it makes sense that chassis are not kept under SoC, but I am asking if
> > it would not make more sense to keep them on the same level?
> > Any SoCs depending on Pcds defined by a specific chassis could access those by
> > importing the package fr that chassis.
>
> Hmm. This can be done. We can make Silicon/NXP/Chassis2 and
> Silicon/NXP/LS1043A.
Sorry, I think I forgot to reply to this.
Yes, this would be most excellent.
Best Regards,
Leif
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 08/19] Silicon/NXP: Remove unnecessary PCDs
2020-02-11 8:45 ` Pankaj Bansal
@ 2020-02-20 18:56 ` Leif Lindholm
0 siblings, 0 replies; 49+ messages in thread
From: Leif Lindholm @ 2020-02-20 18:56 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi,
devel@edk2.groups.io
On Tue, Feb 11, 2020 at 08:45:13 +0000, Pankaj Bansal wrote:
> > -----Original Message-----
> > From: Leif Lindholm <leif@nuviainc.com>
> > Sent: Monday, February 10, 2020 11:02 PM
> > To: Pankaj Bansal <pankaj.bansal@nxp.com>
> > Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Michael D Kinney
> > <michael.d.kinney@intel.com>; Varun Sethi <V.Sethi@nxp.com>;
> > devel@edk2.groups.io
> > Subject: Re: [PATCH 08/19] Silicon/NXP: Remove unnecessary PCDs
> >
> > On Fri, Feb 07, 2020 at 18:13:17 +0530, Pankaj Bansal wrote:
> > > There is no need to keep SOC specific PCDs defined for each SOC.
> >
> > That sound like the definition of why we have SoC-specific Pcds, so I don't
> > follow.
> >
> > > we can do away with these PCDs.
> >
> > After looking through this patchset, it looks like:
> > 1) Initial implementation defined a bunch of things as Pcds which
> > really cannot vary between different platforms using the same SoC.
>
> Yes.
>
> > 2) This patch moves several things that can differ between platforms
> > into #defines, when they should be Pcds.
> >
> > I am OK with the 1)s, but there are some you would need to convince me are not
> > 2:s.
>
> I have moved only those things to #define, which would be common for all platforms using the SOC.
> I will explain more below.
Thanks.
> >
> > > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> > > ---
> > > .../Drivers/PlatformDxe/PlatformDxe.c | 15 +--
> > > .../Drivers/PlatformDxe/PlatformDxe.inf | 8 +-
> > > Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 1 -
> > > .../Library/PlatformLib/ArmPlatformLib.inf | 21 +---
> > > .../Library/PlatformLib/NxpQoriqLsMem.c | 103 +++++++++---------
> > > Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 6 -
> > > Silicon/NXP/Include/Chassis2/NxpSoc.h | 2 +
> > > Silicon/NXP/LS1043A/Include/Soc.h | 44 ++++++++
> > > Silicon/NXP/LS1043A/LS1043A.dsc.inc | 32 ------
> > > Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 2 +-
> > > Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 4 -
> > > Silicon/NXP/NxpQoriqLs.dec | 74 -------------
> > > 12 files changed, 108 insertions(+), 204 deletions(-) create mode
> > > 100644 Silicon/NXP/LS1043A/Include/Soc.h
> > >
> > > diff --git
> > > a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> > > b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> > > index f89dcdeff3..62c400eb1a 100644
> > > --- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> > > +++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> > > @@ -1,7 +1,7 @@
> > > /** @file
> > > LS1043 DXE platform driver.
> > >
> > > - Copyright 2018-2019 NXP
> > > + Copyright 2018-2020 NXP
> > >
> > > SPDX-License-Identifier: BSD-2-Clause-Patent
> > >
> > > @@ -14,6 +14,7 @@
> > > #include <Library/PcdLib.h>
> > > #include <Library/UefiBootServicesTableLib.h>
> > > #include <Library/UefiLib.h>
> > > +#include <Soc.h>
> > >
> > > #include <Protocol/NonDiscoverableDevice.h>
> > >
> > > @@ -22,7 +23,7 @@ typedef struct {
> > > UINT8 EndDesc;
> > > } ADDRESS_SPACE_DESCRIPTOR;
> > >
> > > -STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[FixedPcdGet64
> > > (PcdNumI2cController)];
> > > +STATIC ADDRESS_SPACE_DESCRIPTOR
> > > +mI2cDesc[LS1043A_I2C_NUM_CONTROLLERS];
> >
> > Sure, this one sounds like something not configurable in software or board
> > design.
> >
> > >
> > > STATIC
> > > EFI_STATUS
> > > @@ -65,19 +66,19 @@ PopulateI2cInformation ( {
> > > UINT32 Index;
> > >
> > > - for (Index = 0; Index < FixedPcdGet32 (PcdNumI2cController);
> > > Index++) {
> > > + for (Index = 0; Index < ARRAY_SIZE (mI2cDesc); Index++) {
> > > mI2cDesc[Index].StartDesc.Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
> > > mI2cDesc[Index].StartDesc.Len = sizeof
> > (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
> > > mI2cDesc[Index].StartDesc.ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
> > > mI2cDesc[Index].StartDesc.GenFlag = 0;
> > > mI2cDesc[Index].StartDesc.SpecificFlag = 0;
> > > mI2cDesc[Index].StartDesc.AddrSpaceGranularity = 32;
> > > - mI2cDesc[Index].StartDesc.AddrRangeMin = FixedPcdGet64
> > (PcdI2c0BaseAddr) +
> > > - (Index * FixedPcdGet32 (PcdI2cSize));
> >
> > As does this.
> >
> > > + mI2cDesc[Index].StartDesc.AddrRangeMin =
> > LS1043A_I2C0_PHYS_ADDRESS +
> > > + (Index *
> > > + LS1043A_I2C_SIZE);
> > > mI2cDesc[Index].StartDesc.AddrRangeMax =
> > mI2cDesc[Index].StartDesc.AddrRangeMin +
> > > - FixedPcdGet32 (PcdI2cSize) - 1;
> > > + LS1043A_I2C_SIZE - 1;
> > > mI2cDesc[Index].StartDesc.AddrTranslationOffset = 0;
> > > - mI2cDesc[Index].StartDesc.AddrLen = FixedPcdGet32 (PcdI2cSize);
> > > + mI2cDesc[Index].StartDesc.AddrLen = LS1043A_I2C_SIZE;
> > >
> > > mI2cDesc[Index].EndDesc = ACPI_END_TAG_DESCRIPTOR;
> > > }
> > > diff --git
> > > a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> > > b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> > > index d689cf4db5..126a1174fa 100644
> > > --- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> > > +++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> > > @@ -2,7 +2,7 @@
> > > #
> > > # Component description file for LS1043 DXE platform driver.
> > > #
> > > -# Copyright 2018-2019 NXP
> > > +# Copyright 2018-2020 NXP
> > > #
> > > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -25,6 +25,7 @@
> > > MdeModulePkg/MdeModulePkg.dec
> > > Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
> > > Silicon/NXP/NxpQoriqLs.dec
> > > + Silicon/NXP/LS1043A/LS1043A.dec
> >
> > Please insert sorted alphabetically.
> >
> > >
> > > [LibraryClasses]
> > > BaseLib
> > > @@ -43,10 +44,5 @@
> > > gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES
> > > gDs1307RealTimeClockLibI2cMasterProtocolGuid ## PRODUCES
> > >
> > > -[FixedPcd]
> > > - gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
> > > - gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
> > > - gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
> >
> > Still good.
> >
> > > -
> > > [Depex]
> > > TRUE
> > > diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > > b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > > index 802cccdce6..74a1948fc6 100644
> > > --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > > +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > > @@ -42,7 +42,6 @@
> > > #
> > > # Board Specific Pcds
> > > #
> > > - gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
> >
> > But this sounds exactly like the kind of thing that would be configured differently
> > for different boards. Can you please explain why this should be removed?
>
> This PCD was defined because LS1043A (Chassis2 based SOC) has one Serdes.
> Other Soc based on Chassis2 LS1046A, has two Serdes. So this Pcd is false for LS1043A
> and true for LS1046A. Serdes block in Layerscape SOCs control which devices are enabled
> and which devices are disabled ? e.g. (hypothetical example) with Serdes protocol 5,
> out of 8 MACs, only 3 and 6 and enabled.
>
> Going forward the plan is to move the Serdes handling
> to SOC specific code and NOT to Chassis specific code. This is because the serdes
> protocols are SOC specific and not chassis specific. i.e. both LS1046A and LS1043A can have
> serdes protocol 5. But their meaning can be different for both
>
> For the time being we have removed Serdes related code (in PATCH 07/19). We will introduce
> It after PEI phase changes are merged.
OK. This explanation makes sense, and I approve of the future
strategy. But I think it would be clearer if this change moved to the
same patch as the one deleting the code.
> >
> > > gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
> > >
> > > #
> > > diff --git
> > > a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> > > b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> > > index f7ae74afc6..054dc4d003 100644
> > > ---
> > > a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> > > +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.in
> > > +++ f
> > > @@ -1,7 +1,7 @@
> > > # @file
> > > #
> > > # Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> > > -# Copyright 2017, 2019 NXP
> > > +# Copyright 2017, 2019-2020 NXP
> > > #
> > > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -20,6 +20,7 @@
> > > EmbeddedPkg/EmbeddedPkg.dec
> > > MdePkg/MdePkg.dec
> > > Silicon/NXP/NxpQoriqLs.dec
> > > + Silicon/NXP/LS1043A/LS1043A.dec
> >
> > Insert sorted.
> >
> > >
> > > [LibraryClasses]
> > > ArmLib
> > > @@ -35,21 +36,3 @@
> > >
> > > [FixedPcd]
> > > gArmTokenSpaceGuid.PcdArmPrimaryCore
> > > - gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
> > > - gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
> > > - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
> > > - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
> > > - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
> > > - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
> > > - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr
> > > - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize
> > > - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr
> > > - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize
> > > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
> > > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
> > > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
> > > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
> > > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
> > > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
> > > - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
> > > - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
> > > diff --git
> > > a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> > > b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> > > index c6c256da07..3a72c8bdd8 100644
> > > --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> > > +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> > > @@ -6,7 +6,7 @@
> > > *
> > > * Copyright (c) 2011, ARM Limited. All rights reserved.
> > > * Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> > > -* Copyright 2017, 2019 NXP
> > > +* Copyright 2017, 2019-2020 NXP
> > > *
> > > * SPDX-License-Identifier: BSD-2-Clause-Patent
> > > *
> > > @@ -16,7 +16,7 @@
> > > #include <Library/DebugLib.h>
> > > #include <Library/PcdLib.h>
> > > #include <Library/MemoryAllocationLib.h> -#include <DramInfo.h>
> > > +#include <Soc.h>
> > >
> > > #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
> > >
> > > @@ -38,7 +38,6 @@ ArmPlatformGetVirtualMemoryMap ( {
> > > UINTN Index;
> > > ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
> > > - DRAM_INFO DramInfo;
> > >
> > > Index = 0;
> > >
> > > @@ -51,25 +50,21 @@ ArmPlatformGetVirtualMemoryMap (
> > > return;
> > > }
> > >
> > > - if (GetDramBankInfo (&DramInfo)) {
> > > - DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n"));
> > > - return;
> > > - }
> > > + VirtualMemoryTable[Index].PhysicalBase =
> > > + LS1043A_DRAM0_PHYS_ADDRESS; VirtualMemoryTable[Index].VirtualBase
> > = LS1043A_DRAM0_PHYS_ADDRESS;
> > > + VirtualMemoryTable[Index].Length = LS1043A_DRAM0_SIZE;
> > > + VirtualMemoryTable[Index++].Attributes =
> > ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> > >
> > > -
> > > - for (Index = 0; Index < DramInfo.NumOfDrams; Index++) {
> > > - // DRAM1 (Must be 1st entry)
> > > - VirtualMemoryTable[Index].PhysicalBase =
> > DramInfo.DramRegion[Index].BaseAddress;
> > > - VirtualMemoryTable[Index].VirtualBase =
> > DramInfo.DramRegion[Index].BaseAddress;
> > > - VirtualMemoryTable[Index].Length = DramInfo.DramRegion[Index].Size;
> > > - VirtualMemoryTable[Index].Attributes =
> > ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> > > - }
> > > + VirtualMemoryTable[Index].PhysicalBase =
> > > + LS1043A_DRAM1_PHYS_ADDRESS; VirtualMemoryTable[Index].VirtualBase
> > = LS1043A_DRAM1_PHYS_ADDRESS;
> > > + VirtualMemoryTable[Index].Length = LS1043A_DRAM1_SIZE;
> > > + VirtualMemoryTable[Index++].Attributes =
> > ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> >
> > No changes to this file so far appear to have anything to do with what the
> > commit message says the patch does.
> >
> > >
> > > // CCSR Space
> > > - VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64
> > > (PcdCcsrBaseAddr);
> > > - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdCcsrBaseAddr);
> > > - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
> > > - VirtualMemoryTable[Index].Attributes =
> > ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> > > + VirtualMemoryTable[Index].PhysicalBase = LS1043A_CCSR_PHYS_ADDRESS;
> > > + VirtualMemoryTable[Index].VirtualBase = LS1043A_CCSR_PHYS_ADDRESS;
> > > + VirtualMemoryTable[Index].Length = LS1043A_CCSR_SIZE;
> > > + VirtualMemoryTable[Index++].Attributes =
> > ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> >
> > If these are not reconfigurable for different platforms, sure.
>
> Yes. The SOC memory map is fixed in hardware. It doesn't change with Platform using SOC.
OK, cool. Then I'm OK with all of these.
> >
> > >
> > > // IFC region 1
> > > //
> > > @@ -85,60 +80,60 @@ ArmPlatformGetVirtualMemoryMap (
> > > // For write transactions from non-core masters (like system DMA),
> > the address
> > > // should be 16 byte aligned and the data size should be multiple of
> > 16 bytes.
> > > //
> > > - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64
> > > (PcdIfcRegion1BaseAddr);
> > > - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64
> > (PcdIfcRegion1BaseAddr);
> > > - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion1Size);
> > > - VirtualMemoryTable[Index].Attributes =
> > ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> > > + VirtualMemoryTable[Index].PhysicalBase = LS1043A_IFC0_PHYS_ADDRESS;
> > > + VirtualMemoryTable[Index].VirtualBase = LS1043A_IFC0_PHYS_ADDRESS;
> > > + VirtualMemoryTable[Index].Length = LS1043A_IFC0_SIZE;
> > > + VirtualMemoryTable[Index++].Attributes =
> > ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> >
> > If these are not reconfigurable for different platforms, sure.
> >
> > >
> > > // QMAN SWP
> > > - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64
> > > (PcdQmanSwpBaseAddr);
> > > - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64
> > (PcdQmanSwpBaseAddr);
> > > - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQmanSwpSize);
> > > - VirtualMemoryTable[Index].Attributes =
> > ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> > > + VirtualMemoryTable[Index].PhysicalBase =
> > > + LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS;
> > > + VirtualMemoryTable[Index].VirtualBase =
> > LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS;
> > > + VirtualMemoryTable[Index].Length = LS1043A_QMAN_SW_PORTAL_SIZE;
> > > + VirtualMemoryTable[Index++].Attributes =
> > ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> > >
> >
> > If these are not reconfigurable for different platforms, sure.
> >
> > > // BMAN SWP
> > > - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64
> > > (PcdBmanSwpBaseAddr);
> > > - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64
> > (PcdBmanSwpBaseAddr);
> > > - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdBmanSwpSize);
> > > - VirtualMemoryTable[Index].Attributes =
> > ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> > > + VirtualMemoryTable[Index].PhysicalBase =
> > > + LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS;
> > > + VirtualMemoryTable[Index].VirtualBase =
> > LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS;
> > > + VirtualMemoryTable[Index].Length = LS1043A_QMAN_SW_PORTAL_SIZE;
> > > + VirtualMemoryTable[Index++].Attributes =
> > ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> > >
> >
> > If these are not reconfigurable for different platforms, sure.
> >
> > > // IFC region 2
> > > - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64
> > > (PcdIfcRegion2BaseAddr);
> > > - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64
> > (PcdIfcRegion2BaseAddr);
> > > - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion2Size);
> > > - VirtualMemoryTable[Index].Attributes =
> > ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> > > + VirtualMemoryTable[Index].PhysicalBase = LS1043A_IFC1_PHYS_ADDRESS;
> > > + VirtualMemoryTable[Index].VirtualBase = LS1043A_IFC1_PHYS_ADDRESS;
> > > + VirtualMemoryTable[Index].Length = LS1043A_IFC1_SIZE;
> > > + VirtualMemoryTable[Index++].Attributes =
> > ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> > >
> >
> > If these are not reconfigurable for different platforms, sure.
> >
> > > // PCIe1
> > > - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64
> > > (PcdPciExp1BaseAddr);
> > > - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64
> > (PcdPciExp1BaseAddr);
> > > - VirtualMemoryTable[Index].Length = FixedPcdGet64
> > (PcdPciExp1BaseSize);
> > > - VirtualMemoryTable[Index].Attributes =
> > ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> > > + VirtualMemoryTable[Index].PhysicalBase = LS1043A_PCI0_PHYS_ADDRESS;
> > > + VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI0_PHYS_ADDRESS;
> > > + VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
> > > + VirtualMemoryTable[Index++].Attributes =
> > ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> > >
> >
> > If these are not reconfigurable for different platforms, sure.
> >
> > > // PCIe2
> > > - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64
> > > (PcdPciExp2BaseAddr);
> > > - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64
> > (PcdPciExp2BaseAddr);
> > > - VirtualMemoryTable[Index].Length = FixedPcdGet64
> > (PcdPciExp2BaseSize);
> > > - VirtualMemoryTable[Index].Attributes =
> > ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> > > + VirtualMemoryTable[Index].PhysicalBase = LS1043A_PCI1_PHYS_ADDRESS;
> > > + VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI1_PHYS_ADDRESS;
> > > + VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
> > > + VirtualMemoryTable[Index++].Attributes =
> > ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> > >
> >
> > If these are not reconfigurable for different platforms, sure.
> >
> > > // PCIe3
> > > - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64
> > > (PcdPciExp3BaseAddr);
> > > - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64
> > (PcdPciExp3BaseAddr);
> > > - VirtualMemoryTable[Index].Length = FixedPcdGet64
> > (PcdPciExp3BaseSize);
> > > - VirtualMemoryTable[Index].Attributes =
> > ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> > > + VirtualMemoryTable[Index].PhysicalBase = LS1043A_PCI2_PHYS_ADDRESS;
> > > + VirtualMemoryTable[Index].VirtualBase = LS1043A_PCI2_PHYS_ADDRESS;
> > > + VirtualMemoryTable[Index].Length = LS1043A_PCI_SIZE;
> > > + VirtualMemoryTable[Index++].Attributes =
> > ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> >
> > If these are not reconfigurable for different platforms, sure.
> > >
> > > // QSPI region
> > > - VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64
> > > (PcdQspiRegionBaseAddr);
> > > - VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64
> > (PcdQspiRegionBaseAddr);
> > > - VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegionSize);
> > > - VirtualMemoryTable[Index].Attributes =
> > ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> > > + VirtualMemoryTable[Index].PhysicalBase = LS1043A_QSPI_PHYS_ADDRESS;
> > > + VirtualMemoryTable[Index].VirtualBase = LS1043A_QSPI_PHYS_ADDRESS;
> > > + VirtualMemoryTable[Index].Length = LS1043A_QSPI_SIZE;
> > > + VirtualMemoryTable[Index++].Attributes =
> > ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> >
> > If these are not reconfigurable for different platforms, sure.
> >
> > >
> > > // End of Table
> > > - VirtualMemoryTable[++Index].PhysicalBase = 0;
> > > + VirtualMemoryTable[Index].PhysicalBase = 0;
> >
> > Move that ++ back where it belongs - there is no functional change here.
>
> I will remove this change and will keep functional changes only in this patch.
Thx.
> >
> > > VirtualMemoryTable[Index].VirtualBase = 0;
> > > VirtualMemoryTable[Index].Length = 0;
> > > - VirtualMemoryTable[Index].Attributes =
> > (ARM_MEMORY_REGION_ATTRIBUTES)0;
> > > + VirtualMemoryTable[Index++].Attributes =
> > (ARM_MEMORY_REGION_ATTRIBUTES)0;
> >
> > Move that ++ back where it belongs - there is no functional change here.
> >
> > >
> > > - ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
> > > + ASSERT (Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
> >
> > Drop that +1 = - there is no functional change here.
> >
> > If you want to submit separate patches for coding style changes, that's fine. But
> > given that this set looks like it's making up for not synchronising internal
> > development with the (very long) upstreaming effort so far, I am not interested
> > in those until all functional changes are in.
>
> I will remove this change and will keep functional changes only in this patch.
Thanks.
> >
> > >
> > > *VirtualMemoryMap = VirtualMemoryTable; } diff --git
> > > a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> > > b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> > > index 784139065f..fc4bb618fa 100644
> > > --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> > > +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> > > @@ -49,11 +49,5 @@
> > > gEdkiiNonDiscoverableDeviceProtocolGuid ## TO_START
> > > gEfiI2cMasterProtocolGuid ## BY_START
> > >
> > > -[Pcd]
> > > - gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed
> > > - gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
> > > - gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
> > > - gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
> > > -
> > > [Depex]
> > > TRUE
> > > diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h
> > > b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> > > index 74330b6205..6812beafe4 100644
> > > --- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
> > > +++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> > > @@ -12,6 +12,8 @@
> > >
> > > #define CLK_FREQ 100000000
> > >
> > > +#define CHASSIS2_DCFG_ADDRESS 0x1EE0000
> > > +
> > > /* SMMU Defintions */
> > > #define SMMU_BASE_ADDR 0x09000000
> > > #define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
> > > diff --git a/Silicon/NXP/LS1043A/Include/Soc.h
> > > b/Silicon/NXP/LS1043A/Include/Soc.h
> > > new file mode 100644
> > > index 0000000000..c1e00394af
> > > --- /dev/null
> > > +++ b/Silicon/NXP/LS1043A/Include/Soc.h
> > > @@ -0,0 +1,44 @@
> > > +/** @file
> > > +
> > > + Copyright 2020 NXP
> > > +
> > > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > > +
> > > +**/
> > > +#ifndef __SOC_H__
> > > +#define __SOC_H__
> > > +
> > > +/**
> > > + Soc Memory Map
> > > +**/
> > > +#define LS1043A_DRAM0_PHYS_ADDRESS 0x80000000
> > > +#define LS1043A_DRAM0_SIZE SIZE_2GB
> > > +#define LS1043A_DRAM1_PHYS_ADDRESS 0x880000000
> > > +#define LS1043A_DRAM1_SIZE 0x780000000 // 30 GB
> > > +
> > > +#define LS1043A_CCSR_PHYS_ADDRESS 0x1000000
> > > +#define LS1043A_CCSR_SIZE 0xF000000
> > > +
> > > +#define LS1043A_IFC0_PHYS_ADDRESS 0x60000000
> > > +#define LS1043A_IFC0_SIZE SIZE_512MB
> > > +#define LS1043A_IFC1_PHYS_ADDRESS 0x620000000
> > > +#define LS1043A_IFC1_SIZE 0xE0000000 // 3.5 GB
> > > +
> > > +#define LS1043A_QSPI_PHYS_ADDRESS 0x40000000
> > > +#define LS1043A_QSPI_SIZE SIZE_512MB
> > > +
> > > +#define LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS 0x500000000
> > > +#define LS1043A_QMAN_SW_PORTAL_SIZE SIZE_128MB
> > > +#define LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS 0x508000000
> > > +#define LS1043A_BMAN_SW_PORTAL_SIZE SIZE_128MB
> > > +
> > > +#define LS1043A_PCI0_PHYS_ADDRESS 0x4000000000
> > > +#define LS1043A_PCI1_PHYS_ADDRESS 0x4800000000
> > > +#define LS1043A_PCI2_PHYS_ADDRESS 0x5000000000
> > > +#define LS1043A_PCI_SIZE SIZE_32GB
> > > +
> > > +#define LS1043A_I2C0_PHYS_ADDRESS 0x2180000
> > > +#define LS1043A_I2C_SIZE 0x10000
> > > +#define LS1043A_I2C_NUM_CONTROLLERS 4
> > > +
> > > +#endif
> > > diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > > b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > > index 754eff396a..7ebbb1a495 100644
> > > --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > > +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> > > @@ -26,40 +26,8 @@
> > > [PcdsFixedAtBuild.common]
> > > gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
> > >
> > > - #
> > > - # CCSR Address Space and other attached Memories
> > > - #
> > > - gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
> > > - gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
> > > - gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000
> > > - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000
> > > - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000
> > > - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000
> > > - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000
> > > - gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA
> > > - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000
> > > - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000
> > > - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000
> > > - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000
> > > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000
> > > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000
> > > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000
> > > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000
> > > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000
> > > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000
> > > - gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000
> > > - gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000
> > > - gNxpQoriqLsTokenSpaceGuid.PcdWatchdog1BaseAddr|0x02AD0000
> > > - gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000
> > > - gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000
> > > - gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
> > > - gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
> > > - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
> > > - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
> > > -
> > > #
> > > # Big Endian IPs
> > > #
> > > gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
> > > - gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|TRUE
> > > ##
> > > diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > > b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > > index 9baeb17ecf..a3dabc93d1 100644
> > > --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > > +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > > @@ -34,7 +34,7 @@ GetSysInfo (
> > > CCSR_GUR *GurBase;
> > > UINTN SysClk;
> > >
> > > - GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> > > + GurBase = (CCSR_GUR *)CHASSIS2_DCFG_ADDRESS;
> > > SysClk = CLK_FREQ;
> > >
> > > SetMem (PtrSysInfo, sizeof (SYS_INFO), 0); diff --git
> > > a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > > b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > > index fe77717337..d8707927b7 100644
> > > --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > > +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> > > @@ -40,9 +40,5 @@
> > > gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
> > > gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
> > > gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> > > - gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
> > > gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
> > > - gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
> > > gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
> > > - gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr
> > > - gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
> > > diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> > > index 4a1cfb3e27..b478560450 100644
> > > --- a/Silicon/NXP/NxpQoriqLs.dec
> > > +++ b/Silicon/NXP/NxpQoriqLs.dec
> > > @@ -22,89 +22,15 @@
> > > gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4,
> > > {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
> > >
> > > [PcdsFixedAtBuild.common]
> > > - #
> > > - # Pcds for I2C Controller
> > > - #
> > > - gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000001
> > > - gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000002
> > > -
> > > - #
> > > - # Pcds for base address and size
> > > - #
> > > - gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x0|UINT64|0x00000100
> > > - gNxpQoriqLsTokenSpaceGuid.PcdPiFdSize|0x0|UINT32|0x00000101
> > > -
> > gNxpQoriqLsTokenSpaceGuid.PcdPiFdBaseAddress|0x0|UINT64|0x00000102
> > > - gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x0|UINT64|0x00000103
> > > -
> > >
> > gNxpQoriqLsTokenSpaceGuid.PcdWatchdog1BaseAddr|0x0|UINT64|0x0000010
> > 4
> > > - gNxpQoriqLsTokenSpaceGuid.PcdDdrBaseAddr|0x0|UINT64|0x00000105
> > > - gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x0|UINT64|0x00000106
> > > - gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x0|UINT64|0x00000107
> > > - gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x0|UINT64|0x00000108
> > > - gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x0|UINT32|0x00000109
> > > - gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x0|UINT64|0x0000010A
> > > - gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0|UINT64|0x0000010B
> > > - gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x0000010C
> > > - gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x0000010D
> > > -
> > gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0|UINT64|0x0000010E
> > > - gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0|UINT64|0x0000010F
> > > -
> > gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0|UINT64|0x00000110
> > > - gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0|UINT64|0x00000111
> > > -
> > gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x0|UINT64|0x00000112
> > > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x0|UINT64|0x00000113
> > > -
> > gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x0|UINT64|0x00000114
> > > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x0|UINT64|0x00000115
> > > -
> > gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x0|UINT64|0x00000116
> > > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x0|UINT64|0x00000117
> > > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x0|UINT64|0x0000118
> > > - gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x0|UINT64|0x0000119
> > > -
> > >
> > gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x0|UINT64|0x0000011
> > A
> > > - gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x0|UINT64|0x0000011B
> > > -
> > >
> > gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x0|UINT64|0x000001
> > 1C
> > > -
> > gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x0|UINT64|0x0000011D
> > > -
> > >
> > gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExBase|0x0|UINT64|0x00000
> > 11E
> > > -
> > >
> > gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExSize|0x0|UINT64|0x000001
> > 1F
> > > - gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x0|UINT32|0x00000120
> > > - gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x0|UINT32|0x00000121
> > > - gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000122
> > > - gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000123
> > > -
> > > - #
> > > - # IFC PCDs
> > > - #
> > > -
> > >
> > gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x0|UINT64|0x0000019
> > 0
> > > - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x0|UINT64|0x00000191
> > > -
> > >
> > gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0|UINT64|0x0000019
> > 2
> > > - gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x0|UINT64|0x00000193
> > > -
> > >
> > gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x0|UINT32|0x0000019
> > 4
> > > -
> > >
> > gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x0|UINT64|0x00000195
> > > -
> > >
> > gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x0|UINT64|0x0
> > 0
> > > 000196
> > > -
> > > - #
> > > - # NV Pcd
> > > - #
> > > - gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase|0x0|UINT64|0x00000210
> > > - gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize|0x0|UINT64|0x00000211
> >
> > Not able to be different between different platforms using the same SoC?
>
> This is a redundant Pcd. For Non Volatile Variables we already have PCDs like
> gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64
> gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64
Could you break out deletion of any unused Pcds in a separate patch?
> >
> > > -
> > > #
> > > # Platform PCDs
> > > #
> > > gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
> > > -
> > >
> > gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x0000025
> > 1
> > > -
> > > - #
> > > - # Clock PCDs
> > > - #
> > > - gNxpQoriqLsTokenSpaceGuid.PcdSysClk|0x0|UINT64|0x000002A0
> > > - gNxpQoriqLsTokenSpaceGuid.PcdDdrClk|0x0|UINT64|0x000002A1
> >
> > And clocks also sound very much like something that can change per platform?
>
> Yes Clocks can change. And also clocks are not fixed in all
> platforms. i.e. in most of the platforms based on the
> switch settings, FPGA or Clock generator can be configured to
> provide different SYS clock / DDR Clock / SERDES clock etc.
OK, so these are simply more redundant Pcds?
> Also we need the clock even when we don't have the support for PCD
> framework.
> Which is why we have moved the clock functionality in ArmPlatformLib
> Refer "NxpPlatformGetClock" in patch 14/19.
OK. So, does this belong in 14/19 or in the patch that deletes already
redundant Pcds?
Best Regards,
Leif
> >
> > /
> > Leif
> >
> > >
> > > #
> > > # Pcds to support Big Endian IPs
> > > #
> > > -
> > gNxpQoriqLsTokenSpaceGuid.PcdMmcBigEndian|FALSE|BOOLEAN|0x0000310
> > >
> > gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311
> > > -
> > >
> > gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x0000031
> > 2
> > > -
> > >
> > gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|FALSE|BOOLEAN|0x0000
> > 031
> > > 3
> > > -
> > gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314
> > >
> > > [PcdsFeatureFlag]
> > >
> > >
> > gNxpQoriqLsTokenSpaceGuid.PcdI2cErratumA009203|FALSE|BOOLEAN|0x0000
> > 031
> > > 5
> > > --
> > > 2.17.1
> > >
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 07/19] Silicon/NXP: remove not needed components
2020-02-11 7:24 ` Pankaj Bansal
@ 2020-02-20 19:05 ` Leif Lindholm
0 siblings, 0 replies; 49+ messages in thread
From: Leif Lindholm @ 2020-02-20 19:05 UTC (permalink / raw)
To: Pankaj Bansal
Cc: Meenakshi Aggarwal, Michael D Kinney, Varun Sethi,
devel@edk2.groups.io
On Tue, Feb 11, 2020 at 07:24:04 +0000, Pankaj Bansal wrote:
> > On Fri, Feb 07, 2020 at 18:13:16 +0530, Pankaj Bansal wrote:
> > > We are changing the directory structure of code.
> > > After PEI phase impelmentation this info would be put back into
> > > appropriate location.
> >
> > The message needs clarifying:
> > What is being deleted, why is this not a problem, and what is being put back?
>
> The structures elements and functions that are not necessary for
> booting are being deleted. Once the directory structure has been
> changed (i.e. we have clear distinction between chassis code and
> header files and SOC code and header files), we will put back the
> code and structure components back at their appropriate respective
> place.
I'm going to be honest here. I'm not super happy about code just
merged (after 3 years) being pulled back out to simplify further
upstreaming...
> Also right now all the elements are being defined in structures,
> which are not being used right now. So to simplify the review, I
> have removed those for now. When we need to use those elements, we
> can define those one by one.
...to then be put back afterwards.
To be blunt, this looks like extra effort for me in order to keep
your project managers happy... (yes, I realise it is also extra
effort for you).
...but I can go along with this if you remain as responsive and
receptive to feedback as you have so far. Let's just not do this
again.
Best Regards,
Leif
> >
> > /
> > Leif
> >
> > > Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> > > ---
> > > Silicon/NXP/Include/Chassis2/NxpSoc.h | 314 +---------------------
> > > Silicon/NXP/Library/SocLib/Chassis.c | 15 --
> > > Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 79 ------
> > > 3 files changed, 2 insertions(+), 406 deletions(-)
> > >
> > > diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h
> > > b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> > > index f05a813750..74330b6205 100644
> > > --- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
> > > +++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> > > @@ -1,7 +1,7 @@
> > > /** Soc.h
> > > * Header defining the Base addresses, sizes, flags etc for chassis 1
> > > *
> > > -* Copyright 2017-2019 NXP
> > > +* Copyright 2017-2020 NXP
> > > *
> > > * SPDX-License-Identifier: BSD-2-Clause-Patent
> > > *
> > > @@ -10,22 +10,7 @@
> > > #ifndef NXP_SOC_H_
> > > #define NXP_SOC_H_
> > >
> > > -#define HWA_CGA_M1_CLK_SEL 0xe0000000
> > > -#define HWA_CGA_M1_CLK_SHIFT 29
> > > -
> > > -#define TP_CLUSTER_EOC_MASK 0xc0000000 /* end of clusters mask */
> > > -#define NUM_CC_PLLS 2
> > > #define CLK_FREQ 100000000
> > > -#define MAX_CPUS 4
> > > -#define NUM_FMAN 1
> > > -#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) ==
> > 0x0)
> > > -
> > > -/* RCW SERDES MACRO */
> > > -#define RCWSR_INDEX 4
> > > -#define RCWSR_SRDS1_PRTCL_MASK 0xffff0000
> > > -#define RCWSR_SRDS1_PRTCL_SHIFT 16
> > > -#define RCWSR_SRDS2_PRTCL_MASK 0x0000ffff
> > > -#define RCWSR_SRDS2_PRTCL_SHIFT 0
> > >
> > > /* SMMU Defintions */
> > > #define SMMU_BASE_ADDR 0x09000000
> > > @@ -41,312 +26,17 @@
> > > #define IDR1_PAGESIZE_MASK 0x80000000
> > >
> > > typedef struct {
> > > - UINTN FreqProcessor[MAX_CPUS];
> > > UINTN FreqSystemBus;
> > > - UINTN FreqDdrBus;
> > > - UINTN FreqLocalBus;
> > > - UINTN FreqSdhc;
> > > - UINTN FreqFman[NUM_FMAN];
> > > - UINTN FreqQman;
> > > } SYS_INFO;
> > >
> > > /* Device Configuration and Pin Control */ typedef struct {
> > > - UINT32 PorSr1; /* POR status 1 */
> > > -#define CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
> > > - UINT32 PorSr2; /* POR status 2 */
> > > - UINT8 Res008[0x20-0x8];
> > > - UINT32 GppOrCr1; /* General-purpose POR configuration */
> > > - UINT32 GppOrCr2;
> > > - UINT32 DcfgFuseSr; /* Fuse status register */
> > > - UINT8 Res02c[0x70-0x2c];
> > > - UINT32 DevDisr; /* Device disable control */
> > > - UINT32 DevDisr2; /* Device disable control 2 */
> > > - UINT32 DevDisr3; /* Device disable control 3 */
> > > - UINT32 DevDisr4; /* Device disable control 4 */
> > > - UINT32 DevDisr5; /* Device disable control 5 */
> > > - UINT32 DevDisr6; /* Device disable control 6 */
> > > - UINT32 DevDisr7; /* Device disable control 7 */
> > > - UINT8 Res08c[0x94-0x8c];
> > > - UINT32 CoreDisrU; /* uppper portion for support of 64 cores */
> > > - UINT32 CoreDisrL; /* lower portion for support of 64 cores */
> > > - UINT8 Res09c[0xa0-0x9c];
> > > - UINT32 Pvr; /* Processor version */
> > > - UINT32 Svr; /* System version */
> > > - UINT32 Mvr; /* Manufacturing version */
> > > - UINT8 Res0ac[0xb0-0xac];
> > > - UINT32 RstCr; /* Reset control */
> > > - UINT32 RstRqPblSr; /* Reset request preboot loader status */
> > > - UINT8 Res0b8[0xc0-0xb8];
> > > - UINT32 RstRqMr1; /* Reset request mask */
> > > - UINT8 Res0c4[0xc8-0xc4];
> > > - UINT32 RstRqSr1; /* Reset request status */
> > > - UINT8 Res0cc[0xd4-0xcc];
> > > - UINT32 RstRqWdTmrL; /* Reset request WDT mask */
> > > - UINT8 Res0d8[0xdc-0xd8];
> > > - UINT32 RstRqWdtSrL; /* Reset request WDT status */
> > > - UINT8 Res0e0[0xe4-0xe0];
> > > - UINT32 BrrL; /* Boot release */
> > > - UINT8 Res0e8[0x100-0xe8];
> > > + UINT8 Res0[0x100-0x00];
> > > UINT32 RcwSr[16]; /* Reset control word status */
> > > #define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25 #define
> > > CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f -#define
> > > CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16 -#define
> > > CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
> > > - UINT8 Res140[0x200-0x140];
> > > - UINT32 ScratchRw[4]; /* Scratch Read/Write */
> > > - UINT8 Res210[0x300-0x210];
> > > - UINT32 ScratcHw1R[4]; /* Scratch Read (Write once) */
> > > - UINT8 Res310[0x400-0x310];
> > > - UINT32 CrstSr[12];
> > > - UINT8 Res430[0x500-0x430];
> > > - /* PCI Express n Logical I/O Device Number register */
> > > - UINT32 DcfgCcsrPex1LiodNr;
> > > - UINT32 DcfgCcsrPex2LiodNr;
> > > - UINT32 DcfgCcsrPex3LiodNr;
> > > - UINT32 DcfgCcsrPex4LiodNr;
> > > - /* RIO n Logical I/O Device Number register */
> > > - UINT32 DcfgCcsrRio1LiodNr;
> > > - UINT32 DcfgCcsrRio2LiodNr;
> > > - UINT32 DcfgCcsrRio3LiodNr;
> > > - UINT32 DcfgCcsrRio4LiodNr;
> > > - /* USB Logical I/O Device Number register */
> > > - UINT32 DcfgCcsrUsb1LiodNr;
> > > - UINT32 DcfgCcsrUsb2LiodNr;
> > > - UINT32 DcfgCcsrUsb3LiodNr;
> > > - UINT32 DcfgCcsrUsb4LiodNr;
> > > - /* SD/MMC Logical I/O Device Number register */
> > > - UINT32 DcfgCcsrSdMmc1LiodNr;
> > > - UINT32 DcfgCcsrSdMmc2LiodNr;
> > > - UINT32 DcfgCcsrSdMmc3LiodNr;
> > > - UINT32 DcfgCcsrSdMmc4LiodNr;
> > > - /* RIO Message Unit Logical I/O Device Number register */
> > > - UINT32 DcfgCcsrRiomaintLiodNr;
> > > - UINT8 Res544[0x550-0x544];
> > > - UINT32 SataLiodNr[4];
> > > - UINT8 Res560[0x570-0x560];
> > > - UINT32 DcfgCcsrMisc1LiodNr;
> > > - UINT32 DcfgCcsrMisc2LiodNr;
> > > - UINT32 DcfgCcsrMisc3LiodNr;
> > > - UINT32 DcfgCcsrMisc4LiodNr;
> > > - UINT32 DcfgCcsrDma1LiodNr;
> > > - UINT32 DcfgCcsrDma2LiodNr;
> > > - UINT32 DcfgCcsrDma3LiodNr;
> > > - UINT32 DcfgCcsrDma4LiodNr;
> > > - UINT32 DcfgCcsrSpare1LiodNr;
> > > - UINT32 DcfgCcsrSpare2LiodNr;
> > > - UINT32 DcfgCcsrSpare3LiodNr;
> > > - UINT32 DcfgCcsrSpare4LiodNr;
> > > - UINT8 Res5a0[0x600-0x5a0];
> > > - UINT32 DcfgCcsrPblSr;
> > > - UINT32 PamuBypENr;
> > > - UINT32 DmaCr1;
> > > - UINT8 Res60c[0x610-0x60c];
> > > - UINT32 DcfgCcsrGenSr1;
> > > - UINT32 DcfgCcsrGenSr2;
> > > - UINT32 DcfgCcsrGenSr3;
> > > - UINT32 DcfgCcsrGenSr4;
> > > - UINT32 DcfgCcsrGenCr1;
> > > - UINT32 DcfgCcsrGenCr2;
> > > - UINT32 DcfgCcsrGenCr3;
> > > - UINT32 DcfgCcsrGenCr4;
> > > - UINT32 DcfgCcsrGenCr5;
> > > - UINT32 DcfgCcsrGenCr6;
> > > - UINT32 DcfgCcsrGenCr7;
> > > - UINT8 Res63c[0x658-0x63c];
> > > - UINT32 DcfgCcsrcGenSr1;
> > > - UINT32 DcfgCcsrcGenSr0;
> > > - UINT8 Res660[0x678-0x660];
> > > - UINT32 DcfgCcsrcGenCr1;
> > > - UINT32 DcfgCcsrcGenCr0;
> > > - UINT8 Res680[0x700-0x680];
> > > - UINT32 DcfgCcsrSrIoPstecr;
> > > - UINT32 DcfgCcsrDcsrCr;
> > > - UINT8 Res708[0x740-0x708]; /* add more registers when needed */
> > > - UINT32 TpItyp[64]; /* Topology Initiator Type Register */
> > > - struct {
> > > - UINT32 Upper;
> > > - UINT32 Lower;
> > > - } TpCluster[16];
> > > - UINT8 Res8c0[0xa00-0x8c0]; /* add more registers when needed */
> > > - UINT32 DcfgCcsrQmBmWarmRst;
> > > - UINT8 Resa04[0xa20-0xa04]; /* add more registers when needed */
> > > - UINT32 DcfgCcsrReserved0;
> > > - UINT32 DcfgCcsrReserved1;
> > > } CCSR_GUR;
> > >
> > > -/* Supplemental Configuration Unit */ -typedef struct {
> > > - UINT8 Res000[0x070-0x000];
> > > - UINT32 Usb1Prm1Cr;
> > > - UINT32 Usb1Prm2Cr;
> > > - UINT32 Usb1Prm3Cr;
> > > - UINT32 Usb2Prm1Cr;
> > > - UINT32 Usb2Prm2Cr;
> > > - UINT32 Usb2Prm3Cr;
> > > - UINT32 Usb3Prm1Cr;
> > > - UINT32 Usb3Prm2Cr;
> > > - UINT32 Usb3Prm3Cr;
> > > - UINT8 Res094[0x100-0x094];
> > > - UINT32 Usb2Icid;
> > > - UINT32 Usb3Icid;
> > > - UINT8 Res108[0x114-0x108];
> > > - UINT32 DmaIcid;
> > > - UINT32 SataIcid;
> > > - UINT32 Usb1Icid;
> > > - UINT32 QeIcid;
> > > - UINT32 SdhcIcid;
> > > - UINT32 EdmaIcid;
> > > - UINT32 EtrIcid;
> > > - UINT32 Core0SftRst;
> > > - UINT32 Core1SftRst;
> > > - UINT32 Core2SftRst;
> > > - UINT32 Core3SftRst;
> > > - UINT8 Res140[0x158-0x140];
> > > - UINT32 AltCBar;
> > > - UINT32 QspiCfg;
> > > - UINT8 Res160[0x180-0x160];
> > > - UINT32 DmaMcr;
> > > - UINT8 Res184[0x188-0x184];
> > > - UINT32 GicAlign;
> > > - UINT32 DebugIcid;
> > > - UINT8 Res190[0x1a4-0x190];
> > > - UINT32 SnpCnfGcr;
> > > -#define CCSR_SCFG_SNPCNFGCR_SECRDSNP BIT31
> > > -#define CCSR_SCFG_SNPCNFGCR_SECWRSNP BIT30
> > > -#define CCSR_SCFG_SNPCNFGCR_SATARDSNP BIT23
> > > -#define CCSR_SCFG_SNPCNFGCR_SATAWRSNP BIT22
> > > -#define CCSR_SCFG_SNPCNFGCR_USB1RDSNP BIT21
> > > -#define CCSR_SCFG_SNPCNFGCR_USB1WRSNP BIT20
> > > -#define CCSR_SCFG_SNPCNFGCR_USB2RDSNP BIT15
> > > -#define CCSR_SCFG_SNPCNFGCR_USB2WRSNP BIT16
> > > -#define CCSR_SCFG_SNPCNFGCR_USB3RDSNP BIT13
> > > -#define CCSR_SCFG_SNPCNFGCR_USB3WRSNP BIT14
> > > - UINT8 Res1a8[0x1ac-0x1a8];
> > > - UINT32 IntpCr;
> > > - UINT8 Res1b0[0x204-0x1b0];
> > > - UINT32 CoreSrEnCr;
> > > - UINT8 Res208[0x220-0x208];
> > > - UINT32 RvBar00;
> > > - UINT32 RvBar01;
> > > - UINT32 RvBar10;
> > > - UINT32 RvBar11;
> > > - UINT32 RvBar20;
> > > - UINT32 RvBar21;
> > > - UINT32 RvBar30;
> > > - UINT32 RvBar31;
> > > - UINT32 LpmCsr;
> > > - UINT8 Res244[0x400-0x244];
> > > - UINT32 QspIdQScr;
> > > - UINT32 EcgTxcMcr;
> > > - UINT32 SdhcIoVSelCr;
> > > - UINT32 RcwPMuxCr0;
> > > - /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
> > > - *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
> > > - *Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS
> > > - Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS*/
> > > -#define CCSR_SCFG_RCWPMUXCRO_SELCR_USB 0x3333
> > > - /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
> > > - *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
> > > - *Setting RCW PinMux Register bits 25-27 to select IIC4_SCL
> > > - Setting RCW PinMux Register bits 29-31 to select IIC4_SDA*/
> > > -#define CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300
> > > - UINT32 UsbDrvVBusSelCr;
> > > -#define CCSR_SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
> > > -#define CCSR_SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
> > > -#define CCSR_SCFG_USBDRVVBUS_SELCR_USB3 0x00000003
> > > - UINT32 UsbPwrFaultSelCr;
> > > -#define CCSR_SCFG_USBPWRFAULT_INACTIVE 0x00000000
> > > -#define CCSR_SCFG_USBPWRFAULT_SHARED 0x00000001
> > > -#define CCSR_SCFG_USBPWRFAULT_DEDICATED 0x00000002
> > > -#define CCSR_SCFG_USBPWRFAULT_USB3_SHIFT 4
> > > -#define CCSR_SCFG_USBPWRFAULT_USB2_SHIFT 2
> > > -#define CCSR_SCFG_USBPWRFAULT_USB1_SHIFT 0
> > > - UINT32 UsbRefclkSelcr1;
> > > - UINT32 UsbRefclkSelcr2;
> > > - UINT32 UsbRefclkSelcr3;
> > > - UINT8 Res424[0x600-0x424];
> > > - UINT32 ScratchRw[4];
> > > - UINT8 Res610[0x680-0x610];
> > > - UINT32 CoreBCr;
> > > - UINT8 Res684[0x1000-0x684];
> > > - UINT32 Pex1MsiIr;
> > > - UINT32 Pex1MsiR;
> > > - UINT8 Res1008[0x2000-0x1008];
> > > - UINT32 Pex2;
> > > - UINT32 Pex2MsiR;
> > > - UINT8 Res2008[0x3000-0x2008];
> > > - UINT32 Pex3MsiIr;
> > > - UINT32 Pex3MsiR;
> > > -} CCSR_SCFG;
> > > -
> > > -#define USB_TXVREFTUNE 0x9
> > > -#define USB_SQRXTUNE 0xFC7FFFFF
> > > -#define USB_PCSTXSWINGFULL 0x47
> > > -#define USB_PHY_RX_EQ_VAL_1 0x0000
> > > -#define USB_PHY_RX_EQ_VAL_2 0x8000
> > > -#define USB_PHY_RX_EQ_VAL_3 0x8003
> > > -#define USB_PHY_RX_EQ_VAL_4 0x800b
> > > -
> > > -/*USB_PHY_SS memory map*/
> > > -typedef struct {
> > > - UINT16 IpIdcodeLo;
> > > - UINT16 SupIdcodeHi;
> > > - UINT8 Res4[0x0006-0x0004];
> > > - UINT16 RtuneDebug;
> > > - UINT16 RtuneStat;
> > > - UINT16 SupSsPhase;
> > > - UINT16 SsFreq;
> > > - UINT8 ResE[0x0020-0x000e];
> > > - UINT16 Ateovrd;
> > > - UINT16 MpllOvrdInLo;
> > > - UINT8 Res24[0x0026-0x0024];
> > > - UINT16 SscOvrdIn;
> > > - UINT8 Res28[0x002A-0x0028];
> > > - UINT16 LevelOvrdIn;
> > > - UINT8 Res2C[0x0044-0x002C];
> > > - UINT16 ScopeCount;
> > > - UINT8 Res46[0x0060-0x0046];
> > > - UINT16 MpllLoopCtl;
> > > - UINT8 Res62[0x006C-0x0062];
> > > - UINT16 SscClkCntrl;
> > > - UINT8 Res6E[0x2002-0x006E];
> > > - UINT16 Lane0TxOvrdInHi;
> > > - UINT16 Lane0TxOvrdDrvLo;
> > > - UINT8 Res2006[0x200C-0x2006];
> > > - UINT16 Lane0RxOvrdInHi;
> > > - UINT8 Res200E[0x2022-0x200E];
> > > - UINT16 Lane0TxCmWaitTimeOvrd;
> > > - UINT8 Res2024[0x202A-0x2024];
> > > - UINT16 Lane0TxLbertCtl;
> > > - UINT16 Lane0RxLbertCtl;
> > > - UINT16 Lane0RxLbertErr;
> > > - UINT8 Res2030[0x205A-0x2030];
> > > - UINT16 Lane0TxAltBlock;
> > > -} CCSR_USB_PHY;
> > > -
> > > -/* Clocking */
> > > -typedef struct {
> > > - struct {
> > > - UINT32 ClkCnCSr; /* core cluster n clock control status */
> > > - UINT8 Res004[0x0c];
> > > - UINT32 ClkcGHwAcSr; /* Clock generator n hardware accelerator */
> > > - UINT8 Res014[0x0c];
> > > - } ClkcSr[4];
> > > - UINT8 Res040[0x780]; /* 0x100 */
> > > - struct {
> > > - UINT32 PllCnGSr;
> > > - UINT8 Res804[0x1c];
> > > - } PllCgSr[NUM_CC_PLLS];
> > > - UINT8 Res840[0x1c0];
> > > - UINT32 ClkPCSr; /* 0xa00 Platform clock domain control/status */
> > > - UINT8 Resa04[0x1fc];
> > > - UINT32 PllPGSr; /* 0xc00 Platform PLL General Status */
> > > - UINT8 Resc04[0x1c];
> > > - UINT32 PllDGSr; /* 0xc20 DDR PLL General Status */
> > > - UINT8 Resc24[0x3dc];
> > > -} CCSR_CLOCK;
> > > -
> > > VOID
> > > GetSysInfo (
> > > OUT SYS_INFO *
> > > diff --git a/Silicon/NXP/Library/SocLib/Chassis.c
> > > b/Silicon/NXP/Library/SocLib/Chassis.c
> > > index 18a1f5e4e1..847331a631 100644
> > > --- a/Silicon/NXP/Library/SocLib/Chassis.c
> > > +++ b/Silicon/NXP/Library/SocLib/Chassis.c
> > > @@ -53,21 +53,6 @@ GetBusFrequency (
> > > return SocSysInfo.FreqSystemBus;
> > > }
> > >
> > > -/*
> > > - * Return SDXC bus frequency
> > > - */
> > > -UINT64
> > > -GetSdxcFrequency (
> > > - VOID
> > > - )
> > > -{
> > > - SYS_INFO SocSysInfo;
> > > -
> > > - GetSysInfo (&SocSysInfo);
> > > -
> > > - return SocSysInfo.FreqSdhc;
> > > -}
> > > -
> > > /*
> > > * Setup SMMU in bypass mode
> > > * and also set its pagesize
> > > diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > > b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > > index 3d803716c9..9baeb17ecf 100644
> > > --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > > +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> > > @@ -32,38 +32,14 @@ GetSysInfo (
> > > )
> > > {
> > > CCSR_GUR *GurBase;
> > > - CCSR_CLOCK *ClkBase;
> > > - UINTN CpuIndex;
> > > - UINT32 TempRcw;
> > > - UINT32 CPllSel;
> > > - UINT32 CplxPll;
> > > - CONST UINT8 CoreCplxPll[8] = {
> > > - [0] = 0, /* CC1 PPL / 1 */
> > > - [1] = 0, /* CC1 PPL / 2 */
> > > - [4] = 1, /* CC2 PPL / 1 */
> > > - [5] = 1, /* CC2 PPL / 2 */
> > > - };
> > > -
> > > - CONST UINT8 CoreCplxPllDivisor[8] = {
> > > - [0] = 1, /* CC1 PPL / 1 */
> > > - [1] = 2, /* CC1 PPL / 2 */
> > > - [4] = 1, /* CC2 PPL / 1 */
> > > - [5] = 2, /* CC2 PPL / 2 */
> > > - };
> > > -
> > > - UINTN PllCount;
> > > - UINTN FreqCPll[NUM_CC_PLLS];
> > > - UINTN PllRatio[NUM_CC_PLLS];
> > > UINTN SysClk;
> > >
> > > GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> > > - ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
> > > SysClk = CLK_FREQ;
> > >
> > > SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
> > >
> > > PtrSysInfo->FreqSystemBus = SysClk;
> > > - PtrSysInfo->FreqDdrBus = SysClk;
> > >
> > > //
> > > // selects the platform clock:SYSCLK ratio and calculate @@ -72,61
> > > +48,6 @@ GetSysInfo (
> > > PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
> > > CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
> > > CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
> > > - //
> > > - // selects the DDR PLL:SYSCLK Ratio and calculate DDR frequency
> > > - //
> > > - PtrSysInfo->FreqDdrBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
> > > - CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
> > > - CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
> > > -
> > > - for (PllCount = 0; PllCount < NUM_CC_PLLS; PllCount++) {
> > > - PllRatio[PllCount] = (GurRead ((UINTN)&ClkBase-
> > >PllCgSr[PllCount].PllCnGSr) >> 1) & 0xff;
> > > - if (PllRatio[PllCount] > 4) {
> > > - FreqCPll[PllCount] = SysClk * PllRatio[PllCount];
> > > - } else {
> > > - FreqCPll[PllCount] = PtrSysInfo->FreqSystemBus * PllRatio[PllCount];
> > > - }
> > > - }
> > > -
> > > - //
> > > - // Calculate Core frequency
> > > - //
> > > - for (CpuIndex = 0; CpuIndex < MAX_CPUS; CpuIndex++) {
> > > - CPllSel = (GurRead ((UINTN)&ClkBase->ClkcSr[CpuIndex].ClkCnCSr) >> 27) &
> > 0xf;
> > > - CplxPll = CoreCplxPll[CPllSel];
> > > -
> > > - PtrSysInfo->FreqProcessor[CpuIndex] = FreqCPll[CplxPll] /
> > CoreCplxPllDivisor[CPllSel];
> > > - }
> > > -
> > > - //
> > > - // Calculate FMAN frequency
> > > - //
> > > - TempRcw = GurRead ((UINTN)&GurBase->RcwSr[7]);
> > > - switch ((TempRcw & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT)
> > {
> > > - case 2:
> > > - PtrSysInfo->FreqFman[0] = FreqCPll[0] / 2;
> > > - break;
> > > - case 3:
> > > - PtrSysInfo->FreqFman[0] = FreqCPll[0] / 3;
> > > - break;
> > > - case 4:
> > > - PtrSysInfo->FreqFman[0] = FreqCPll[0] / 4;
> > > - break;
> > > - case 5:
> > > - PtrSysInfo->FreqFman[0] = PtrSysInfo->FreqSystemBus;
> > > - break;
> > > - case 6:
> > > - PtrSysInfo->FreqFman[0] = FreqCPll[1] / 2;
> > > - break;
> > > - case 7:
> > > - PtrSysInfo->FreqFman[0] = FreqCPll[1] / 3;
> > > - break;
> > > - default:
> > > - DEBUG ((DEBUG_WARN, "Error: Unknown FMan1 clock select!\n"));
> > > - break;
> > > - }
> > > - PtrSysInfo->FreqSdhc = PtrSysInfo->FreqSystemBus/PcdGet32
> > > (PcdPlatformFreqDiv);
> > > - PtrSysInfo->FreqQman = PtrSysInfo->FreqSystemBus/PcdGet32
> > > (PcdPlatformFreqDiv); }
> > >
> > > /**
> > > --
> > > 2.17.1
> > >
^ permalink raw reply [flat|nested] 49+ messages in thread
end of thread, other threads:[~2020-02-20 19:05 UTC | newest]
Thread overview: 49+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-02-07 12:43 [PATCH 00/19] ADD LX2160ARDB Platform Support Pankaj Bansal
2020-02-07 12:43 ` [PATCH 01/19] Silicon/NXP: Add I2c lib Pankaj Bansal
2020-02-08 17:13 ` Leif Lindholm
2020-02-09 11:49 ` [edk2-devel] " Ard Biesheuvel
2020-02-07 12:43 ` [PATCH 02/19] Silicon/NXP: changes to use I2clib in i2cdxe Pankaj Bansal
2020-02-08 17:23 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 03/19] NXP/LS1043aRdb: Move Soc specific components to soc files Pankaj Bansal
2020-02-08 17:27 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 04/19] Silicon/NXP: Remove DuartLib and use BaseSerialPortLib16550 Pankaj Bansal
2020-02-08 17:46 ` Leif Lindholm
2020-02-10 5:48 ` Pankaj Bansal
2020-02-12 23:27 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 05/19] NXP/BaseSerialPortLib16550: remove SerialPortInitalize functionality Pankaj Bansal
2020-02-07 12:43 ` [PATCH 06/19] Silicon/NXP: remove print information from Soc lib Pankaj Bansal
2020-02-10 17:09 ` [EXTERNAL] " Leif Lindholm
2020-02-07 12:43 ` [PATCH 07/19] Silicon/NXP: remove not needed components Pankaj Bansal
2020-02-10 17:11 ` Leif Lindholm
2020-02-11 7:24 ` Pankaj Bansal
2020-02-20 19:05 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 08/19] Silicon/NXP: Remove unnecessary PCDs Pankaj Bansal
2020-02-10 17:32 ` Leif Lindholm
2020-02-11 8:45 ` Pankaj Bansal
2020-02-20 18:56 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 09/19] Silicon/NXP: Move dsc file Pankaj Bansal
2020-02-11 11:35 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 10/19] Platform/NXP: rename the ArmPlatformLib as per ArmPlatformPkg Pankaj Bansal
2020-02-11 11:40 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 11/19] Silicon/NXP: Add Chassis Lib for Chassis2 Pankaj Bansal
2020-02-11 12:28 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 12/19] Silicon/NXP/LS1043A: Add SocLib Pankaj Bansal
2020-02-11 12:38 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 13/19] Silicon/NXP: Move RAM retrieval from SocLib Pankaj Bansal
2020-02-11 13:28 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 14/19] Silicon/NXP/LS1043A: Replce SocLib Pankaj Bansal
2020-02-11 13:35 ` Leif Lindholm
2020-02-12 9:37 ` Pankaj Bansal
2020-02-12 22:50 ` Leif Lindholm
2020-02-13 11:00 ` Pankaj Bansal
2020-02-20 18:45 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 15/19] Platform/NXP/LS1043ARDB: introduce PEI Phase Pankaj Bansal
2020-02-12 20:24 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 16/19] Silicon/NXP: Add Pl011 Serial port lib Pankaj Bansal
2020-02-12 20:26 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 17/19] Silicon/NXP: Add Chassis3V2 Pankaj Bansal
2020-02-12 20:33 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 18/19] Silicon/NXP: Add LX2160A SocLib Pankaj Bansal
2020-02-12 21:39 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 19/19] Platform/NXP: Add LX2160ARDBPKG Pankaj Bansal
2020-02-12 21:36 ` Leif Lindholm
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