From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga18.intel.com (mga18.intel.com []) by mx.groups.io with SMTP id smtpd.web09.10529.1581105978095314348 for ; Fri, 07 Feb 2020 12:06:22 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: ashraf.javeed@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Feb 2020 12:06:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,414,1574150400"; d="scan'208";a="225644248" Received: from unknown (HELO PIDSBABIOS005.gar.corp.intel.com) ([10.223.9.183]) by fmsmga007.fm.intel.com with ESMTP; 07 Feb 2020 12:06:19 -0800 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Jian J Wang , Hao A Wu , Ray Ni Subject: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 06/12] PciBusDxe: New PCI Express feature No-Snoop Date: Sat, 8 Feb 2020 01:34:41 +0530 Message-Id: <20200207200447.10536-7-ashraf.javeed@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20200207200447.10536-1-ashraf.javeed@intel.com> References: <20200207200447.10536-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2313 The code changes are made; as per the PCI Express Base Specification 4 Revision 1; to enable the configuration of PCI Express feature No-Snoop (NS), that enables the PCI function to initiate requests if it does not require hardware enforced cache-coherency for its transactions. The code changes are made to configure only those PCI devices which are requested by platform for override through the new PCI Express Platform protocol interface for device-specific policies. Signed-off-by: Ashraf Javeed Cc: Jian J Wang Cc: Hao A Wu Cc: Ray Ni --- MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 1 + MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h | 18 ++++++++++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c | 5 ++++- MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c | 62 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 155 insertions(+), 1 deletion(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h index d3d795d..e610b52 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h @@ -293,6 +293,7 @@ struct _PCI_IO_DEVICE { UINT8 SetupMPS; UINT8 SetupMRRS; PCI_FEATURE_POLICY SetupRO; + PCI_FEATURE_POLICY SetupNS; }; #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \ diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c index 3262b76..df85366 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c @@ -451,3 +451,73 @@ ProgramRelaxOrder ( return Status; } +/** + Overrides the PCI Device Control register No-Snoop register field; if + the hardware value is different than the intended value. + + @param PciDevice A pointer to the PCI_IO_DEVICE instance. + + @retval EFI_SUCCESS The data was read from or written to the PCI device. + @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not + valid for the PCI configuration header of the PCI controller. + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. + +**/ +EFI_STATUS +ProgramNoSnoop ( + IN PCI_IO_DEVICE *PciDevice, + IN VOID *PciExFeatureConfiguration + ) +{ + PCI_REG_PCIE_DEVICE_CONTROL PcieDev; + UINT32 Offset; + EFI_STATUS Status; + EFI_TPL OldTpl; + + PcieDev.Uint16 = 0; + Offset = PciDevice->PciExpressCapabilityOffset + + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl); + Status = PciDevice->PciIo.Pci.Read ( + &PciDevice->PciIo, + EfiPciIoWidthUint16, + Offset, + 1, + &PcieDev.Uint16 + ); + ASSERT (Status == EFI_SUCCESS); + + if (PciDevice->SetupNS.Override + && PcieDev.Bits.NoSnoop != PciDevice->SetupNS.Act + ) { + PcieDev.Bits.NoSnoop = PciDevice->SetupNS.Act; + DEBUG (( DEBUG_INFO, "NS=%d", PciDevice->SetupNS.Act)); + + // + // Raise TPL to high level to disable timer interrupt while the write operation completes + // + OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL); + + Status = PciDevice->PciIo.Pci.Write ( + &PciDevice->PciIo, + EfiPciIoWidthUint16, + Offset, + 1, + &PcieDev.Uint16 + ); + // + // Restore TPL to its original level + // + gBS->RestoreTPL (OldTpl); + + if (!EFI_ERROR(Status)) { + PciDevice->PciExpressCapabilityStructure.DeviceControl.Uint16 = PcieDev.Uint16; + } else { + ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, PciDevice->FunctionNumber, Offset); + } + } else { + DEBUG (( DEBUG_INFO, "No NS,", PciDevice->SetupRO.Act)); + } + + return Status; +} + diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h index 0d17801..ee636ce 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h @@ -115,4 +115,22 @@ ProgramRelaxOrder ( IN VOID *PciExFeatureConfiguration ); +/** + Overrides the PCI Device Control register No-Snoop register field; if + the hardware value is different than the intended value. + + @param PciDevice A pointer to the PCI_IO_DEVICE instance. + + @retval EFI_SUCCESS The data was read from or written to the PCI device. + @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not + valid for the PCI configuration header of the PCI controller. + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. + +**/ +EFI_STATUS +ProgramNoSnoop ( + IN PCI_IO_DEVICE *PciDevice, + IN VOID *PciExFeatureConfiguration + ); + #endif diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c index 267f570..d264d13 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c @@ -46,7 +46,7 @@ EFI_PCI_EXPRESS_PLATFORM_POLICY mPciExpressPlatformPolicy = { // // support for PCI Express feature - No-Snoop // - FALSE, + TRUE, // // support for PCI Express feature - ASPM state // @@ -116,6 +116,9 @@ PCI_EXPRESS_FEATURE_INITIALIZATION_POINT mPciExpressFeatureInitializationList[] }, { PciExpressFeatureProgramPhase, PciExpressRelaxOrder, ProgramRelaxOrder + }, + { + PciExpressFeatureProgramPhase, PciExpressNoSnoop, ProgramNoSnoop } }; diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c index 40eb8a3..954ce16 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c @@ -188,6 +188,46 @@ SetDevicePolicyPciExpressRo ( } } +/** + Routine to set the device-specific policy for the PCI feature No-Snoop enable + or disable + + @param NoSnoop value corresponding to data type EFI_PCI_EXPRESS_NO_SNOOP + @param PciDevice A pointer to PCI_IO_DEVICE +**/ +VOID +SetDevicePolicyPciExpressNs ( + IN EFI_PCI_EXPRESS_NO_SNOOP NoSnoop, + OUT PCI_IO_DEVICE *PciDevice + ) +{ + // + // implementation specific rules for the usage of PCI_FEATURE_POLICY members + // exclusively for the PCI Feature No-Snoop + // + // .Override = 0 to skip this PCI feature No-Snoop for the PCI device + // .Override = 1 to program this No-Snoop PCI feature + // .Act = 1 to enable the No-Snoop in the PCI device + // .Act = 0 to disable the No-Snoop in the PCI device + // + switch (NoSnoop) { + case EFI_PCI_EXPRESS_NS_AUTO: + PciDevice->SetupNS.Override = 0; + break; + case EFI_PCI_EXPRESS_NS_DISABLE: + PciDevice->SetupNS.Override = 1; + PciDevice->SetupNS.Act = 0; + break; + case EFI_PCI_EXPRESS_NS_ENABLE: + PciDevice->SetupNS.Override = 1; + PciDevice->SetupNS.Act = 1; + break; + default: + PciDevice->SetupNS.Override = 0; + break; + } +} + /** Generic routine to setup the PCI features as per its predetermined defaults. **/ @@ -211,6 +251,8 @@ SetupDefaultPciExpressDevicePolicy ( PciDevice->SetupRO.Override = 0; + PciDevice->SetupNS.Override = 0; + } /** @@ -309,6 +351,15 @@ GetPciExpressDevicePolicy ( PciDevice->SetupRO.Override = 0; } + // + // set the device specific policy for No-Snoop + // + if (mPciExpressPlatformPolicy.NoSnoop) { + SetDevicePolicyPciExpressNs (PciExpressDevicePolicy.DeviceCtlNoSnoop, PciDevice); + } else { + PciDevice->SetupNS.Override = 0; + } + DEBUG (( DEBUG_INFO, @@ -499,6 +550,17 @@ PciExpressPlatformNotifyDeviceState ( PciExDeviceConfiguration.DeviceCtlRelaxOrder = EFI_PCI_EXPRESS_NOT_APPLICABLE; } + // + // get the device-specific state for the PCIe NoSnoop feature + // + if (mPciExpressPlatformPolicy.NoSnoop) { + PciExDeviceConfiguration.DeviceCtlNoSnoop = PciDevice->PciExpressCapabilityStructure.DeviceControl.Bits.NoSnoop + ? EFI_PCI_EXPRESS_NS_ENABLE + : EFI_PCI_EXPRESS_NS_DISABLE; + } else { + PciExDeviceConfiguration.DeviceCtlNoSnoop = EFI_PCI_EXPRESS_NOT_APPLICABLE; + } + if (mPciExPlatformProtocol != NULL) { return mPciExPlatformProtocol->NotifyDeviceState ( -- 2.21.0.windows.1