From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.20492.1581332674325391852 for ; Mon, 10 Feb 2020 03:04:34 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: siyuan.fu@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Feb 2020 03:04:33 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,424,1574150400"; d="scan'208";a="227156900" Received: from shwdeopenpsi787.ccr.corp.intel.com ([10.239.158.56]) by fmsmga008.fm.intel.com with ESMTP; 10 Feb 2020 03:04:33 -0800 From: "Siyuan, Fu" To: devel@edk2.groups.io Cc: Ray Ni , Rangasai V Chaganty Subject: [Patch] IntelSiliconPkg: FIT based shadow microcode PPI support. Date: Mon, 10 Feb 2020 19:04:29 +0800 Message-Id: <20200210110429.33612-1-siyuan.fu@intel.com> X-Mailer: git-send-email 2.19.1.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This patch adds a platform PEIM for FIT based shadow microcode PPI support. A detailed design doc can be found here: https://edk2.groups.io/g/devel/files/Designs/2020/0214/Support%20 the%202nd%20Microcode%20FV%20Flash%20Region.pdf TEST: Tested on FIT enabled platform. BZ: https://tianocore.acgmultimedia.com/show_bug.cgi?id=2449 Cc: Ray Ni Cc: Rangasai V Chaganty Signed-off-by: Siyuan Fu --- .../Feature/ShadowMicrocode/ShadowMicrocodePei.c | 4 ++++ .../Feature/ShadowMicrocode/ShadowMicrocodePei.inf | 3 +++ Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 7 +++++++ 3 files changed, 14 insertions(+) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.c b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.c index 0ad3eeaa07..f160f59b87 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.c @@ -248,6 +248,10 @@ ShadowMicrocodePatchByFit ( UINTN TotalSize; UINTN TotalLoadSize; + if (!FeaturePcdGet (PcdCpuShadowMicrocodeByFit)) { + return EFI_UNSUPPORTED; + } + FitPointer = *(UINT64 *) (UINTN) FIT_POINTER_ADDRESS; if ((FitPointer == 0) || (FitPointer == 0xFFFFFFFFFFFFFFFF) || diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.inf b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.inf index 27d07ac56c..fecb7c3904 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.inf +++ b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.inf @@ -39,5 +39,8 @@ gEdkiiMicrocodeShadowInfoHobGuid gEdkiiMicrocodeStorageTypeFlashGuid +[Pcd] + gIntelSiliconPkgTokenSpaceGuid.PcdCpuShadowMicrocodeByFit + [Depex] TRUE diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec index 2d8e40f0b8..ad093928b7 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec @@ -64,6 +64,13 @@ # Include/Protocol/PlatformDeviceSecurityPolicy.h gEdkiiDeviceSecurityPolicyProtocolGuid = {0x7ea41a99, 0x5e32, 0x4c97, {0x88, 0xc4, 0xd6, 0xe7, 0x46, 0x84, 0x9, 0xd4}} +[PcdsFeatureFlag] + ## Indicates if FIT based microcode shadowing will be enabled.

+ # TRUE - FIT base microcode shadowing will be enabled.
+ # FALSE - FIT base microcode shadowing will be disabled.
+ # @Prompt FIT based microcode shadowing. + gIntelSiliconPkgTokenSpaceGuid.PcdCpuShadowMicrocodeByFit|FALSE|BOOLEAN|0x00000006 + [PcdsFixedAtBuild, PcdsPatchableInModule] ## Error code for VTd error.

# EDKII_ERROR_CODE_VTD_ERROR = (EFI_IO_BUS_UNSPECIFIED | (EFI_OEM_SPECIFIC | 0x00000000)) = 0x02008000
-- 2.19.1.windows.1