From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) by mx.groups.io with SMTP id smtpd.web10.978.1581354555601942825 for ; Mon, 10 Feb 2020 09:09:16 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=RW8VRaZ9; spf=pass (domain: nuviainc.com, ip: 209.85.128.67, mailfrom: leif@nuviainc.com) Received: by mail-wm1-f67.google.com with SMTP id a5so58104wmb.0 for ; Mon, 10 Feb 2020 09:09:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=EOW1qqpnnw6fWxY9rb18G8LF6gL7VOOATac+VID9Pgc=; b=RW8VRaZ9tnl34vuVZ3STCGSiawxd7lPH6Fax8Icfl03+x84ov1eQ/FZ+ymY9MSXeuQ Ce8ZFDIbDFFnv9DQb91MrNHeq6JOzFQ1xACgeHZWd7yhEZXTL1BNQAbOcQLp0spoVx6y pjsSPMEeCOXL2zAlNJ79XxKeukKNzTH9CFIht318FV0Cz5jtSsFUaVxw+qU6dz0+yR4B IXFQPexN52Qxe6jrAG9t9rPkMSgDEfEd/ccjTXIolwhZ4xlmb9Aj6Vhk6FJPcGYhtduY ZFWS/Y9+743y0vmdc9vDDMu7RM18SD6iyjsUy8XSdJWDPuKcnxeSxSOZO4XRDtgutL37 i0CA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=EOW1qqpnnw6fWxY9rb18G8LF6gL7VOOATac+VID9Pgc=; b=YEm2C+z7hfRjU9Sb+PkgPewVx7trIYLfG4SYa7zRZyggSXnfyEWcUHdezVyEvH2+tN QW76J4wOvOXkC+6lGz8yvyjo/GyAZ0fyBuik+KBCr1Wfyp4RLTWxlCfeOTKhOA3UVRbJ 1iKmqzONpg+s3dFPMJtFh4ahbvu8QfIA5ST4J4aFCgId4RBJEwSYaBT7/5B4vnD1uffg Y0nDOcNC8rzLTfBjgcj3Xm/qI1I/EO1/MdsBBzUhJv7Bkna8n26WarrEun6ZRlUKZIOe r+MA0Ot2aVCOepyZ6XsLuN4pkEbBTXZIoMHOPoWn+GVDR4L0UbBahC+ApoG2ZfRhj1bz eEaQ== X-Gm-Message-State: APjAAAVZmA+CmUpQktxHIPVRr/AzF10TagjOFPbgFUXJI2k2aEQEHNZ+ HgaFfZeXRPRYJxhYJiz5O0adAw== X-Google-Smtp-Source: APXvYqxibaSeWcw+EmDaBTSJj7JFphXymAR2dVEr1HyGIQVxYpjwCdAvhE/sJ3U3aWCT8W2/61Azew== X-Received: by 2002:a1c:59c6:: with SMTP id n189mr7122wmb.178.1581354553864; Mon, 10 Feb 2020 09:09:13 -0800 (PST) Return-Path: Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id 21sm8448wmo.8.2020.02.10.09.09.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Feb 2020 09:09:12 -0800 (PST) Date: Mon, 10 Feb 2020 17:09:11 +0000 From: "Leif Lindholm" To: Pankaj Bansal Cc: Meenakshi Aggarwal , Michael D Kinney , Varun Sethi , devel@edk2.groups.io Subject: Re: [EXTERNAL] [PATCH 06/19] Silicon/NXP: remove print information from Soc lib Message-ID: <20200210170911.GK23627@bivouac.eciton.net> References: <20200207124328.8723-1-pankaj.bansal@nxp.com> <20200207124328.8723-7-pankaj.bansal@nxp.com> MIME-Version: 1.0 In-Reply-To: <20200207124328.8723-7-pankaj.bansal@nxp.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Feb 07, 2020 at 18:13:15 +0530, Pankaj Bansal wrote: > The Soc info being printed can be removed from SOC lib. > We are in the process of implementing PEI Phase. > After PEI phase impelmentation this info would be printed in > common PEIM based on the information retrieved from PPIs. > e.g. gArmMpCoreInfoPpiGuid can be used to print cluser and > core info. > > Signed-off-by: Pankaj Bansal Reviewed-by: Leif Lindholm / Leif > --- > Silicon/NXP/Include/Chassis2/LsSerDes.h | 62 ---- > Silicon/NXP/LS1043A/Include/SocSerDes.h | 51 --- > Silicon/NXP/Library/SocLib/Chassis.c | 337 ------------------- > Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 8 - > Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 1 - > Silicon/NXP/Library/SocLib/SerDes.c | 268 --------------- > 6 files changed, 727 deletions(-) > delete mode 100644 Silicon/NXP/Include/Chassis2/LsSerDes.h > delete mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h > delete mode 100644 Silicon/NXP/Library/SocLib/SerDes.c > > diff --git a/Silicon/NXP/Include/Chassis2/LsSerDes.h b/Silicon/NXP/Include/Chassis2/LsSerDes.h > deleted file mode 100644 > index 9afbc52239..0000000000 > --- a/Silicon/NXP/Include/Chassis2/LsSerDes.h > +++ /dev/null > @@ -1,62 +0,0 @@ > -/** LsSerDes.h > - The Header file of SerDes Module for Chassis 2 > - > - Copyright 2017-2019 NXP > - > - SPDX-License-Identifier: BSD-2-Clause-Patent > - > -**/ > - > -#ifndef LS_SERDES_H_ > -#define LS_SERDES_H_ > - > -#include > - > -#define SRDS_MAX_LANES 4 > - > -typedef enum { > - None = 0, > - Pcie1, > - Pcie2, > - Pcie3, > - Sata, > - SgmiiFm1Dtsec1, > - SgmiiFm1Dtsec2, > - SgmiiFm1Dtsec5, > - SgmiiFm1Dtsec6, > - SgmiiFm1Dtsec9, > - SgmiiFm1Dtsec10, > - QsgmiiFm1A, > - XfiFm1Mac9, > - XfiFm1Mac10, > - Sgmii2500Fm1Dtsec2, > - Sgmii2500Fm1Dtsec5, > - Sgmii2500Fm1Dtsec9, > - Sgmii2500Fm1Dtsec10, > - SerdesPrtclCount > -} SERDES_PROTOCOL; > - > -typedef enum { > - Srds1 = 0, > - Srds2, > - SrdsMaxNum > -} SERDES_NUMBER; > - > -typedef struct { > - UINT16 Protocol; > - UINT8 SrdsLane[SRDS_MAX_LANES]; > -} SERDES_CONFIG; > - > -typedef VOID > -(*SERDES_PROBE_LANES_CALLBACK) ( > - IN SERDES_PROTOCOL LaneProtocol, > - IN VOID *Arg > - ); > - > -VOID > -SerDesProbeLanes( > - IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, > - IN VOID *Arg > - ); > - > -#endif /* LS_SERDES_H_ */ > diff --git a/Silicon/NXP/LS1043A/Include/SocSerDes.h b/Silicon/NXP/LS1043A/Include/SocSerDes.h > deleted file mode 100644 > index 2d1c6f10f9..0000000000 > --- a/Silicon/NXP/LS1043A/Include/SocSerDes.h > +++ /dev/null > @@ -1,51 +0,0 @@ > -/** @file > - The Header file of SerDes Module for LS1043A > - > - Copyright 2017-2019 NXP > - > - SPDX-License-Identifier: BSD-2-Clause-Patent > - > -**/ > - > -#ifndef SOC_SERDES_H_ > -#define SOC_SERDES_H_ > - > -#ifdef CHASSIS2 > -#include > -#endif > - > -SERDES_CONFIG SerDes1ConfigTbl[] = { > - /* SerDes 1 */ > - {0x1555, {XfiFm1Mac9, Pcie1, Pcie2, Pcie3 } }, > - {0x2555, {Sgmii2500Fm1Dtsec9, Pcie1, Pcie2, Pcie3 } }, > - {0x4555, {QsgmiiFm1A, Pcie1, Pcie2, Pcie3 } }, > - {0x4558, {QsgmiiFm1A, Pcie1, Pcie2, Sata } }, > - {0x1355, {XfiFm1Mac9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } }, > - {0x2355, {Sgmii2500Fm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } }, > - {0x3335, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, Pcie3 } }, > - {0x3355, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } }, > - {0x3358, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Sata } }, > - {0x3555, {SgmiiFm1Dtsec9, Pcie1, Pcie2, Pcie3 } }, > - {0x3558, {SgmiiFm1Dtsec9, Pcie1, Pcie2, Sata } }, > - {0x7000, {Pcie1, Pcie1, Pcie1, Pcie1 } }, > - {0x9998, {Pcie1, Pcie2, Pcie3, Sata } }, > - {0x6058, {Pcie1, Pcie1, Pcie2, Sata } }, > - {0x1455, {XfiFm1Mac9, QsgmiiFm1A, Pcie2, Pcie3 } }, > - {0x2455, {Sgmii2500Fm1Dtsec9, QsgmiiFm1A, Pcie2, Pcie3 } }, > - {0x2255, {Sgmii2500Fm1Dtsec9, Sgmii2500Fm1Dtsec2, Pcie2, Pcie3 } }, > - {0x3333, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 } }, > - {0x1460, {XfiFm1Mac9, QsgmiiFm1A, Pcie3, Pcie3 } }, > - {0x2460, {Sgmii2500Fm1Dtsec9, QsgmiiFm1A, Pcie3, Pcie3 } }, > - {0x3460, {SgmiiFm1Dtsec9, QsgmiiFm1A, Pcie3, Pcie3 } }, > - {0x3455, {SgmiiFm1Dtsec9, QsgmiiFm1A, Pcie2, Pcie3 } }, > - {0x9960, {Pcie1, Pcie2, Pcie3, Pcie3 } }, > - {0x2233, {Sgmii2500Fm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 }}, > - {0x2533, {Sgmii2500Fm1Dtsec9, Pcie1, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 } }, > - {} > -}; > - > -SERDES_CONFIG *SerDesConfigTbl[] = { > - SerDes1ConfigTbl > -}; > - > -#endif /* SOC_SERDES_H_ */ > diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c > index b8a8118c5e..18a1f5e4e1 100644 > --- a/Silicon/NXP/Library/SocLib/Chassis.c > +++ b/Silicon/NXP/Library/SocLib/Chassis.c > @@ -25,16 +25,6 @@ > #include > #include "NxpChassis.h" > > -/* > - * Structure to list available SOCs. > - * Name, Soc Version, Number of Cores > - */ > -STATIC CPU_TYPE mCpuTypeList[] = { > - CPU_TYPE_ENTRY (LS1043A, LS1043A, 4), > - CPU_TYPE_ENTRY (LS1046A, LS1046A, 4), > - CPU_TYPE_ENTRY (LS2088A, LS2088A, 8), > -}; > - > UINT32 > EFIAPI > GurRead ( > @@ -48,235 +38,6 @@ GurRead ( > } > } > > -/* > - * Return the type of initiator (core or hardware accelerator) > - */ > -UINT32 > -InitiatorType ( > - IN UINT32 Cluster, > - IN UINTN InitId > - ) > -{ > - CCSR_GUR *GurBase; > - UINT32 Idx; > - UINT32 Type; > - > - GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr); > - Idx = (Cluster >> (InitId * 8)) & TP_CLUSTER_INIT_MASK; > - Type = GurRead ((UINTN)&GurBase->TpItyp[Idx]); > - > - if (Type & TP_ITYP_AV_MASK) { > - return Type; > - } > - > - return 0; > -} > - > -/* > - * Return the mask for number of cores on this SOC. > - */ > -UINT32 > -CpuMask ( > - VOID > - ) > -{ > - CCSR_GUR *GurBase; > - UINTN ClusterIndex; > - UINTN Count; > - UINT32 Cluster; > - UINT32 Type; > - UINT32 Mask; > - UINTN InitiatorIndex; > - > - GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr); > - ClusterIndex = 0; > - Count = 0; > - Mask = 0; > - > - do { > - Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower); > - for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) { > - Type = InitiatorType (Cluster, InitiatorIndex); > - if (Type) { > - if (TP_ITYP_TYPE_MASK (Type) == TP_ITYP_TYPE_ARM) { > - Mask |= 1 << Count; > - } > - Count++; > - } > - } > - ClusterIndex++; > - } while (CHECK_CLUSTER (Cluster)); > - > - return Mask; > -} > - > -/* > - * Return the number of cores on this SOC. > - */ > -UINTN > -CpuNumCores ( > - VOID > - ) > -{ > - UINTN Count; > - UINTN Num; > - > - Count = 0; > - Num = CpuMask (); > - > - while (Num) { > - Count += Num & 1; > - Num >>= 1; > - } > - > - return Count; > -} > - > -/* > - * Return core's cluster > - */ > -INT32 > -QoriqCoreToCluster ( > - IN UINTN Core > - ) > -{ > - CCSR_GUR *GurBase; > - UINTN ClusterIndex; > - UINTN Count; > - UINT32 Cluster; > - UINT32 Type; > - UINTN InitiatorIndex; > - > - GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr); > - ClusterIndex = 0; > - Count = 0; > - do { > - Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower); > - for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) { > - Type = InitiatorType (Cluster, InitiatorIndex); > - if (Type) { > - if (Count == Core) { > - return ClusterIndex; > - } > - Count++; > - } > - } > - ClusterIndex++; > - } while (CHECK_CLUSTER (Cluster)); > - > - return -1; // cannot identify the cluster > -} > - > -/* > - * Return the type of core i.e. A53, A57 etc of inputted > - * core number. > - */ > -UINTN > -QoriqCoreToType ( > - IN UINTN Core > - ) > -{ > - CCSR_GUR *GurBase; > - UINTN ClusterIndex; > - UINTN Count; > - UINT32 Cluster; > - UINT32 Type; > - UINTN InitiatorIndex; > - > - GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr); > - ClusterIndex = 0; > - Count = 0; > - > - do { > - Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower); > - for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) { > - Type = InitiatorType (Cluster, InitiatorIndex); > - if (Type) { > - if (Count == Core) { > - return Type; > - } > - Count++; > - } > - } > - ClusterIndex++; > - } while (CHECK_CLUSTER (Cluster)); > - > - return EFI_NOT_FOUND; /* cannot identify the cluster */ > -} > - > -STATIC > -UINTN > -CpuMaskNext ( > - IN UINTN Cpu, > - IN UINTN Mask > - ) > -{ > - for (Cpu++; !((1 << Cpu) & Mask); Cpu++); > - > - return Cpu; > -} > - > -/* > - * Print CPU information > - */ > -VOID > -PrintCpuInfo ( > - VOID > - ) > -{ > - SYS_INFO SysInfo; > - UINTN CoreIndex; > - UINTN Core; > - UINT32 Type; > - UINT32 NumCpus; > - UINT32 Mask; > - CHAR8 *CoreName; > - > - GetSysInfo (&SysInfo); > - DEBUG ((DEBUG_INIT, "Clock Configuration:")); > - > - NumCpus = CpuNumCores (); > - Mask = CpuMask (); > - > - for (CoreIndex = 0, Core = CpuMaskNext(-1, Mask); > - CoreIndex < NumCpus; > - CoreIndex++, Core = CpuMaskNext(Core, Mask)) > - { > - if (!(CoreIndex % 3)) { > - DEBUG ((DEBUG_INIT, "\n ")); > - } > - > - Type = TP_ITYP_VERSION (QoriqCoreToType (Core)); > - switch (Type) { > - case TY_ITYP_VERSION_A7: > - CoreName = "A7"; > - break; > - case TY_ITYP_VERSION_A53: > - CoreName = "A53"; > - break; > - case TY_ITYP_VERSION_A57: > - CoreName = "A57"; > - break; > - case TY_ITYP_VERSION_A72: > - CoreName = "A72"; > - break; > - default: > - CoreName = " Unknown Core "; > - } > - DEBUG ((DEBUG_INIT, "CPU%d(%a):%-4d MHz ", > - Core, CoreName, SysInfo.FreqProcessor[Core] / MHZ)); > - } > - > - DEBUG ((DEBUG_INIT, "\n Bus: %-4d MHz ", SysInfo.FreqSystemBus / MHZ)); > - DEBUG ((DEBUG_INIT, "DDR: %-4d MT/s", SysInfo.FreqDdrBus / MHZ)); > - > - if (SysInfo.FreqFman[0] != 0) { > - DEBUG ((DEBUG_INIT, "\n FMAN: %-4d MHz ", SysInfo.FreqFman[0] / MHZ)); > - } > - > - DEBUG ((DEBUG_INIT, "\n")); > -} > - > /* > * Return system bus frequency > */ > @@ -307,77 +68,6 @@ GetSdxcFrequency ( > return SocSysInfo.FreqSdhc; > } > > -/* > - * Print Soc information > - */ > -VOID > -PrintSoc ( > - VOID > - ) > -{ > - CHAR8 Buf[20]; > - CCSR_GUR *GurBase; > - UINTN Count; > - // > - // Svr : System Version Register > - // > - UINTN Svr; > - UINTN Ver; > - > - GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr); > - > - Svr = GurRead ((UINTN)&GurBase->Svr); > - Ver = SVR_SOC_VER (Svr); > - > - for (Count = 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) { > - if ((mCpuTypeList[Count].SocVer & SVR_WO_E) == Ver) { > - AsciiStrCpyS (Buf, sizeof (Buf), mCpuTypeList[Count].Name); > - > - if (IS_E_PROCESSOR (Svr)) { > - AsciiStrCatS (Buf, sizeof (Buf), "E"); > - } > - break; > - } > - } > - > - DEBUG ((DEBUG_INFO, "SoC: %a (0x%x); Rev %d.%d\n", > - Buf, Svr, SVR_MAJOR (Svr), SVR_MINOR (Svr))); > - > - return; > -} > - > -/* > - * Dump RCW (Reset Control Word) on console > - */ > -VOID > -PrintRCW ( > - VOID > - ) > -{ > - CCSR_GUR *Base; > - UINTN Count; > - > - Base = (VOID *)PcdGet64 (PcdGutsBaseAddr); > - > - /* > - * Display the RCW, so that no one gets confused as to what RCW > - * we're actually using for this boot. > - */ > - > - DEBUG ((DEBUG_INIT, "Reset Configuration Word (RCW):")); > - for (Count = 0; Count < ARRAY_SIZE (Base->RcwSr); Count++) { > - UINT32 Rcw = SwapMmioRead32 ((UINTN)&Base->RcwSr[Count]); > - > - if ((Count % 4) == 0) { > - DEBUG ((DEBUG_INIT, "\n %08x:", Count * 4)); > - } > - > - DEBUG ((DEBUG_INIT, " %08x", Rcw)); > - } > - > - DEBUG ((DEBUG_INIT, "\n")); > -} > - > /* > * Setup SMMU in bypass mode > * and also set its pagesize > @@ -400,33 +90,6 @@ SmmuInit ( > MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value); > } > > -/* > - * Return current Soc Name form mCpuTypeList > - */ > -CHAR8 * > -GetSocName ( > - VOID > - ) > -{ > - UINT8 Count; > - UINTN Svr; > - UINTN Ver; > - CCSR_GUR *GurBase; > - > - GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr); > - > - Svr = GurRead ((UINTN)&GurBase->Svr); > - Ver = SVR_SOC_VER (Svr); > - > - for (Count = 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) { > - if ((mCpuTypeList[Count].SocVer & SVR_WO_E) == Ver) { > - return (CHAR8 *)mCpuTypeList[Count].Name; > - } > - } > - > - return NULL; > -} > - > UINTN > GetDramSize ( > IN VOID > diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c > index 5a1a7376cd..3d803716c9 100644 > --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c > +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c > @@ -171,13 +171,5 @@ SocInit ( > DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a on %a)\n", > (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__)); > > - PrintCpuInfo (); > - > - // > - // Print Reset control Word > - // > - PrintRCW (); > - PrintSoc (); > - > return; > } > diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf > index 3334d4d4f1..fe77717337 100644 > --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf > +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf > @@ -30,7 +30,6 @@ > [Sources.common] > Chassis.c > Chassis2/Soc.c > - SerDes.c > > [BuildOptions] > GCC:*_*_*_CC_FLAGS = -DCHASSIS2 > diff --git a/Silicon/NXP/Library/SocLib/SerDes.c b/Silicon/NXP/Library/SocLib/SerDes.c > deleted file mode 100644 > index b9909d9221..0000000000 > --- a/Silicon/NXP/Library/SocLib/SerDes.c > +++ /dev/null > @@ -1,268 +0,0 @@ > -/** SerDes.c > - Provides the basic interfaces for SerDes Module > - > - Copyright 2017-2019 NXP > - > - SPDX-License-Identifier: BSD-2-Clause-Patent > - > -**/ > - > -#ifdef CHASSIS2 > -#include > -#include > -#elif CHASSIS3 > -#include > -#include > -#endif > -#include > -#include > -#include > - > -/** > - Function to get serdes Lane protocol corresponding to > - serdes protocol. > - > - @param SerDes Serdes number. > - @param Cfg Serdes Protocol. > - @param Lane Serdes Lane number. > - > - @return Serdes Lane protocol. > - > -**/ > -STATIC > -SERDES_PROTOCOL > -GetSerDesPrtcl ( > - IN INTN SerDes, > - IN INTN Cfg, > - IN INTN Lane > - ) > -{ > - SERDES_CONFIG *Config; > - > - if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) { > - return 0; > - } > - > - Config = SerDesConfigTbl[SerDes]; > - while (Config->Protocol) { > - if (Config->Protocol == Cfg) { > - return Config->SrdsLane[Lane]; > - } > - Config++; > - } > - > - return EFI_SUCCESS; > -} > - > -/** > - Function to check if inputted protocol is a valid serdes protocol. > - > - @param SerDes Serdes number. > - @param Prtcl Serdes Protocol to be verified. > - > - @return EFI_INVALID_PARAMETER Input parameter in invalid. > - @return EFI_NOT_FOUND Serdes Protocol not a valid protocol. > - @return EFI_SUCCESS Serdes Protocol is a valid protocol. > - > -**/ > -STATIC > -EFI_STATUS > -CheckSerDesPrtclValid ( > - IN INTN SerDes, > - IN UINT32 Prtcl > - ) > -{ > - SERDES_CONFIG *Config; > - INTN Cnt; > - > - if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) { > - return EFI_INVALID_PARAMETER; > - } > - > - Config = SerDesConfigTbl[SerDes]; > - while (Config->Protocol) { > - if (Config->Protocol == Prtcl) { > - DEBUG ((DEBUG_INFO, "Protocol: %x Matched with the one in Table\n", Prtcl)); > - break; > - } > - Config++; > - } > - > - if (!Config->Protocol) { > - return EFI_NOT_FOUND; > - } > - > - for (Cnt = 0; Cnt < SRDS_MAX_LANES; Cnt++) { > - if (Config->SrdsLane[Cnt] != None) { > - return EFI_SUCCESS; > - } > - } > - > - return EFI_NOT_FOUND; > -} > - > -/** > - Function to fill serdes map information. > - > - @param Srds Serdes number. > - @param SerdesProtocolMask Serdes Protocol Mask. > - @param SerdesProtocolShift Serdes Protocol shift value. > - @param SerDesPrtclMap Pointer to Serdes Protocol map. > - > -**/ > -STATIC > -VOID > -LSSerDesMap ( > - IN UINT32 Srds, > - IN UINT32 SerdesProtocolMask, > - IN UINT32 SerdesProtocolShift, > - OUT UINT64 *SerDesPrtclMap > - ) > -{ > - CCSR_GUR *Gur; > - UINT32 SrdsProt; > - INTN Lane; > - UINT32 Flag; > - > - Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr); > - *SerDesPrtclMap = 0x0; > - Flag = 0; > - > - SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask; > - SrdsProt >>= SerdesProtocolShift; > - > - DEBUG ((DEBUG_INFO, "Using SERDES%d Protocol: %d (0x%x)\n", > - Srds + 1, SrdsProt, SrdsProt)); > - > - if (EFI_SUCCESS != CheckSerDesPrtclValid (Srds, SrdsProt)) { > - DEBUG ((DEBUG_ERROR, "SERDES%d[PRTCL] = 0x%x is not valid\n", > - Srds + 1, SrdsProt)); > - Flag++; > - } > - > - for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) { > - SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane); > - if (LanePrtcl >= SerdesPrtclCount) { > - DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl)); > - Flag++; > - } else { > - *SerDesPrtclMap |= (1u << LanePrtcl); > - } > - } > - > - if (Flag) { > - DEBUG ((DEBUG_ERROR, "Could not configure SerDes module!!\n")); > - } else { > - DEBUG ((DEBUG_INFO, "Successfully configured SerDes module!!\n")); > - } > -} > - > -/** > - Get lane protocol on provided serdes lane and execute callback function. > - > - @param Srds Serdes number. > - @param SerdesProtocolMask Mask to get Serdes Protocol for Srds > - @param SerdesProtocolShift Shift value to get Serdes Protocol for Srds. > - @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol > - @param Arg Pointer to Arguments to be passed to callback function. > - > -**/ > -STATIC > -VOID > -SerDesInstanceProbeLanes ( > - IN UINT32 Srds, > - IN UINT32 SerdesProtocolMask, > - IN UINT32 SerdesProtocolShift, > - IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, > - IN VOID *Arg > - ) > -{ > - > - CCSR_GUR *Gur; > - UINT32 SrdsProt; > - INTN Lane; > - > - Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);; > - > - SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask; > - SrdsProt >>= SerdesProtocolShift; > - > - /* > - * Invoke callback for all lanes in the SerDes instance: > - */ > - for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) { > - SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane); > - if ((LanePrtcl >= SerdesPrtclCount) || (LanePrtcl < None)) { > - DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl)); > - } else if (LanePrtcl != None) { > - SerDesLaneProbeCallback (LanePrtcl, Arg); > - } > - } > -} > - > -/** > - Probe all serdes lanes for lane protocol and execute provided callback function. > - > - @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol > - @param Arg Pointer to Arguments to be passed to callback function. > - > -**/ > -VOID > -SerDesProbeLanes ( > - IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, > - IN VOID *Arg > - ) > -{ > - SerDesInstanceProbeLanes (Srds1, > - RCWSR_SRDS1_PRTCL_MASK, > - RCWSR_SRDS1_PRTCL_SHIFT, > - SerDesLaneProbeCallback, > - Arg); > - > - if (PcdGetBool (PcdSerdes2Enabled)) { > - SerDesInstanceProbeLanes (Srds2, > - RCWSR_SRDS2_PRTCL_MASK, > - RCWSR_SRDS2_PRTCL_SHIFT, > - SerDesLaneProbeCallback, > - Arg); > - } > -} > - > -/** > - Function to return Serdes protocol map for all serdes available on board. > - > - @param SerDesPrtclMap Pointer to Serdes protocl map. > - > -**/ > -VOID > -GetSerdesProtocolMaps ( > - OUT UINT64 *SerDesPrtclMap > - ) > -{ > - LSSerDesMap (Srds1, > - RCWSR_SRDS1_PRTCL_MASK, > - RCWSR_SRDS1_PRTCL_SHIFT, > - SerDesPrtclMap); > - > - if (PcdGetBool (PcdSerdes2Enabled)) { > - LSSerDesMap (Srds2, > - RCWSR_SRDS2_PRTCL_MASK, > - RCWSR_SRDS2_PRTCL_SHIFT, > - SerDesPrtclMap); > - } > - > -} > - > -BOOLEAN > -IsSerDesLaneProtocolConfigured ( > - IN UINT64 SerDesPrtclMap, > - IN SERDES_PROTOCOL Device > - ) > -{ > - if ((Device >= SerdesPrtclCount) || (Device < None)) { > - ASSERT ((Device > None) && (Device < SerdesPrtclCount)); > - DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol Device %d\n", Device)); > - } > - > - return (SerDesPrtclMap & (1u << Device)) != 0 ; > -} > -- > 2.17.1 >