From: "Leif Lindholm" <leif@nuviainc.com>
To: Pankaj Bansal <pankaj.bansal@nxp.com>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>,
Michael D Kinney <michael.d.kinney@intel.com>,
Varun Sethi <V.Sethi@nxp.com>,
devel@edk2.groups.io
Subject: Re: [PATCH 14/19] Silicon/NXP/LS1043A: Replce SocLib
Date: Tue, 11 Feb 2020 13:35:18 +0000 [thread overview]
Message-ID: <20200211133518.GX23627@bivouac.eciton.net> (raw)
In-Reply-To: <20200207124328.8723-15-pankaj.bansal@nxp.com>
On Fri, Feb 07, 2020 at 18:13:23 +0530, Pankaj Bansal wrote:
> Replace SocLib with new SocLib in which code structure has been
> changed.
I don't think there's much point to me reviewing this one until we've
discussed the ChassisLib/SocLib split and layout in more detail.
/
Leif
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> .../Drivers/PlatformDxe/PlatformDxe.inf | 3 +-
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 3 +-
> .../Library/ArmPlatformLib/ArmPlatformLib.c | 53 ++++++-
> .../Library/ArmPlatformLib/ArmPlatformLib.inf | 6 +-
> Silicon/NXP/Chassis2/Include/Chassis.h | 12 ++
> Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc | 1 +
> .../Chassis2/LS1043A/Library/SocLib/SocLib.c | 28 ++++
> .../LS1043A/Library/SocLib/SocLib.inf | 8 ++
> .../Chassis2/Library/ChassisLib/ChassisLib.c | 25 ++++
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 2 +-
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 7 +-
> Silicon/NXP/Include/Chassis2/NxpSoc.h | 53 -------
> Silicon/NXP/Include/Library/ChassisLib.h | 2 -
> Silicon/NXP/Include/Library/SocLib.h | 1 -
> Silicon/NXP/LS1043A/Include/Soc.h | 44 ------
> Silicon/NXP/LS1043A/LS1043A.dec | 16 ---
> Silicon/NXP/LS1043A/LS1043A.dsc.inc | 33 -----
> .../BaseSerialPortLib16550.c | 11 +-
> .../BaseSerialPortLib16550.inf | 3 +-
> Silicon/NXP/Library/SocLib/Chassis.c | 76 ----------
> Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 96 -------------
> Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 44 ------
> Silicon/NXP/Library/SocLib/NxpChassis.h | 136 ------------------
> 23 files changed, 142 insertions(+), 521 deletions(-)
> delete mode 100644 Silicon/NXP/Include/Chassis2/NxpSoc.h
> delete mode 100644 Silicon/NXP/LS1043A/Include/Soc.h
> delete mode 100644 Silicon/NXP/LS1043A/LS1043A.dec
> delete mode 100644 Silicon/NXP/LS1043A/LS1043A.dsc.inc
> delete mode 100644 Silicon/NXP/Library/SocLib/Chassis.c
> delete mode 100644 Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> delete mode 100644 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> delete mode 100644 Silicon/NXP/Library/SocLib/NxpChassis.h
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> index 126a1174fa..95f60b00f0 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> +++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> @@ -25,7 +25,8 @@
> MdeModulePkg/MdeModulePkg.dec
> Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
> Silicon/NXP/NxpQoriqLs.dec
> - Silicon/NXP/LS1043A/LS1043A.dec
> + Silicon/NXP/Chassis2/Chassis2.dec
> + Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
>
> [LibraryClasses]
> BaseLib
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> index bc6fa4f19d..4bc7f6ef97 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> @@ -23,7 +23,8 @@
> FLASH_DEFINITION = Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
>
> !include Silicon/NXP/NxpQoriqLs.dsc.inc
> -!include Silicon/NXP/LS1043A/LS1043A.dsc.inc
> +!include Silicon/NXP/Chassis2/Chassis2.dsc.inc
> +!include Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
>
> [LibraryClasses.common]
> ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> index 718c71bf02..821d413a3e 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.c
> @@ -14,7 +14,10 @@
> #include <Library/ArmPlatformLib.h>
> #include <Ppi/ArmMpCoreInfo.h>
>
> -extern VOID SocInit (VOID);
> +#include <Library/DebugLib.h>
> +#include <Library/I2cLib.h>
> +#include <Library/SocLib.h>
> +#include <Ppi/NxpPlatformGetClock.h>
>
> /**
> Return the current Boot Mode
> @@ -30,6 +33,49 @@ ArmPlatformGetBootMode (
> return BOOT_WITH_FULL_CONFIGURATION;
> }
>
> +/**
> + Get the clocks supplied by Platform(Board) to NXP Layerscape SOC
> +
> + The core can be of type ARM or PowerPC or Hardware Accelerator.
> + If the core is enabled and of type ARM EFI_SUCCESS is returned and a code for type of ARM core is returned
> +
> + @param[in] ClockType Type of clock
> + @param[in] ... Variable argument list which is parsed based on ClockType
> +
> + @return Actual Clock Frequency. return value 0 should be interpreted as clock not provided by Board.
> +**/
> +UINT64
> +EFIAPI
> +NxpPlatformGetClock(
> + IN UINT32 ClockType,
> + ...
> + )
> +{
> + UINT64 Clock;
> + VA_LIST Args;
> +
> + Clock = 0;
> +
> + VA_START (Args, ClockType);
> +
> + switch (ClockType) {
> + case NXP_SYSTEM_CLOCK:
> + Clock = 100 * 1000 * 1000; // 100 MHz
> + break;
> + case NXP_I2C_CLOCK:
> + case NXP_UART_CLOCK:
> + Clock = NxpPlatformGetClock (NXP_SYSTEM_CLOCK);
> + Clock = SocGetClock (Clock, ClockType, Args);
> + break;
> + default:
> + break;
> + }
> +
> + VA_END (Args);
> +
> + return Clock;
> +}
> +
> /**
> Placeholder for Platform Initialization
> **/
> @@ -38,9 +84,9 @@ ArmPlatformInitialize (
> IN UINTN MpId
> )
> {
> - SocInit ();
> + SocInit ();
>
> - return EFI_SUCCESS;
> + return EFI_SUCCESS;
> }
>
> ARM_CORE_INFO LS1043aMpCoreInfoCTA53x4[] = {
> @@ -69,6 +115,7 @@ PrePeiCoreGetMpCoreInfo (
> }
>
> ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
> +NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi = { NxpPlatformGetClock };
>
> EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
> {
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> index 6396d2982b..8b79fd7490 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/ArmPlatformLib/ArmPlatformLib.inf
> @@ -20,11 +20,14 @@
> EmbeddedPkg/EmbeddedPkg.dec
> MdePkg/MdePkg.dec
> Silicon/NXP/NxpQoriqLs.dec
> - Silicon/NXP/LS1043A/LS1043A.dec
> + Silicon/NXP/Chassis2/Chassis2.dec
> + Silicon/NXP/Chassis2/LS1043A/LS1043A.dec
>
> [LibraryClasses]
> ArmLib
> SocLib
> + I2cLib
> + DebugLib
>
> [Sources.common]
> AArch64/NxpQoriqLsHelper.S | GCC
> @@ -36,3 +39,4 @@
>
> [FixedPcd]
> gArmTokenSpaceGuid.PcdArmPrimaryCore
> + gArmPlatformTokenSpaceGuid.PcdCoreCount
> diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h b/Silicon/NXP/Chassis2/Include/Chassis.h
> index 48ba2e7bfb..8f26faf297 100644
> --- a/Silicon/NXP/Chassis2/Include/Chassis.h
> +++ b/Silicon/NXP/Chassis2/Include/Chassis.h
> @@ -20,6 +20,18 @@
> #define TP_ITYPE_VERSION_A53 0x2
> #define TP_ITYPE_VERSION_A72 0x4
>
> +/* SMMU Defintions */
> +#define SMMU_BASE_ADDR 0x09000000
> +#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
> +#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
> +#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
> +#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
> +#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
> +
> +#define SCR0_USFCFG_MASK 0x00000400
> +#define SCR0_CLIENTPD_MASK 0x00000001
> +#define SACR_PAGESIZE_MASK 0x00010000
> +
> /**
> The Device Configuration Unit provides general purpose configuration and status for the
> device. These registers only support 32-bit accesses.
> diff --git a/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
> index 4511203443..8440e5f0f3 100644
> --- a/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
> +++ b/Silicon/NXP/Chassis2/LS1043A/LS1043A.dsc.inc
> @@ -8,6 +8,7 @@
>
> [LibraryClasses.common]
> SocLib|Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> + SerialPortLib|Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
>
> ################################################################################
> #
> diff --git a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
> index 2a08ad87db..24241e9b02 100644
> --- a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
> +++ b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.c
> @@ -4,8 +4,10 @@
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
> **/
> +#include <Soc.h>
> #include <Library/ChassisLib.h>
> #include <Library/SocLib.h>
> +#include <Library/SerialPortLib.h>
>
> /**
> Return the input clock frequency to an IP Module.
> @@ -66,8 +68,34 @@ SocInit (
> VOID
> )
> {
> + UINT64 BaudRate;
> + UINT32 ReceiveFifoDepth;
> + EFI_PARITY_TYPE Parity;
> + UINT8 DataBits;
> + EFI_STOP_BITS_TYPE StopBits;
> + UINT32 Timeout;
> +
> + BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
> + ReceiveFifoDepth = FixedPcdGet16 (PcdUartDefaultReceiveFifoDepth); // Use default FIFO depth
> + Timeout = 0;
> + Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
> + DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
> + StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);
> +
> ChassisInit ();
>
> + //
> + // Early init serial Port to get board information.
> + //
> + SerialPortSetAttributes (
> + &BaudRate,
> + &ReceiveFifoDepth,
> + &Timeout,
> + &Parity,
> + &DataBits,
> + &StopBits
> + );
> +
> return;
> }
>
> diff --git a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> index c9a4fbc01f..fb39424bc5 100644
> --- a/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> +++ b/Silicon/NXP/Chassis2/LS1043A/Library/SocLib/SocLib.inf
> @@ -29,4 +29,12 @@
>
> [LibraryClasses]
> ChassisLib
> + PcdLib
> + SerialPortLib
>
> +[FixedPcd]
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth
> diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> index fa6a36e96f..e7573a0e06 100644
> --- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c
> @@ -150,6 +150,29 @@ SocGetMpCoreInfo (
> return CoreCount;
> }
>
> +/*
> + * Setup SMMU in bypass mode
> + * and also set its pagesize
> + */
> +STATIC
> +VOID
> +SmmuInit (
> + VOID
> + )
> +{
> + UINT32 Value;
> +
> + /* set pagesize as 64K and ssmu-500 in bypass mode */
> + Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
> + MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
> +
> + Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
> + MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
> +
> + Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
> + MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
> +}
> +
> /**
> Function to initialize Chassis Specific functions
> **/
> @@ -183,4 +206,6 @@ ChassisInit (
> &DataBits,
> &StopBits
> );
> +
> + SmmuInit();
> }
> diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> index 8e3a82efca..e79b106c8d 100644
> --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> @@ -50,7 +50,7 @@ SetBusFrequency (
>
> I2cBase = (UINTN)(I2c->Dev->Resources[0].AddrRangeMin);
>
> - I2cClock = GetBusFrequency ();
> + I2cClock = mPlatformGetClockPpi.PlatformGetClock (NXP_I2C_CLOCK, 0);
>
> I2cInitialize (I2cBase, I2cClock, *BusClockHertz);
>
> diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> index 88316f3133..f446f0d4f9 100644
> --- a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> @@ -13,6 +13,7 @@
> #include <Library/UefiLib.h>
> #include <Uefi.h>
>
> +#include <Ppi/NxpPlatformGetClock.h>
> #include <Protocol/I2cMaster.h>
> #include <Protocol/NonDiscoverableDevice.h>
>
> @@ -37,11 +38,7 @@ typedef struct {
> NON_DISCOVERABLE_DEVICE *Dev;
> } NXP_I2C_MASTER;
>
> -extern
> -UINT64
> -GetBusFrequency (
> - VOID
> - );
> +extern NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi;
>
> EFI_STATUS
> NxpI2cInit (
> diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> deleted file mode 100644
> index 6812beafe4..0000000000
> --- a/Silicon/NXP/Include/Chassis2/NxpSoc.h
> +++ /dev/null
> @@ -1,53 +0,0 @@
> -/** Soc.h
> -* Header defining the Base addresses, sizes, flags etc for chassis 1
> -*
> -* Copyright 2017-2020 NXP
> -*
> -* SPDX-License-Identifier: BSD-2-Clause-Patent
> -*
> -**/
> -
> -#ifndef NXP_SOC_H_
> -#define NXP_SOC_H_
> -
> -#define CLK_FREQ 100000000
> -
> -#define CHASSIS2_DCFG_ADDRESS 0x1EE0000
> -
> -/* SMMU Defintions */
> -#define SMMU_BASE_ADDR 0x09000000
> -#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
> -#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
> -#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
> -#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
> -#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
> -
> -#define SCR0_USFCFG_MASK 0x00000400
> -#define SCR0_CLIENTPD_MASK 0x00000001
> -#define SACR_PAGESIZE_MASK 0x00010000
> -#define IDR1_PAGESIZE_MASK 0x80000000
> -
> -typedef struct {
> - UINTN FreqSystemBus;
> -} SYS_INFO;
> -
> -/* Device Configuration and Pin Control */
> -typedef struct {
> - UINT8 Res0[0x100-0x00];
> - UINT32 RcwSr[16]; /* Reset control word status */
> -#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
> -#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
> -} CCSR_GUR;
> -
> -VOID
> -GetSysInfo (
> - OUT SYS_INFO *
> - );
> -
> -UINT32
> -EFIAPI
> -GurRead (
> - IN UINTN Address
> - );
> -
> -#endif /* NXP_SOC_H_ */
> diff --git a/Silicon/NXP/Include/Library/ChassisLib.h b/Silicon/NXP/Include/Library/ChassisLib.h
> index b51b024374..d07c59b82d 100644
> --- a/Silicon/NXP/Include/Library/ChassisLib.h
> +++ b/Silicon/NXP/Include/Library/ChassisLib.h
> @@ -9,8 +9,6 @@
> #ifndef __CHASSIS_LIB_H__
> #define __CHASSIS_LIB_H__
>
> -#include <Chassis.h>
> -
> /**
> Read Dcfg register
> **/
> diff --git a/Silicon/NXP/Include/Library/SocLib.h b/Silicon/NXP/Include/Library/SocLib.h
> index 3def396171..700e877bdf 100644
> --- a/Silicon/NXP/Include/Library/SocLib.h
> +++ b/Silicon/NXP/Include/Library/SocLib.h
> @@ -8,7 +8,6 @@
> #ifndef __SOC_LIB_H__
> #define __SOC_LIB_H__
>
> -#include <Soc.h>
> #include <Uefi.h>
> #include <Ppi/ArmMpCoreInfo.h>
> #include <Ppi/NxpPlatformGetClock.h>
> diff --git a/Silicon/NXP/LS1043A/Include/Soc.h b/Silicon/NXP/LS1043A/Include/Soc.h
> deleted file mode 100644
> index c1e00394af..0000000000
> --- a/Silicon/NXP/LS1043A/Include/Soc.h
> +++ /dev/null
> @@ -1,44 +0,0 @@
> -/** @file
> -
> - Copyright 2020 NXP
> -
> - SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -#ifndef __SOC_H__
> -#define __SOC_H__
> -
> -/**
> - Soc Memory Map
> -**/
> -#define LS1043A_DRAM0_PHYS_ADDRESS 0x80000000
> -#define LS1043A_DRAM0_SIZE SIZE_2GB
> -#define LS1043A_DRAM1_PHYS_ADDRESS 0x880000000
> -#define LS1043A_DRAM1_SIZE 0x780000000 // 30 GB
> -
> -#define LS1043A_CCSR_PHYS_ADDRESS 0x1000000
> -#define LS1043A_CCSR_SIZE 0xF000000
> -
> -#define LS1043A_IFC0_PHYS_ADDRESS 0x60000000
> -#define LS1043A_IFC0_SIZE SIZE_512MB
> -#define LS1043A_IFC1_PHYS_ADDRESS 0x620000000
> -#define LS1043A_IFC1_SIZE 0xE0000000 // 3.5 GB
> -
> -#define LS1043A_QSPI_PHYS_ADDRESS 0x40000000
> -#define LS1043A_QSPI_SIZE SIZE_512MB
> -
> -#define LS1043A_QMAN_SW_PORTAL_PHYS_ADDRESS 0x500000000
> -#define LS1043A_QMAN_SW_PORTAL_SIZE SIZE_128MB
> -#define LS1043A_BMAN_SW_PORTAL_PHYS_ADDRESS 0x508000000
> -#define LS1043A_BMAN_SW_PORTAL_SIZE SIZE_128MB
> -
> -#define LS1043A_PCI0_PHYS_ADDRESS 0x4000000000
> -#define LS1043A_PCI1_PHYS_ADDRESS 0x4800000000
> -#define LS1043A_PCI2_PHYS_ADDRESS 0x5000000000
> -#define LS1043A_PCI_SIZE SIZE_32GB
> -
> -#define LS1043A_I2C0_PHYS_ADDRESS 0x2180000
> -#define LS1043A_I2C_SIZE 0x10000
> -#define LS1043A_I2C_NUM_CONTROLLERS 4
> -
> -#endif
> diff --git a/Silicon/NXP/LS1043A/LS1043A.dec b/Silicon/NXP/LS1043A/LS1043A.dec
> deleted file mode 100644
> index cd79949790..0000000000
> --- a/Silicon/NXP/LS1043A/LS1043A.dec
> +++ /dev/null
> @@ -1,16 +0,0 @@
> -# LS1043A.dec
> -#
> -# Copyright 2017-2019 NXP
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -#
> -
> -[Defines]
> - DEC_SPECIFICATION = 0x0001001A
> -
> -[Guids.common]
> - gNxpLs1043ATokenSpaceGuid = {0x6834fe45, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
> -
> -[Includes]
> - Include
> diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> deleted file mode 100644
> index 7ebbb1a495..0000000000
> --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> +++ /dev/null
> @@ -1,33 +0,0 @@
> -# LS1043A.dsc
> -# LS1043A Soc package.
> -#
> -# Copyright 2017-2020 NXP
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -#
> -
> -[LibraryClasses.common]
> - SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> - SerialPortLib|Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
> -
> -################################################################################
> -#
> -# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> -#
> -################################################################################
> -[PcdsDynamicDefault.common]
> -
> - #
> - # ARM General Interrupt Controller
> - gArmTokenSpaceGuid.PcdGicDistributorBase|0x01401000
> - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01402000
> -
> -[PcdsFixedAtBuild.common]
> - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
> -
> - #
> - # Big Endian IPs
> - #
> - gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
> -##
> diff --git a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> index 6b2aa46ff6..2e35f09d8f 100644
> --- a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> +++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> @@ -15,6 +15,9 @@
> #include <Library/PcdLib.h>
> #include <Library/IoLib.h>
> #include <Library/BaseLib.h>
> +#include <Ppi/NxpPlatformGetClock.h>
> +
> +extern NXP_PLATFORM_GET_CLOCK_PPI mPlatformGetClockPpi;
>
> //
> // 16550 UART register offsets and bitfields
> @@ -42,12 +45,6 @@
> #define B_UART_MSR_RI BIT6
> #define B_UART_MSR_DCD BIT7
>
> -extern
> -UINT64
> -GetBusFrequency (
> - VOID
> - );
> -
> /**
> Read an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is read from
> MMIO space. If PcdSerialUseMmio is FALSE, then the value is read from I/O space. The
> @@ -577,7 +574,7 @@ SerialPortSetAttributes (
> return RETURN_UNSUPPORTED;
> }
>
> - SerialClock = GetBusFrequency ();
> + SerialClock = mPlatformGetClockPpi.PlatformGetClock (NXP_UART_CLOCK, 0);
> if (SerialClock == 0) {
> return EFI_DEVICE_ERROR;
> }
> diff --git a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
> index 45ae9dc0af..7823bc5be5 100644
> --- a/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
> +++ b/Silicon/NXP/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
> @@ -19,11 +19,12 @@
> [Packages]
> MdePkg/MdePkg.dec
> MdeModulePkg/MdeModulePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
>
> [LibraryClasses]
> PcdLib
> IoLib
> - SocLib
> + ArmPlatformLib
>
> [Sources]
> BaseSerialPortLib16550.c
> diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
> deleted file mode 100644
> index 1ef99e8de2..0000000000
> --- a/Silicon/NXP/Library/SocLib/Chassis.c
> +++ /dev/null
> @@ -1,76 +0,0 @@
> -/** @file
> - SoC specific Library containg functions to initialize various SoC components
> -
> - Copyright 2017-2020 NXP
> -
> - SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Base.h>
> -#ifdef CHASSIS2
> -#include <Chassis2/NxpSoc.h>
> -#elif CHASSIS3
> -#include <Chassis3/NxpSoc.h>
> -#endif
> -#include <Library/ArmSmcLib.h>
> -#include <Library/BaseLib.h>
> -#include <Library/IoAccessLib.h>
> -#include <Library/DebugLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/PrintLib.h>
> -#include <Library/SerialPortLib.h>
> -
> -#include "NxpChassis.h"
> -
> -UINT32
> -EFIAPI
> -GurRead (
> - IN UINTN Address
> - )
> -{
> - if (FixedPcdGetBool (PcdGurBigEndian)) {
> - return SwapMmioRead32 (Address);
> - } else {
> - return MmioRead32 (Address);
> - }
> -}
> -
> -/*
> - * Return system bus frequency
> - */
> -UINT64
> -GetBusFrequency (
> - VOID
> - )
> -{
> - SYS_INFO SocSysInfo;
> -
> - GetSysInfo (&SocSysInfo);
> -
> - return SocSysInfo.FreqSystemBus;
> -}
> -
> -/*
> - * Setup SMMU in bypass mode
> - * and also set its pagesize
> - */
> -VOID
> -SmmuInit (
> - VOID
> - )
> -{
> - UINT32 Value;
> -
> - /* set pagesize as 64K and ssmu-500 in bypass mode */
> - Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
> - MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
> -
> - Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
> - MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
> -
> - Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
> - MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
> -}
> -
> diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> deleted file mode 100644
> index a3dabc93d1..0000000000
> --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> +++ /dev/null
> @@ -1,96 +0,0 @@
> -/** @Soc.c
> - SoC specific Library containg functions to initialize various SoC components
> -
> - Copyright 2017-2020 NXP
> -
> - SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -#include <Base.h>
> -#include <NxpChassis.h>
> -#include <Chassis2/NxpSoc.h>
> -#include <Library/BaseLib.h>
> -#include <Library/BaseMemoryLib.h>
> -#include <Library/DebugLib.h>
> -#include <Library/IoAccessLib.h>
> -#include <Library/IoLib.h>
> -#include <Library/PcdLib.h>
> -#include <Library/PrintLib.h>
> -#include <Library/SerialPortLib.h>
> -
> -/**
> - Calculate the frequency of various controllers and
> - populate the passed structure with frequuencies.
> -
> - @param PtrSysInfo Input structure to populate with
> - frequencies.
> -**/
> -VOID
> -GetSysInfo (
> - OUT SYS_INFO *PtrSysInfo
> - )
> -{
> - CCSR_GUR *GurBase;
> - UINTN SysClk;
> -
> - GurBase = (CCSR_GUR *)CHASSIS2_DCFG_ADDRESS;
> - SysClk = CLK_FREQ;
> -
> - SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
> -
> - PtrSysInfo->FreqSystemBus = SysClk;
> -
> - //
> - // selects the platform clock:SYSCLK ratio and calculate
> - // system frequency
> - //
> - PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
> - CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
> - CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
> -}
> -
> -/**
> - Function to initialize SoC specific constructs
> - CPU Info
> - SoC Personality
> - Board Personality
> - RCW prints
> - **/
> -VOID
> -SocInit (
> - VOID
> - )
> -{
> - UINT64 BaudRate;
> - UINT32 ReceiveFifoDepth;
> - EFI_PARITY_TYPE Parity;
> - UINT8 DataBits;
> - EFI_STOP_BITS_TYPE StopBits;
> - UINT32 Timeout;
> -
> - BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
> - ReceiveFifoDepth = 0; // Use default FIFO depth
> - Timeout = 0;
> - Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
> - DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
> - StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);
> -
> - SmmuInit ();
> -
> - //
> - // Early init serial Port to get board information.
> - //
> - SerialPortSetAttributes (
> - &BaudRate,
> - &ReceiveFifoDepth,
> - &Timeout,
> - &Parity,
> - &DataBits,
> - &StopBits
> - );
> - DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a on %a)\n",
> - (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__));
> -
> - return;
> -}
> diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> deleted file mode 100644
> index d8707927b7..0000000000
> --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> +++ /dev/null
> @@ -1,44 +0,0 @@
> -# @file
> -#
> -# Copyright 2017-2020 NXP
> -#
> -# SPDX-License-Identifier: BSD-2-Clause-Patent
> -#
> -
> -[Defines]
> - INF_VERSION = 0x0001001A
> - BASE_NAME = SocLib
> - FILE_GUID = e868c5ca-9729-43ae-bff4-438c67de8c68
> - MODULE_TYPE = BASE
> - VERSION_STRING = 1.0
> - LIBRARY_CLASS = SocLib
> -
> -[Packages]
> - ArmPkg/ArmPkg.dec
> - MdeModulePkg/MdeModulePkg.dec
> - MdePkg/MdePkg.dec
> - Silicon/NXP/NxpQoriqLs.dec
> - Silicon/NXP/LS1043A/LS1043A.dec
> -
> -[LibraryClasses]
> - ArmSmcLib
> - BaseLib
> - DebugLib
> - IoAccessLib
> - SerialPortLib
> -
> -[Sources.common]
> - Chassis.c
> - Chassis2/Soc.c
> -
> -[BuildOptions]
> - GCC:*_*_*_CC_FLAGS = -DCHASSIS2
> -
> -[FixedPcd]
> - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
> - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
> - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
> - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
> - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> - gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
> - gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
> diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h b/Silicon/NXP/Library/SocLib/NxpChassis.h
> deleted file mode 100644
> index 99f6439d8f..0000000000
> --- a/Silicon/NXP/Library/SocLib/NxpChassis.h
> +++ /dev/null
> @@ -1,136 +0,0 @@
> -/** @file
> -* Header defining the Base addresses, sizes, flags etc for chassis 1
> -*
> -* Copyright 2017-2019 NXP
> -*
> -* SPDX-License-Identifier: BSD-2-Clause-Patent
> -*
> -**/
> -
> -#ifndef NXP_CHASSIS_H_
> -#define NXP_CHASSIS_H_
> -
> -#define TP_ITYP_AV_MASK 0x00000001 /* Initiator available */
> -#define TP_ITYP_TYPE_MASK(x) (((x) & 0x6) >> 1) /* Initiator Type */
> -#define TP_ITYP_TYPE_ARM 0x0
> -#define TP_ITYP_TYPE_PPC 0x1
> -#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
> -#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
> -#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
> -#define TP_ITYP_VERSION(x) (((x) & 0xe0) >> 5) /* Initiator Version */
> -#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
> -#define TP_INIT_PER_CLUSTER 4
> -
> -#define TY_ITYP_VERSION_A7 0x1
> -#define TY_ITYP_VERSION_A53 0x2
> -#define TY_ITYP_VERSION_A57 0x3
> -#define TY_ITYP_VERSION_A72 0x4
> -
> -#define CPU_TYPE_ENTRY(N, V, NC) { .Name = #N, .SocVer = SVR_##V, .NumCores = (NC)}
> -
> -#define SVR_WO_E 0xFFFFFE
> -#define SVR_LS1043A 0x879200
> -#define SVR_LS1046A 0x870700
> -#define SVR_LS2088A 0x870901
> -
> -#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
> -#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
> -#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
> -#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
> -
> -#define MHZ 1000000
> -
> -typedef struct {
> - CHAR8 *Name;
> - UINT32 SocVer;
> - UINT32 NumCores;
> -} CPU_TYPE;
> -
> -typedef struct {
> - UINTN CpuClk; /* CPU clock in Hz! */
> - UINTN BusClk;
> - UINTN MemClk;
> - UINTN PciClk;
> - UINTN SdhcClk;
> -} SOC_CLOCK_INFO;
> -
> -/*
> - * Print Soc information
> - */
> -VOID
> -PrintSoc (
> - VOID
> - );
> -
> -/*
> - * Initialize Clock structure
> - */
> -VOID
> -ClockInit (
> - VOID
> - );
> -
> -/*
> - * Setup SMMU in bypass mode
> - * and also set its pagesize
> - */
> -VOID
> -SmmuInit (
> - VOID
> - );
> -
> -/*
> - * Print CPU information
> - */
> -VOID
> -PrintCpuInfo (
> - VOID
> - );
> -
> -/*
> - * Dump RCW (Reset Control Word) on console
> - */
> -VOID
> -PrintRCW (
> - VOID
> - );
> -
> -UINT32
> -InitiatorType (
> - IN UINT32 Cluster,
> - IN UINTN InitId
> - );
> -
> -/*
> - * Return the mask for number of cores on this SOC.
> - */
> -UINT32
> -CpuMask (
> - VOID
> - );
> -
> -/*
> - * Return the number of cores on this SOC.
> - */
> -UINTN
> -CpuNumCores (
> - VOID
> - );
> -
> -/*
> - * Return the type of initiator for core/hardware accelerator for given core index.
> - */
> -UINTN
> -QoriqCoreToType (
> - IN UINTN Core
> - );
> -
> -/*
> - * Return the cluster of initiator for core/hardware accelerator for given core index.
> - */
> -INT32
> -QoriqCoreToCluster (
> - IN UINTN Core
> - );
> -
> -#endif /* NXP_CHASSIS_H_ */
> --
> 2.17.1
>
next prev parent reply other threads:[~2020-02-11 13:35 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-07 12:43 [PATCH 00/19] ADD LX2160ARDB Platform Support Pankaj Bansal
2020-02-07 12:43 ` [PATCH 01/19] Silicon/NXP: Add I2c lib Pankaj Bansal
2020-02-08 17:13 ` Leif Lindholm
2020-02-09 11:49 ` [edk2-devel] " Ard Biesheuvel
2020-02-07 12:43 ` [PATCH 02/19] Silicon/NXP: changes to use I2clib in i2cdxe Pankaj Bansal
2020-02-08 17:23 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 03/19] NXP/LS1043aRdb: Move Soc specific components to soc files Pankaj Bansal
2020-02-08 17:27 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 04/19] Silicon/NXP: Remove DuartLib and use BaseSerialPortLib16550 Pankaj Bansal
2020-02-08 17:46 ` Leif Lindholm
2020-02-10 5:48 ` Pankaj Bansal
2020-02-12 23:27 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 05/19] NXP/BaseSerialPortLib16550: remove SerialPortInitalize functionality Pankaj Bansal
2020-02-07 12:43 ` [PATCH 06/19] Silicon/NXP: remove print information from Soc lib Pankaj Bansal
2020-02-10 17:09 ` [EXTERNAL] " Leif Lindholm
2020-02-07 12:43 ` [PATCH 07/19] Silicon/NXP: remove not needed components Pankaj Bansal
2020-02-10 17:11 ` Leif Lindholm
2020-02-11 7:24 ` Pankaj Bansal
2020-02-20 19:05 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 08/19] Silicon/NXP: Remove unnecessary PCDs Pankaj Bansal
2020-02-10 17:32 ` Leif Lindholm
2020-02-11 8:45 ` Pankaj Bansal
2020-02-20 18:56 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 09/19] Silicon/NXP: Move dsc file Pankaj Bansal
2020-02-11 11:35 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 10/19] Platform/NXP: rename the ArmPlatformLib as per ArmPlatformPkg Pankaj Bansal
2020-02-11 11:40 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 11/19] Silicon/NXP: Add Chassis Lib for Chassis2 Pankaj Bansal
2020-02-11 12:28 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 12/19] Silicon/NXP/LS1043A: Add SocLib Pankaj Bansal
2020-02-11 12:38 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 13/19] Silicon/NXP: Move RAM retrieval from SocLib Pankaj Bansal
2020-02-11 13:28 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 14/19] Silicon/NXP/LS1043A: Replce SocLib Pankaj Bansal
2020-02-11 13:35 ` Leif Lindholm [this message]
2020-02-12 9:37 ` Pankaj Bansal
2020-02-12 22:50 ` Leif Lindholm
2020-02-13 11:00 ` Pankaj Bansal
2020-02-20 18:45 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 15/19] Platform/NXP/LS1043ARDB: introduce PEI Phase Pankaj Bansal
2020-02-12 20:24 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 16/19] Silicon/NXP: Add Pl011 Serial port lib Pankaj Bansal
2020-02-12 20:26 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 17/19] Silicon/NXP: Add Chassis3V2 Pankaj Bansal
2020-02-12 20:33 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 18/19] Silicon/NXP: Add LX2160A SocLib Pankaj Bansal
2020-02-12 21:39 ` Leif Lindholm
2020-02-07 12:43 ` [PATCH 19/19] Platform/NXP: Add LX2160ARDBPKG Pankaj Bansal
2020-02-12 21:36 ` Leif Lindholm
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200211133518.GX23627@bivouac.eciton.net \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox