From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.4536.1582071063296354080 for ; Tue, 18 Feb 2020 16:11:03 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: nathaniel.l.desimone@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Feb 2020 16:11:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,458,1574150400"; d="scan'208";a="434294397" Received: from orsmsx107.amr.corp.intel.com ([10.22.240.5]) by fmsmga005.fm.intel.com with ESMTP; 18 Feb 2020 16:11:02 -0800 Received: from orsmsx125.amr.corp.intel.com (10.22.240.125) by ORSMSX107.amr.corp.intel.com (10.22.240.5) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 18 Feb 2020 16:11:02 -0800 Received: from orsmsx114.amr.corp.intel.com ([169.254.8.140]) by ORSMSX125.amr.corp.intel.com ([169.254.3.208]) with mapi id 14.03.0439.000; Tue, 18 Feb 2020 16:11:02 -0800 From: "Nate DeSimone" To: "Agyeman, Prince" CC: "devel@edk2.groups.io" , "Chiu, Chasel" Subject: Re: [edk2-platforms] [PATCH v2 4/4] WhiskeylakeOpenBoardPkg/UpXtreme: Add DSC and build files Thread-Topic: [edk2-platforms] [PATCH v2 4/4] WhiskeylakeOpenBoardPkg/UpXtreme: Add DSC and build files Thread-Index: AQHV4pbCvoRBfsW71E6fpPuYULY/vagiMxAA Date: Wed, 19 Feb 2020 00:11:01 +0000 Message-ID: <20200219001100.GB7915@nate-virtualbox> References: In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.7.159.63] MIME-Version: 1.0 Return-Path: nathaniel.l.desimone@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-ID: <768A6AB0AFE0C843900F8F2B0C51247F@intel.com> Content-Transfer-Encoding: quoted-printable Hi Prince, Please update the copyright year on build.cfg. Thanks, Nate On Thu, Feb 13, 2020 at 05:55:11PM +0000, Agyeman, Prince wrote: > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2191 >=20 > Adds the DSC and build files necessary to build the > UpXtreme board instance. >=20 > Key files > =3D=3D=3D=3D=3D=3D=3D=3D=3D > * build_config.cfg - Board-specific build configuration file. > * OpenBoardPkg.dsc - The UpXtreme board description file. > * OpenBoardPkgPcd.dsc - Used for other PCD customization. > * OpenBoardPkg.fdf - The UpXtreme board flash file. > * OpenBoardPkgBuildOption.dsc - Sets build options Based > on PCD values. >=20 > Co-authored-by: Michael Kubacki > Cc: Chasel Chiu > Cc: Nate DeSimone > Signed-off-by: Prince Agyeman > --- > Platform/Intel/Readme.md | 19 +- > .../UpXtreme/OpenBoardPkg.dsc | 448 +++++++++++ > .../UpXtreme/OpenBoardPkg.fdf | 708 ++++++++++++++++++ > .../UpXtreme/OpenBoardPkgBuildOption.dsc | 154 ++++ > .../UpXtreme/OpenBoardPkgPcd.dsc | 409 ++++++++++ > .../UpXtreme/build_config.cfg | 35 + > Platform/Intel/build.cfg | 1 + > 7 files changed, 1772 insertions(+), 2 deletions(-) > create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenB= oardPkg.dsc > create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenB= oardPkg.fdf > create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenB= oardPkgBuildOption.dsc > create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenB= oardPkgPcd.dsc > create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/build= _config.cfg >=20 > diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md > index 02d9517d19..55cf02a8ca 100644 > --- a/Platform/Intel/Readme.md > +++ b/Platform/Intel/Readme.md > @@ -59,6 +59,12 @@ A UEFI firmware implementation using MinPlatformPkg is= constructed using the fol > =20 > ### **Supported Hardware** > =20 > +#### AAEON > + > +| Machine Name | Supported Chipsets = | BoardPkg | Board Name | > +----------------------------------------|-------------------------------= -------------|------------------------------|--------------------| > +| UP Xtreme | Whiskey Lake = | WhiskeylakeOpenBoardPkg | UpXtreme | > + > #### Intel > =20 > ***Intel Reference and Validation Platform*** > @@ -233,6 +239,9 @@ return back to the minimum platform caller. > | | | build s= ettings, environment variables. > | | | > | | |------WhiskeylakeOpenBoardPkg > + | | | |------UpXtreme > + | | | |---build_config.cfg: UpXtrem= e specific build > + | | | setting= s environment variables. > | | | |------WhiskeylakeURvp > | | | |---build_config.cfg: Whiskey= lakeURvp specific build > | | | setting= s environment variables. > @@ -254,8 +263,14 @@ return back to the minimum platform caller. > 1. This firmware project has only been tested booting to Microsoft Windo= ws 10 x64 and Ubuntu 17.10 with AHCI mode. > =20 > **WhiskeylakeOpenBoardPkg** > -1. This firmware project has only been tested booting to Microsoft Windo= ws 10 x64 with AHCI mode and Integrated Graphic > +1. This firmware project has mainly been tested booting to Microsoft Win= dows 10 x64 with AHCI mode and Integrated Graphic > Device. > +2. UP Xtreme boards might hang during Windows 10 boot. > +3. Not all UP Xtreme boards are supported at this time. > + * The model below boots to x64 windows 10 home edition and Ubuntu 18= .04 > + * Xtreme Intel(R) Core(TM) i3-8145UE CPU @ 2.20GHz with 8GB RAM > + * Xtreme Intel(R) Core(TM) i7-8565U CPU @ 1.80GHz with 16GB RAM > + * Intel(R) Celeron(R) CPU 4305UE @ 2.00GHz with 4GB RAM hangs during= memory initialization > =20 > ### **Package Builds** > =20 > @@ -293,5 +308,5 @@ If you would like to help but are not sure where to s= tart some areas currently i > * Adding board ports for more motherboards and systems > * Adding Clang support > =20 > -Please feel free to contact Michael Kubacki (michael.a.kubacki at intel.= com) and Isaac Oram (isaac.w.oram at intel.com) > +Please feel free to contact Isaac Oram (isaac.w.oram at intel.com) > if you would like to discuss contribution ideas. > diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg= .dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc > new file mode 100644 > index 0000000000..2ab9cb03ea > --- /dev/null > +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc > @@ -0,0 +1,448 @@ > +## @file > +# The main build description file for the UpXtreme board. > +# > +# Copyright (c) 2020, Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + DEFINE PLATFORM_PACKAGE =3D MinPlatformPkg > + DEFINE PLATFORM_SI_PACKAGE =3D CoffeelakeSiliconPkg > + DEFINE PLATFORM_SI_BIN_PACKAGE =3D CoffeelakeSiliconBinPkg > + DEFINE PLATFORM_FSP_BIN_PACKAGE =3D CoffeeLakeFspBinPkg > + DEFINE PLATFORM_BOARD_PACKAGE =3D WhiskeylakeOpenBoardPkg > + DEFINE BOARD =3D UpXtreme > + DEFINE PROJECT =3D $(PLATFORM_BOARD_PACKAGE)/$(= BOARD) > + DEFINE PEI_ARCH =3D IA32 > + DEFINE DXE_ARCH =3D X64 > + DEFINE TOP_MEMORY_ADDRESS =3D 0x0 > + > + # > + # Default value for OpenBoardPkg.fdf use > + # > + DEFINE BIOS_SIZE_OPTION =3D SIZE_80 > + > + PLATFORM_NAME =3D $(PLATFORM_PACKAGE) > + PLATFORM_GUID =3D A12B2802-BF37-4886-A307-C060F7= 929F8F > + PLATFORM_VERSION =3D 0.1 > + DSC_SPECIFICATION =3D 0x00010005 > + OUTPUT_DIRECTORY =3D Build/$(PROJECT) > + SUPPORTED_ARCHITECTURES =3D IA32|X64 > + BUILD_TARGETS =3D DEBUG|RELEASE > + SKUID_IDENTIFIER =3D ALL > + > + FLASH_DEFINITION =3D $(PROJECT)/OpenBoardPkg.fdf > + FIX_LOAD_TOP_MEMORY_ADDRESS =3D 0x0 > + > + # > + # Include PCD configuration for this board. > + # > + !include AdvancedFeaturePkg/TemporaryBuildWorkaround/TemporaryBuildWor= karound.dsc > + !include OpenBoardPkgPcd.dsc > + !include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc > + > +########################################################################= ######## > +# > +# SKU Identification section - list of all SKU IDs supported by this boa= rd. > +# > +########################################################################= ######## > +[SkuIds] > + 0|DEFAULT # 0|DEFAULT is reserved and always required. > + 0x10|UpXtreme > + > +########################################################################= ######## > +# > +# Includes section - other DSC file contents included for this board bui= ld. > +# > +########################################################################= ######## > + > +####################################### > +# Library Includes > +####################################### > +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc > +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc > +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc > +!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc > +!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc > +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc > + > +####################################### > +# Component Includes > +####################################### > +# @todo: Change below line to [Components.$(PEI_ARCH)] after https://bug= zilla.tianocore.org/show_bug.cgi?id=3D2308 > +# is completed > +[Components.IA32] > +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc > +!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc > + > +# @todo: Change below line to [Components.$(DXE_ARCH)] after https://bug= zilla.tianocore.org/show_bug.cgi?id=3D2308 > +# is completed > +[Components.X64] > +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc > +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc > + > +####################################### > +# Build Option Includes > +####################################### > +!include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc > +!include OpenBoardPkgBuildOption.dsc > + > +########################################################################= ######## > +# > +# Library Class section - list of all Library Classes needed by this boa= rd. > +# > +########################################################################= ######## > + > +[LibraryClasses.common] > + ####################################### > + # Edk2 Packages > + ####################################### > + FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/Base= FspWrapperApiLib.inf > + FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestL= ib/PeiFspWrapperApiTestLib.inf > + > + ####################################### > + # Silicon Initialization Package > + ####################################### > + ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBl= ockLib.inf > + MmPciLib|$(PLATFORM_SI_PACKAGE)/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmP= ciLib.inf > + PchHsioLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchHsioLib/PeiD= xeSmmPchHsioLib.inf > + PchPmcLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxe= SmmPchPmcLib.inf > + > + ##################################### > + # Platform Package > + ##################################### > + BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull= /BoardInitLibNull.inf > + FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspW= rapperHobProcessLib/PeiFspWrapperHobProcessLib.inf > + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWra= pperPlatformLib/PeiFspWrapperPlatformLib.inf > + PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimpl= e/PciHostBridgeLibSimple.inf > + PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSim= ple/PciSegmentInfoLibSimple.inf > + PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf > + PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBoot= ManagerLib/DxePlatformBootManagerLib.inf > + ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/Pe= iReportFvLib.inf > + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNu= ll/TestPointCheckLibNull.inf > + > + ####################################### > + # Board Package > + ####################################### > + GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/= BaseGpioExpanderLib.inf > + HdaVerbTableLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiHdaVerbTableLib/P= eiHdaVerbTableLib.inf > + I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cA= ccessLib.inf > + PlatformSecLib|$(PROJECT)/FspWrapper/Library/SecFspWrapperPlatformSecL= ib/SecFspWrapperPlatformSecLib.inf > + TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerL= ib.inf > + # Thunderbolt > +!if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE > + TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDxeSmmT= btCommonLib/TbtCommonLib.inf > +!endif > + > + ####################################### > + # Board-specific > + ####################################### > + PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHoo= kLib.inf > + > +[LibraryClasses.IA32.SEC] > + ####################################### > + # Platform Package > + ####################################### > + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/S= ecTestPointCheckLib.inf > + SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitL= ibNull/SecBoardInitLibNull.inf > + > + ####################################### > + # Board Package > + ####################################### > + SiliconPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiF= spPolicyInitLib/PeiFspPolicyInitLib.inf > + SiliconPolicyUpdateLib|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyU= pdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf > + TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerL= ib.inf > + > +[LibraryClasses.common.PEIM] > + ####################################### > + # Silicon Initialization Package > + ####################################### > + SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSil= iconInitLib.inf > + > + ####################################### > + # Platform Package > + ####################################### > + BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSu= pportLib/PeiMultiBoardInitSupportLib.inf > + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWra= pperPlatformLib/PeiFspWrapperPlatformLib.inf > + MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Mult= iBoardInitSupportLib/PeiMultiBoardInitSupportLib.inf > + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPoin= tLib.inf > +!if $(TARGET) =3D=3D DEBUG > + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/P= eiTestPointCheckLib.inf > +!endif > + SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheMt= rrLibNull.inf > + > + ####################################### > + # Board Package > + ####################################### > + # Thunderbolt > +!if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE > + PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/= PeiDTbtInitLib/PeiDTbtInitLib.inf > + PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbtP= olicyLib/PeiTbtPolicyLib.inf > +!endif > + PeiPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiPolicyIni= tLib/PeiPolicyInitLib.inf > + PeiPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiPolicyU= pdateLib/PeiPolicyUpdateLib.inf > + SiliconPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiF= spPolicyInitLib/PeiFspPolicyInitLib.inf > + SiliconPolicyUpdateLib|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyU= pdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf > + TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerL= ib.inf > + > + ####################################### > + # Board-specific > + ####################################### > + PeiPlatformHookLib|$(PROJECT)/Library/PeiPlatformHookLib/PeiPlatformHo= okLib.inf > + PeiPolicyBoardConfigLib|$(PROJECT)/Library/PeiPolicyBoardConfigLib/Pei= PolicyBoardConfigLib.inf > + > +!if $(TARGET) =3D=3D DEBUG > + GpioCheckConflictLib|$(PROJECT)/Library/BaseGpioCheckConflictLib/BaseG= pioCheckConflictLib.inf > +!else > + GpioCheckConflictLib|$(PROJECT)/Library/BaseGpioCheckConflictLibNull/B= aseGpioCheckConflictLibNull.inf > +!endif > + > +[LibraryClasses.common.DXE_DRIVER] > + ####################################### > + # Edk2 Packages > + ####################################### > + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.= inf > + > + ####################################### > + # Platform Package > + ####################################### > + BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSuppo= rtLib/DxeMultiBoardAcpiSupportLib.inf > + BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSu= pportLib/DxeMultiBoardInitSupportLib.inf > + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeFspWra= pperPlatformLib/DxeFspWrapperPlatformLib.inf > + MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAc= piSupportLib/DxeMultiBoardAcpiSupportLib.inf > + MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Mult= iBoardInitSupportLib/DxeMultiBoardInitSupportLib.inf > + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPoin= tLib.inf > + > +!if $(TARGET) =3D=3D DEBUG > + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/D= xeTestPointCheckLib.inf > +!endif > + > + ####################################### > + # Board Package > + ####################################### > + DxePolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/DxePolicyU= pdateLib/DxePolicyUpdateLib.inf > + DxeTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/DxeTbtP= olicyLib/DxeTbtPolicyLib.inf > + > + ####################################### > + # Board-specific > + ####################################### > + DxePolicyBoardConfigLib|$(PROJECT)/Library/DxePolicyBoardConfigLib/Dxe= PolicyBoardConfigLib.inf > + > +[LibraryClasses.X64.DXE_RUNTIME_DRIVER] > + ####################################### > + # Edk2 Packages > + ####################################### > + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.= inf > + > + ####################################### > + # Silicon Initialization Package > + ####################################### > + ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSyste= mLib/DxeRuntimeResetSystemLib.inf > + > +[LibraryClasses.X64.DXE_SMM_DRIVER] > + ####################################### > + # Edk2 Packages > + ####################################### > + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.= inf > + > + ####################################### > + # Silicon Initialization Package > + ####################################### > + SpiFlashCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/SmmSpiFlashCommon= Lib/SmmSpiFlashCommonLib.inf > + > + ####################################### > + # Platform Package > + ####################################### > + BoardAcpiEnableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupp= ortLib/SmmMultiBoardAcpiSupportLib.inf > + MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAc= piSupportLib/SmmMultiBoardAcpiSupportLib.inf > + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPoin= tLib.inf > +!if $(TARGET) =3D=3D DEBUG > + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/S= mmTestPointCheckLib.inf > +!endif > + > +####################################### > +# PEI Components > +####################################### > +# @todo: Change below line to [Components.$(PEI_ARCH)] after https://bug= zilla.tianocore.org/show_bug.cgi?id=3D2308 > +# is completed > +[Components.IA32] > + ####################################### > + # Edk2 Packages > + ####################################### > + UefiCpuPkg/SecCore/SecCore.inf { > + > + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf > + } > + > + # > + # In FSP API mode the policy has to be installed before FSP Wrapper up= dating UPD. > + # Add policy as dependency for FSP Wrapper > + # > + IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > + IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > + > + ####################################### > + # Silicon Initialization Package > + ####################################### > + IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf > + IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSa= mplePei.inf > + > + ####################################### > + # Platform Package > + ####################################### > + $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf > + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.in= f { > + > + !if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport = =3D=3D FALSE > + BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemL= ib.inf > + !else > + NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.= inf > + !endif > + NULL|$(PROJECT)/Library/BaseFuncLib/BaseFuncLib.inf > + } > + > + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.i= nf { > + > + !if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport = =3D=3D FALSE > + BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPostMem= Lib.inf > + !else > + NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib= .inf > + !endif > + } > + > + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreM= em.inf > + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPost= Mem.inf > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE > + $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf > +!endif > + > + > + ####################################### > + # Board Package > + ####################################### > + # Thunderbolt > +!if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE > + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf > +!endif > + $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf > + > +####################################### > +# DXE Components > +####################################### > +# @todo: Change below line to [Components.$(DXE_ARCH)] after https://bug= zilla.tianocore.org/show_bug.cgi?id=3D2308 > +# is completed > +[Components.X64] > + ####################################### > + # Edk2 Packages > + ####################################### > + IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf > + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf > + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf > + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf > + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf > + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf > + MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf > + UefiCpuPkg/CpuDxe/CpuDxe.inf > + > + # > + # eMMC/SD Card > + # > + MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf > + MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf > + MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf > + > + ShellPkg/Application/Shell/Shell.inf { > + > + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE > + > + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Com= mandsLib.inf > + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Com= mandsLib.inf > + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Com= mandsLib.inf > + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1C= ommandsLib.inf > + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall= 1CommandsLib.inf > + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Com= mandsLib.inf > + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork= 1CommandsLib.inf > + NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork= 2CommandsLib.inf > + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComma= ndLib.inf > + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePa= rsingLib.inf > + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBc= fgCommandLib.inf > + ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryL= ib.inf > + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf > + } > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE > + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { > + > + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80080046 > + > + !if $(TARGET) =3D=3D DEBUG > + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSeria= lPort.inf > + !endif > + } > +!endif > + > + ####################################### > + # Silicon Initialization Package > + ####################################### > + IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf > + $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf > + $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf > + > + ####################################### > + # Platform Package > + ####################################### > + $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf > + $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf > + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf > + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf= { > + > + SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPo= licyInitLibNull/SiliconPolicyInitLibNull.inf > + SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/Silicon= PolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf > + } > + $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf > + $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE > + $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE > + > + $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf > + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf > + > + $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf { > + > + !if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport = =3D=3D FALSE > + BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiE= nableLib.inf > + !else > + NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib= .inf > + !endif > + } > + > + $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf > + > +!endif > + > + ####################################### > + # Board Package > + ####################################### > + $(PLATFORM_BOARD_PACKAGE)/Policy/PolicyInitDxe/PolicyInitDxe.inf{ > + > + NULL|$(PROJECT)/Library/BaseFuncLib/BaseFuncLib.inf > + } > + > + # Thunderbolt > +!if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE > + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf > + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf > + $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE > + $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf > +!endif > + BoardModulePkg/LegacySioDxe/LegacySioDxe.inf > diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg= .fdf b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf > new file mode 100644 > index 0000000000..36a7e05a49 > --- /dev/null > +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.fdf > @@ -0,0 +1,708 @@ > +## @file > +# FDF file for the UpXtreme. > +# > +# > +# Copyright (c) 2020, Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +# > +## > + > +[Defines] > + !include $(PROJECT)/Include/Fdf/FlashMapInclude.fdf > + > +########################################################################= ######## > +# > +# FD Section > +# The [FD] Section is made up of the definition statements and a > +# description of what goes into the Flash Device Image. Each FD sectio= n > +# defines one flash "device" image. A flash device image may be one of > +# the following: Removable media bootable image (like a boot floppy > +# image,) an Option ROM image (that would be "flashed" into an add-in > +# card,) a System "Flash" image (that would be burned into a system's > +# flash) or an Update ("Capsule") image that will be used to update and > +# existing system flash. > +# > +########################################################################= ######## > +[FD.UpXtreme] > +# > +# FD Tokens, BaseAddress, Size, ErasePolarity, BlockSize, and NumBlocks,= cannot be > +# assigned with PCD values. Instead, it uses the definitions for its var= iety, which > +# are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS. > +# > +BaseAddress =3D $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAd= dress #The base address of the FLASH Device. > +Size =3D $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdBiosSize = #The size in bytes of the FLASH Device > +ErasePolarity =3D 1 > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +NumBlocks =3D $(FLASH_NUM_BLOCKS) > + > +DEFINE SIPKG_DXE_SMM_BIN =3D INF > +DEFINE SIPKG_PEI_BIN =3D INF > + > +# Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because ma= cro expression is not supported. > +# So, PlatformSecLib uses PcdBiosAreaBaseAddress + PcdNemCodeCacheBase t= o get the real CodeCache base address. > +SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =3D $(gMinPlatformPkgTokenS= paceGuid.PcdFlashFvPreMemoryOffset) > +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gSiPkgTokenSpaceG= uid.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOff= set) > +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gSiPkgTokenSpaceG= uid.PcdFlashMicrocodeFvSize) > +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiPkgTo= kenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 > +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gSiPk= gTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gS= iPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlas= hMicrocodeFvOffset) > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $= (gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset =3D 0x60 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvBase > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvOffset > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gSiPkgT= okenSpaceGuid.PcdBiosAreaBaseAddress > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gSiPkgT= okenSpaceGuid.PcdBiosSize > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gSiPk= gTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.P= cdFlashFvFspTOffset) > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gSiPk= gTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.P= cdFlashFvFspMOffset) > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gSiPk= gTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.P= cdFlashFvFspSOffset) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gSiPkgT= okenSpaceGuid.PcdBiosAreaBaseAddress > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gSiPkgT= okenSpaceGuid.PcdBiosSize > +########################################################################= ######## > +# > +# Following are lists of FD Region layout which correspond to the locati= ons of different > +# images within the flash device. > +# > +# Regions must be defined in ascending order and may not overlap. > +# > +# A Layout Region start with a eight digit hex offset (leading "0x" requ= ired) followed by > +# the pipe "|" character, followed by the size of the region, also in he= x with the leading > +# "0x" characters. Like: > +# Offset|Size > +# PcdOffsetCName|PcdSizeCName > +# RegionType > +# Fv Size can be adjusted > +# > +########################################################################= ######## > +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeMod= ulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize > +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize > +#NV_VARIABLE_STORE > +DATA =3D { > + ## This is the EFI_FIRMWARE_VOLUME_HEADER > + # ZeroVector [] > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + # FileSystemGuid > + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, > + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, > + # FvLength: 0x40000 > + 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, > + #Signature "_FVH" #Attributes > + 0x5F, 0x46, 0x56, 0x48, 0xFF, 0xFE, 0x04, 0x00, > + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision > + # > + # Be careful on CheckSum field. > + # > + 0x48, 0x00, 0x32, 0x09, 0x00, 0x00, 0x00, 0x02, > + #Blockmap[0]: 4 Blocks 0x10000 Bytes / Block > + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, > + #Blockmap[1]: End > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + ## This is the VARIABLE_STORE_HEADER > +!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable =3D=3D TRUE > + # Signature: gEfiAuthenticatedVariableGuid =3D { 0xaaf32c78, 0x947b, = 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} > + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, > + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, > +!else > + # Signature: gEfiVariableGuid =3D { 0xddcf3616, 0x3275, 0x4164, { 0x9= 8, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} > + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, > + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, > +!endif > + #Size: 0x1E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariab= leSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x1DFB8 > + # This can speed up the Variable Dispatch a bit. > + 0xB8, 0xDF, 0x01, 0x00, > + #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 > + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 > +} > + > +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeM= odulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize > +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeMo= dulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize > +#NV_FTW_WORKING > +DATA =3D { > + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D gEdkiiWorking= BlockSignatureGuid =3D > + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f,= 0x1b, 0x95 }} > + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, > + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, > + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, R= eserved > + 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, > + # WriteQueueSize: UINT64 > + 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 > +} > + > +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeMod= ulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize > +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize > +#NV_FTW_SPARE > + > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvAdvancedSize > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvAdvancedSize > +FV =3D FvAdvanced > + > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvSecuritySize > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvSecuritySize > +FV =3D FvSecurity > + > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvOsBootSize > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvOsBootSize > +FV =3D FvOsBoot > + > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvUefiBootSize > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvUefiBootSize > +FV =3D FvUefiBoot > + > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkg= TokenSpaceGuid.PcdFlashFvPostMemorySize > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvPostMemorySize > +FV =3D FvPostMemory > + > +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdF= lashMicrocodeFvSize > +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFla= shMicrocodeFvSize > +#Microcode > +FV =3D FvMicrocode > + > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvFspSSize > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspSSize > +# FSP_S Section > +FILE =3D $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd > + > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvFspMSize > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspMSize > +# FSP_M Section > +FILE =3D $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M.fd > + > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvFspTSize > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspTSize > +# FSP_T Section > +FILE =3D $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_T.fd > + > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset|gMinPlat= formPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryBase|gMinPlatfo= rmPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize > +FV =3D FvAdvancedPreMemory > + > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgT= okenSpaceGuid.PcdFlashFvPreMemorySize > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgTok= enSpaceGuid.PcdFlashFvPreMemorySize > +FV =3D FvPreMemory > + > +########################################################################= ######## > +# > +# FV Section > +# > +# [FV] section is used to define what components or modules are placed w= ithin a flash > +# device file. This section also defines order the components and modul= es are positioned > +# within the image. The [FV] section consists of define statements, set= statements and > +# module statements. > +# > +########################################################################= ######## > +[FV.FvMicrocode] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D FALSE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D FALSE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > + > +FILE RAW =3D 197DB236-F856-4924-90F8-CDF12FB875F3 { > + $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/X64/MicrocodeUpdates.b= in > +} > + > +[FV.FvPreMemory] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D > + > +INF UefiCpuPkg/SecCore/SecCore.inf > +INF MdeModulePkg/Core/Pei/PeiMain.inf > +!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf > + > +INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf > +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.= inf > +INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > +INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPr= eMem.inf > +INF $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf > + > +[FV.FvPostMemoryUncompact] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 7C4DCFC6-AECA-4707-85B9-FD4B2EEA49E7 > + > +!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf > + > +# Init Board Config PCD > +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem= .inf > +INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > +INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPo= stMem.inf > + > +FILE RAW =3D C9505BC0-AA3D-4056-9995-870C8DE8594E { > + $(PLATFORM_SI_BIN_PACKAGE)/ChipsetInit/CnlPchLpChipsetInitTable_Dx.b= in > + } > +!if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable =3D=3D TRUE > +FILE FREEFORM =3DPCD(gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtF= ileGuid) { > + SECTION RAW =3D $(PLATFORM_FSP_BIN_PACKAGE)/SampleCode/Vbt/Vbt.bin > + SECTION UI =3D "Vbt" > +} > +FILE FREEFORM =3D 7BB28B99-61BB-11D5-9A5D-0090273FC14D { > + SECTION RAW =3D MdeModulePkg/Logo/Logo.bmp > +} > +!endif # PcdPeiDisplayEnable > + > + > +[FV.FvPostMemory] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 9DFE49DB-8EF0-4D9C-B273-0036144DE917 > + > +FILE FV_IMAGE =3D 244FAAF4-FAE1-4892-8B7D-7EF84CBFA709 { > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQ= UIRED =3D TRUE { > + SECTION FV_IMAGE =3D FvPostMemoryUncompact > + } > +} > + > +[FV.FvUefiBootUncompact] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D A881D567-6CB0-4eee-8435-2E72D33E45B5 > + > +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf > +INF $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxeCnl.inf > + > +INF UefiCpuPkg/CpuDxe/CpuDxe.inf > +INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf > + > +INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf > +INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf > +INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf > +INF MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.= inf > +INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf > +INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf > + > +# > +# eMMC/SD Card > +# > +INF MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf > +INF MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf > +INF MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf > + > +INF ShellPkg/Application/Shell/Shell.inf > + > +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.in= f > +INF $(PLATFORM_BOARD_PACKAGE)/Policy/PolicyInitDxe/PolicyInitDxe.inf > +INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.= inf > +INF IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf > + > +INF $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf > + > + > +[FV.FvUefiBoot] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 0496D33D-EA79-495C-B65D-ABF607184E3B > + > +FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_RE= QUIRED =3D TRUE { > + SECTION FV_IMAGE =3D FvUefiBootUncompact > + } > + } > + > +[FV.FvOsBootUncompact] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D A0F04529-B715-44C6-BCA4-2DEBDD01EEEC > + > +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE > +INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf > +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.in= f > +INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf > + > +INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf > +INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf > + > +INF RuleOverride =3D DRIVER_ACPITABLE $(PLATFORM_BOARD_PACKAGE)/Acpi/Bo= ardAcpiDxe/BoardAcpiDxe.inf > +INF $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.in= f > + > +!endif > + > +[FV.FvLateSilicon] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 97F09B89-9E83-4DDC-A3D1-10C4AF539D1E > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE > +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaIni= tDxe.inf > +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SmmAccess/Dxe/Sm= mAccess.inf > +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/Pch= SmiDispatcher.inf > +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/Sm= mControl.inf > +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/Spi/Smm/PchSpiSmm.inf > +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.i= nf > + > +INF RuleOverride =3D ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiT= ables/SaAcpiTables.inf > +INF RuleOverride =3D ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiT= ables/SaSsdt/SaSsdt.inf > + > +!endif > + > +[FV.FvOsBoot] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 13BF8810-75FD-4B1A-91E6-E16C4201F80A > + > +FILE FV_IMAGE =3D B9020753-84A8-4BB6-947C-CE7D41F5CE39 { > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_RE= QUIRED =3D TRUE { > + SECTION FV_IMAGE =3D FvOsBootUncompact > + } > + } > + > +FILE FV_IMAGE =3D D4632741-510C-44E3-BE21-C3D6D7881485 { > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_RE= QUIRED =3D TRUE { > + SECTION FV_IMAGE =3D FvLateSilicon > + } > + } > + > +[FV.FvSecurityPreMemory] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 #FV alignment and FV attributes settin= g. > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 9B7FA59D-71C6-4A36-906E-9725EA6ADD5B > + > +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fd= f > + > +INF IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInf= oSamplePei.inf > + > +INF IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf > + > +[FV.FvSecurityPostMemory] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 #FV alignment and FV attributes settin= g. > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 4199E560-54AE-45E5-91A4-F7BC3804E14A > + > +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.f= df > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE > +INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf > +!endif > + > +[FV.FvSecurityLate] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D F753FE9A-EEFD-485B-840B-E032D538102C > + > +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf > +INF IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE > +INF $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf > +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE > +INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf > +!endif > +!endif > + > +[FV.FvSecurity] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 5A9A8B4E-149A-4CB2-BDC7-C8D62DE2C8CF > + > +FILE FV_IMAGE =3D 757CC075-1428-423D-A73C-22639706C119 { > + SECTION FV_IMAGE =3D FvSecurityPreMemory > + } > + > +FILE FV_IMAGE =3D 80BB8482-44D5-4BEC-82B5-8D87A933830B { > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_RE= QUIRED =3D TRUE { > + SECTION FV_IMAGE =3D FvSecurityPostMemory > + } > + } > + > +FILE FV_IMAGE =3D C83522D9-80A1-4D95-8C25-3F1370497406 { > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_RE= QUIRED =3D TRUE { > + SECTION FV_IMAGE =3D FvSecurityLate > + } > + } > + > +# > +# Pre-memory Advanced Features > +# > +[FV.FvAdvancedPreMemory] > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 6053D78A-457E-4490-A237-31D0FBE2F305 > + > +!include AdvancedFeaturePkg/Include/PreMemory.fdf > + > +!if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE > +INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf > +!endif > + > +# > +# Post-Memory Advanced Features > +# > +[FV.FvAdvancedUncompact] > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D BE3DF86F-E464-44A3-83F7-0D27E6B88C27 > + > +!include AdvancedFeaturePkg/Include/PostMemory.fdf > + > +!if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE > +INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf > +INF $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf > +INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf > +!endif > + > +# > +# Compressed FV with Post-Memory Advanced Features > +# > +[FV.FvAdvanced] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D B23E7388-9953-45C7-9201-0473DDE5487A > + > +FILE FV_IMAGE =3D 5248467B-B87B-4E74-AC02-398AF4BCB712 { > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_RE= QUIRED =3D TRUE { > + SECTION FV_IMAGE =3D FvAdvancedUncompact > + } > + } > + > +########################################################################= ######## > +# > +# Rules are use with the [FV] section's module INF type to define > +# how an FFS file is created for a given INF file. The following Rule ar= e the default > +# rules for the different module type. User can add the customized rules= to define the > +# content of the FFS file. > +# > +########################################################################= ######## > + > +!include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf > + > + > diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg= BuildOption.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoard= PkgBuildOption.dsc > new file mode 100644 > index 0000000000..4881431e33 > --- /dev/null > +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgBuildOp= tion.dsc > @@ -0,0 +1,154 @@ > +## @file > +# UpXtreme build option configuration file. > +# > +# > +# Copyright (c) 2020, Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +# > +## > + > +[BuildOptions] > +# Define Build Options both for EDK and EDKII drivers. > + > + > + DEFINE DSC_S3_BUILD_OPTIONS =3D > + > + DEFINE DSC_CSM_BUILD_OPTIONS =3D > + > +!if gSiPkgTokenSpaceGuid.PcdAcpiEnable =3D=3D TRUE > + DEFINE DSC_ACPI_BUILD_OPTIONS =3D -DACPI_SUPPORT=3D1 > +!else > + DEFINE DSC_ACPI_BUILD_OPTIONS =3D > +!endif > + > + DEFINE BIOS_GUARD_BUILD_OPTIONS =3D > + > + DEFINE OVERCLOCKING_BUILD_OPTION =3D > + > + DEFINE FSP_BINARY_BUILD_OPTIONS =3D > + > + DEFINE FSP_WRAPPER_BUILD_OPTIONS =3D -DFSP_WRAPPER_FLAG > + > + DEFINE SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS =3D > + > + DEFINE RESTRICTED_OPTION =3D > + > + > + DEFINE SV_BUILD_OPTIONS =3D > + > + DEFINE TEST_MENU_BUILD_OPTION =3D > + > +!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable =3D=3D FALSE > + DEFINE OPTIMIZE_DISABLE_OPTIONS =3D -Od -GL- > +!else > + DEFINE OPTIMIZE_DISABLE_OPTIONS =3D > +!endif > + > + DEFINE UP_SERVER_SUPPORT_BUILD_OPTIONS =3D > + > + > + DEFINE TPM_BUILD_OPTION =3D > + > + DEFINE TPM2_BUILD_OPTION =3D > + > + DEFINE DSC_TBT_BUILD_OPTIONS =3D > + > + DEFINE DSC_DCTT_BUILD_OPTIONS =3D > + > + DEFINE EMB_BUILD_OPTIONS =3D > + > + DEFINE DSC_MEMORY_DOWN_BUILD_OPTIONS =3D -DMEM_DOWN_FLAG=3D1 > + > + DEFINE DSC_KBCEMUL_BUILD_OPTIONS =3D > + > + DEFINE BOOT_GUARD_BUILD_OPTIONS =3D > + > + DEFINE SECURE_BOOT_BUILD_OPTIONS =3D > + > + DEFINE USBTYPEC_BUILD_OPTION =3D > + > + DEFINE CAPSULE_BUILD_OPTIONS =3D > + > + DEFINE PERFORMANCE_BUILD_OPTION =3D > + > + DEFINE DEBUGUSEUSB_BUILD_OPTION =3D > + > + DEFINE DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION =3D -DDISABLE_NE= W_DEPRECATED_INTERFACES=3D1 > + > + DEFINE SINITBIN_BUILD_OPTION =3D > + > + DEFINE MINTREE_FLAG_BUILD_OPTION =3D -DMINTREE_FLAG=3D1 > + > + DEFINE CPUTYPE_BUILD_OPTION =3D -DCPU_CFL=3D1 > + > +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_SIPKG_FEATURE_BUILD_OP= TIONS) $(OVERCLOCKING_BUILD_OPTION) $(PERFORMANCE_BUILD_OPTION) $(EMB_BUIL= D_OPTIONS) $(BIOS_GUARD_BUILD_OPTIONS) $(DSC_TBT_BUILD_OPTIONS) > +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_O= PTIONS) $(BOOT_GUARD_BUILD_OPTIONS) $(DSC_MEMORY_DOWN_BUILD_OPTIONS) $(DEBU= GUSEUSB_BUILD_OPTION) $(DSC_S3_BUILD_OPTIONS) > +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_O= PTIONS) $(FSP_BINARY_BUILD_OPTIONS) $(FSP_WRAPPER_BUILD_OPTIONS) $(SKIP_FSP= _TEMPRAM_INIT_AND_EXIT_OPTIONS) > +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_O= PTIONS) $(DSC_KBCEMUL_BUILD_OPTIONS) $(CAPSULE_BUILD_OPTIONS) $(SECURE_BOOT= _BUILD_OPTIONS) $(DSC_CSM_BUILD_OPTIONS) $(DISABLE_NEW_DEPRECATED_INTERFACE= S_BUILD_OPTION) > +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_O= PTIONS) $(TPM2_BUILD_OPTION) $(TPM_BUILD_OPTION) $(DSC_DCTT_BUILD_OPTIONS) > +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_O= PTIONS) $(DSC_ACPI_BUILD_OPTIONS) $(UP_SERVER_SUPPORT_BUILD_OPTIONS) $(USBT= YPEC_BUILD_OPTION) $(SINITBIN_BUILD_OPTION) $(MINTREE_FLAG_BUILD_OPTION) > +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_O= PTIONS) $(CPUTYPE_BUILD_OPTION) > +[BuildOptions.Common.EDKII] > + > +# > +# For IA32 Global Build Flag > +# > + *_*_IA32_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D= PI_SPECIFICATION_VERSION=3D0x00010015 -DASF_PEI > + *_*_IA32_VFRPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > + *_*_IA32_APP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > + *_*_IA32_ASLPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > + *_*_IA32_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > + *_*_IA32_NASM_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > + > +# > +# For IA32 Specific Build Flag > +# > +GCC: *_*_IA32_PP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > +MSFT: *_*_IA32_ASM_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > +MSFT: *_*_IA32_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(= OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=3D0x00010015 -DASF_PE= I > +MSFT: *_*_IA32_VFRPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(= OPTIMIZE_DISABLE_OPTIONS) > +MSFT: *_*_IA32_APP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(= OPTIMIZE_DISABLE_OPTIONS) > +MSFT: *_*_IA32_ASLPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(= OPTIMIZE_DISABLE_OPTIONS) > +MSFT: *_*_IA32_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(= OPTIMIZE_DISABLE_OPTIONS) > + > +# > +# For X64 Global Build Flag > +# > + *_*_X64_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D= PI_SPECIFICATION_VERSION=3D0x00010015 > + *_*_X64_VFRPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > + *_*_X64_APP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > + *_*_X64_ASLPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > + *_*_X64_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > + *_*_X64_NASM_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > + > + > +# > +# For X64 Specific Build Flag > +# > +GCC: *_*_X64_PP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > +MSFT: *_*_X64_ASM_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > +MSFT: *_*_X64_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(= OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=3D0x00010015 > +MSFT: *_*_X64_VFRPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(= OPTIMIZE_DISABLE_OPTIONS) > +MSFT: *_*_X64_APP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(= OPTIMIZE_DISABLE_OPTIONS) > +MSFT: *_*_X64_ASLPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > +MSFT: *_*_X64_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > + > + > +# Force PE/COFF sections to be aligned at 4KB boundaries to support page= level protection > +[BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM= _CORE] > + MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096 > + GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 > + > +# Force PE/COFF sections to be aligned at 4KB boundaries to support Memo= ryAttribute table > +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] > + MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096 > + GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 > + > +# Force PE/COFF sections to be aligned at 4KB boundaries to support NX p= rotection > +[BuildOptions.common.EDKII.DXE_DRIVER, BuildOptions.common.EDKII.DXE_COR= E, BuildOptions.common.EDKII.UEFI_DRIVER, BuildOptions.common.EDKII.UEFI_AP= PLICATION] > + #MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096 > + #GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 > + > + > diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg= Pcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.d= sc > new file mode 100644 > index 0000000000..af548dc81b > --- /dev/null > +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc > @@ -0,0 +1,409 @@ > +## @file > +# PCD configuration build description file for the UpXtreme board. > +# > +# Copyright (c) 2020, Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +########################################################################= ######## > +# > +# Pcd Section - list of all PCD Entries used by this board. > +# > +########################################################################= ######## > + > +[PcdsFixedAtBuild.common] > + ###################################### > + # Key Boot Stage and FSP configuration > + ###################################### > + # > + # Please select the Boot Stage here. > + # Stage 1 - enable debug (system deadloop after debug init) > + # Stage 2 - mem init (system deadloop after mem init) > + # Stage 3 - boot to shell only > + # Stage 4 - boot to OS > + # Stage 5 - boot to OS with security boot enabled > + # Stage 6 - boot with advanced features enabled > + # > + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 > + > + # > + # 0: FSP Wrapper is running in Dispatch mode. > + # 1: FSP Wrapper is running in API mode. > + # Note: Dispatch mode is currently NOT supported for this board. > + # > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|1 > + > + # > + # FALSE: The board is not a FSP wrapper (FSP binary not used) > + # TRUE: The board is a FSP wrapper (FSP binary is used) > + # > + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE > + > + # > + # FSP Base address PCD will be updated in FDF basing on flash map. > + # > + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0 > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0 > + > + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000 > + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 > + gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000 > + gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 > + gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000 > + > + # > + # When sharing stack with boot loader, FSP only needs a small temp ram= for heap > + # > + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x10000 > + > + # > + # Boot loader stack size has to be large enough for FSP execution > + # > + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x30000 > + > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 > + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 > + > +[PcdsFeatureFlag.common] > + ###################################### > + # Edk2 Configuration > + ###################################### > + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFir= st|FALSE > + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE > +!if $(TARGET) =3D=3D RELEASE > + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE > +!else > + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE > +!endif > + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE > + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE > + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE > + > + ###################################### > + # Silicon Configuration > + ###################################### > + # Build switches > + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE > + > + # CPU > + gSiPkgTokenSpaceGuid.PcdCflCpuEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE > + > + # SA > + gSiPkgTokenSpaceGuid.PcdGnaEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdIpuEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdSaOcEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE > + > + # ME > + gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE > + gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE > + > + # Others > + gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE > + gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE > + gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE > + gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdUseHpetTimer|TRUE # TRUE - HPET / FALSE - 82= 54 timer is used. > + > + ###################################### > + # Platform Configuration > + ###################################### > + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 > + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 > + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE > + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE > +!endif > + > +!if $(TARGET) =3D=3D DEBUG > + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE > +!else > + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE > +!endif > + > + ###################################### > + # Board Configuration > + ###################################### > + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable|TRUE > + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport|TRUE > + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable|FALSE > + > +[PcdsFixedAtBuild.common] > + ###################################### > + # Edk2 Configuration > + ###################################### > +!if $(TARGET) =3D=3D RELEASE > + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0 > + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3 > +!else > + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F > + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 > +!endif > +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE > + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 > +!endif > + > + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE > + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01 > + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0 > + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800 > + gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_M= EMORY_ADDRESS) > + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400 > +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE > + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140 > +!endif > + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000 > + gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE > +!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable =3D=3D TRUE > + gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1 > +!endif > + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE > + > + # > + # Serial UART settings > + # > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|115200 > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|1843200 > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|FALSE > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x07 > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|0x03 > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialPciDeviceInfo|{0x19, 0x02, 0x8= 4, 0x00, 0xFF} > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterAccessWidth|8 > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0xFE036000 > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|4 > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE > + > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80 > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x00 > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0 > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44 > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2 > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800 > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08 > + > + # Specifies timeout value in microseconds for the BSP to detect all AP= s for the first time. > + gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000 > + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 > + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000 > + > + # > + # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtB= uild > + # (They will be DynamicEx in FSP Dispatch mode) > + # > + > + ## Specifies the size of the microcode Region. > + # @Prompt Microcode Region size. > + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0 > + > + ## Specifies the AP wait loop state during POST phase. > + # The value is defined as below. > + # 1: Place AP in the Hlt-Loop state. > + # 2: Place AP in the Mwait-Loop state. > + # 3: Place AP in the Run-Loop state. > + # @Prompt The AP wait loop state. > + gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 > + > + ###################################### > + # Silicon Configuration > + ###################################### > +!if $(TARGET) =3D=3D DEBUG > + gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1 > +!endif > + gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber|2 > + gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpa= ceGuid.PcdPciExpressRegionLength > + > + ###################################### > + # Platform Configuration > + ###################################### > + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 > + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8 > + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 > + > + # > + # The PCDs are used to control the Windows SMM Security Mitigations Ta= ble - Protection Flags > + # > + # BIT0: If set, expresses that for all synchronous SMM entries,SMM wil= l validate that input and output buffers lie entirely within the expected f= ixed memory regions. > + # BIT1: If set, expresses that for all synchronous SMM entries, SMM wi= ll validate that input and output pointers embedded within the fixed commun= ication buffer only refer to address ranges \ > + # that lie entirely within the expected fixed memory regions. > + # BIT2: Firmware setting this bit is an indication that it will not al= low reconfiguration of system resources via non-architectural mechanisms. > + # BIT3-31: Reserved > + # > + gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07 > + > +!if $(TARGET) =3D=3D RELEASE > + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402 > +!else > + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B > +!endif > + > + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b > +!if $(TARGET) =3D=3D RELEASE > + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70 > +!else > + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0 > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 1 > + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x= 00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,= 0x00, 0x00} > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 2 > + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x= 07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,= 0x00, 0x00} > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 3 > + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x= 07, 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,= 0x00, 0x00} > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 4 > + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x= 07, 0x03, 0x05, 0x1F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,= 0x00, 0x00} > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 5 > + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x= 0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,= 0x00, 0x00} > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 6 > + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x= 0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,= 0x00, 0x00} > +!endif > + > + ###################################### > + # Board Configuration > + ###################################### > + gBoardModulePkgTokenSpaceGuid.PcdPs2KbMsEnable|0 > + gBoardModulePkgTokenSpaceGuid.PcdSuperIoPciIsaBridgeDevice|{0x00, 0x00= , 0x1F, 0x00} > + > +[PcdsFixedAtBuild.IA32] > + ###################################### > + # Edk2 Configuration > + ###################################### > + gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 > + gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148 > + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 > + > + ###################################### > + # Platform Configuration > + ###################################### > + gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000 > + > +[PcdsFixedAtBuild.X64] > + ###################################### > + # Edk2 Configuration > + ###################################### > + > + # Default platform supported RFC 4646 languages: (American) English > + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-U= S" > + > +[PcdsPatchableInModule.common] > + ###################################### > + # Edk2 Configuration > + ###################################### > + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208 > + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 > + > +[PcdsDynamicDefault] > + ###################################### > + # Edk2 Configuration > + ###################################### > + gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE > + gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE > + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0 > + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0 > + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0 > + > + # > + # Set video to native resolution as Windows 8 WHCK requirement. > + # > + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x0 > + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x0 > + > + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum|0x00 > + > + # > + # FSP Base address PCD will be updated in FDF basing on flash map. > + # > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0 > + > + # Platform will pre-allocate UPD buffer and pass it to FspWrapper > + # Those dummy address will be patched before FspWrapper executing > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x0 > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x0 > + > + gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0 > + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16 > + > + ###################################### > + # Board Configuration > + ###################################### > + > + # Thunderbolt Configuration > + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch|0x0 > + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm|0x0 > + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad|0x02= 010011 > + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtForcepowerGpioPad|13 > + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioLevel|0x1 > + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify|0x1 > + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI|0x1 > + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax|26 > + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax|28 > + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd|100 > + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq|0x1 > + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport|0x0 > + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt|0x1 > + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq|0x1 > + > +[PcdsDynamicHii.X64.DEFAULT] > + ###################################### > + # Edk2 Configuration > + ###################################### > + gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport= "|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" > +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE > + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalV= ariableGuid|0x0|1 # Variable: L"Timeout" > +!else > + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalV= ariableGuid|0x0|5 # Variable: L"Timeout" > +!endif > diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/build_config= .cfg b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/build_config.cfg > new file mode 100644 > index 0000000000..f90df20dbb > --- /dev/null > +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/build_config.cfg > @@ -0,0 +1,35 @@ > +# @ build_config.cfg > +# This is the UpXtreme board specific build settings > +# > +# Copyright (c) 2020, Intel Corporation. All rights reserved.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > + > + > +[CONFIG] > +WORKSPACE_PLATFORM_BIN =3D > +EDK_SETUP_OPTION =3D > +openssl_path =3D > +BIOS_SIZE_OPTION =3D -DBIOS_SIZE_OPTION=3DSIZE_80 > +PLATFORM_BOARD_PACKAGE =3D WhiskeylakeOpenBoardPkg > +PROJECT =3D WhiskeylakeOpenBoardPkg/UpXtreme > +BOARD =3D UpXtreme > +FLASH_MAP_FDF =3D WhiskeylakeOpenBoardPkg/UpXtreme/Include/Fdf/FlashMapI= nclude.fdf > +PROJECT_DSC =3D WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkg.dsc > +BOARD_PKG_PCD_DSC =3D WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.d= sc > +PrepRELEASE =3D DEBUG > +SILENT_MODE =3D FALSE > +EXT_CONFIG_CLEAR =3D > +CapsuleBuild =3D FALSE > +EXT_BUILD_FLAGS =3D > +CAPSULE_BUILD =3D 0 > +TARGET =3D DEBUG > +TARGET_SHORT =3D D > +PERFORMANCE_BUILD =3D FALSE > +FSP_WRAPPER_BUILD =3D TRUE > +FSP_BIN_PKG =3D CoffeeLakeFspBinPkg > +FSP_PKG_NAME =3D CoffeelakeSiliconPkg > +FSP_BINARY_BUILD =3D FALSE > +FSP_TEST_RELEASE =3D FALSE > +SECURE_BOOT_ENABLE =3D FALSE > +BIOS_INFO_GUID =3D A842B2D2-5C88-44E9-A9E2-4830F26662B7 > diff --git a/Platform/Intel/build.cfg b/Platform/Intel/build.cfg > index 86a9115021..dbaec39876 100644 > --- a/Platform/Intel/build.cfg > +++ b/Platform/Intel/build.cfg > @@ -57,4 +57,5 @@ BIOS_INFO_GUID =3D > BoardX58Ich10 =3D SimicsOpenBoardPkg/BoardX58Ich10/build_config.cfg > GalagoPro3 =3D KabylakeOpenBoardPkg/GalagoPro3/build_config.cfg > KabylakeRvp3 =3D KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg > +UpXtreme =3D WhiskeylakeOpenBoardPkg/UpXtreme/build_config.cfg > WhiskeylakeURvp =3D WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config= .cfg > --=20 > 2.19.1.windows.1 > =