From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web09.7627.1582085209428759762 for ; Tue, 18 Feb 2020 20:06:49 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.115, mailfrom: nathaniel.l.desimone@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Feb 2020 20:06:49 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,459,1574150400"; d="scan'208";a="436099507" Received: from orsmsx105.amr.corp.intel.com ([10.22.225.132]) by fmsmga006.fm.intel.com with ESMTP; 18 Feb 2020 20:06:49 -0800 Received: from orsmsx111.amr.corp.intel.com (10.22.240.12) by ORSMSX105.amr.corp.intel.com (10.22.225.132) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 18 Feb 2020 20:06:48 -0800 Received: from orsmsx114.amr.corp.intel.com ([169.254.8.140]) by ORSMSX111.amr.corp.intel.com ([169.254.12.135]) with mapi id 14.03.0439.000; Tue, 18 Feb 2020 20:06:48 -0800 From: "Nate DeSimone" To: "devel@edk2.groups.io" , "Esakkithevar, Kathappan" CC: "Chaganty, Rangasai V" , "Chiu, Chasel" , "Kethi Reddy, Deepika" , "Agyeman, Prince" Subject: Re: [edk2-devel] [edk2-platforms] [PATCH V1 1/2] CoffeeLakeSiliconPkg: Add Cometlake U Silicon support Thread-Topic: [edk2-devel] [edk2-platforms] [PATCH V1 1/2] CoffeeLakeSiliconPkg: Add Cometlake U Silicon support Thread-Index: AQHV5mtFAHHd9txOFU6NemnteBWv16gibUWA Date: Wed, 19 Feb 2020 04:06:48 +0000 Message-ID: <20200219040645.GB2439@nate-virtualbox> References: <20200218145343.11820-1-kathappan.esakkithevar@intel.com> <20200218145343.11820-2-kathappan.esakkithevar@intel.com> In-Reply-To: <20200218145343.11820-2-kathappan.esakkithevar@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.7.159.63] MIME-Version: 1.0 Return-Path: nathaniel.l.desimone@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-ID: Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone On Tue, Feb 18, 2020 at 02:53:42PM +0000, Esakkithevar, Kathappan wrote: > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2280 >=20 > Adds CPU model, SA Device ID, PCH SKU ID for Cometlake U V1. >=20 > Key files > =3D=3D=3D=3D=3D=3D=3D=3D=3D > * CpuReg.h - Add CPU Family Model support. > * SaRegsHostBridge.h - Add SA Device ID support. > * MrcInterface.h - Add CPU Family Model support in MRC. > * PchRegsLpcCnl.h - Add PCH SKU ID support. >=20 > Signed-off-by: Kathappan Esakkithevar > Cc: Sai Chaganty > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Deepika Kethi Reddy > Cc: Prince Agyeman > --- > .../Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h | 5 ++++- > .../PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c | 18 +++++++++++= ++++++- > .../Pch/Include/Register/PchRegsLpcCnl.h | 3 ++- > .../Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLibCnl.c | 5 ++++- > .../SystemAgent/Include/Register/SaRegsHostBridge.h | 5 ++++- > .../MemoryInit/Include/Coffeelake/MrcInterface.h | 5 +++-- > 6 files changed, 34 insertions(+), 7 deletions(-) >=20 > diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h b/= Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h > index 68f2c019e2..4b9ce8d4d3 100644 > --- a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h > @@ -9,7 +9,7 @@ > - Definitions beginning with "S_" are register sizes > - Definitions beginning with "N_" are the bit position > > - Copyright (c) 2019 Intel Corporation. All rights reserved.
> + Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. > > SPDX-License-Identifier: BSD-2-Clause-Patent > **/ > @@ -181,6 +181,7 @@ > #define CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX 0x000806E0 > #define CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO 0x000906E0 > #define CPUID_FULL_FAMILY_MODEL_CANNONLAKE_DT_HALO 0x00060670 > +#define CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT 0x000A0660 > > #ifndef STALL_ONE_MICRO_SECOND > #define STALL_ONE_MICRO_SECOND 1 > @@ -206,6 +207,7 @@ typedef enum { > EnumCpuCflUltUlx =3D CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX, > EnumCpuCflDtHalo =3D CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO, > EnumCpuCnlDtHalo =3D CPUID_FULL_FAMILY_MODEL_CANNONLAKE_DT_HALO, > + EnumCpuCmlUlt =3D CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT, > EnumCpuMax =3D CPUID_FULL_FAMILY_MODEL > } CPU_FAMILY; > > @@ -256,6 +258,7 @@ typedef enum { > /// > typedef enum { > EnumCflCpu =3D 0, > + EnumCmlCpu, > EnumCpuUnknownGeneration =3D 255 > } CPU_GENERATION; > #endif > diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpu= PlatformLib/CpuPlatformLibrary.c b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/L= ibrary/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c > index 18f2028fa9..702a10c9d8 100644 > --- a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatfor= mLib/CpuPlatformLibrary.c > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatfor= mLib/CpuPlatformLibrary.c > @@ -1,7 +1,7 @@ > /** @file > CPU Platform Lib implementation. > > - Copyright (c) 2019 Intel Corporation. All rights reserved.
> + Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. > > SPDX-License-Identifier: BSD-2-Clause-Patent > **/ > @@ -80,6 +80,15 @@ GetCpuSku ( > CpuDid =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_= MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_MC_DEVICE_ID)); > > switch (CpuFamilyModel) { > + case CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT: > + switch (CpuDid) { > + case V_SA_DEVICE_ID_CML_ULT_1: // CML ULT > + case V_SA_DEVICE_ID_CML_ULT_2: // CML ULT > + case V_SA_DEVICE_ID_CML_ULT_3: // CML ULT > + CpuType =3D EnumCpuUlt; > + break; > + } > + break; > case CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX: > switch (CpuDid) { > case V_SA_DEVICE_ID_KBL_MB_ULT_1: // KBL ULT OPI > @@ -87,6 +96,9 @@ GetCpuSku ( > case V_SA_DEVICE_ID_CFL_ULT_2: // CFL ULT > case V_SA_DEVICE_ID_CFL_ULT_3: // CFL ULT > case V_SA_DEVICE_ID_CFL_ULT_4: // CFL ULT > + case V_SA_DEVICE_ID_CML_ULT_1: // CML ULT > + case V_SA_DEVICE_ID_CML_ULT_2: // CML ULT > + case V_SA_DEVICE_ID_CML_ULT_3: // CML ULT > CpuType =3D EnumCpuUlt; > break; > > @@ -378,6 +390,10 @@ GetCpuGeneration ( > CpuGeneration =3D EnumCflCpu; > break; > > + case EnumCpuCmlUlt: > + CpuGeneration =3D EnumCmlCpu; > + break; > + > default: > CpuGeneration =3D EnumCpuUnknownGeneration; > ASSERT (FALSE); > diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/Pch= RegsLpcCnl.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchR= egsLpcCnl.h > index 74789a87ce..e8a18cac3e 100644 > --- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpc= Cnl.h > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpc= Cnl.h > @@ -21,7 +21,7 @@ > - Registers / bits of new devices introduced in a PCH generation will= be just named > as "_PCH_" without [generation_name] inserted. > > - Copyright (c) 2019 Intel Corporation. All rights reserved.
> + Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. > > SPDX-License-Identifier: BSD-2-Clause-Patent > **/ > @@ -31,6 +31,7 @@ > > #define V_LPC_CFG_DID_CNL_H 0xA300 > #define V_LPC_CFG_DID_CNL_LP 0x9D80 > +#define V_LPC_CFG_DID_CML_LP 0x0280 > > // > // PCH-LP Device IDs > diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPch= InfoLib/PchInfoLibCnl.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Pe= iDxeSmmPchInfoLib/PchInfoLibCnl.c > index 431b1470c2..da6479f212 100644 > --- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib= /PchInfoLibCnl.c > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib= /PchInfoLibCnl.c > @@ -4,7 +4,7 @@ > All function in this library is available for PEI, DXE, and SMM, > But do not support UEFI RUNTIME environment call. > > - Copyright (c) 2019 Intel Corporation. All rights reserved.
> + Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. > > SPDX-License-Identifier: BSD-2-Clause-Patent > **/ > @@ -37,6 +37,9 @@ PchSeriesFromLpcDid ( > case V_LPC_CFG_DID_CNL_LP: > return PCH_LP; > > + case V_LPC_CFG_DID_CML_LP: > + return PCH_LP; > + > default: > return PCH_UNKNOWN_SERIES; > } > diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Regi= ster/SaRegsHostBridge.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/In= clude/Register/SaRegsHostBridge.h > index 2cc0e5be68..67bbf13d77 100644 > --- a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/Sa= RegsHostBridge.h > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/Sa= RegsHostBridge.h > @@ -15,7 +15,7 @@ > - Registers / bits of new devices introduced in a SA generation will = be just named > as "_SA_" without [generation_name] inserted. > > - Copyright (c) 2019 Intel Corporation. All rights reserved.
> + Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. > > SPDX-License-Identifier: BSD-2-Clause-Patent > **/ > @@ -112,6 +112,9 @@ > #define V_SA_DEVICE_ID_CFL_ULT_4 0x3E35 ///< CoffeeLake Mobile= (CFL-U 2+(1 or 2)) SA DID > #define V_SA_DEVICE_ID_CFL_ULT_6 0x3ECC ///< CoffeeLake Mobile= (CFL-U 2+3e) SA DID > > +#define V_SA_DEVICE_ID_CML_ULT_1 0x9B51 ///< CometLake (CML-U 6= +2) SA DID > +#define V_SA_DEVICE_ID_CML_ULT_2 0x9B61 ///< CometLake (CML-U 4= +2) SA DID > +#define V_SA_DEVICE_ID_CML_ULT_3 0x9B71 ///< CometLake (CML-U 2= +2) SA DID > // > // CoffeeLake CPU Desktop SA Device IDs B0:D0:F0 > // > diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/I= nclude/Coffeelake/MrcInterface.h b/Silicon/Intel/CoffeelakeSiliconPkg/Syste= mAgent/MemoryInit/Include/Coffeelake/MrcInterface.h > index 635906cc2b..b9b390cc71 100644 > --- a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/= Coffeelake/MrcInterface.h > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/= Coffeelake/MrcInterface.h > @@ -1,7 +1,7 @@ > /** @file > This file includes all the data structures that the MRC considers "gl= obal data". > > - Copyright (c) 2019 Intel Corporation. All rights reserved.
> + Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. > > SPDX-License-Identifier: BSD-2-Clause-Patent > **/ > @@ -477,7 +477,8 @@ typedef enum { > /// > typedef enum { > cmCFL_ULX_ULT =3D CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX, ///<= Coffeelake ULT/ULX > - cmCFL_DT_HALO =3D CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO ///<= Coffeelake DT/Halo > + cmCFL_DT_HALO =3D CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO, ///<= Coffeelake DT/Halo > + cmCML_ULX_ULT =3D CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT ///<= Cometlake ULT/ULX > } MrcCpuModel; > > /// > --=20 > 2.16.2.windows.1 >=20 >=20 >=20 >