From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mx.groups.io with SMTP id smtpd.web09.227.1582655326843213005 for ; Tue, 25 Feb 2020 10:28:46 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: kernel.org, ip: 198.145.29.99, mailfrom: srs0=fd/a=4n=linaro.org=ard.biesheuvel@kernel.org) Received: from localhost.localdomain (aaubervilliers-681-1-8-223.w90-88.abo.wanadoo.fr [90.88.13.223]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 610B52082F; Tue, 25 Feb 2020 18:28:45 +0000 (UTC) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, lersek@redhat.com, pete@akeo.ie, Ard Biesheuvel Subject: [PATCH 1/1] ArmPlatformPkg/PrePi: replace set/way cache ops with by-VA ones Date: Tue, 25 Feb 2020 19:28:34 +0100 Message-Id: <20200225182834.19380-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Cache maintenance operations by set/way are only intended to be used in the context of on/offlining a core, while it has been taken out of the coherency domain. Any use intended to ensure that the contents of the cache have made it to main memory is unreliable, since cacheline migration and non-architected system caches may cause these contents to linger elsewhere, without being visible in main memory once the MMU and caches are disabled. In KVM on Linux, there are horrid hacks in place to ensure that such set/way operations are trapped, and replaced with a single by-VA clean/invalidate of the entire guest VA space once the MMU state changes, which can be costly, and is unnecessary if we manage the caches a bit more carefully, and perform maintenance by virtual address only. So let's get rid of the call to ArmInvalidateDataCache () in the PrePeiCore startup code, and instead, invalidate the UEFI memory region by virtual address, which is the only memory region we will be touching with the caches and MMU both disabled and enabled. (This will lead to data corruption if data written with the MMU off is shadowed by clean, stale cachelines that stick around when the MMU is enabled again.) Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/PrePi/PeiMPCore.inf | 1 + ArmPlatformPkg/PrePi/PeiUniCore.inf | 1 + ArmPlatformPkg/PrePi/PrePi.c | 8 +++++--- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/ArmPlatformPkg/PrePi/PeiMPCore.inf b/ArmPlatformPkg/PrePi/Pe= iMPCore.inf index 9c5da0d42a7b..053f9fd9e616 100644 --- a/ArmPlatformPkg/PrePi/PeiMPCore.inf +++ b/ArmPlatformPkg/PrePi/PeiMPCore.inf @@ -37,6 +37,7 @@ [Packages] =20 [LibraryClasses] BaseLib + CacheMaintenanceLib DebugLib DebugAgentLib ArmLib diff --git a/ArmPlatformPkg/PrePi/PeiUniCore.inf b/ArmPlatformPkg/PrePi/P= eiUniCore.inf index ee9b05b25337..78d218ae09ca 100644 --- a/ArmPlatformPkg/PrePi/PeiUniCore.inf +++ b/ArmPlatformPkg/PrePi/PeiUniCore.inf @@ -37,6 +37,7 @@ [Packages] =20 [LibraryClasses] BaseLib + CacheMaintenanceLib DebugLib DebugAgentLib ArmLib diff --git a/ArmPlatformPkg/PrePi/PrePi.c b/ArmPlatformPkg/PrePi/PrePi.c index 2bb144958139..254fb331733e 100644 --- a/ArmPlatformPkg/PrePi/PrePi.c +++ b/ArmPlatformPkg/PrePi/PrePi.c @@ -8,6 +8,7 @@ =20 #include =20 +#include #include #include #include @@ -178,8 +179,6 @@ CEntryPoint ( =20 // Data Cache enabled on Primary core when MMU is enabled. ArmDisableDataCache (); - // Invalidate Data cache - ArmInvalidateDataCache (); // Invalidate instruction cache ArmInvalidateInstructionCache (); // Enable Instruction Caches on all cores. @@ -200,6 +199,10 @@ CEntryPoint ( =20 // If not primary Jump to Secondary Main if (ArmPlatformIsPrimaryCore (MpId)) { + + InvalidateDataCacheRange ((VOID *)UefiMemoryBase, + FixedPcdGet32(PcdSystemMemoryUefiRegionSiz= e)); + // Goto primary Main. PrimaryMain (UefiMemoryBase, StacksBase, StartTimeStamp); } else { @@ -209,4 +212,3 @@ CEntryPoint ( // DXE Core should always load and never return ASSERT (FALSE); } - --=20 2.20.1