From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web12.7272.1582768711434299530 for ; Wed, 26 Feb 2020 17:58:31 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: siyuan.fu@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Feb 2020 17:58:30 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,490,1574150400"; d="scan'208";a="271980533" Received: from shwdeopenpsi787.ccr.corp.intel.com ([10.239.158.56]) by fmsmga002.fm.intel.com with ESMTP; 26 Feb 2020 17:58:29 -0800 From: "Siyuan, Fu" To: devel@edk2.groups.io Cc: Ray Ni , Rangasai V Chaganty , Liming Gao Subject: [Patch] IntelSiliconPkg/ShadowMicrocodePei: Fix GCC build error. Date: Thu, 27 Feb 2020 09:58:26 +0800 Message-Id: <20200227015826.67948-1-siyuan.fu@intel.com> X-Mailer: git-send-email 2.19.1.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This patch fixes compiler error introduced by commit b0099a39bd. BZ: https://tianocore.acgmultimedia.com/show_bug.cgi?id=2449 Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Liming Gao Signed-off-by: Siyuan Fu --- .../Feature/ShadowMicrocode/ShadowMicrocodePei.c | 2 +- .../Intel/IntelSiliconPkg/Include/Guid/MicrocodeShadowInfoHob.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.c b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.c index 7e4084247e..8d6574f667 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.c @@ -247,7 +247,7 @@ ShadowMicrocodePatchWorker ( (VOID *) Patches[Index].Address, Patches[Index].Size ); - MicrocodeAddressInMemory[Index] = (UINT64) Walker; + MicrocodeAddressInMemory[Index] = (UINT64) (UINTN) Walker; Flashcontext->MicrocodeAddressInFlash[Index] = (UINT64) Patches[Index].Address; Walker += Patches[Index].Size; } diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Guid/MicrocodeShadowInfoHob.h b/Silicon/Intel/IntelSiliconPkg/Include/Guid/MicrocodeShadowInfoHob.h index d887b39123..1daae1234a 100644 --- a/Silicon/Intel/IntelSiliconPkg/Include/Guid/MicrocodeShadowInfoHob.h +++ b/Silicon/Intel/IntelSiliconPkg/Include/Guid/MicrocodeShadowInfoHob.h @@ -58,7 +58,7 @@ typedef struct { // microcode patch address on flash. The address is placed in same // order as the microcode patches in MicrocodeAddrInMemory. // - UINT64 MicrocodeAddressInFlash[]; + UINT64 MicrocodeAddressInFlash[0]; } EFI_MICROCODE_STORAGE_TYPE_FLASH_CONTEXT; #endif -- 2.19.1.windows.1