From: "Pete Batard" <pete@akeo.ie>
To: devel@edk2.groups.io
Cc: ard.biesheuvel@linaro.org, leif@nuviainc.com, philmd@redhat.com
Subject: [edk2-platforms][PATCH 02/15] Silicon/Bcm283x: Add missing peripherals constants
Date: Fri, 28 Feb 2020 10:38:42 +0000 [thread overview]
Message-ID: <20200228103855.11352-3-pete@akeo.ie> (raw)
In-Reply-To: <20200228103855.11352-1-pete@akeo.ie>
In order to be able to reference them in ACPI tables and elsewhere
we add some missing constants to be the Bcm283x headers.
These include:
* I2C, SPI and DMA constants
* Length of the peripherals register space
We also take this opportunity to clean up and harmonize the headers.
Signed-off-by: Pete Batard <pete@akeo.ie>
---
Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836.h | 39 ++++++++++++++++-
Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836Gpio.h | 6 ++-
Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836SdHost.h | 6 ++-
Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836Sdio.h | 44 ++++++++++----------
4 files changed, 71 insertions(+), 24 deletions(-)
diff --git a/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836.h b/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836.h
index cee5fb6a4e15..0b402e9ac56e 100644
--- a/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836.h
+++ b/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836.h
@@ -56,6 +56,7 @@
/* mailbox interface constants */
#define BCM2836_MBOX_OFFSET 0x0000b880
#define BCM2836_MBOX_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_MBOX_OFFSET)
+#define BCM2836_MBOX_LENGTH 0x00000024
#define BCM2836_MBOX_READ_OFFSET 0x00000000
#define BCM2836_MBOX_STATUS_OFFSET 0x00000018
#define BCM2836_MBOX_CONFIG_OFFSET 0x0000001c
@@ -75,7 +76,7 @@
#define BCM2836_USB_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_USB_OFFSET)
#define BCM2836_USB_LENGTH 0x00010000
-/* uart constants */
+/* serial based protocol constants */
#define BCM2836_PL011_UART_OFFSET 0x00201000
#define BCM2836_PL011_UART_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PL011_UART_OFFSET)
#define BCM2836_PL011_UART_LENGTH 0x00001000
@@ -86,4 +87,40 @@
#define BCM2836_MINI_UART_LENGTH 0x00000070
#define BCM2836_MINI_UART_INTERRUPT 0x7D
+#define BCM2836_I2C0_OFFSET 0x00205000
+#define BCM2836_I2C0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_I2C0_OFFSET)
+#define BCM2836_I2C0_LENGTH 0x00000020
+
+#define BCM2836_I2C1_OFFSET 0x00804000
+#define BCM2836_I2C1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_I2C1_OFFSET)
+#define BCM2836_I2C1_LENGTH 0x00000020
+
+#define BCM2836_I2C2_OFFSET 0x00805000
+#define BCM2836_I2C2_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_I2C2_OFFSET)
+#define BCM2836_I2C2_LENGTH 0x00000020
+
+#define BCM2836_SPI0_OFFSET 0x00204000
+#define BCM2836_SPI0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SPI0_OFFSET)
+#define BCM2836_SPI0_LENGTH 0x00000020
+
+#define BCM2836_SPI1_OFFSET 0x00215080
+#define BCM2836_SPI1_LENGTH 0x00000040
+#define BCM2836_SPI1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SPI1_OFFSET)
+
+#define BCM2836_SPI2_OFFSET 0x002150C0
+#define BCM2836_SPI2_LENGTH 0x00000040
+#define BCM2836_SPI2_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SPI2_OFFSET)
+
+/* dma constants */
+#define BCM2836_DMA0_OFFSET 0x00007000
+#define BCM2836_DMA0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_DMA0_OFFSET)
+
+#define BCM2836_DMA15_OFFSET 0x00E05000
+#define BCM2836_DMA15_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_DMA15_OFFSET)
+
+#define BCM2836_DMA_CTRL_OFFSET 0x00007FE0
+#define BCM2836_DMA_CTRL_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_DMA_CTRL_OFFSET)
+
+#define BCM2836_DMA_CHANNEL_LENGTH 0x00000100
+
#endif /*__BCM2836_H__ */
diff --git a/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836Gpio.h b/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836Gpio.h
index 123de2c2d1ad..e65cc5c3bbb4 100644
--- a/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836Gpio.h
+++ b/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836Gpio.h
@@ -7,10 +7,14 @@
*
**/
+#include <IndustryStandard/Bcm2836.h>
+
#ifndef __BCM2836_GPIO_H__
#define __BCM2836_GPIO_H__
-#define GPIO_BASE_ADDRESS (BCM2836_SOC_REGISTERS + 0x00200000)
+#define GPIO_OFFSET 0x00200000
+#define GPIO_BASE_ADDRESS (BCM2836_SOC_REGISTERS + GPIO_OFFSET)
+#define GPIO_LENGTH 0x000000B4
#define GPIO_GPFSEL0 (GPIO_BASE_ADDRESS + 0x00)
#define GPIO_GPFSEL1 (GPIO_BASE_ADDRESS + 0x04)
diff --git a/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836SdHost.h b/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836SdHost.h
index d0492a4ff43d..83fbeb99cb35 100644
--- a/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836SdHost.h
+++ b/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836SdHost.h
@@ -7,10 +7,14 @@
*
**/
+#include <IndustryStandard/Bcm2836.h>
+
#ifndef __BCM2836_SDHOST_H__
#define __BCM2836_SDHOST_H__
-#define SDHOST_BASE_ADDRESS (BCM2836_SOC_REGISTERS + 0x00202000)
+#define SDHOST_OFFSET 0x00202000
+#define SDHOST_BASE_ADDRESS (BCM2836_SOC_REGISTERS + SDHOST_OFFSET)
+#define SDHOST_LENGTH 0x00000100
#define SDHOST_REG(X) (SDHOST_BASE_ADDRESS + (X))
#define SDHOST_CMD SDHOST_REG(0x0)
#define SDHOST_ARG SDHOST_REG(0x4)
diff --git a/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836Sdio.h b/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836Sdio.h
index 708a1d7a4f47..fd07b4717068 100644
--- a/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836Sdio.h
+++ b/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836Sdio.h
@@ -6,20 +6,22 @@
*
**/
+#include <IndustryStandard/Bcm2836.h>
+
#ifndef __BCM2836_SDIO_H__
#define __BCM2836_SDIO_H__
-//MMC/SD/SDIO1 register definitions.
+// MMC/SD/SDIO1 register definitions.
#define MMCHS1_OFFSET 0x00300000
-#define MMCHS1BASE (FixedPcdGet64 (PcdBcm283xRegistersAddress) \
- + MMCHS1_OFFSET)
+#define MMCHS1_BASE (BCM2836_SOC_REGISTERS + MMCHS1_OFFSET)
+#define MMCHS1_LENGTH 0x00000100
-#define MMCHS_BLK (MMCHS1BASE + 0x4)
+#define MMCHS_BLK (MMCHS1_BASE + 0x4)
#define BLEN_512BYTES (0x200UL << 0)
-#define MMCHS_ARG (MMCHS1BASE + 0x8)
+#define MMCHS_ARG (MMCHS1_BASE + 0x8)
-#define MMCHS_CMD (MMCHS1BASE + 0xC)
+#define MMCHS_CMD (MMCHS1_BASE + 0xC)
#define BCE_ENABLE BIT1
#define DDIR_READ BIT4
#define DDIR_WRITE (0x0UL << 4)
@@ -41,13 +43,13 @@
#define INDX(CMD_INDX) (TYPE(CMD_TYPE_NORMAL) | _INDX(CMD_INDX))
#define INDX_ABORT(CMD_INDX) (TYPE(CMD_TYPE_ABORT) | _INDX(CMD_INDX))
-#define MMCHS_RSP10 (MMCHS1BASE + 0x10)
-#define MMCHS_RSP32 (MMCHS1BASE + 0x14)
-#define MMCHS_RSP54 (MMCHS1BASE + 0x18)
-#define MMCHS_RSP76 (MMCHS1BASE + 0x1C)
-#define MMCHS_DATA (MMCHS1BASE + 0x20)
+#define MMCHS_RSP10 (MMCHS1_BASE + 0x10)
+#define MMCHS_RSP32 (MMCHS1_BASE + 0x14)
+#define MMCHS_RSP54 (MMCHS1_BASE + 0x18)
+#define MMCHS_RSP76 (MMCHS1_BASE + 0x1C)
+#define MMCHS_DATA (MMCHS1_BASE + 0x20)
-#define MMCHS_PRES_STATE (MMCHS1BASE + 0x24)
+#define MMCHS_PRES_STATE (MMCHS1_BASE + 0x24)
#define CMDI_MASK BIT0
#define CMDI_ALLOWED (0x0UL << 0)
#define CMDI_NOT_ALLOWED BIT0
@@ -56,7 +58,7 @@
#define DATI_NOT_ALLOWED BIT1
#define WRITE_PROTECT_OFF BIT19
-#define MMCHS_HCTL (MMCHS1BASE + 0x28)
+#define MMCHS_HCTL (MMCHS1_BASE + 0x28)
#define DTW_1_BIT (0x0UL << 1)
#define DTW_4_BIT BIT1
#define SDBP_MASK BIT8
@@ -66,7 +68,7 @@
#define SDVS_3_0_V (0x6UL << 9)
#define IWE BIT24
-#define MMCHS_SYSCTL (MMCHS1BASE + 0x2C)
+#define MMCHS_SYSCTL (MMCHS1_BASE + 0x2C)
#define ICE BIT0
#define ICS_MASK BIT1
#define ICS BIT1
@@ -82,7 +84,7 @@
#define SRC BIT25
#define SRD BIT26
-#define MMCHS_INT_STAT (MMCHS1BASE + 0x30)
+#define MMCHS_INT_STAT (MMCHS1_BASE + 0x30)
#define CC BIT0
#define TC BIT1
#define BWR BIT4
@@ -94,7 +96,7 @@
#define DCRC BIT21
#define DEB BIT22
-#define MMCHS_IE (MMCHS1BASE + 0x34)
+#define MMCHS_IE (MMCHS1_BASE + 0x34)
#define CC_EN BIT0
#define TC_EN BIT1
#define BWR_EN BIT4
@@ -110,7 +112,7 @@
#define BADA_EN BIT29
#define ALL_EN 0xFFFFFFFF
-#define MMCHS_ISE (MMCHS1BASE + 0x38)
+#define MMCHS_ISE (MMCHS1_BASE + 0x38)
#define CC_SIGEN BIT0
#define TC_SIGEN BIT1
#define BWR_SIGEN BIT4
@@ -125,14 +127,14 @@
#define CERR_SIGEN BIT28
#define BADA_SIGEN BIT29
-#define MMCHS_AC12 (MMCHS1BASE + 0x3C)
+#define MMCHS_AC12 (MMCHS1_BASE + 0x3C)
-#define MMCHS_CAPA (MMCHS1BASE + 0x40)
+#define MMCHS_CAPA (MMCHS1_BASE + 0x40)
#define VS30 BIT25
#define VS18 BIT26
-#define MMCHS_CUR_CAPA (MMCHS1BASE + 0x48)
-#define MMCHS_REV (MMCHS1BASE + 0xFC)
+#define MMCHS_CUR_CAPA (MMCHS1_BASE + 0x48)
+#define MMCHS_REV (MMCHS1_BASE + 0xFC)
#define BLOCK_COUNT_SHIFT 16
#define RCA_SHIFT 16
--
2.21.0.windows.1
next prev parent reply other threads:[~2020-02-28 10:39 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-28 10:38 [edk2-platforms][PATCH 00/15] Platform/RPi: Clean up and factorize ACPI Pete Batard
2020-02-28 10:38 ` [edk2-platforms][PATCH 01/15] Platform/RPi: Move DW USB base address to Silicon Pete Batard
2020-03-02 11:21 ` Philippe Mathieu-Daudé
2020-02-28 10:38 ` Pete Batard [this message]
2020-02-28 10:38 ` [edk2-platforms][PATCH 03/15] Silicon/Bcm283x: Add GPU/VideoCore and Power Management constants Pete Batard
2020-02-28 10:38 ` [edk2-platforms][PATCH 04/15] Silicon/BcmGenet: Add missing I/O mapping length and clean up Pete Batard
2020-02-28 10:45 ` Ard Biesheuvel
2020-02-28 10:51 ` Pete Batard
2020-02-28 10:58 ` Ard Biesheuvel
2020-02-28 11:01 ` Pete Batard
2020-02-28 10:38 ` [edk2-platforms][PATCH 05/15] Platform/RPi4: Use Silicon constants in ACPI headers Pete Batard
2020-02-28 10:38 ` [edk2-platforms][PATCH 06/15] Platform/RPi3: " Pete Batard
2020-02-28 10:38 ` [edk2-platforms][PATCH 07/15] Platform/RPi3: Switch to .aslc for serial related ACPI tables Pete Batard
2020-02-28 10:38 ` [edk2-platforms][PATCH 08/15] Platform/RPi3: Update CSRT table to ACPI 5.1 Pete Batard
2020-02-28 10:38 ` [edk2-platforms][PATCH 09/15] Platform/RPi3: Use proper aslc for FADT, GTDT and MADT tables generation Pete Batard
2020-02-28 10:38 ` [edk2-platforms][PATCH 10/15] Platform/RPi4: Add RPI_MODEL constant and replace PL011_ENABLE Pete Batard
2020-02-28 10:38 ` [edk2-platforms][PATCH 11/15] Platform/RPi4: Move ACPI interrupts definitions to AcpiTables.h Pete Batard
2020-02-28 10:38 ` [edk2-platforms][PATCH 12/15] Platform/RPi3: " Pete Batard
2020-02-28 10:38 ` [edk2-platforms][PATCH 13/15] Platform/RPi4: Prepare ACPI code for factorization Pete Batard
2020-02-28 10:38 ` [edk2-platforms][PATCH 14/15] Platform/RPi3: Merge ACPI code from RPi4 Pete Batard
2020-02-28 10:38 ` [edk2-platforms][PATCH 15/15] Platform/RPi: Factorize ACPI tables Pete Batard
2020-02-28 12:17 ` [edk2-platforms][PATCH 00/15] Platform/RPi: Clean up and factorize ACPI Ard Biesheuvel
2020-03-02 11:14 ` Ard Biesheuvel
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