From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ot1-f66.google.com (mail-ot1-f66.google.com [209.85.210.66]) by mx.groups.io with SMTP id smtpd.web11.15502.1583345593566510654 for ; Wed, 04 Mar 2020 10:13:13 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=ODgtrow2; spf=pass (domain: linaro.org, ip: 209.85.210.66, mailfrom: ard.biesheuvel@linaro.org) Received: by mail-ot1-f66.google.com with SMTP id v22so2937645otq.11 for ; Wed, 04 Mar 2020 10:13:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=j9Lf5E7gk9UP8d5P3FF3ca54OJhG/tbfi2x9TBr9Qdk=; b=ODgtrow27aCOaIejbOZXice3ywEbXbIzw+Pj7Ehmtwpt+bDsDrXsWVjeN8WrEZFn8d CtXGPwrcc+kIATgDItgkDaFYxhBh7RxxH4SGCCBc34KDpjefwNdITnerKH6RSE4uQnii gv8kU1qXoioNugfWmT0eiuKQsMblfFIHtjECxVwOx+QJfxZL4HxflB2HjR0WjRk0tq/p dttrY4c19UTlDsJnqQj+u23dWWQopcKQansUseMm6+9oWVYSN/DRXBW2BSCbON6xqmzG tyT4TYJBfnRsf9QptlveuNplK/t0kOKfXJ2qXuDn2PyupbXVMvrMRNfYrgh/FyXKiEci M2sA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=j9Lf5E7gk9UP8d5P3FF3ca54OJhG/tbfi2x9TBr9Qdk=; b=M9jurz2sxa8ML2Bb7fY3jjwvSYvNDZ7husQ67mNKH5y7Ir/UJ/mABAWu0Whh7EIeMc OCCfrP8Wi8J6X5zw2sbx74amsrprsD6Mg5EYz/7JVVpbcWOavBDdMsO/9sO2HeVtBXx+ Fo/w96gzJiTUYaWpRJA9uh4TSi3TAReM62VSlhvFFp6zWwOD41PIaI3J5GDpiUdSdKdg f6k8aXGiMPI4eNw2NNUYepd085Hv/w0kyikwQew9qdYk2lcuHUtVDgqZYIuM81xgTaMK 3b8EcAhsqtHS362SkB48DCIOFTvTHRqa6D5TE+4GnkuWIRhM/Cymn1eJamOGMAuFDi8k +bPA== X-Gm-Message-State: ANhLgQ3WSmikl0qKZpqeN2YD6m2yg88w1yduUNXstPcQHUBPagvJiDzq eg/ENQduUpbMXWR1SHpOOELcEALBPtjxmA== X-Google-Smtp-Source: ADFU+vueXbtsc1EH0wG6B9ckzIXT86CaRgD4ihxxClOOj9FxdseQWDnoY++xZgRQaEqV7sv75Y1oLA== X-Received: by 2002:a05:6830:16c8:: with SMTP id l8mr3335971otr.2.1583345592526; Wed, 04 Mar 2020 10:13:12 -0800 (PST) Return-Path: Received: from cam-smtp0.cambridge.arm.com ([2a01:cb1d:112:6f00:816e:ff0d:fb69:f613]) by smtp.gmail.com with ESMTPSA id p65sm9083971oif.47.2020.03.04.10.13.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2020 10:13:11 -0800 (PST) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif@nuviainc.com, Ard Biesheuvel Subject: [PATCH v2 9/9] ArmPkg/ArmLib: ASSERT on set/way cache ops being used with MMU on Date: Wed, 4 Mar 2020 19:12:46 +0100 Message-Id: <20200304181246.23513-10-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200304181246.23513-1-ard.biesheuvel@linaro.org> References: <20200304181246.23513-1-ard.biesheuvel@linaro.org> On ARMv7 and up, doing cache maintenance by set/way is only permitted in the context of on/offlining a core, and any other uses should be avoided. Add ASSERT()s in the right place to ensure that any uses with the MMU enabled are caught in DEBUG builds. Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c | 7 +++++++ ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c | 7 +++++++ ArmPkg/Library/ArmLib/ArmBaseLib.inf | 3 +++ 3 files changed, 17 insertions(+) diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c index 924bf48020e0..3fbd591192e2 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c @@ -10,6 +10,7 @@ #include #include +#include #include @@ -41,6 +42,8 @@ ArmInvalidateDataCache ( VOID ) { + ASSERT (!ArmMmuEnabled ()); + ArmDataSynchronizationBarrier (); AArch64DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay); } @@ -51,6 +54,8 @@ ArmCleanInvalidateDataCache ( VOID ) { + ASSERT (!ArmMmuEnabled ()); + ArmDataSynchronizationBarrier (); AArch64DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay); } @@ -61,6 +66,8 @@ ArmCleanDataCache ( VOID ) { + ASSERT (!ArmMmuEnabled ()); + ArmDataSynchronizationBarrier (); AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay); } diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c b/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c index 5d93aa6e0b8c..2c4a23e1a1b2 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c +++ b/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c @@ -10,6 +10,7 @@ #include #include +#include #include @@ -41,6 +42,8 @@ ArmInvalidateDataCache ( VOID ) { + ASSERT (!ArmMmuEnabled ()); + ArmDataSynchronizationBarrier (); ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay); } @@ -51,6 +54,8 @@ ArmCleanInvalidateDataCache ( VOID ) { + ASSERT (!ArmMmuEnabled ()); + ArmDataSynchronizationBarrier (); ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay); } @@ -61,6 +66,8 @@ ArmCleanDataCache ( VOID ) { + ASSERT (!ArmMmuEnabled ()); + ArmDataSynchronizationBarrier (); ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay); } diff --git a/ArmPkg/Library/ArmLib/ArmBaseLib.inf b/ArmPkg/Library/ArmLib/ArmBaseLib.inf index 106a09f821e1..f61c71b673d1 100644 --- a/ArmPkg/Library/ArmLib/ArmBaseLib.inf +++ b/ArmPkg/Library/ArmLib/ArmBaseLib.inf @@ -44,6 +44,9 @@ [Sources.AARCH64] AArch64/AArch64Support.S AArch64/AArch64ArchTimerSupport.S +[LibraryClasses] + DebugLib + [Packages] ArmPkg/ArmPkg.dec MdePkg/MdePkg.dec -- 2.17.1